Relevant bibliographies by topics / Electrical interconnect modeling

Academic literature on the topic 'Electrical interconnect modeling'

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Published: 14 March 2023

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Journal articles on the topic "Electrical interconnect modeling"

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Dong, Chen, Wei Wang, and Maher Rizkalla. "Modeling and Simulation of Carbon Nanotube Interconnect Network." Solid State Phenomena 121-123 (March 2007): 1057–60. http://dx.doi.org/10.4028/www.scientific.net/ssp.121-123.1057.

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The electrical properties of metallic carbon nanotubes (CNT) can rival, or even exceed, the best metals known. It is a potential candidate for future on-chip interconnect, whose performance will be dominant in the next generation integrated circuits. In this paper, a study on the modeling and simulation techniques for the CNT interconnect network is carried out. The frequency-independent models of CNT interconnects in terms of resistance, inductance and capacitance are summarized. A novel frequencydependent circuit model is proposed for CNT for various high-frequency applications. Preliminary analysis shows a good match between numerical simulations and the compact model. The proposed modeling and simulation techniques for CNT interconnect network are expected to play an important role in the future CNT nanotechnology applications.
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Kumari, B., R. Sharma, and M. Sahoo. "Electro-thermal modeling and reliability analysis of Cu–carbon hybrid interconnects for beyond-CMOS computing." Applied Physics Letters 121, no. 10 (September 5, 2022): 101901. http://dx.doi.org/10.1063/5.0101329.

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A Cu–carbon hybrid interconnect was recently proposed as an alternate interconnect structure for future VLSI applications because of its superior electrical performance over its counterparts. This study focuses on the electro-thermal aspects of Cu–carbon hybrid interconnects to be adopted as a potential replacement of copper as the back-end-of-line (BEOL) interconnect material. Cu–carbon hybrid shows promise in terms of electro-thermal efficiency when compared to copper as well as other suggested hybrid materials. The maximum temperature attained by the Cu–carbon hybrid interconnect is less than copper by 16%, and its mean time to failure is improved by 96%. Uniform distribution of heat can be observed in the Cu–carbon hybrid BEOL in addition to low temperature rise as compared to the copper based BEOL. These analyses strengthen the claim of Cu–carbon hybrid interconnects to be a worthier possibility for electro-thermal efficient nanoscale systems.
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Xu, Yao, Ashok Srivastava, and Ashwani K. Sharma. "Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance." VLSI Design 2010 (February 17, 2010): 1–8. http://dx.doi.org/10.1155/2010/864165.

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Current transport and dynamic models of carbon nanotube field-effect transistors are presented. A model of single-walled carbon nanotube as interconnect is also presented and extended in modeling of single-walled carbon nanotube bundles. These models are applied in studying the performances of circuits such as the complementary carbon nanotube inverter pair and carbon nanotube as interconnect. Cadence/Spectre simulations show that carbon nanotube field-effect transistor circuits can operate at upper GHz frequencies. Carbon nanotube interconnects give smaller delay than copper interconnects used in nanometer CMOS VLSI circuits.
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Poltz, J. "MODELING OF VLSI INTERCONNECT." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 13, no. 1 (January 1994): 191–94. http://dx.doi.org/10.1108/eb051872.

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Carver, Chase, Norman Seastrand, and Robert Welte. "PWB Z Interconnect Technology - Electrical Performance." International Symposium on Microelectronics 2014, no. 1 (October 1, 2014): 000217–21. http://dx.doi.org/10.4071/isom-tp23.

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Driven mainly by Moore's law, there is an ever accelerating drive for smaller, lighter, higher function, and lower power electronics. For PWBs this translates into higher wiring and component densities with ever increasing electrical performance requirements. As high speed serial data rates reach 30 Gbps and beyond, design considerations to promote signal integrity become ever more important. These tighter signal integrity constraints put increased emphasis on via stub effects, via to trace crosstalk in BGA escapes, and adequate ground stitch vias around layer transition vias. With the maturation of sintered paste VIAs in PWBs, VIA structures can be assembled to span only the layers to be connected. This paste technology allows vias to be specifically tailored to only connect the required layers. VIA stubs and their adverse SI effects for high speed signaling are completely eliminated. The elimination of via stubs also makes PWB fabrication easier by removing the need to backdrill or counterbore high speed signal vias. This increases yields and reduces costs associated with this complex and tight tolerance process. In addition to manufacturing advantages provided by Z technology, increased wireability is enabled by opening up area above and below the layers being connected, as well as the ability to use smaller diameter VIAs. These smaller vias also help to reduce crosstalk between high speed wiring channels. Z Interconnect technology also reduces BGA escape crosstalk by the ability to route in areas where via stubs have been removed, and also allows for the tailoring of ground stitch vias to only connect the ground planes associated with the specific stripline environments. However, Z VIAs usually require more pads within the padstack than conventional VIAs (cannot strip pads from non-connection layers) and the resistivity of the paste can be as much as 30 times greater than copper. This paper will quantify the high frequency signal characteristics associated with a PWB design using i3 Electronics sintered paste Z-VIAs. Results are presented based on modeling which is correlated with test vehicle measurements. Modeling also addresses manufacturing tolerances. Suggestions are made for optimizing passive channel structures to use this technology in support of high speed serial interconnects. Integration of i3's 2s1p Cores into new compact high speed stripline structures, which can be built without expensive subassemblies and sequential lamination processes, is also presented. These cores implement the positive aspects of Z Interconnect technology to eliminate via stubs and increase wireability in dense areas. Comparisons of Z Interconnect technology are also made to alternate methods of PWB construction to explain the risks and benefits of this technology.
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Hazra, Arnab, and Sukumar Basu. "Graphene Nanoribbon as Potential On-Chip Interconnect Material—A Review." C 4, no. 3 (August 30, 2018): 49. http://dx.doi.org/10.3390/c4030049.

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In recent years, on-chip interconnects have been considered as one of the most challenging areas in ultra-large scale integration. In ultra-small feature size, the interconnect delay becomes more pronounced than the gate delay. The continuous scaling of interconnects introduces significant parasitic effects. The resistivity of interconnects increases because of the grain boundary scattering and side wall scattering of electrons. An increased Joule heating and the low current carrying capability of interconnects in a nano-scale dimension make it unreliable for future technology. The devices resistivity and reliability have become more and more serious problems for choosing the best interconnect materials, like Cu, W, and others. Because of its remarkable electrical and its other properties, graphene becomes a reliable candidate for next-generation interconnects. Graphene is the lowest resistivity material with a high current density, large mean free path, and high electron mobility. For practical implementation, narrow width graphene sheet or graphene nanoribbon (GNR) is the most suitable interconnect material. However, the geometric structure changes the electrical property of GNR to a small extent compared to the ideal behavior of graphene film. In the current article, the structural and electrical properties of single and multilayer GNRs are discussed in detail. Also, the fabrication techniques are discussed so as to pattern the graphene nanoribbons for interconnect application and measurement. A circuit modeling of the resistive-inductive-capacitive distributed network for multilayer GNR interconnects is incorporated in the article, and the corresponding simulated results are compared with the measured data. The performance of GNR interconnects is discussed from the view of the resistivity, resistive-capacitive delay, energy delay product, crosstalk effect, stability analysis, and so on. The performance of GNR interconnects is well compared with the conventional interconnects, like Cu, and other futuristic potential materials, like carbon nanotube and doped GNRs, for different technology nodes of the International Technology Roadmap for Semiconductors (ITRS).
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Myeong-Eun Hwang, Seong-Ook Jung, and K. Roy. "Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation." IEEE Transactions on Circuits and Systems I: Regular Papers 56, no. 7 (July 2009): 1428–41. http://dx.doi.org/10.1109/tcsi.2008.2006217.

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Liao, Weiping, and Lei He. "Microarchitecture Level Interconnect Modeling Considering Layout Optimization." Journal of Low Power Electronics 1, no. 3 (December 1, 2005): 297–308. http://dx.doi.org/10.1166/jolpe.2005.036.

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Banan, Behnam, Farhad Shokraneh, Pierre Berini, and Odile Liboiron-Ladouceur. "Electrical performance analysis of a CPW capable of transmitting microwave and optical signals." International Journal of Microwave and Wireless Technologies 9, no. 8 (June 5, 2017): 1679–86. http://dx.doi.org/10.1017/s1759078717000575.

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A study on the microwave performance of a metallic transmission line capable of simultaneously transmitting microwave and optical signals is presented targeting millimeter-long interconnects. Conventional analytical solution is used to find the optimal structure for a given characteristic impedance. Then, functionality of the link is validated through S-parameter measurements for 3–13 mm long lines. The waveguide parameters, such as resistance, inductance, capacitance, and conductance are extracted based on a lumped circuit model. The modeling enables structure optimization for interconnect bandwidth density of 1 Gb/s/μm and more.
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Kurokawa, Atsushi, Takashi Sato, Toshiki Kanamoto, and Masanori Hashimoto. "Interconnect Modeling: A Physical Design Perspective." IEEE Transactions on Electron Devices 56, no. 9 (September 2009): 1840–51. http://dx.doi.org/10.1109/ted.2009.2026208.

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Dissertations / Theses on the topic "Electrical interconnect modeling"

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Kim, Byungsub 1978. "Equalized on-chip interconnect : modeling, analysis, and design." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/58076.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 115-118).
This thesis work explores the use of equalization techniques to improve throughput and reduce power consumption of on-chip interconnect. A theoretical model for an equalized on-chip interconnect is first suggested to provide mathematical formulation for the link behavior. Based on the model, a fast-design space exploration methodology is demonstrated to search for the optimal link design parameters (wire and circuit) and to generate the optimal performance-power trade-off curve for the equalized interconnects. This thesis also proposes new circuit techniques, which improve the revealed demerits of the conventional circuit topologies. The proposed charge-injection transmitter directly conducts pre-emphasis current from the supply into the channel, eliminating the power overhead of analog current subtraction in the conventional transmit pre-emphasis, while significantly relaxing the driver coefficient accuracy requirements. The transmitter utilizes a power efficient nonlinear driver by compensating non-linearity with pre-distorted equalization coefficients. A trans-impedance amplifier at the receiver achieves low static power consumption, large signal amplitude, and high bandwidth by mitigating limitations of purely-resistive termination. A test chip is fabricated in 90-nm bulk CMOS technology and tested over a 10 mm, 2[micro]m pitched on-chip differential wire. The transceiver consumes 0.37-0.63 pJ/b with 2-6 Gb/s/ch.
by Byungsub Kim.
Ph.D.
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Sotiriadis, Paul Peter P. (Paul Peter Peter-Paul) 1973. "Interconnect modeling and optimization in deep sub-micron technologies." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/29230.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
Includes bibliographical references.
Interconnect will be a major bottleneck for deep sub-micron technologies in the years to come. This dissertation addresses the communication aspect from a power consumption and transmission speed perspective. A model for the energy consumption associated with data transmission through deep sub-micron technology buses is derived. The capacitive and inductive coupling between the bus lines as well as the distributed nature of the wires is taken into account. The model is used to estimate the power consumption of the bus as a function of the Transition Activity Matrix, a quantity generalizing the transition activity factors of the individual lines. An information theoretic framework has been developed to study the relation between speed (number of operations per time unit) and energy consumption per operation in the case of synchronous digital systems. The theory provides us with the fundamental minimum energy per input information bit that is required to process or communicate information at a certain rate. The minimum energy is a function of the information rate, and it is, in theory, asymptotically achievable using coding. This energy-information theory combined with the bus energy model result in the derivation of the fundamental performance limits of coding for low power in deep sub-micron buses. Although linear, block linear and differential coding schemes are favorable candidates for error correction, it is shown that they only increase power consumption in buses. Their resulting power consumption is related to structural properties of their generator matrices. In some cases the power is calculated exactly and in other cases bounds are derived.
(cont.) Both provide intuition about how to re-structure a given linear (block linear, etc.) code so that the energy is minimized within the set of all equivalent codes. A large class of nonlinear coding schemes is examined that leads to significant power reduction. This class contains all encoding schemes that have the form of connected Finite State Machines. The deep sub-micron bus energy model is used to evaluate their power reduction properties. Mathematical analysis of this class of coding schemes has led to the derivation of two coding optimization algorithms. Both algorithms derive efficient coding schemes taking into account statistical properties of the data and the particular structure of the bus. This coding design approach is generally applicable to any discrete channel with transition costs. For power reduction, a charge recycling technique appropriate for deep sub-micron buses is developed. A detailed mathematical analysis provides the theoretical limits of power reduction. It is shown that for large buses power can be reduced by a factor of two. An efficient modular circuit implementation is presented that demonstrates the practicality of the technique and its significant net power reduction. Coding for speed on the bus is introduced. This novel idea is based on the fact that coupling between the lines in a deep sub-micron bus implies that different transitions require different amounts of time to complete. By allowing only "fast" transitions to take place, we can increase the clock frequency of the bus. The combinatorial capacity of such a constrained bus ...
by Paul Peter P. Sotiriadis.
Ph.D.
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Vittala, Kavya. "Interconnect Modeling and Lifetime Failure Detection in FPGAs using Delay Faults." University of Toledo / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1404728195.

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Percey, Andrew K. (Andrew Kenneth). "Analysis and modeling of capacitive coupling along metal interconnect lines." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/39067.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.
Includes bibliographical references (leaf 87).
by Andrew K. Percey.
M.Eng.
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Kuo, Benjamin S. "Modeling and evaluation of a hierarchical ring interconnect for system-on-chip multiprocessing." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=81543.

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This thesis proposes a software model for a multiprocessor system, which is targeted for SoC implementation. The proposed design is based on the two-level ring architecture adopted in the NUMAchine multiprocessor developed at University of Toronto. The proposed system reconsiders the interconnect design alternatives for smaller design area and energy consumption. The system uses an alternative memory architecture to reduce logic complexity, as well as a different deadlock prevention scheme to reflect changes in memory architecture. The software model is implemented in the SystemC modeling language, which allows high-level behavior modeling to reduce both the development time and the simulation time. The model is also at a level of detail which reflects true communication characteristics on the interconnect network. Burst length, memory access latency, FIFO depth, and the operating frequencies for the rings are the four key SoC design parameters which have been identified and optimized for the system.
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Chou, Mike Chuan 1969. "Fast algorithms for ill-conditioned dense matrix problems in VLSI interconnect and substrate modeling." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46180.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
Includes bibliographical references (leaves 131-135).
by Mike Chuan Chou.
Ph.D.
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Seo, Chung-Seok. "Physical Design of Optoelectronic System-on-a-Chip/Package Using Electrical and Optical Interconnects: CAD Tools and Algorithms." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-11102004-150844/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
David E. Schimmel, Committee Member ; C.P. Wong, Committee Member ; John A. Buck, Committee Member ; Abhijit Chatterjee, Committee Chair ; Madhavan Swaminathan, Committee Member. Vita. Includes bibliographical references.
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Lee, Laurence H. (Laurence Hongsing). "Modeling and design of superconducting microwave passive devices and interconnects." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36452.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (p. 157-163).
by Laurence H. Lee.
Ph.D.
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Chiun-Shen, Liao. "A network approach for thermo-electrical modelling : from IC interconnects to textile composites." Thesis, University of British Columbia, 2010. http://hdl.handle.net/2429/28471.

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Simulations of the temperature distribution in regular IC interconnect networks and textile composites are achieved by means of an analytical-symbolic approach. Analytical heating solutions along each interconnect can provide accurate solutions with far fewer nodes than numerical solutions. To simulate the case of textile composite, the textile composite is modelled by a network of interconnects. The necessary input information is contained in netlist files, similar to the SPICE (Simulation Program with Integrated Circuit Emphasis) input format. Analytical solutions to the heat equation along each interconnect can provide accuracy and require the minimum number of symbolic network nodes. The LU decomposition of the symbolic network scales as the cube of the number of nodes. Multiple evaluations, including iterating temperature-dependent thermal conductivity to achieve a self-consistent solution, scale linearly with the number of nodes and hardly affect the total solution time. Memory consumption, CPU time, and solutions of the new network calculation method compare favorably to a finite element analysis using ABAQUS.
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Bourduas, Stephan. "Modeling, evaluation, and implementation of ring-based interconnects for network-on-chip." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=19244.

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This thesis investigates the properties of a hierarchical ring architecture, which is composed of several unidirectional rings arranged to form a hierarchy. The proposed hierarchical ring topology exhibits several characteristics that make it well suited for on-chip use as a system-on-chip (SoC) interconnect. First, unidirectional rings reduce routing complexity thereby lowering buffer, area and energy requirements. Second, the simplicity of the routing logic results in low latencies and high clock rates. Finally, the hierarchical ring structure can be partitioned into multiple clock domains enabling the clock rates of individual rings to be tuned to save power while meeting design constraints. The hierarchical ring architecture has been evaluated using high-level behavioral models as well as a low-level register transfer-level (RTL) implementation. Furthermore, the hierarchical rings are combined with the popular two-dimensional mesh architecture to form several composite architectures in order to improve network performance. The mesh architecture exhibits increased latencies, hop-counts, and congestion with increasing network size. To combat these scalability issues, the hierarchical rings are used in the composite architectures to relieve congestion in the center of the mesh and to reduce hop-counts and latencies for long-distance communication, thereby achieving an overall improvement in performance. Simulation results show that the composite architectures decrease the latencies and hop-counts incurred by global traffic, thereby validating the claim that the use of hierarchical rings for global routing can in fact increase the scalability of the normal mesh network used for network-on-chip (NoC) implementations. Finally,
Cette thèse étudie les propriétés d'une interconnexion hiérarchique composée d'anneaux unidirectionnels. La topologie d'anneaux hiérarchique possède plusieurs caractéristiques souhaitables pour être utilisée comme interconnexion pour réseau-sur-puce (NoC). En premier lieu, la structure unidirectionnelle des anneaux sert à réduire la complexité de routage, ce qui implique une diminution de l'importance des mémoires tampon requises et économise l'énergie consommée par l'interconnexion. En second lieu, les faibles temps de latences et d'horloge système élevé résultent de la simplicité logique de chaque routeur. Finalement, la structure de l'interconnexion facilite une partition où chaque anneau appartient à son propre domaine contrôlé par une horloge individuelle, ce qui rend possible l'application de stratégies dynamiques permettant l'économie d'énergie. L'architecture proposée a été évaluée grâce à des simulations de modèles de hauts niveaux et par une implémentation logique résistance-transistor (RTL). De plus, les anneaux hiérarchiques sont combinés avec l'architecture de maille (« mesh ») bidimensionnelle pour former plusieurs architectures hybrides afin d'améliorer la performance du réseau. La topologie de maille démontre l'augmentation de latences, du nombre de sauts, et de la congestion avec l'agrandissement du réseau. Cependant, les architectures hybrides utilisent les anneaux hiérarchiques pour réduire la congestion au centre du réseau et diminuer le nombre de sauts et les temps de latences associés avec les communications à longue distance. Il en résulte donc une amélioration globale de la performance du système. Les résultats des simulations démontrent que les$
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Books on the topic "Electrical interconnect modeling"

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Package electrical modeling, thermal modeling, and processing for GaAs wireless applications. Boston: Kluwer Academic, 1999.

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Yazdani, Amirnaser. Voltage-sourced converters in power systems: Modeling, control, and applications. Hoboken, N.J: IEEE Press/John Wiley, 2010.

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Yazdani, Amirnaser. Voltage-sourced converters in power systems: Modeling, control, and applications. Hoboken, N.J: IEEE Press/John Wiley, 2010.

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1955-, Iravani Reza, ed. Voltage-sourced converters in power systems: Modeling, control, and applications. Hoboken, N.J: Wiley, 2010.

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Zhang, Xiao-Ping. Flexible AC Transmission Systems: Modelling and Control. 2nd ed. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012.

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Thomas, Basso, California Energy Commission. Public Interest Energy Research., Northern Power Systems Inc, Virginia Polytechnic Institute and State University., and National Renewable Energy Laboratory (U.S.), eds. Modeling and testing of unbalanced loading and voltage regulation: PIER final project report. [Sacramento, Calif.]: California Energy Commission, 2009.

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Thomas, Basso, California Energy Commission. Public Interest Energy Research., Northern Power Systems Inc, Virginia Polytechnic Institute and State University., and National Renewable Energy Laboratory (U.S.), eds. Modeling and testing of unbalanced loading and voltage regulation: PIER final project report. [Sacramento, Calif.]: California Energy Commission, 2009.

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Flexible AC Transmission Systems - Modelling and Control. London: Springer, 2012.

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Pal, Bikash, Xiao-Ping Zhang, and Christian Rehtanz. Flexible AC Transmission Systems: Modelling and Control (Power Systems). Springer, 2006.

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Pal, Bikash, Xiao-Ping Zhang, and Christian Rehtanz. Flexible AC Transmission Systems: Modelling and Control. Springer, 2010.

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Book chapters on the topic "Electrical interconnect modeling"

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Moiseev, Konstantin, Avinoam Kolodny, and Shmuel Wimer. "Scaling Dependent Electrical Modeling of Interconnects." In Multi-Net Optimization of VLSI Interconnect, 17–34. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4614-0821-5_3.

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Maffucci, Antonio, Sergey A. Maksimenko, Giovanni Miano, and Gregory Ya Slepyan. "Electrical Conductivity of Carbon Nanotubes: Modeling and Characterization." In Carbon Nanotubes for Interconnects, 101–28. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29746-0_4.

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Griese, Elmar, Detlef Krabe, and Engelbert Strake. "Electrical-Optical Printed Circuit Boards: Technology - Design - Modeling." In Interconnects in VLSI Design, 221–36. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4349-7_18.

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Yi, Guan, and Zhao Jiacong. "Reliability Modelling of a Typical Peripheral Component Interconnect (PCI) System with Dynamic Reliability Modelling Diagram." In Lecture Notes in Electrical Engineering, 1569–76. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3648-5_203.

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de Magistris, M., L. De Tommasi, A. Maffucci, and G. Miano. "On the Formulation and Lumped Equivalents Extraction Techniques for the Efficient Modeling of Long Interconnects." In Scientific Computing in Electrical Engineering, 81–86. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/978-3-540-32862-9_12.

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Qi, Xiaoning, Sherry Y. Shen, Ze-Kai Hsiau, Zhiping Yu, and Robert Dutton. "Layout-Based 3D Solid Modeling of IC Structures and Interconnects Including Electrical Parameter Extraction." In Simulation of Semiconductor Processes and Devices 1998, 61–64. Vienna: Springer Vienna, 1998. http://dx.doi.org/10.1007/978-3-7091-6827-1_18.

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Nakhla, Michel, and Ramachandra Achar. "Interconnect Modeling and Simulation." In Electrical Engineering Handbook. CRC Press, 1999. http://dx.doi.org/10.1201/9781420049671.ch17.

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Youssef, Nadir, Belahrach Hassan, Ghammaz Abdelilah, Naamane Aze-eddine, and Radouani Mohammed. "Electrical Transport Modeling of Graphene-Based Interconnects." In Carbon Nanotubes - Recent Advances, New Perspectives and Potential Applications [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.105456.

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Due to the downscaling in the design of modern ICs, copper interconnects reach their limitations such as delay, power dissipation, and electromigration. However, a new era of discovered materials, including carbon nanotube, graphene nanoribbon (GNR), and their composite, has been proposed as promising alternatives for interconnect applications. The purpose of this review is to give an overview of the various approaches that are used to model graphene-based interconnects. In this work we focus on why opting for graphene-based interconnect properties as an alternative for copper interconnect replacement; what are the deep theories, which are explaining the electrical transport on those interconnects; and what are the electrical models that are used to model the various kind of graphene-based interconnects.
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Liberty, Stanley R. "Modeling Interconnected Systems: A Functional Perspective." In The Electrical Engineering Handbook, 1079–84. Elsevier, 2005. http://dx.doi.org/10.1016/b978-012170960-0/50084-0.

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"Macromodeling of Complex Interconnects in 3D Integration." In Electrical Modeling and Design for 3D System Integration, 16–96. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2012. http://dx.doi.org/10.1002/9781118166727.ch2.

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Conference papers on the topic "Electrical interconnect modeling"

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Nosrati, Nooshin, Katayoon Basharkhah, Rezgar Sadeghi, and Zainalabedin Navabi. "An ESL Environment for Modeling Electrical Interconnect Faults." In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2019. http://dx.doi.org/10.1109/isvlsi.2019.00024.

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Vinson, J. E. "Aluminum Interconnect Response to Electrical Overstress." In ISTFA 1998. ASM International, 1998. http://dx.doi.org/10.31399/asm.cp.istfa1998p0203.

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Abstract The response of aluminum interconnect to electrical overstress (EOS) is an important component of semiconductor reliability. Proper modeling of the fusing characteristics are necessary to build more robust circuits without wasting die area and allow estimation of the events that cause failures. This paper reviews previous work on aluminum EOS and presents experimental evidence of the mechanisms involved in aluminum EOS. From this evidence a simplified model is proposed based on the physical characteristics of the structure.
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Chen, Xiaohe, James Drewniak, Jianmin Zhang, Michael Cracraft, Bruce Archambeault, and Samuel Connor. "Large Scale Signal and Interconnect FDTD Modeling for BGA Package." In 2006 IEEE Electrical Performane of Electronic Packaging. IEEE, 2006. http://dx.doi.org/10.1109/epep.2006.321160.

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Cadix, L., M. Rousseau, C. Fuchs, P. Leduc, A. Thuaire, R. El Farhane, H. Chaabouni, et al. "Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs." In 2010 IEEE International Interconnect Technology Conference - IITC. IEEE, 2010. http://dx.doi.org/10.1109/iitc.2010.5510728.

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Beyene, Wendemagegnehu. "Modeling and Analysis Techniques of Jitter Enhancement Across High-Speed Interconnect Systems." In 2007 IEEE Electrical Performance of Electronic Packaging. IEEE, 2007. http://dx.doi.org/10.1109/epep.2007.4387115.

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Barker, Donald B., Brent M. Mager, and Michael D. Osterman. "Analytic Characterization of Area Array Interconnect Shear Force Behavior." In ASME 2002 International Mechanical Engineering Congress and Exposition. ASMEDC, 2002. http://dx.doi.org/10.1115/imece2002-39494.

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Shear forces in the interconnects of electronic devices can cause electrical opens, which result in device failure. The shear forces are often caused by the thermal expansion (CTE) mismatch between a component and the printed wiring board (PWB). In this paper, an elastic strength of materials analytic model, which is demonstrated by Vandevelde [21], is used to characterize the interconnect shear force behavior in area array packages. The benefit of modeling the shear forces is that they can be related to the device life, a relationship obtained by converting shear to average stress, which can be converted to strain and used as input in a failure model equation. The most significant characterization that will be presented is that the maximum shear force behavior in the outermost interconnects can be characterized by three distinct regions of maximum shear force behavior.
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Chen, Wen Jie, and Mei Song Tong. "Electromagnetic modeling for lossy interconnect structures based on hybrid surface integral equations." In 2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS). IEEE, 2016. http://dx.doi.org/10.1109/edaps.2016.7893154.

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Bekmambetova, Fadime, Xinyue Zhang, and Piero Triverio. "A passivity approach to FDTD stability with application to interconnect modeling." In 2016 IEEE 25th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS). IEEE, 2016. http://dx.doi.org/10.1109/epeps.2016.7835451.

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Naik, Bhattu HariPrasad, Md Misbahuddin, and Chandra Sekhar Paidimarry. "S-Parameter Modeling and Analysis of RGLC Interconnect for Signal Integrity." In 2017 International Conference on Recent Trends in Electrical, Electronics and Computing Technologies (ICRTEECT). IEEE, 2017. http://dx.doi.org/10.1109/icrteect.2017.41.

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Bosman, Dries, Martijn Huynen, Daniel De Zutter, Xiao Sun, Nicolas Pantano, Geert Van der Plas, Eric Beyne, and Dries Vande Ginste. "Interconnect Modeling using a Surface Admittance Operator Derived with the Fokas Method." In 2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS). IEEE, 2022. http://dx.doi.org/10.1109/epeps53828.2022.9947108.

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