Dissertations / Theses on the topic 'Electrical circuits and systems'
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1
Smith, Nathan. "Substrate integrated waveguide circuits and systems." Thesis, McGill University, 2010. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=92388.
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This thesis investigates substrate integrated waveguide (SIW) based interconnects, components, and systems. SIWs are high performance broadband interconnects with excellent immunity to electromagnetic interference and suitable for use in microwave and millimetre-wave electronics, as well as wideband systems. They are very low-cost in comparison to the classic milled metallic waveguides as they may be developed using inexpensive printed circuit board (PCB) fabrication techniques. In this thesis, the interconnect design is studied by investigating the modes supported by SIW using fullwave simulations. Also, SIW transitions, as well as miniaturization methods to decrease the waveguide footprint are evaluated. Next, a miniaturized Wilkinson SIW power divider is developed exhibiting excellent isolation of up to 40dB between its output ports. Another SIW component investigated in this thesis is an SIW cavity resonator. A circular SIW cavity resonator fed by a microstrip line and via probe through an opening on the top cavity wall is designed. The aperture on the top wall creates a radiating folded slot and measurements show a gain of 7.76dB for this cavity-backed antenna at 16.79GHz. The antenna exhibits a bandwidth of 250MHz (return loss > 10dB). With this resonator, a microwave oscillator is designed to produce a 10dBm tone. Measurements of the fabricated oscillator demonstrate a low phase noise of -82dBc/Hz. Finally, a new SIW component, i.e. tapered SIW reflector, is designed to counteract the dispersive behavior of an SIW interconnect near cutoff. Two dispersion equalization systems are implemented using either a circulator or a coupler to route the compensated reflected signal. The systems are tested when a 1Gbps pseudo-random binary signal is up-converted to 10.7GHz and launched into the SIW interconnect. Observation of the compensated output eye-diagrams reveals achievement of a lower distortion in the highly dispersive band just above the cutoff frequency.Cette thèse examine des interconnexions, des composantes et des systèmes basés sur des guides d'ondes intégrés au substrat (GIS). Les GIS sont des interconnexions de haute performance à large bande qui possèdent d'excellentes caractéristiques d'immunité contre les interférences électromagnétiques et qu'on pourrait utiliser dans des systèmes microondes et des circuits d'ondes millimétriques. Le coût des GIS est très faible comparativement à celui des guides d'ondes métalliques communs, car leur fabrication utilise des techniques peu coûteuses de production de cartes de circuits imprimés. Cette thèse étudie, au moyen de simulations à onde entière, le design de l'interconnexion et les modes supportés par le GIS. De plus, la thèse évalue les transitions des GIS ainsi que les méthodes de miniaturisation visant à diminuer l'empreinte du guide d'onde. Ensuite, la thèse expose le développement d'un répartiteur de puissance GIS Wilkinson qui possède d'excellentes propriétés isolantes allant jusqu'à 40dB entre les bornes de sortie. La thèse examine aussi une autre composante GIS: un résonateur à cavité GIS. La thèse décrit la conception d'un résonateur à cavité GIS qui est alimenté par une ligne microbande et une sonde passées par une aperture sur le mur supérieur de la cavité. L'aperture dans le mur supérieur crée une encoche plissée rayonnante, et des mesures ont révélé un gain de 7,76dB pour l'antenne adossée d'une cavité de 16,79 GHz. L'antenne possède une bande passante de 250MHz (perte de réflexion > 10dB). En plus de ce résonateur, un oscillateur micro-onde est conçu pour produire une tonalité de 10dBm. Les mesures de l'oscillateur fabriqué montrent un faible bruit de phase de -82dBc/Hz. Enfin, une nouvelle composante de GIS (un réflecteur effilé) est conçue pour compenser la caractéristique dispersive d'une interconnexion GIS près de la fréquence de coupure. Deux systèmes de correction de la disp
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Tassoudji, Mohammad Ali. "Electromagnetic interference in electronic circuits and systems." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/35392.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 191-198).
by Mohammad Ali Tassoudji.
Ph.D.
3
Tavakoli, Dastjerdi Maziar 1976. "Analog VLSI circuits for inertial sensory systems." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86766.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references (leaves 67-68).
by Maziar Tavakoli Dastjerdi.
S.M.
4
Macqueen, Christopher Neil. "Time based load-flow analysis and loss costing in electrical distribution systems." Thesis, Durham University, 1994. http://etheses.dur.ac.uk/1700/.
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El-Damak, Dina Reda. "Power management circuits for ultra-low power systems." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99821.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 137-145).
Power management circuits perform a wide range of vital tasks for electronic systems including DC-DC conversion, energy harvesting, battery charging and protection as well as dynamic voltage scaling. The impact of the efficiency of the power management circuits is highly profound for ultra-low power systems such as implantable, ingestible or wearable devices. Typically the size of the system for such applications does not allow the integration of a large energy storage device. Therefore, extreme energy efficiency of the power management circuits is critical for extended operation time. In addition, flexibility and small form factor are desirable to conform to the human body and reduce the system's over all size. Thus, this thesis presents highly efficient and miniature power converters for multiple applications using architecture and circuit level optimization as well as emerging technologies. The first part presents a power management IC (PMIC) featuring an integrated reconfigurable switched capacitor DC-DC converter using on-chip ferroelectric caps in 130 nm CMOS process. Digital pulse frequency modulation and gain selection circuits allow for efficient output voltage regulation. The converter utilizes four gain settings (1, 2/3, 1/2, 1/3) to support an output voltage of 0.4 V to 1.1 V from 1.5 V input while delivering load current of 20 [mu]A to 1 mA. The PMIC occupies 0.366 mm² and achieves a peak efficiency of 93% including the control circuit overhead at a load current of 500 [mu]A. The second part presents a solar energy harvesting system with 3.2 nW overall quiescent power. The chip integrates self-startup, battery management, supplies 1 V regulated rail with a single inductor and supports power range of 10 nW to 1 [mu]W. The control circuit is designed in an asynchronous fashion that scales the effective switching frequency of the converter with the level of the power transferred. The ontime of the converter switches adapts dynamically to the input and output voltages for peak-current control and zero-current switching. The system has been implemented in 180 nm CMOS process. For input power of 500 nW, the proposed system achieves an efficiency of 82%, including the control circuit overhead, while charging a battery at 3 V from 0.5 V input. The third part focuses on developing an energy harvesting system for an ingestible device using gastric acid. An integrated switched capacitor DC-DC converter is designed to efficiently power sensors and RF transmitter with a 2.5 V regulated voltage rail. A reconfigurable Dickson topology with four gain settings (3, 4, 6, 10) is used to support a wide input voltage range from 0.3 V to 1.1 V. The converter is designed in 65 nm CMOS process and achieves a peak efficiency of 80% in simulation for output power of 2 [mu]W. The last part focuses on flexible circuit design using Molybdenum Disulfide (MoS₂), one of the emerging 2D materials. A computer-aided design flow is developed for MoS₂-based circuits supporting device modeling, circuit simulation and parametric cell-based layout - which paves the road for the realization of large-scale flexible MoS₂ systems.
by Dina Reda El-Damak.
Ph. D.
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Mandal, Soumyajit 1979. "Far field RF power extraction circuits and systems." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/28551.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 195-199).
In this thesis, I describe efficient methods for extracting DC power from electromagnetic radiation. This will become an important necessity for a number of applications involving remotely powered devices, such as Radio Frequency Identification (RFID) tags and bionic implants. I first investigate the problem abstractly, allowing theoretical bounds on system performance to be derived. Next I devise circuit, antenna and impedance matching network design strategies to efficiently approach these theoretical bounds. Finally, I use these strategies to create an experimental power extraction system that collects RF power at low electromagnetic field strengths. This system enables a substantial increase in the operating range of remotely powered devices.
by Soumyajit Mandal.
S.M.
7
Zhang, Zheng Ph D. Massachusetts Institute of Technology. "Uncertainty quantification for integrated circuits and microelectrornechanical systems." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99855.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 155-168).
Uncertainty quantification has become an important task and an emerging topic in many engineering fields. Uncertainties can be caused by many factors, including inaccurate component models, the stochastic nature of some design parameters, external environmental fluctuations (e.g., temperature variation), measurement noise, and so forth. In order to enable robust engineering design and optimal decision making, efficient stochastic solvers are highly desired to quantify the effects of uncertainties on the performance of complex engineering designs. Process variations have become increasingly important in the semiconductor industry due to the shrinking of micro- and nano-scale devices. Such uncertainties have led to remarkable performance variations at both circuit and system levels, and they cannot be ignored any more in the design of nano-scale integrated circuits and microelectromechanical systems (MEMS). In order to simulate the resulting stochastic behaviors, Monte Carlo techniques have been employed in SPICE-like simulators for decades, and they still remain the mainstream techniques in this community. Despite of their ease of implementation, Monte Carlo simulators are often too time-consuming due to the huge number of repeated simulations. This thesis reports the development of several stochastic spectral methods to accelerate the uncertainty quantification of integrated circuits and MEMS. Stochastic spectral methods have emerged as a promising alternative to Monte Carlo in many engineering applications, but their performance may degrade significantly as the parameter dimensionality increases. In this work, we develop several efficient stochastic simulation algorithms for various integrated circuits and MEMS designs, including problems with both low-dimensional and high-dimensional random parameters, as well as complex systems with hierarchical design structures. The first part of this thesis reports a novel stochastic-testing circuit/MEMS simulator as well as its advanced simulation engine for radio-frequency (RF) circuits. The proposed stochastic testing can be regarded as a hybrid variant of stochastic Galerkin and stochastic collocation: it is an intrusive simulator with decoupled computation and adaptive time stepping inside the solver. As a result, our simulator gains remarkable speedup over standard stochastic spectral methods and Monte Carlo in the DC, transient and AC simulation of various analog, digital and RF integrated circuits. An advanced uncertainty quantification algorithm for the periodic steady states (or limit cycles) of analog/RF circuits is further developed by combining stochastic testing and shooting Newton. Our simulator is verified by various integrated circuits, showing 10² x to 10³ x speedup over Monte Carlo when a similar level of accuracy is required. The second part of this thesis presents two approaches for hierarchical uncertainty quantification. In hierarchical uncertainty quantification, we propose to employ stochastic spectral methods at different design hierarchies to simulate efficiently complex systems. The key idea is to ignore the multiple random parameters inside each subsystem and to treat each subsystem as a single random parameter. The main difficulty is to recompute the basis functions and quadrature rules that are required for the high-level uncertainty quantification, since the density function of an obtained low-level surrogate model is generally unknown. In order to address this issue, the first proposed algorithm computes new basis functions and quadrature points in the low-level (and typically high-dimensional) parameter space. This approach is very accurate; however it may suffer from the curse of dimensionality. In order to handle high-dimensional problems, a sparse stochastic testing simulator based on analysis of variance (ANOVA) is developed to accelerate the low-level simulation. At the high-level, a fast algorithm based on tensor decompositions is proposed to compute the basis functions and Gauss quadrature points. Our algorithm is verified by some MEMS/IC co-design examples with both low-dimensional and high-dimensional (up to 184) random parameters, showing about 102 x speedup over the state-of-the-art techniques. The second proposed hierarchical uncertainty quantification technique instead constructs a density function for each subsystem by some monotonic interpolation schemes. This approach is capable of handling general low-level possibly non-smooth surrogate models, and it allows computing new basis functions and quadrature points in an analytical way. The computational techniques developed in this thesis are based on stochastic differential algebraic equations, but the results can also be applied to many other engineering problems (e.g., silicon photonics, heat transfer problems, fluid dynamics, electromagnetics and power systems). There exist lots of research opportunities in this direction. Important open problems include how to solve high-dimensional problems (by both deterministic and randomized algorithms), how to deal with discontinuous response surfaces, how to handle correlated non-Gaussian random variables, how to couple noise and random parameters in uncertainty quantification, how to deal with correlated and time-dependent subsystems in hierarchical uncertainty quantification, and so forth.
by Zheng Zhang.
Ph. D.
8
Groom, C. G. "Fuzzy logic and its application to dynamic security assessment of electrical power systems." Thesis, University of Bath, 1994. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239955.
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Arfin, Scott K. (Scott Kenneth). "Low power circuits and systems for wireless neural stimulation." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/65999.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 155-161).
Electrical stimulation of tissues is an increasingly valuable tool for treating a variety of disorders, with applications including cardiac pacemakers, cochlear implants, visual prostheses, deep brain stimulators, spinal cord stimulators, and muscle stimulators. Brain implants for paralysis treatments are increasingly providing sensory feedback via neural stimulation. Within the field of neuroscience, the perturbation of neuronal circuits wirelessly in untethered, freely-behaving animals is of particular importance. In implantable systems, power consumption is often the limiting factor in determining battery or power coil size, cost, and level of tissue heating, with stimulation circuitry typically dominating the power budget of the entire implant. Thus, there is strong motivation to improve the energy efficiency of implantable electrical stimulators. In this thesis, I present two examples of low-power tissue stimulators. The first type is a wireless, low-power neural stimulation system for use in freely behaving animals. The system consists of an external transmitter and a miniature, implantable wireless receiver-and-stimulator utilizing a custom integrated chip built in a standard 0.5 ptm CMOS process. Low power design permits 12 days of continuous experimentation from a 5 mAh battery, extended by an automatic sleep mode that reduces standby power consumption by 2.5x. To test this device, bipolar stimulating electrodes were implanted into the songbird motor nucleus HVC of zebra finches. Single-neuron recordings revealed that wireless stimulation of HVC led to a strong increase of spiking activity in its downstream target, the robust nucleus of the arcopallium (RA). When this device was used to deliver biphasic pulses of current randomly during singing, singing activity was prematurely terminated in all birds tested. The second stimulator I present is a novel, energy-efficient electrode stimulator with feedback current regulation. This stimulator uses inductive storage and recycling of energy based on a dynamic power supply to drive an electrode in an adiabatic fashion such that energy consumption is minimized. Since there are no explicit current sources or current limiters, wasteful energy dissipation across such elements is naturally avoided. The stimulator also utilizes a shunt current-sensor to monitor and regulate the current through the electrode via feedback, thus enabling flexible and safe stimulation. The dynamic power supply allows efficient transfer of energy both to and from the electrode, and is based on a DC-DC converter topology that is used in a bidirectional fashion. In an exemplary electrode implementation, I show how the stimulator combines the efficiency of voltage control and the safety and accuracy of current control in a single low-power integrated-circuit built in a standard 0.35 pm CMOS process. I also perform a theoretical analysis of the energy efficiency that is in accord with experimental measurements. In its current proof-of-concept implementation, this stimulator achieves a 2x-3x reduction in energy consumption as compared to a conventional current-source-based stimulator operating from a fixed power supply.
by Scott Kenneth Arfin.
Ph.D.
10
Paidimarri, Arun. "Circuits and protocols for low duty cycle wireless systems." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/103674.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 191-200).
IoT devices are helping improve efficiency and expanding capabilities in an increasing number of applications including industrial, home and personal fitness. Device lifetimes are still a concern, and improved energy efficiency is needed. Additionally, aggressive duty cycling is needed to operate these IoT devices in severely energy-constrained applications. Wireless communication, which consumes a large fraction of the power in these devices, is the primary focus of this thesis. We present circuit (active RF, leakage management and timing) and protocol (medium access and coding) techniques for total power minimization in low duty cycle systems. First, we present a Bluetooth Low Energy (BLE) transmitter optimized for low duty cycles. It maintains a high efficiency >40% while delivering +10dBm. At the same time, aggressive power gating brings the leakage down to <400pW, giving an on/off power ratio of 7.6 x 10⁷. Second, we look at protocols for low duty cycle wireless communication. The tradeoffs between network capacity and sensor node power consumption are considered and a fully asynchronous protocol is proposed. Additionally, we look at two coding techniques, Digital Network Coding (DNC) and Spinal coding, to enhance the intrinsic range of communication. Finally, for systems requiring accurate clocks, the standard is to use crystal oscillators. However, in order to reduce cost and board area, we propose a fully-integrated RC oscillator architecture that achieves high stability while maintaining low power. Overall, the techniques explored in this thesis aim to expand operation of IoT devices to ever more energy constrained situations and with increased lifetimes.
by Arun Paidimarri.
Ph. D.
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Reis, Timo [Verfasser]. "Systems Theoretic Aspects of PDAEs and Applications to Electrical Circuits / Timo Reis." Aachen : Shaker, 2006. http://d-nb.info/1170535453/34.
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Thompson, Jeffrey Craig. "An expert system for protection system design of interconnected electrical distribution circuits." Diss., This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-06062008-170345/.
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Jin, Rui M. Eng Massachusetts Institute of Technology. "Circuits and systems for efficient portable-to-portable wireless charging." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91694.
Full textAbstract:
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 121-125).
In today's world of ever-increasing low-power portable electronics, from implants to wireless accessories, powering these devices efficiently and conveniently is an escalating issue. The proposed solution is to wirelessly recharge these lower-power portable devices through a common magnetic link with a higher-power portable device, such as a smartphone. Such a method is convenient for users, environmentally friendly, and cheap to implement. This portable-to-portable wireless charging application differs from conventional charging pad-based systems in that the transmitter is energy constrained, so system efficiency is key. Also, since both the transmitter and receiver are portable, loading on the transmitter changes dynamically, which affects efficiency and delivered power. This thesis addresses these challenges through the design of an efficient and robust wireless charging system. The first half of the thesis presents a transmitter power amplifier control loop for increasing efficiency and balancing power across changing loading conditions. Mathematical analysis of the resonant inductive wireless power circuit shows the impact of changing conditions on power amplifier zero-voltage switching, and its effect on efficiency and power. The control loop adjusts the power amplifier shunt capacitance and series inductance to maintain zero-voltage switching while regulating delivered power. The second half of the thesis presents the implementation of a resonant inductive wireless charging system operating at 6.78 MHz that transfers energy between portable devices with high efficiency. A custom integrated circuit designed in 0.18 [mu]m HVCMOS implements the derived control loop by sensing for power amplifier zero-voltage switching and adjusting the power amplifier components. An end-to-end efficiency of 78% is achieved when delivering 200 mW over a 7 mm distance. Efficiencies over 70% are maintained over 4-12 mm distances. A diverse set of applications are demonstrated that use a smartphone to wirelessly recharge a fitness tracker, a cochlear implant, an MP3 player, a calculator, a toy light, a wireless keyboard, and a bicycle light, charging most devices in 2 minutes for a typical day's use.
by Rui Jin.
M. Eng.
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Park, Min Ph D. Massachusetts Institute of Technology. "Time-based circuits for communication systems in advanced CMOS technology." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/54229.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student submitted PDF version of thesis.
Includes bibliographical references (p. 145-151).
As device size scales down, there have been challenges to design conventional analog circuits, such as low voltage headroom and the low intrinsic gain of a device. Although ever-decreasing device channel length in CMOS technology has mainly negative effects on analog circuits, it increases device speed and reduces the power consumption of digital circuits. As a result, time-based signal processing has been attracting attention because time-based circuits take advantage of high speed and low power devices to deal with analog information in the time domain. In this thesis, we focus on a ring oscillator as a core time-based circuit for communication systems. Ring oscillators are employed in analog-to-time conversion or time-to-digital conversion. In this work, we present A/D converters and an RF modulator based on ring oscillators in deep sub-micron CMOS processes. We introduce a VCO-based [sigma][delta] A/D converter utilizing a voltage-controlled ring oscillator (ring VCO) as a continuous-time integrator. We propose to replace conventional integrators designed with analog circuits in a [sigma][delta] modulator with a ring VCO and a phase detector, thereby implementing an A/D converter without traditional analog circuits. We also propose a single-slope A/D converter using time-to-digital conversion. By combining a few analog circuits and a ring oscillator based Time-to-Digital Converter (TDC), we achieve highly digital A/D conversion. Finally, we demonstrate a VCO-based RF modulator. The proposed RF modulator generates an RF signal by simply switching transistors. As opposed to an RFDAC approach, the proposed RF modulator is not limited by quantization noise because it employs multiphase PWM signals. A VCO-based OP amp is also introduced as an alternative method of designing an OP amp in deep sub-micron CMOS. The proposed VCO-based OP amp is utilized to generate the multiphase PWM signals in the RF modulator. This thesis also presents the fundamental limitations of a ring oscillator as a timebased circuit. Although the idea of time-based signal processing employing a ring oscillator has its own limitations such as non-linear tuning characteristics and phase noise, the basic idea is worth investigating to solve the serious problems of analog circuits for future CMOS technology.
by Min Park.
Ph.D.
15
Ghosh, Suvradip. "Energy and data conversion circuits for low power sensory systems." Thesis, University of Missouri - Kansas City, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3610195.
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This dissertation focuses on the problem of increasing the lifetime of wireless sensors. This problem is addressed from two different angles: energy harvesting and data compression. Energy harvesting enables a sensor to extract energy from its environment and use it to power itself or recharge its batteries. Data compression, on the other hand, allows a sensor to save energy by reducing the radio transmission bandwidth.
This dissertation proposes a fractal-based photodiode fabricated on standard CMOS process as an energy harvesting device with increased efficiency. Experiments show that, the fractal based photodiodes are 6% more efficient compared to the conventional square shaped photodiode. The fractal shape photodiode has more perimeter-to-area ratio which increases the lateral response, improving its efficiency.
With increased efficiency, more current is generated but the open-circuit voltage still remains low (0.3V–0.45V depending on illumination condition). These voltages have to be boosted up to higher values if they are going to be used to power up any sensory circuit or recharge a battery. We propose a switched-inductor DC-DC converter to boost the low voltage of the photodiodes to higher voltages. The proposed circuit uses two on-chip switches and two off-chip Components: an inductor and a capacitor. Experiments show a voltage up to 2.81V can be generated from a single photodiode of 1mm2 area. The voltage booster circuit achieved a conversion efficiency of 59%.
Data compression was also explored in an effort to reduce energy consumption during radio transmission. An analog-to-digital converter (ADC), which can jointly perform the tasks of digital conversion and entropy encoding, has also been proposed in this dissertation. The joint data conversion/compression help savings in area and power resources, making it suitable for on-sensor compression. The proposed converter combines a cyclic converter architecture and Golomb-Rice entropy encoder. The converter hardware design is based on current-mode circuits and it was fabricated on a 0.5 μm CMOS process and tested. Experiment results show a lossless compression ratio of 1.52 and a near-lossless compression of 5.2 can be achieved for 32 × 32 pixel image.
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Drego, Nigel Anthony 1980. "Characterization and mitigation of process variation in digital circuits and systems." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/53271.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 155-166).
Process variation threatens to negate a whole generation of scaling in advanced process technologies due to performance and power spreads of greater than 30-50%. Mitigating this impact requires a thorough understanding of the variation sources, magnitudes and spatial components at the device, circuit and architectural levels. This thesis explores the impacts of variation at each of these levels and evaluates techniques to alleviate them in the context of digital circuits and systems. At the device level, we propose isolation and measurement of variation in the intrinsic threshold voltage of a MOSFET using sub-threshold leakage currents. Analysis of the measured data, from a test-chip implemented on a 0. 18[mu]m CMOS process, indicates that variation in MOSFET threshold voltage is a truly random process dependent only on device dimensions. Further decomposition of the observed variation reveals no systematic within-die variation components nor any spatial correlation. A second test-chip capable of characterizing spatial variation in digital circuits is developed and implemented in a 90nm triple-well CMOS process. Measured variation results show that the within-die component of variation is small at high voltages but is an increasing fraction of the total variation as power-supply voltage decreases. Once again, the data shows no evidence of within-die spatial correlation and only weak systematic components. Evaluation of adaptive body-biasing and voltage scaling as variation mitigation techniques proves voltage scaling is more effective in performance modification with reduced impact to idle power compared to body-biasing.
(cont.) Finally, the addition of power-supply voltages in a massively parallel multicore processor is explored to reduce the energy required to cope with process variation. An analytic optimization framework is developed and analyzed; using a custom simulation methodology, total energy of a hypothetical 1K-core processor based on the RAW core is reduced by 6-16% with the addition of only a single voltage. Analysis of yield versus required energy demonstrates that a combination of disabling poor-performing cores and additional power-supply voltages results in an optimal trade-off between performance and energy.
by Nigel Anthony Drego.
Ph.D.
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Bohorquez, Jose L. "Digitally-assisted, ultra-low power circuits and systems for medical applications." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/58074.
Full textAbstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 219-225).
In recent years, trends in the medical industry have created a growing demand for a variety of implantable medical devices. At the same time, advances in integrated circuits techniques, particularly in CMOS, have opened possibilities for advanced implantable systems that are very small and consume minimal energy. Minimizing the volume of medical implants is important as it allows for less invasive procedures and greater comfort to patients. Minimizing energy consumption is imperative as batteries must last at least a decade without replacement. Two primary functions that consume energy in medical implants are sensor interfaces that collect information from biomedical signals, and radios that allow the implant to communicate with a base-station outside of the body. The general focus of this work was the development of circuits and systems that minimize the size and energy required to carry out these two functions. The first part of this work focuses on laying down the theoretical framework for an ultra-low power radio, including advances to the literature in the area of super-regeneration. The second part includes the design of a transceiver optimized for medical implants, and its implementation in a CMOS process. The final part describes the design of a sensor interface that leverages novel analog and digital techniques to reduce the system's size and improve its functionality. This final part was developed in conjunction with Marcus Yip.
by Jose L. Bohorquez.
Ph.D.
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Alhajj, Tarek. "TCSIM: a top-down approach to mixed-signal circuits and systems design." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=19236.
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Design methodologies have evolved over the years, especially due to shrinking transistors in CMOS technology. This has encouraged the use of behavioural modelling in Matlab and Simulink over other less accurate or time consuming options for design and simulation, hence the development of TCSIM (Top-down Circuit Simulation In Matlab). The following components are modelled for this initial prototype: the output voltage limitation of operational amplifiers (opamps), the current limitation and parasitic capacitances of operational transconductance amplifiers (OTAs), the finite and nonlinear variation of on resistance in switches, and the nonideal behaviour of switched capacitor (SC) integrators. This is complemented by an analysis of the noise in these circuits. The models are verified with Cadence simulations and are shown to be both accurate and easy to map to the circuit level. It is also possible to optimize complete systems to efficiently meet specifications. The top-down methodology is demonstrated with the design of a delta-sigma analog-to-digital converter (ADC) to be both accurate and simple with TCSIM.Les methodologies de conception ont evolue au fil des annees, notamment en raison de la diminution de la taille des transistors dans la technologie CMOS. Ceci a favorise l'utilisation de la modelisation comportementale a l'aide de Matlab et Simulink, en remplacement des anciennes techniques qui etaient moins precises et demandaient plus de temps, ce qui a mene au developpement de TCSIM (Topdown Circuit Simulation In Matlab). Dans le cadre de ce prototype initial, les composantes suivantes ont ete modelisees: la limitation du voltage de sortie des amplificateurs operationnels (opamps), la limitation du courant et de la capacitance parasitique des amplificateurs-transconductance operationnels (OTAs), les variations finies et non-lineaire de la resistance des interrupteurs et le comportement non-ideal des integrateurs a condensateur commute. A ces modelisations s'ajoute une analyse du bruit dans ces circuits. Les modeles ont ete valides a l'aide de simulations dans Cadence. Ces simulations demontrent la precision des modeles mais aussi la facilite avec laquelle ils peuvent etre transposes au niveau circuit. Les modeles permettent l'optimisation de systemes complets en vue d'atteindre les specifications. La methodologie "top-down" est illustree a l'aide du design d'un convertisseur analogue-a-digital (ADC) delta-sigma. Le travail demontre la facilite avec laquelle ce design peut etre effectue grace a TCSIM.
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Yakopcic, Chris. "Memristor Device Modeling and Circuit Design for Read Out Integrated Circuits, Memory Architectures, and Neuromorphic Systems." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1398725462.
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Yip, Marcus. "Ultra-low-power circuits and systems for wearable and implantable medical devices." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84902.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 219-231).
Advances in circuits, sensors, and energy storage elements have opened up many new possibilities in the health industry. In the area of wearable devices, the miniaturization of electronics has spurred the rapid development of wearable vital signs, activity, and fitness monitors. Maximizing the time between battery recharge places stringent requirements on power consumption by the device. For implantable devices, the situation is exacerbated by the fact that energy storage capacity is limited by volume constraints, and frequent battery replacement via surgery is undesirable. In this case, the design of energy-efficient circuits and systems becomes even more crucial. This thesis explores the design of energy-efficient circuits and systems for two medical applications. The first half of the thesis focuses on the design and implementation of an ultra-low-power, mixed-signal front-end for a wearable ECG monitor in a 0.18pm CMOS process. A mixed-signal architecture together with analog circuit optimizations enable ultra-low-voltage operation at 0.6V which provides power savings through voltage scaling, and ensures compatibility with state-of-the-art DSPs. The fully-integrated front-end consumes just 2.9[mu]W, which is two orders of magnitude lower than commercially available parts. The second half of this thesis focuses on ultra-low-power system design and energy-efficient neural stimulation for a proof-of-concept fully-implantable cochlear implant. First, implantable acoustic sensing is demonstrated by sensing the motion of a human cadaveric middle ear with a piezoelectric sensor. Second, alternate energy-efficient electrical stimulation waveforms are investigated to reduce neural stimulation power when compared to the conventional rectangular waveform. The energy-optimal waveform is analyzed using a computational nerve fiber model, and validated with in-vivo ECAP recordings in the auditory nerve of two cats and with psychophysical tests in two human cochlear implant users. Preliminary human subject testing shows that charge and energy savings of 20-30% and 15-35% respectively are possible with alternative waveforms. A system-on-chip comprising the sensor interface, reconfigurable sound processor, and arbitrary-waveform neural stimulator is implemented in a 0.18[mu]m high-voltage CMOS process to demonstrate the feasibility of this system. The sensor interface and sound processor consume just 12[mu]W of power, representing just 2% of the overall system power which is dominated by stimulation. As a result, the energy savings from using alternative stimulation waveforms transfer directly to the system.
by Marcus Yip.
Ph.D.
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Garcha, Preetinder(Preetinder Kaur). "Low power circuits with integrated magnetics for sensors and energy harvesting systems." Thesis, Massachusetts Institute of Technology, 2020. https://hdl.handle.net/1721.1/127019.
Full textAbstract:
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, May, 2020Cataloged from the official PDF of thesis.
Includes bibliographical references (pages 145-151).
The continued expansion of Internet of Things has led to a proliferation of wireless sensors and systems across the globe. The application space for sensors is wide-ranging: from industries, to serve the upcoming era of Industry 4.0, to consumer products, like body wearable sensors. The rise to billions of sensors relies on two key trends in sensor systems: miniaturization and energy-efficiency. This work explores the use of integrated magnetics in microelectronics to enable low power, energy-efficient sensing, as well as energy harvesting to power the sensors, in a compact form factor. For industrial applications, we present the design of a bandwidth-scalable, integrated fluxgate magnetic-to-digital converter for energy-efficient contactless current sensing in smart connectors. The system uses mixed signal front-end design to en-able duty cycling and quick convergence techniques leading to 20x reduction in power consumption at low bandwidths of 1 kHz for power monitoring. It also employs fast read-out circuits to achieve a bandwidth of 125 kHz for machine health diagnosis. For personal body wearable electronics and beyond, we present the design of a cold start system with integrated magnetics for ultra low voltage startup in thermal energy harvesting applications. The Meissner Oscillator analysis with on-chip magnetics allows co-optimization of magnetics and circuits to achieve start up from as low as 25 mV input voltage to the circuits, despite 1000x lower inductance than off-chip transformers. Given the recent push towards artificial intelligence and a growing need for data, along with sensors to collect that data, we need to explore novel uses of technologies to meet the demands for small form factor and low power operation, as the number of sensors scale. The ideas presented in this thesis, with two very different applications of the integrated magnetics technology, can contribute to the continued growth towards trillions of sensors.
by Preetinder Garcha.
Ph. D.
Ph.D. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
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Karami, Armine. "Study of electrical interfaces for electrostatic vibration energy harvesting." Thesis, Sorbonne université, 2018. http://www.theses.fr/2018SORUS134/document.
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Les récupérateurs d'énergie vibratoire électrostatiques (REV) sont des systèmes convertissant une partie de l'énergie cinétique de leur environnement en énergie électrique, afin d'alimenter de petits systèmes électroniques. Les REV inertiels sont constituées d'un sous-système mécanique bâti autour d'une masse mobile, ainsi que d'une interface électrique. Ces deux blocs sont couplés par un transducteur électrostatique. Cette thèse étudie l'amélioration des performances des REV par la conception optimisée de leur interface électrique. La première partie de cette thèse étudie une famille d'interfaces électriques appelées pompes de charge (PC). On commence par la construction d'une théorie formelle des PC. Des interfaces rapportées dans la littérature sont identifiées comme membres de cette famille. Cette dernière est ensuite complétée par une nouvelle topologie de PC. Une comparaison des différents PC est alors faite dans le domaine électrique, puis un outil semi-analytique est présenté pour la comparaison des PC en prenant en compte le couplage électromécanique. L'étude des PC se termine par la présentation d'une nouvelle méthode de mesure du potentiel d'électret des REV. La deuxième partie de la thèse présente une approche de conception radicalement différente de ce qui est présenté dans les travaux actuels sur les REV. Elle préconise une synthèse active de la dynamique de la masse des REV à travers leur interface électrique. Nous montrons d'abord que cela permet la conversion d'énergie en quantités proches des limites physiques, et ce à partir de vibrations d'entrée de forme arbitraire. Enfin, une architecture pour un tel REV est proposée et testée en simulationElectrostatic vibration energy harvesters (e-VEHs) are systems that convert part of their surroundings' kinetic energy into electrical energy, in order to supply small-scale electronic systems. Inertial E-VEHs are comprised of a mechanical subsystem that revolves around a mobile mass, and of an electrical interface. The mechanical and electrical parts are coupled by an electrostatic transducer. This thesis is focused on improving the performances of e-VEHs by the design of their electrical interface. The first part of this thesis consists in the study of a family of electrical interfaces called charge-pumps conditioning circuits (CPCC). It starts by building a formal theory of CPCCs. State-of-the-art reported conditioning circuits are shown to belong to this family. This family is then completed by a new CPCC topology. An electrical domain comparison of different CPCCs is then reported. Next, a semi-analytical tool allowing for the comparison of CPCC-based e-VEHs accounting for electromechanical effects is reported. The first part of the thesis ends by presenting a novel method for the measurement of e-VEHs' built-in electret potential. The second part of the thesis presents a radically different design approach than what is followed in most of state-of-the-art works on e-VEHs. It advocates for e-VEHs that actively synthesize the dynamics of their mobile mass through their electrical interface. We first show that this enables to convert energy in amounts approaching the physical limits, and from arbitrary types of input vibrations. Then, a complete architecture such an e-VEH is proposed and tested in simulations submitted to human body vibrations
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Raina, Priyanka. "Energy-efficient circuits and systems for computational imaging and vision on mobile devices." Thesis, Massachusetts Institute of Technology, 2018. http://hdl.handle.net/1721.1/115787.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 125-127).
Eighty five percent of images today are taken by cell phones. These images are not merely projections of light from the scene onto the camera sensor but result from a deep calculation. This calculation involves a number of computational imaging algorithms such as high dynamic range (HDR) imaging, panorama stitching, image deblurring and low-light imaging that compensate for camera limitations, and a number of deep learning based vision algorithms such as face recognition, object recognition and scene understanding that make inference on these images for a variety of emerging applications. However, because of their high computational complexity, mobile CPU or GPU based implementations of these algorithms do not achieve real-time performance. Moreover, offloading these algorithms to the cloud is not a viable solution because wirelessly transmitting large amounts of image data results in long latency and high energy consumption, making them unsuitable for mobile devices. This work solves these problems by designing energy-efficient hardware accelerators targeted at these applications. It presents the architecture of two complete computational imaging systems for energy-constrained mobile environments: (1) an energy-scalable accelerator for blind image deblurring, with an on-chip implementation and (2) a low-power processor for real-time motion magnification in videos, with an FPGA implementation. It also presents a 3D imaging platform and image processing workflow for 3D surface area assessment of dermatologic lesions. It demonstrates that such accelerator-based systems can enable energy-efficient integration of computational imaging and vision algorithms into mobile and wearable devices.
by Priyanka Raina.
Ph. D.
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Hasan, Md Raqibul. "Memristor Based Low Power High Throughput Circuits and Systems Design." University of Dayton / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1459522347.
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Xie, Jianyong. "Electrical-thermal modeling and simulation for three-dimensional integrated systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50307.
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The continuous miniaturization of electronic systems using the three-dimensional (3D) integration technique has brought in new challenges for the computer-aided design and modeling of 3D integrated circuits (ICs) and systems. The major challenges for the modeling and analysis of 3D integrated systems mainly stem from four aspects: (a) the interaction between the electrical and thermal domains in an integrated system, (b) the increasing modeling complexity arising from 3D systems requires the development of multiscale techniques for the modeling and analysis of DC voltage drop, thermal gradients, and electromagnetic behaviors, (c) efficient modeling of microfluidic cooling, and (d) the demand of performing fast thermal simulation with varying design parameters. Addressing these challenges for the electrical/thermal modeling and analysis of 3D systems necessitates the development of novel numerical modeling methods.
This dissertation mainly focuses on developing efficient electrical and thermal numerical modeling and co-simulation methods for 3D integrated systems. The developed numerical methods can be classified into three categories. The first category aims to investigate the interaction between electrical and thermal characteristics for power delivery networks (PDNs) in steady state and the thermal effect on characteristics of through-silicon via (TSV) arrays at high frequencies. The steady-state electrical-thermal interaction for PDNs is addressed by developing a voltage drop-thermal co-simulation method while the thermal effect on TSV characteristics is studied by proposing a thermal-electrical analysis approach for TSV arrays.
The second category of numerical methods focuses on developing multiscale modeling approaches for the voltage drop and thermal analysis. A multiscale modeling method based on the finite-element non-conformal domain decomposition technique has been developed for the voltage drop and thermal analysis of 3D systems. The proposed method allows the modeling of a 3D multiscale system using independent mesh grids in sub-domains. As a result, the system unknowns can be greatly reduced. In addition, to improve the simulation efficiency, the cascadic multigrid solving approach has been adopted for the voltage drop-thermal co-simulation with a large number of unknowns.
The focus of the last category is to develop fast thermal simulation methods using compact models and model order reduction (MOR). To overcome the computational cost using the computational fluid dynamics simulation, a finite-volume compact thermal model has been developed for the microchannel-based fluidic cooling. This compact thermal model enables the fast thermal simulation of 3D ICs with a large number of microchannels for early-stage design. In addition, a system-level thermal modeling method using domain decomposition and model order reduction is developed for both the steady-state and transient thermal analysis. The proposed approach can efficiently support thermal modeling with varying design parameters without using parameterized MOR techniques.
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Huang, Deping. "Design Techniques for Timing Circuits in Wireline and Wireless Communication Systems." Diss., The University of Arizona, 2014. http://hdl.handle.net/10150/344107.
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Clock and data recovery (CDR) circuit and frequency synthesizer are two essential timing circuits in wireline and wireless communication systems, respectively. With multigigabits/s high speed links and emerging 4G wireless system widely used in communication backbone infrastructures and consumer electronic devices, effective design of CDR and frequency synthesizer has become more and more important. The advanced scaled-down CMOS process has the limitations of leakage current, low supply voltage and process variation which pose great challenge to the analog circuit design. To overcome these issues, a digital intensive CDR solution is needed. Besides, it is desirable for the CDR to cover a wide range of data-rate and to be reference-less for improved flexibility. As for the frequency synthesizer design, the support for multi-standard to reduce the cost and area is desirable. In this work, a digital reference-less CDR is proposed to support continuous datarate ranging from 1 Gbps to 16 Gbps. The CDR adopts an 8 GHz~16 GHz DCO to achieve low random noise performance. A reference-less digital frequency locking loop is included in the system as the acquisition assistance for the CDR loop. To address the difficulty of jitter and stability evaluations for bang-band CDR, a Simulink model is developed to find out the jitter transfer (JTRAN), jitter generation (JGEN) and jitter tolerance (JTOL) performances for the CDR. The prototype CDR is implemented in a 65 nm CMOS process. The core area is 0.68 mm². At 16 Gbps, the CDR consumes a power of 92.5 mW and is able to tolerate a sinusoidal jitter with an amplitude of 0.4 UI and a frequency of 4 MHz. The second part of this dissertation develops a frequency synthesizer for multistandard wireless receivers. The frequency synthesizer is based on an analog fractional-N PLL. Optimally-coupled quadrature voltage-controlled-oscillator (QVCO), dividers and harmonic rejection single sideband mixer (HR-SSBmixer) are combined to synthesize the desired frequency range without posing much phase noise penalty on the QVCO. The QVCO adopts a new phase-shift scheme to improve phase noise and to eliminate bimodal oscillation. Combining harmonic rejection and single sideband mixing, the HR-SSBmixer is developed to suppress spurious signals. Designed in a 0.13-μm CMOS technology, the synthesizer occupies an active area of 1.86 mm² and consumes 35.6 to 52.62 mW of power. Measurement results show that the synthesizer frequency range, the phase noise, the settling time and the spur performances meet the specifications of the wireless receivers for the above standards. For a wide range frequency synthesizer, an automatic frequency calibration circuit (AFC) is needed to select proper oscillator tuning curve before the PLL settling. An improved counter-based AFC is proposed in this dissertation that provides a more robust and faster tuning curve searching process. The proposed AFC adopts a time-to-digital converter (TDC), which is able to captures the fractional VCO cycle information within the counting window, to improve the AFC frequency detection accuracy. The TDC-based AFC is designed in a 0.13-μm CMOS technology. Simulation results show that the TDCbased AFC greatly improves the frequency detection accuracy and consequently for a given frequency detection resolution reduces the AFC calibration time.
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Liando, Johnny 1964. "Enhancement and evaluation of SCIRTSS (sequential circuits test search system) on ISCAS'89 benchmark sequential circuits." Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/278283.
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SCIRTSS, the automatic test pattern generation system for sequential circuit described in AHPL, has been improved to have the best and correct version of the D-Algorithm. This improvement works together with the recent enhancement of the backward state justification search. SCIRTSS now has a complete set of procedures to generate tests for sequential circuits. The performance of SCIRTSS is evaluated using the recent ISCAS'89 sequential benchmark circuits. The overall concepts of how SCIRTSS generate tests, the improvements made on the D-Algorithm, and the benchmark results are presented in this thesis.
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Sengupta, Arindam. "Multidimensional Signal Processing Using Mixed-Microwave-Digital Circuits and Systems." University of Akron / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=akron1407977367.
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Gupta, Narendra Kumar. "Inductive interference into a lineside signalling cable in A.C. electric railway systems." Thesis, University of Manchester, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.252792.
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Rahman, Arifur 1970. "System-level performance evaluation of three-dimensional integrated circuits." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8760.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references (p. 173-187).
As the critical dimensions in VLSI design continue to shrink, system performance of integrated circuits (ICs) will be increasingly dominated by interconnect delay [1]. For the technology generations approaching 50 nm and beyond, innovative system architectures and interconnect technologies will be required to meet the projected system performance [2]. Interconnect material solutions such as copper and low-k inter-level dielectric (ILD) offer only a limited improvement in system performance. Significant and scalable solutions to the interconnect delay problem will require fundamental changes in system design, architecture, and fabrication technologies. Three-dimensional (3-D) ICs can alleviate interconnect delay problems by offering flexibility in system design, placement and routing. They (3-D ICs) can be formed by vertical integration of multiple device layers using wafer bonding, recrystallization, or selective epitaxial growth. The flexibility to place devices along the vertical dimension allows higher device density and smaller form factor in 3-D ICs. The critical signal path that may limit system performance can also be shortened to achieve faster clock speed. By 3-D integration, device layers fabricated with different front-end process technologies can be stacked along the 3rd dimension to form systems-on-a-chip [3]. In this thesis work, opportunities and challenges for 3-D integration of logic networks, microprocessors, and programmable logic have been explored based on system-level modeling and analysis. A stochastic wire-length distribution model has been derived to predict interconnection complexity in 3-D ICs. As more device layers are integrated, the 3-D wire-length distribution becomes narrower compared to that of 2-D ICs, resulting in a significant reduction in the number and length of semi-global and global wires. In 3-D ICs with 2-4 device layers, 30% - 50% reduction in wire-length can be achieved. Besides performance modeling, thermal analysis has also been performed to assess power dissipation and heat removal issues in 3-D ICs. The total capacitance associated with signal interconnects and clock networks can be reduced by 3-D integration, leading to lower power dissipation for system performance comparable to that of 2-D ICs. However, for higher system performance in 3-D ICs, power dissipation increases significantly, and it is likely that innovative cooling techniques will be needed for reliable operation of devices and interconnects.
by Arifur Rahman.
Ph.D.
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Taber, Caleb N. "Conversion of Digital Circuits Labs." Digital Commons @ East Tennessee State University, 2016. https://dc.etsu.edu/honors/395.
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The engineering technology department at ETSU currently lacks a modern method to teach digital circuits. The aim of this thesis is to convert our current digital circuits labs to equivalent labs suited to run on the Basys 3. The Basys has several advantages over the aging NI Elvis boards (and now just breadboards) currently in use. The first advantage is that the Basys gives students a taste of FPGA programming without being overwhelmingly; like the systems currently in place for the digital signal processing class. The Basys is also a more modern system; our current integrated circuit and breadboard system is from the 70’s and has little to do with the modern world of electronics.
There are several major difficulties with moving towards the Basys 3. It requires several tweaks to the current computer security setting of the lab computers. The other issue to be solved is that very few people in the department have even an inkling of how to program in VHDL and most of them are outgoing students. This lack of skills could be a threat to the class but I have included an appendix and a few recommendations for books on the subject to ensure that system development can continue.
The other objective of this project was to see if there were ways to incorporate new educational techniques into the engineering technology curriculum. While there have been no actual tests on students, the groundwork has been laid to use some new ideas in the classroom. All of these new systems are designed to get students to think about how devices actually work and develop models to help them fully understand what is being taught.
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Kenning, Raymond A. "Modeling switched circuit network systems using PLANITU." Thesis, Monterey California. Naval Postgraduate School, 2005. http://hdl.handle.net/10945/1770.
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The realization of today's telecommunication networks is a challenging task. Network architectures are constantly changing to meet new requirements for many new and exciting services and applications. As a result of these added new requirements, new types and mixes of traffic profiles are being introduced into these networks. To facilitate these needs, there are many tools which have been developed to aid in the planning, development, optimization and traffic prediction process. One such tool is PLANITU 3.0. PLANITU is designed to handle many types of circuit network systems and features a powerful graphics capability. The software uses wellestablished, iterative prediction concepts, such as Erlang-B loss equation and the Wilkinson ERT method. Two types of network systems were modeled using real data supplied by Siemens Indonesia. Target networks for study included a fixed switched networks and a GSM (Global System for Mobile Communications) network. PLANITU 3.0 performed well for the fixed switched network systems demonstrating reasonable results within an acceptable degree of accuracy, but performed poorly for GSM systems yielding inoperable simulation features, numerous bugs and software instability.
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Chen, Bojie. "HUMIDITY SENSOR CIRCUIT USING REAL TIME OPERATING SYSTEM (FREERTOS) KERNEL." UKnowledge, 2014. http://uknowledge.uky.edu/ece_etds/61.
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A humidity sensor can be used to measure the moisture content of the environment. The physical change of the sensor expresses as the change of electrical property like capacitance, resistance, voltage, current, frequency, etc. In order to process these analog signals digitally, microprocessor is involved in the measurement. This thesis presents design of a circuit to measure low moisture levels. The 16-bit RISC mixed signal microcontroller MSP430F249 from Texas Instruments will be used. The circuit has good performance at extremely low humidity levels.
Meanwhile, a small real time operating system kernel FreeRTOS, a market leading RTOS from Real Time Engineer Ltd is ported to the microcontroller. The basic concept about FreeRTOS and how to port this RTOS to MSP430F249 microcontrollers will be the topics of this thesis as well.
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Das, Angan. "Algorithms for Topology Synthesis of Analog Circuits." University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1227204301.
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Norouz, Pour Shirazi Arashk. "Advanced interface systems for readout, control, and self-calibration of MEMS resonant gyroscopes." Diss., Georgia Institute of Technology, 2016. http://hdl.handle.net/1853/54936.
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MEMS gyroscopes have become an essential component in consumer, industrial and automotive applications, owing to their small form factor and low production cost. However, their poor stability, also known as drift, has hindered their penetration into high-end tactical and navigation applications, where highly stable bias and scale factor are required over long period of time to avoid significant positioning error. Improving the long-term stability of MEMS gyroscopes has created new challenges in both the physical sensor design and fabrication, as well as the system architecture used for interfacing with the physical sensor. The objective of this research is to develop interface circuits and systems for in-situ control and self-calibration of MEMS resonators and resonant gyroscopes to enhance the stability of bias and scale factor without the need for any mechanical rotary stage, or expensive bulky lab characterization equipment. The self-calibration techniques developed in this work provide 1-2 orders of magnitude
improvement in the drift of bias and scale factor of a resonant gyroscope over temperature and time.
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Schaeffer, Ben. "Synthesis of Linear Reversible Circuits and EXOR-AND-based Circuits for Incompletely Specified Multi-Output Functions." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3783.
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At this time the synthesis of reversible circuits for quantum computing is an active area of research. In the most restrictive quantum computing models there are no ancilla lines and the quantum cost, or latency, of performing a reversible form of the AND gate, or Toffoli gate, increases exponentially with the number of input variables. In contrast, the quantum cost of performing any combination of reversible EXOR gates, or CNOT gates, on n input variables requires at most O(n2/log2n) gates. It was under these conditions that EXOR-AND-EXOR, or EPOE, synthesis was developed.
In this work, the GF(2) logic theory used in EPOE is expanded and the concept of an EXOR-AND product transform is introduced. Because of the generality of this logic theory, it is adapted to EXOR-AND-OR, or SPOE, synthesis. Three heuristic spectral logic synthesis algorithms are introduced, implemented in a program called XAX, and compared with previous work in classical logic circuits of up to 26 inputs. Three linear reversible circuit methods are also introduced and compared with previous work in linear reversible logic circuits of up to 100 inputs.
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Yoo, Seoung-Jae. "Design of analog baseband circuits for wireless communication receivers." Columbus, Ohio Ohio State University, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1073617255.
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Thesis (Ph. D.)--Ohio State University, 2004.Title from first page of PDF file. Document formatted into pages; contains xvi, 167 p.; also includes graphics (some col.). Includes abstract and vita. Advisor: Mohammed Ismail ElNaggar, Dept. of Electrical Engineering. Includes bibliographical references (p. 163-167).
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Almokdad, Saadou. "Non-Foster circuits applied to Full-Duplex systems." Thesis, Brest, 2020. http://www.theses.fr/2020BRES0009.
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Ce travail porte sur la réalisation d’un système FD compact (e.g. applications de type IoT) à partir de composants NF. Pour réaliser un Front-end FD, il est impératif de lutter contre l’auto-interférence (SI) élevée entre émission et réception. Le 1er niveau de réduction de la SI intervient au plus près des antennes (1 TX et 1 RX) pour les miniaturiser puis pour les découpler/isoler l’une de l’autre. Le 2nd a pour fonction de supprimer la SI résiduelle en ajoutant à la réception un signal identique en amplitude à celle de cette interférence mais en opposition de phase. Cet étage requiert un déphaseur variable autour de 180° à environ 1.6GHz et un atténuateur. Comme la topologie retenue pour le déphaseur nécessite des capacités négatives, nos efforts ont d’abord ciblé la réalisation d’un circuit NF basé sur une paire croisée de transistors (XCP) qui constitue le bloc élémentaire de nos dispositifs. Plusieurs idées sont testées pour tendre vers une capacité négative large-bande idéale, mais un circuit stable n’a pu être obtenu qu’en conservant une résistance parasite résiduelle. Ainsi le déphaseur 180° réalisé à base de composants NF voit ses performances être dégradées par rapport au cas idéal. La partie antennaire du front-end FD compact est constituée de 2 antennes planaires très rapprochées. La miniaturisation des antennes est faite en adaptant celles-ci à une fréquence plus basse (1.6 GHz) que leur bande initiale (2.3-2.4 GHz) ou elles sont alors considérées ESA. Une comparaison entre l’adaptation par des réseaux passifs et actifs NF montre que cette dernière permet un élargissement de la bande mais que l’efficacité du système n’est cependant pas améliorée en pratique. Cette limitation provient de la résistance parasite du circuit XCP NF. Le découplage entre antennes à l’aide de circuits NF montre à nouveau un meilleur niveau d’isolation et sur une bande élargie mais sans pénaliser l’efficacité dans ce cas. Au final, les 2 étapes découplage/annulation de la SI sont associés pour obtenir un système FD compact présentant un comportement large-bande de l’adaptation des antennes et de l’isolation (e.g. 45 dB d’isolation à 1,6 GHz). Des perspectives pour réduire la résistance parasite des circuits NF sont proposées pour améliorer l’efficacité du systèmeThis work focuses on achieving a compact FD system (e.g. for wireless IoT) based on NF circuit. The main issue when dealing with FD system is the high self-interference (SI) between transmitter and receiver chains. Thus a two stage decoupling network is studied based on using NF circuits. In this two-level SI canceller, the 1st stage is placed close to the antennas in order to reduce their size, and also to decouple one from each other. The 2nd stage consists of a variable phase shifter and an attenuator. Our goal is to use NF circuit (based on cross-coupled pair of transistors: XCP) to build up a PS tunable around 180° at 1.6 GHz. We identified the origin and solved the stability issue while building a negative capacitance, but a spurious residual resistance remained whatever the improvements made. Our PS performance was thus degraded compared to ideal case.SI cancellation at the antenna level was made by considering two planar monopole antennas (TX and RX). The antennas were miniaturized by making them operate at lower frequency than initially, and then they can be considered as ESA. A comparison between passive matching and NF matching networks showed a wider bandwidth for NF circuits but again the spurious resistor of NF circuit affects the system efficiency. NF circuits also allow improving the decoupling performance (bandwidth and level) compared to passive one but without degrading the efficiency in that case. Finally, we combined the two stages together to get a wideband matching and decoupling response (e.g. 45 dB of SIC at 1.6 GHz for our compact FD system). Some prospects are then put forward in order to face out the residual resistance issue
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Yoon, Heebyung. "Fault detection and identification techniques for embedded analog circuits." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/13041.
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Seo, Chung-Seok. "Physical Design of Optoelectronic System-on-a-Chip/Package Using Electrical and Optical Interconnects: CAD Tools and Algorithms." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-11102004-150844/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.David E. Schimmel, Committee Member ; C.P. Wong, Committee Member ; John A. Buck, Committee Member ; Abhijit Chatterjee, Committee Chair ; Madhavan Swaminathan, Committee Member. Vita. Includes bibliographical references.
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Iindombo, Julia Dimbulukweni. "Efficiency plan for large interconnected urban ring main network under contingency conditions." Thesis, Cape Peninsula University of Technology, 2011. http://hdl.handle.net/20.500.11838/1185.
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Thesis (MTech(Electrical Engineering))--Cape Peninsula University of Technology, 2011In a situation, where there is a shortage of power generation or the power stations are operating with a very low reserve margin, as is typically the current position in South Africa, there is a need to operate distribution network at the highest possible efficiency by utilising network power loss reduction techniques. Such techniques are especially important when contingencies occur as they tend to increase loss, reduce efficiencies and cause power supplies to such networks to increase. This increase can cause the network or multiples of such networks to be load shed as the power stations do not have the reserve margins to meet this increased demand. The ideal situation would thus be to minimise network loss and in so doing decrease the amount of power needed and possibly avoid load shedding. Thus, there is a need to study efficiency, network loss reduction under contingency conditions and this is the focus of the research. Most large urban distribution networks are operated as ring main networks. Ring networks are considered to have less power loss. However, a major component in a ring network can cause the loss to substantially increase; resulting in power shortage in the network. There is an urgency to eliminate high network loss. An efficiency plan was developed for a large ring network that reduces the loss so that its input power can be decreased. In this way, the available power existing due to the contingency can be more evenly spread, and the number of ring main networks to be load shed could be reduced.
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Li, Yimeng. "Self-Tuning NFC Circuits." Thesis, Mittuniversitetet, Avdelningen för elektronikkonstruktion, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-32550.
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Contactless automatic identification procedures which are called RFID systems (Radio-frequency Identification) have become very popular in recent years for transferring power and data. With the development of RFID technology, the demand of easy transmitting of short data packages has made NFC (Near-field Communication) technology wildly used especially in mobile applications. The communication between a mobile and a tag is achieved through a magnetic field generated by the mobile’s NFC interface. In order to get a maximal power transmission, the tag circuit is designed to operate at the resonance frequency of 13.56 MHz, which is equal to the operation frequency of the mobile’s NFC interface. As mutual inductances provided by different kinds of mobiles exist divergence, optimal power transfer cannot be reached every time. This thesis focuses on the optimization of power transfer during the communications between tags and mobiles with uncertain NFC coils. By incorporating a self-tuning parallel variable capacitance compensation circuitry the resonance frequency of an NFC tag circuit can be self-tuned to 13.56 MHz to ensure an optimal power transmission. This thesis presents both theoretical and experimental analysis of this improved self-tuning NFC circuitry in detail and demonstrates that by digitally tuning a parallel capacitor circuit, the energy transferred to an NFC tag can be optimized when facing different kinds of NFC-enabled mobile phones.
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Desfonds, Eric. "Mueller matrix-based system to perform opto-electrical characterization of polarization-sensitive DWDM photonic integrated circuits." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26622.
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The implementation of a novel analysis system to characterize rapidly and accurately polarization-sensitive dense wavelength division multiplexing photonic integrated circuits is detailed within this document. The acquisition and subsequent analysis of passive optical insertion loss and absolute responsivity spectrum of MetroPhotonics Inc.'s products shall be discussed.
Polarization-maintaining fibers are typically manually calibrated and rotated to evaluate the performance of such devices under extreme orthogonal states of polarization, known as transverse electrical and transverse magnetic modes. This highly manual measurement technique has proven unsuitable for a mass production environment.
Device Mueller matrix terms used in conjunction with advanced analysis algorithms have been used to evaluate the performance of these devices for any desired state of polarization, with largely increased overall testing capacity, accuracy and repeatability.
Different novel analysis algorithms have been evaluated to isolate the orthogonal input TE and TM spectrum, while still providing the extremes of insertion loss and/or responsivity at each wavelength steps across the operating wavelength range.
The algorithms described herein to recover said spectra are novel as, to our knowledge, nothing equivalent has yet been reported in any scientific literature.
This technique has enabled the Test and Measurement group of MetroPhotonics Inc. to provide new insight in the polarization-dependent performance of different planar waveguide photonic integrated circuit products, while providing more accurate process related metrics to the fabrication and design groups. These efforts culminated in the delivery of fully calibrated MetroPhotonics SurePath(TM) portfolio products to customers.
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Lu, Shuai. "Infrastructure, operations, and circuits design of an undersea power system /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6029.
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Al-Bayaty, Hussein Kamal Anwer. "Novel methods of utilization, elimination, and description of the distortion power in electrical circuits." Thesis, University of Plymouth, 2018. http://hdl.handle.net/10026.1/10646.
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Firstly, this thesis investigates the electrical power harmonics in an attempt to utilize harmonic current and its distortion power in a novel idea to reconvert the distortion power into useful power. This is done, in order to feed different DC or AC loads in single and three-phase power system by using passive or active filters and accordingly, develop a new topology of hybrid active power filter (HAPF). In addition, this circuit can be considered as a power factor corrector (PFC) because it reduces the total harmonic distortion (THD) and improves the power factor (PF). Secondly, this thesis works on a new design of active power factor correction (APFC) circuit presenting two circuits with the same design principle: the first design consists of two active switches without an external complex control circuit, while the second design contains a single active switch with an additional control circuit. The main contribution of this circuit is 98% reduction of the inductor's value used in the newly proposed PFC circuit in comparison with the conventional boost converter which may lead to a huge reduction in size, weight and the cost of the new PFC circuit. Also, the active switches depend on a carefully designed switching pattern that results in an elimination of the third order harmonic from the input source current which decreases the value of total current harmonic distortion (THDI) to (14%) and improves the input PF to (0.99). Consequently, the simplicity of the design without requiring a complex control circuit and without a snubber circuit plus the minimum size of inductor, gives the newly proposed circuit the superiority on other PFC circuits. Thirdly, this research aims to describe the distortion power through submitting two novel power terms called effective active power (Pef ) & reactive power (Qef ) terms with a new power diagram called Right-Angled Power Triangle (RAPT) Diagram. In addition, a novel de nition of total apparent power (St) has been submitted in order to illustrate the physical meaning of (St) in non-sinusoidal systems. The new RAPT Diagram is based on the orthogonality law and depends on geometrical summation to describe the relationship between different aspects (apparent-active-reactive) of power, and different components (total-fundamental distortion), drawing a bridge to connect the time domain with the frequency domain in a two-dimensional diagram.
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Groves, James O. "Small signal analysis of nonlinear systems with periodic operating trajectories." Diss., This resource online, 1995. http://scholar.lib.vt.edu/theses/available/etd-06062008-162614/.
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Arunachalam, Sivakumar. "A new approach to arc fault detection for AC and DC systems." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2005. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.
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Scheiblauer, Kristopher S. "Quadded GasP: a Fault Tolerant Asynchronous Design." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3475.
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As device scaling continues, process variability and defect densities are becoming increasingly challenging for circuit designers to contend with. Variability reduces timing margins, making it difficult and time consuming to meet design specifications. Defects can cause degraded performance or incorrect operation resulting in circuit failure. Consequently test times are lengthened and production yields are reduced.
This work assess the combination of two concepts, self-timed asynchronous design and fault tolerance, as a possible solution to both variability and defects. Asynchronous design is not as sensitive to variability as synchronous, while fault tolerance allows continued functional operation in the presence of defects.
GasP is a self-timed asynchronous design that provides high performance in a simple circuit. Quadded Logic, is a gate level fault tolerant methodology. This study presents Quadded GasP, a fault tolerant asynchronous design.
This work demonstrates that Quadded GasP circuits continue to function within performance expectations when faults are present. The increased area and reduced performance costs of Quadded GasP area also evaluated.
These results show Quadded GasP circuits are a viable option for managing process variation and defects. Application of these circuits will provide decreased development and test times, as well as increased yield.
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Pal, Subarna. "Simulation of current mode control schemes for power factor correction circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0008/MQ36162.pdf.
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Bansal, Mayur. "DIGITAL CONTROL BOARD FOR PHASED ARRAY ANTENNA BEAM STEERING IN ADAPTIVE COMMUNICATION APPLICATIONS." DigitalCommons@CalPoly, 2013. https://digitalcommons.calpoly.edu/theses/1113.
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The application of adaptive communication techniques for mobile communications has attracted considerable interest in the last decade. One example of these techniques is spatial filtering through planar antenna array beam forming.
This thesis describes the development of a digital system that adaptively controls a phased array antenna. The radiating structure of the phased antenna array is tetrahedral-shaped and contains four antenna elements on each of its three faces. The overall system comprises of a digital control board with an external computer interface, an RF control board, and the phased antenna array. The RF controls the main lobe direction on the phased array antenna. This thesis describes the design and implementation of the digital control board.
The digital control board`s primary responsibilities are implementing inter- faces between the external computer and the RF board, which results in two operational modes: the MATLAB graphical user interface (GUI) mode and the adaptive receive mode. The GUI mode allows users to input parameters that provide interactive control of the phased antenna array by interfacing with an external computer and the RF control board. The adaptive receive mode im- plements an algorithm for an adaptive receive station. This algorithm uses a 58-point scanning technique that locates the maximum receive power direction.
Test results show that the digital control board successfully manages the RF board control voltage with an nominal error of less than 1%, which subsequently allows for precise control of the antenna`s active face. Additionally, testing of the GUI demonstrated the successful interactive application of various system control parameters.