Dissertations / Theses: 'Electric circuit analogie'

1

Spinks, Stephen James. "Fault simulation for structural testing of analogue integrated circuits." Thesis, University of Hull, 1998. http://hydra.hull.ac.uk/resources/hull:8047.

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In this thesis the ANTICS analogue fault simulation software is described which provides a statistical approach to fault simulation for accurate analogue IC test evaluation. The traditional figure of fault coverage is replaced by the average probability of fault detection. This is later refined by considering the probability of fault occurrence to generate a more realistic, weighted test metric. Two techniques to reduce the fault simulation time are described, both of which show large reductions in simulation time with little loss of accuracy. The final section of the thesis presents an accurate comparison of three test techniques and an evaluation of dynamic supply current monitoring. An increase in fault detection for dynamic supply current monitoring is obtained by removing the DC component of the supply current prior to measurement.

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2

Long, David Ian. "Behavioural simulation of mixed analogue/digital circuits." Thesis, Bournemouth University, 1996. http://eprints.bournemouth.ac.uk/278/.

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Continuing improvements in integrated circuit technology have made possible the implementation of complex electronic systems on a single chip. This often requires both analogue and digital signal processing. It is essential to simulate such IC's during the design process to detect errors at an early stage. Unfortunately, the simulators that are currently available are not well-suited to large mixed-signal circuits. This thesis describes the design and development of a new methodology for simulating analogue and digital components in a single, integrated environment. The methodology represents components as behavioural models that are more efficient than the circuit models used in conventional simulators. The signals that flow between models are all represented as piecewise-linear (PWL) waveforms. Since models representing digital and analogue components use the same format to represent their signals, they can be directly connected together. An object-oriented approach was used to create a class hierarchy to implement the component models. This supports rapid development of new models since all models are derived from a common base class and inherit the methods and attributes defined in their parentc lassesT. he signal objectsa re implementedw ith a similar class hierarchy. The development and validation of models representing various digital, analogue and mixed-signal components are described. Comparisons are made between the accuracy and performance of the proposed methodology and several commercial simulators. The development of a Windows-based demonstrations imulation tool called POISE is also described. This permitted models to be tested independently and multiple models to be connected together to form structural models of complex circuits.

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3

Kuznetsov, Eugene. "Trust in analog : analog circuit techniques for reducing the risk of malicious circuits and software." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66431.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 47).
Malicious circuits and software present a significant security risk, especially in control applications. This work is concerned with increasing the trustworthiness of control circuitry by reducing its complexity. The security benefits of substituting analog control techniques in place of digital control are analyzed, and both discrete and integrated circuit designs are demonstrated.
by Eugene Kuznetsov.
M.Eng.

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4

Shana'a, Osama K. "Circuit Implementation of a High-speed Continuous-time Current-mode Field Programmable Analog Array (FPAA)." PDXScholar, 1996. https://pdxscholar.library.pdx.edu/open_access_etds/5103.

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The growing interest in programmable analog circuits has led to the development of Field Programmable Analog Arrays (FPAAs). An FPAA consists of: 1) a programmable cell that can be reconfigured to perform several analog functions. 2) an architecture that interconnects a number of copies of the programmable cell. In this thesis, the full monolithic circuit implementation of the analog part of the programmable cell is presented. Chapter I gives an introduction to the idea of FPAA and introduces the FPAA architecture and the cell block diagram. Chapter II deals with the design and verification of a differential current-mode four-quadrant multiplier. The weighting-summing circuit with the normalizing stage is discussed in Chapter III. Chapter IV presents the design of a current-mode low-voltage programmable integratorgain circuit. Programmability was achieved by changing the bias current in the designed circuits; no analog switches were used in the signal path. This shows no effect on the performance of the circuits. The presented programming method, however, relies on the availability of a programmable current source with a storage capability. The design of this current source is discussed in chapter V. Conclusions are summarized in Chapter VI. The presented designs throughout the whole thesis were supported by detailed analytical derivations with the necessary SPICE simulations to verify the performance.

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5

Cuell, Charles L. "An electric circuit analogue of a nonholonomically constrained Hamiltonian system." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape9/PQDD_0016/MQ47995.pdf.

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6

Bhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.

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7

Cakir, Sinan. "Tolerance Based Reliability Of An Analog Electric Circuit." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12612929/index.pdf.

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This thesis deals with the reliability analysis of a fuel pump driver circuit (FPDC), which regulates the amount of fuel pumped to a turbojet engine. Reliability analysis in such critical circuits has great importance since unexpected failures may cause serious financial loss and even human death. In this study, two types of reliability analysis are used: &ldquo
Worst Case Circuit Tolerance Analysis&rdquo
(WCCTA) and &ldquo
Failure Modes and Effects Analysis&rdquo
(FMEA). WCCTA involves the analysis of the circuit operation under varying parameters in their tolerance bands. These parameters include the resistances of the resistors, operating temperature and voltage input value. The operation of FPDC is checked and the most critical parameters are determined in the worst case conditions. While performing WCCTA, a method that guarantees the exact worst case conditions is used rather than probabilistic methods like Monte Carlo analysis. The results showed that the parameter variations do not affect the circuit operation unfavorably
operating temperature, voltage input variation and tolerance bands for the resistances are fairly compatible with the circuit operation. FMEA is implemented according to the short circuit and open circuit failures of all the electronic components used in FPDC. The components whose failure has catastrophic effect on the circuit operation have been determined and some preventive actions have been offered for some catastrophic failures.

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Hong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.

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9

Lui, Siu-hong. "Analog circuit design by nonconvex polynomial optimization two design examples /." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39557418.

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10

Yoon, Heebyung. "Fault detection and identification techniques for embedded analog circuits." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/13041.

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11

Sheehan, Kevin Michael. "Evolving analogue electronic signal processing circuit behaviour in hardware." Thesis, Royal Holloway, University of London, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.272073.

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Cheung, Wing-tai. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39558526.

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13

Parish, Simon James. "Behavioural synthesis of analogue integrated circuits." Thesis, University of Birmingham, 2010. http://etheses.bham.ac.uk//id/eprint/549/.

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Automatic synthesis of analogue circuits remains a very manually intensive task despite huge strides in the field of Electronic Design Automation (EDA) in recent decades. Genetic Algorithms (GAs) are biologically inspired search algorithms which have previously shown some promise in this field. Their ability to form the basis of a practically useful synthesis system is investigated. A GA-based experimental synthesis system is implemented, which employs a Genetic Programming (GP) style encoding scheme based on tree structures, and a novel fitness function based on pole-zero analysis. The system is capable of synthesising circuit topologies entirely from scratch, but can also utilise user-provided circuit knowledge of arbitrary detail and complexity. The system uses a SPICE-based circuit simulator as a circuit evaluator. Experimental results reveal a number of issues that adversely impact the ability of GAs to reliably synthesise practically useful analogue circuits. These include considerable resource requirements and a tendency for synthesised circuits to contain an unnecessarily large number of components. Most serious is the sensitivity of analogue circuits to changes in topology and/or sizing. GAs are shown to be currently ill-suited to the problem domain of analogue circuit synthesis. The problem of SPICE non-convergence on the GA is also considered.

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14

Eberhardt, Friedemann. "Symbolic tolerance and sensitivity analysis of large scale electronic circuits." Thesis, University of Bath, 1999. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301578.

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15

Lui, Siu-hong, and 呂小康. "Analog circuit design by nonconvex polynomial optimization: two design examples." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39557418.

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Mitros, Piotr 1979. "A framework for analog circuit optimization." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/28447.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (p. 49-50).
This thesis presents a system for optimization of analog circuit topologies and component values. The topology is optimized using simulated annealing, while the component values are optimized using gradient descent. Local minima are avoided and constraints are kept through the use of coordinate transformations, as well as the use of default starting points for component values. The system is targeted for use in 3D integrated circuit design. The architecture is extendable, and is designed to eventually include capabilities for automated layout and mixed-signal design.
by Piotr Mitros.
M.Eng.

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17

Feng, Hong. "Impact of atomistic device variability on analogue circuit design." Thesis, University of Glasgow, 2011. http://theses.gla.ac.uk/3074/.

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Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs. Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm “atomistic” devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem. Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC.

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18

Chakrabarti, Sudip. "Test generation for fault isolation in analog and mixed-mode circuits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14899.

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19

張永泰 and Wing-tai Cheung. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39558526.

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20

Sabzavari, Abbas Mostafavi. "Fault simulation and diagnosis in analog electronic systems." Thesis, University of Exeter, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.328233.

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21

Simayi, Ayanda Njongi. "The use of contextually appropriate analogies to teach direct current electric circuit concepts to isiXhosa speaking learners." Thesis, Nelson Mandela Metropolitan University, 2014. http://hdl.handle.net/10948/d1016161.

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The study investigates the effects of a professional development strategy which focuses on the use of a contextually appropriate analogy on the development of isiXhosa speaking learners‟ conceptual understanding in direct current electric circuits, where the language of instruction is English. An action research design was implemented, using three data collection cycles to document the research journey. The sample comprised of two Grade 8 and 9 classes drawn (with their respective Natural Sciences teachers) from two neighbouring, township schools in Nelson Mandela Metropolitan Municipal area. Qualitative data were generated from interviews and classroom observation of the two science teachers (a qualified and an unqualified teacher) and learners, over a span of two years. Thematic data analysis revealed that ESL learners have alternative conceptions in simple circuits and teachers have no knowledge about analogies that can be used to teach simple circuits. A professional development was designed as a strategy, targeting the development of the Science Content Knowledge (SCK) and Topic Specific Content Pedagogic Content Knowledge (TPSCK) of the teachers. Data analysis of the professional development initiative (PDI) suggests that the teachers developed increased knowledge of concepts and teaching strategies used in teaching simple circuits, selected a contextually appropriate analogy and taught a lesson in simple circuits using the selected analogy. Analysis of learners‟ post-test results suggests that the implementation of the selected analogy developed their conceptual understanding as more learners developed the correct, scientific model of reasoning. The results of the study suggest that when teachers are given support by being exposed to professional development; their scientific reasoning, confidence and classroom climate become more positive and learners‟ conceptual understanding improves.

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22

Hai, Ling. "Modelling Wave Power by Equivalent Circuit Theory." Doctoral thesis, Uppsala universitet, Elektricitetslära, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-265270.

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The motion of ocean waves can be captured and converted into usable electricity. This indicates that wave power has the potential to supply electricity to grids like wind or solar power. A point absorbing wave energy converter (WEC) system has been developed for power production at Uppsala University. This system contains a semi-submerged buoy on the water surface driving a linear synchronous generator placed on the seabed. The concept is to connect many small units together, to form a wave farm for large-scale electricity generation. A lot of effort has gone into researching how to enhance the power absorption from each WEC unit. These improvements are normally done separately for the buoy, the generator or the electrical system, due to the fact that modelling the dynamic behavior of the entire WEC system is complicated and time consuming. Therefore, a quick, yet simple, assessment tool is needed. This thesis focuses on studying the use of the equivalent circuit as a WEC system modelling tool. Based on the force analysis, the physical elements in an actual WEC system can be converted into electrical components. The interactions between the regular waves, the buoy, and the Power Take-off mechanism can be simulated together in one circuit network. WEC performance indicators like the velocity, the force, and the power can be simulated directly from the circuit model. Furthermore, the annual absorbed electric energy can be estimated if the wave data statistics are known. The linear and non-linear equivalent circuit models developed in this thesis have been validated with full scale offshore experimental results. Comparisons indicate that the simplest linear circuit can predict the absorbed power reasonably well, while it is not so accurate in estimating the peak force in the connection line. The non-linear circuit model generates better estimations in both cases. To encourage researchers from different backgrounds to adapt and apply the circuit model, an instruction on how to establish a non-linear equivalent circuit model is supplied, as well as on how to apply the model to accelerate the decision making process when planning a WEC system.

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23

Abel, Jerian. "Students' conceptual modeling of simple DC electric circuits during computer-based instruction." Diss., This resource online, 1995. http://scholar.lib.vt.edu/theses/available/etd-06062008-170004/.

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24

Choi, Pyung. "An equivalent circuit structure macromodel for analog phase locked loops." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/14875.

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25

Besnard, SteÌphane Claude Louis. "Optimising fault modelling and test development for VLSI analogue circuits." Thesis, University of Huddersfield, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.288503.

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26

Odame, Kofi. "Exploiting device nonlinearity in analog circuit design." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29751.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Butera, Robert; Committee Member: Minch, Bradley; Committee Member: Taylor, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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27

Liu, Dong. "Analog and mixed-signal test and fault diagnosis." Ohio : Ohio University, 2003. http://www.ohiolink.edu/etd/view.cgi?ohiou1177701780.

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28

VALLICELLI, ELIA ARTURO. "Design of Mixed-Signal Electronic Instrumentation for Proton Sound Detectors." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2021. http://hdl.handle.net/10281/301978.

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La tecnica acustica di verifica sperimentale del range di protoni (ionoacustica) si basa sul rilevamento del debole segnale termoacustico emesso dalla rapida deposizione di energia che avviene alla fine range del fascio, in corrispondenza del picco di Bragg. In questo contesto, questa tesi presenta le principali caratteristiche della strumentazione microelettronica utilizzata per i Proton Sound Detector introducendo specifiche tecniche di progettazione fortemente orientate sia alla massimizzazione del Rapporto Segnale Rumore SNR (a livello di sensore acustico) che minimizzazione della figura di rumore (a livello di amplificatore analogico). La prima parte di questa tesi tratta delle sfide strumentali relative agli esperimenti ionoacustici fornendo dettagli tecnici specifici riguardanti sia la progettazione del sensore acustico (ovvero come costruire il sensore massimizzando l'SNR) sia il design dell'amplificatore a basso rumore (LNA). Verranno presentati i risultati sperimentali di un primo esperimento effettuato presso il Laboratorio Maier-Leibniz di Garching, Monaco, con un fascio di protoni a 20 MeV (scenario preclinico) e verrà mostrato come una progettazione elettronica dedicata a segnali misti permetta di migliorare significativamente il rapporto segnale-rumore e l'accuratezza della localizzazione del picco di Bragg di 6 dB. In questo contesto, questo primo sviluppo del rivelatore raggiunge due importanti obiettivi: il miglioramento dell'SNR a parità di dose e una forte semplificazione della strumentazione del rivelatore rispetto allo stato dell'arte, consentendo una maggiore precisione della misurazione dell'impulso acustico, e allo stesso tempo incrementando la portabilità e la compattezza del dispositivo. Nelle applicazioni cliniche di adroterapia, l'energia del fascio (da 65 MeV fino a 200 MeV) e la dose vengono scelte in funzione dello specifico scenario clinico. Ciò comporta segnali acustici di ampiezza e larghezza di banda diverse, costringendo l’adozione di soluzioni tecnologiche avanzate in grado di gestire un ampio spettro di segnali in termini di larghezza di banda, ampiezza e rumore. Per questo motivo, la seconda parte di questa tesi propone un modello Matlab efficiente e innovativo del fenomeno fisico ionoacustico, che condensa in un unico sistema lineare tempo invariante tutti i processi di conversione dell'energia coinvolti. Il modello ionoacustico proposto sostituisce i complessi strumenti di simulazione classici (usati per caratterizzare il segnale acustico indotto dal fascio di protoni) e facilita lo sviluppo di rivelatori dedicati fornendo una descrizione precisa del segnale acustico nei diversi scenari. Infine, verrà presentato il progetto di una seconda versione del Proton Sound Detector che introduce il concetto di media nel dominio dello spazio (invece della media nel dominio del tempo, basata sull’elaborazione di più shot del fascio che comporta una significativa extra-dose). Questo rilevatore utilizza un sensore multicanale per eseguire una media spaziale dei segnali acquisiti e aumentare l'SNR di 18 dB a parità di dose rispetto al classico approccio monocanale. Questo approccio tuttavia richiede lo sviluppo di elettronica altamente miniaturizzata che non può essere implementata con componenti standard su circuiti stampati. Viene quindi presentato il progetto e la caratterizzazione di un front-end analogico multicanale implementato su un Application-Specified-Integrated-Circuit (ASIC) in tecnologia CMOS 28 nm che permette di elaborare in parallelo tutti i 64 canali del sensore acustico. Questo High-Resolution Proton Sound Detector (HR-ProSD) è completato da un circuito digitale dedicato implementato su FPGA (Field Programmable Gate Array) che consente di mappare in tempo reale e 2D la deposizione di dose nello spazio.
Acoustic proton range experimental verification technique (iono-acoustics) is based on sensing the weak thermoacoustic signal emitted by the fast energy deposition (and/or the heating process) at the end of the beam range (Bragg Peak). In this context, this thesis presents the main characteristics of the micro-electronics instrumentation used for proton sound detectors introducing specific design techniques strongly oriented to both maximization of the acoustic Signal-to-Noise-Ratio (at the Acoustic Sensor level) and Noise-Figure minimization (at analog amplifier level). The first part of this thesis addresses all the instrumentation challenges related to iono-acoustic experiments providing specific technical details regarding both acoustic sensor design (i.e. how to build the sensor while maximizing the SNR) and the LNA design. The experimental results of a first experiment carried out at Maier-Leibniz Laboratory in Garching, Munich, with a proton beam at 20 MeV (sub-clinical energy) will be presented and it will be shown how a dedicated mixed-signal electronics design allows to significantly improve the signal-to-noise ratio and the accuracy of the BP localization by 6 dB. In this context, this first detector development achieves two important objectives: the improvement of the acoustic SNR and a strong simplification of the detector instrumentation w.r.t. state-of-the-art, enabling increasing accuracy of the acoustic pulse measurement, and at the same time the portability and compactness of the device. In clinical hadron-therapy applications, variable beam energy (from 65 MeV up to 200 MeV) and variable doses are used as a function of the selected medical treatment. This induces different acoustic pulses amplitude and bandwidth, forcing advanced technological solutions capable of handling a wide spectrum of signals in terms of bandwidth, amplitude, and noise. For this reason, the second part of this thesis proposes an efficient and innovative Matlab Model of the ionoacoustic physical phenomenon, based on englobing in a single mathematical Linear-Time-Invariant-System all energy conversion processes involved in iono-acoustics. The proposed ionoacoustics model replaces classical and complex simulation tools (used to characterize the proton induced acoustic signal) and facilitates the development of dedicated detectors. Finally, the design of a second version of the Proton Sound Detector will be presented that introduces the concept of space-domain averaging (instead of time-domain averaging based on multiple beam shot processing for noise attenuation and thus extra-doses). This detector uses a multi-channel sensor to perform a spatial average of the acquired signals and increase the SNR by 18 dB at the same dose compared to the classic single channel approach. This approach however requires the development of highly miniaturized electronics that cannot be implemented with off-the-shelf components on Printed Circuit Boards. The design and characterization of a multichannel analog front-end implemented on a CMOS 28 nm Application-Specified-Integrated-Circuit (ASIC) which allows to process the 64 channels of the acoustic sensor in parallel is then presented. This High-Resolution Proton Sound Detector (HR-ProSD) is completed by digital circuits implemented on Field Programmable Gate Array (FPGA) that allow to locate in real time the deposition of energy in space.

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29

Yoo, Seoung-Jae. "Design of analog baseband circuits for wireless communication receivers." Columbus, Ohio Ohio State University, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1073617255.

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Thesis (Ph. D.)--Ohio State University, 2004.
Title from first page of PDF file. Document formatted into pages; contains xvi, 167 p.; also includes graphics (some col.). Includes abstract and vita. Advisor: Mohammed Ismail ElNaggar, Dept. of Electrical Engineering. Includes bibliographical references (p. 163-167).

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Md, Ali Sawal Hamid. "System level performance and yield optimisation for analogue integrated circuits." Thesis, University of Southampton, 2009. https://eprints.soton.ac.uk/69724/.

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Advances in silicon technology over the last decade have led to increased integration of analogue and digital functional blocks onto the same single chip. In such a mixed signal environment, the analogue circuits must use the same process technology as their digital neighbours. With reducing transistor sizes, the impact of process variations on analogue design has become prominent and can lead to circuit performance falling below specification and hence reducing the yield. This thesis explores the methodology and algorithms for an analogue integrated circuit automation tool that optimizes performance and yield. The trade-offs between performance and yield are analysed using a combination of an evolutionary algorithm and Monte Carlo simulation. Through the integration of yield parameter into the optimisation process, the trade off between the performance functions can be better treated that able to produce a higher yield. The results obtained from the performance and variation exploration are modelled behaviourally using a Verilog-A language. The model has been verified with transistor level simulation and a silicon prototype. For a large analogue system, the circuit is commonly broken down into its constituent sub-blocks, a process known as hierarchical design. The use of hierarchical-based design and optimisation simplifies the design task and accelerates the design flow by encouraging design reuse. A new approach for system level yield optimisation using a hierarchical-based design is proposed and developed. The approach combines Multi-Objective Bottom Up (MUBU) modelling technique to model the circuit performance and variation and Top Down Constraint Design (TDCD) technique for the complete system level design. The proposed method has been used to design a 7th order low pass filter and a charge pump phase locked loop system. The results have been verified with transistor level simulations and suggest that an accurate system level performance and yield prediction can be achieved with the proposed methodology.

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31

Aggarwal, Varun. "Analog circuit optimization using evolutionary algorithms and convex optimization." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40525.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
Includes bibliographical references (p. 83-88).
In this thesis, we analyze state-of-art techniques for analog circuit sizing and compare them on various metrics. We ascertain that a methodology which improves the accuracy of sizing without increasing the run time or the designer effort is a contribution. We argue that the accuracy of geometric programming can be improved without adversely influencing the run time or increasing the designer's effort. This is facilitated by decomposition of geometric programming modeling into two steps, which decouples accuracy of models and run-time of geometric programming. We design a new algorithm for producing accurate posynomial models for MOS transistor parameters, which is the first step of the decomposition. The new algorithm can generate posynomial models with variable number of terms and real-valued exponents. The algorithm is a hybrid of a genetic algorithm and a convex optimization technique. We study the performance of the algorithm on artificially created benchmark problems. We show that the accuracy of posynomial models of MOS parameters is improved by a considerable amount by using the new algorithm. The new posynomial modeling algorithm can be used in any application of geometric programming and is not limited to MOS parameter modeling. In the last chapter, we discuss various ideas to improve the state-of-art in circuit sizing.
by Varun Aggarwal.
S.M.

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32

Mitros, Piotr 1979. "Constraint satisfaction modules : a methodology for analog circuit design." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/42237.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
Includes bibliographical references (p. 119-122).
This dissertation describes a methodology for solving convex constraint problems using analog circuits. It demonstrates how this methodology can be used to design circuits that solve function-fitting problems through iterated gradient descent. In particular, it shows how to build a small circuit that can model a nonlinearity by observation, and predistort to compensate for this nonlinearity. The system fits into a broader effort to investigate non-traditional approaches to circuit design. First, it breaks the traditional input-output abstraction barrier; all ports are bidirectional. Second, it uses a different methodology for proving system stability with local rather than global properties. Such stability arguments can be scaled to much more complex systems than traditional stability criteria.
by Piotr Mitros.
Ph.D.

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33

Li, Harry W. "A noniterative DC analysis program for analog integrated circuits." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/15977.

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34

He, Lizhong. "1-Ghz CMOS Analog Signal Squaring Circuit." Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1472476550.

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Tavakoli, Dastjerdi Maziar 1976. "Analog VLSI circuits for inertial sensory systems." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86766.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
Includes bibliographical references (leaves 67-68).
by Maziar Tavakoli Dastjerdi.
S.M.

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Knight, Clinton D. "WWW-based testing of analog circuits." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/14863.

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A'Ain, Abu Khari Bin. "Power supply voltage control testing technique as a novel electrical test strategy for analogue integrated circuits." Thesis, Lancaster University, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.337370.

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Vichik, Sergey. "Quadratic and linear optimization with analog circuits." Thesis, University of California, Berkeley, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10086165.

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In this work we propose and investigate a new method of solving quadratic and linear optimization problems using analog electrical circuits instead of digital computation.

We present the design of an analog circuit which solves Quadratic Programming (QP) or Linear Programming (LP) problems. In particular, the steady-state circuit voltages are the components of the QP (LP) optimal solution. The thesis shows how to construct the circuit and provides a proof of equivalence between the circuit and the QP (LP) problem.

We study the stability of the analog optimization circuit. The circuit dynamics are modeled as a switched affine system. A piece-wise quadratic Lyapunov function and the KYP lemma are used to derive the stability criterion. The stability criterion characterizes the range of critical circuit parameters for which the QP circuit is globally asymptotically stable.

The proposed method is used to build a printed circuit board (PCB) using programmable components to allow solution of various QP problems. The board supports implementation of an MPC controller for buck DC-DC converter. We conduct an experimental study to evaluate the performance of the analog optimization circuit.

We study the feasibility of very high speed implementation of the optimization circuit using Analog Very Large Scale Integration (AVLSI) technology. In AVLSI, all the required circuit components are built on top of a silicon substrate using advanced photo-lithographic technologies. AVLSI circuits are fast, small and cheap. Thus, AVLSI implementation is paramount to make the proposed technology commercially competitive.

We discuss the possible usage of the proposed method to make fast MPC controllers, image processors, communication decoders and analog co-processors. In fact, any application that requires a repeating solution of related optimization problems can benefit from this technology. Besides being faster than the digital computers, analog computers are more power efficient, may occupy smaller area on silicon and may be more resilient in harsh environments.

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Pous, i. Sabadí Carles. "Case based reasoning as an extension of fault dictionary methods for linear electronic analog circuits diagnosis." Doctoral thesis, Universitat de Girona, 2004. http://hdl.handle.net/10803/7728.

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El test de circuits és una fase del procés de producció que cada vegada pren més importància quan es desenvolupa un nou producte. Les tècniques de test i diagnosi per a circuits digitals han estat desenvolupades i automatitzades amb èxit, mentre que aquest no és encara el cas dels circuits analògics. D'entre tots els mètodes proposats per diagnosticar circuits analògics els més utilitzats són els diccionaris de falles. En aquesta tesi se'n descriuen alguns, tot analitzant-ne els seus avantatges i inconvenients.
Durant aquests últims anys, les tècniques d'Intel·ligència Artificial han esdevingut un dels camps de recerca més importants per a la diagnosi de falles. Aquesta tesi desenvolupa dues d'aquestes tècniques per tal de cobrir algunes de les mancances que presenten els diccionaris de falles. La primera proposta es basa en construir un sistema fuzzy com a eina per identificar. Els resultats obtinguts son força bons, ja que s'aconsegueix localitzar la falla en un elevat tant percent dels casos. Per altra banda, el percentatge d'encerts no és prou bo quan a més a més s'intenta esbrinar la desviació.
Com que els diccionaris de falles es poden veure com una aproximació simplificada al Raonament Basat en Casos (CBR), la segona proposta fa una extensió dels diccionaris de falles cap a un sistema CBR. El propòsit no és donar una solució general del problema sinó contribuir amb una nova metodologia. Aquesta consisteix en millorar la diagnosis dels diccionaris de falles mitjançant l'addició i l'adaptació dels nous casos per tal d'esdevenir un sistema de Raonament Basat en Casos. Es descriu l'estructura de la base de casos així com les tasques d'extracció, de reutilització, de revisió i de retenció, fent èmfasi al procés d'aprenentatge.
En el transcurs del text s'utilitzen diversos circuits per mostrar exemples dels mètodes de test descrits, però en particular el filtre biquadràtic és l'utilitzat per provar les metodologies plantejades, ja que és un dels benchmarks proposats en el context dels circuits analògics. Les falles considerades son paramètriques, permanents, independents i simples, encara que la metodologia pot ser fàcilment extrapolable per a la diagnosi de falles múltiples i catastròfiques. El mètode es centra en el test dels components passius, encara que també es podria extendre per a falles en els actius.
Testing circuits is a stage of the production process that is becoming more and more important when a new product is developed. Test and diagnosis techniques for digital circuits have been successfully developed and automated. But, this is not yet the case for analog circuits. Even though there are plenty of methods proposed for diagnosing analog electronic circuits, the most popular are the fault dictionary techniques. In this thesis some of these methods, showing their advantages and drawbacks, are analyzed.
During these last decades automating fault diagnosis using Artificial Intelligence techniques has become an important research field. This thesis develops two of these techniques in order to fill in some gaps in fault dictionaries techniques. The first proposal is to build a fuzzy system as an identification tool. The results obtained are quite good, since the faulty component is located in a high percentage of the given cases. On the other hand, the percentage of successes when determining the component's exact deviation is far from being good.
As fault dictionaries can be seen as a simplified approach to Case-Based Reasoning, the second proposal extends the fault dictionary towards a Case Based Reasoning system. The purpose is
not to give a general solution, but to contribute with a new methodology. This second proposal improves a fault dictionary diagnosis by means of adding and adapting new cases to develop a
Case Based Reasoning system. The case base memory, retrieval, reuse, revise and retain tasks are described. Special attention to the learning process is taken.
Several circuits are used to show examples of the test methods described throughout the text. But, in particular, the biquadratic filter is used to test the proposed methodology because it is
defined as one of the benchmarks in the analog electronic diagnosis domain. The faults considered are parametric, permanent, independent and simple, although the methodology can be extrapolated to catastrophic and multiple fault diagnosis. The method is only focused and tested on passive faulty components, but it can be extended to cover active devices as well.

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Le, Huy X. P. "Characterization of hot-carrier reliability in analog sub-circuit design." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/41379.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.
Includes bibliographical references (leaves 52-54).
by Huy X.P. Le.
M.Eng.

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Monzon, Joshua Jen C. "Analog VLSI circuit design of spike-timing-dependent synaptic plasticity." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/54636.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 61-63).
Synaptic plasticity is the ability of a synaptic connection to change in strength and is believed to be the basis for learning and memory. Currently, two types of synaptic plasticity exist. First is the spike-timing-dependent-plasticity (STDP), a timing-based protocol that suggests that the efficacy of synaptic connections is modulated by the relative timing between presynaptic and postsynaptic stimuli. The second type is the Bienenstock-Cooper-Munro (BCM) learning rule, a classical ratebased protocol which states that the rate of presynaptic stimulation modulates the synaptic strength. Several theoretical models were developed to explain the two forms of plasticity but none of these models came close in identifying the biophysical mechanism of plasticity. Other studies focused instead on developing neuromorphic systems of synaptic plasticity. These systems used simple curve fitting methods that were able to reproduce some types of STDP but still failed to shed light on the biophysical basis of STDP. Furthermore, none of these neuromorphic systems were able to reproduce the various forms of STDP and relate them to the BCM rule. However, a recent discovery resulted in a new unified model that explains the general biophysical process governing synaptic plasticity using fundamental ideas regarding the biochemical reactions and kinetics within the synapse. This brilliant model considers all types of STDP and relates them to the BCM rule, giving us a fresh new approach to construct a unique system that overcomes all the challenges that existing neuromorphic systems faced. Here, we propose a novel analog verylarge- scale-integration (aVLSI) circuit that successfully and accurately captures the whole picture of synaptic plasticity based from the results of this latest unified model. Our circuit was tested for all types of STDP and for each of these tests, our design was able to reproduce the results predicted by the new-found model. Two inputs are required by the system, a glutamate signal that carries information about the presynaptic stimuli and a dendritic action potential signal that contains information about the postsynaptic stimuli. These two inputs give rise to changes in the excitatory postsynaptic current which represents the modifiable synaptic efficacy output. Finally, we also present several techniques and alternative circuit designs that will further improve the performance of our neuromorphic system.
by Joshua Jen C. Monzon.
M.Eng.

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Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.

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The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.

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Pradhan, Almitra. "Accurate Analog Synthesis Based On Circuit Matrix Models." University of Cincinnati / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1258661691.

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Bagheri, Rajeoni Alireza. "ANALOG CIRCUIT SIZING USING MACHINE LEARNING BASED TRANSISTORCIRCUIT MODEL." University of Akron / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=akron1609428170125214.

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Killens, Jacob. "Utilizing standard CMOS process floating gate devices for analog design." Master's thesis, Mississippi State : Mississippi State University, 2001. http://library.msstate.edu/etd/show.asp?etd=etd-04092001-110957.

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ROTA, LUCIANO. "Implementation and Validation Methods for Electronic Integrated Circuits and Devices." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2023. https://hdl.handle.net/10281/404776.

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Negli ultimi tre decenni l'elettronica delle telecomunicazioni mobili ha subito un grande miglioramento, questo ramo dell'elettronica si è rivelato una delle principali forze trainanti nello sviluppo delle nuove tecnologie CMOS. in tutto il mondo richiedono dispositivi portatili estremamente performanti, più veloci, più affidabili, a basso consumo energetico. Questa situazione è diventata estremamente favorevole per lo sviluppo di dispositivi digitali ad alte prestazioni in grado di raggiungere velocità e capacità di memoria prima incredibili. Anche i blocchi di costruzione analogici devono essere integrati in nodi profondamente ridimensionati, al fine di adattarsi ai circuiti integrati digitali . Il primo compito di questo lavoro di tesi è stata l'implementazione e la misurazione di diversi circuiti integrati in due nodi tecnologici profondamente scalati come CMOS bulk a 28 nm e FinFET (Fin Field Effect Transistor) a 16 nm. In particolare, il secondo di questi introduce novità sulla struttura del transistor utilizzato per implementare i circuiti. Ciascun circuito realizzato incontra diverse difficoltà dovute al particolare comportamento di tali tecnologie avanzate, in particolare in termini di basso intrinsic gain e basso output voltage swing come conseguenza della bassa tensione di alimentazione. Ho lavorato nel progetto FinFET16 con il compito principale di realizzare e validare il layout di un filtro analogico Super-Source-Follower fully-differential del 4° ordine. Dopo le misurazioni, il filtro raggiunge 15,1 dBm IIP3 in banda a 10 MHz e toni di ingresso 11 MHz, con un consumo energetico di 968 µW da una singola tensione di alimentazione da 1 V. Il rumore integrato in banda è 85,78 µVrms per una figura di merito complessiva di 162,8 dB (j-1) che supera lo stato dell'arte dei filtri analogici. Ho anche collaborato come layoutista in altri due progetti realizzati con tecnologia CMOS a 28 nm. Il primo è stato il progetto PRIN Brain28nm che riguarda l'implementazione di una catena di acquisizione del segnale neurale. L'obiettivo di questo lavoro era la realizzazione di un biosensore che utilizza la struttura EOMOSFET con il nodo tecnologico CMOS a 28 nm. L'utilizzo di questa tecnologia rende questo circuito più competitivo rispetto ai biosensori presenti in letteratura. L'ultimo progetto è stato il progetto Pignoletto realizzato in collaborazione con RedCat Devices. Esso riguarda l'implementazione e l'analisi teorica di due diverse tipologie di circuiti integrati misurati sotto irraggiamento: due celle digitali e un convertitore da analogico a digitale. Nella seconda parte del mio terzo anno ho iniziato un'attività lavorativa presso la sede di Pavia della AMS come validation engineer. Questa azienda è leader mondiale nel campo dell'Automotive Interior Lightning. ll progetto che sto portando avanti prevede la realizzazione di un setup di validazione per un IC, al fine di verificare il corretto svolgimento delle molteplici funzioni per le quali questo chip è progettato. Una prima analisi, utile allo studio preliminare per la realizzazione del setup, è stata effettuata attraverso l'utilizzo di un FPGA su cui è stato caricato il codice che realizza la parte logica dell'IC utilizzando il software Quartus. Una volta validato il corretto funzionamento dell'FPGA, attraverso l'utilizzo di un microcontrollore STM32, sono state testate e correttamente validate diverse configurazioni e funzioni. Lo scopo finale di questa attività, che proseguirà nei prossimi mesi, è la validazione di alcune modalità di comunicazione tra diversi dispositivi, fondamentali per l'interfaccia dell'IC con gli standard automotive, e la creazione di una versione aggiornata del codice FPGA e della sua successiva verifica. Questa attività sembra essere una novità nel campo del design di circuiti integrati perché potrebbe permettere di evidenziare eventuali problemi.
In the last three decades Mobile Telecommunication (TLC) electronics has undergone a great improvement, this limited branch of electronics proved to be one of the major driving motor in the development of the new Complementary Metal-Oxide-Semiconductor (CMOS) technologies. People all around the world ask for extremely performing portable devices, faster, more reliable, low power consuming and with impressive memory capability. This situation has become extremely favorable for the development of high performance digital devices which are able to reach speed and memory capability previously unbelievable. Also analog building blocks must be integrated in deeply down-scaled node, in order to adapt with digital integrated circuits (ICs). First task of this thesis work was the implementation and measurement of different integrated circuits in two deep sub-micron technology nodes as 28nm bulk-CMOS and 16nm FinFET (Fin Field Effect Transistor). In particular the second one of these introduces novelty about the structure of transistor used to implement the circuits. Each circuit created faces various difficulties due to the particular behaviour of such advanced technologies, in particular in terms of low intrinsic gain and limited signal swing as consequence of low supply voltage. I worked in FinFET16 project with the main task to realize and validate the layout of a 4^th Order Fully-Differential Super-Source-Follower Analog Filter. After measurements the filter achieves 15.1 dBm in-band IIP3 at 10 MHz & 11 MHz input tones, with 968 µW power consumption from a single 1V supply voltage. In-band integrated noise is 85.78 µVrms for an overall Figure-of-Merit of 162.8 dB (j-1) which outperforms analog filters State-of-the-Art. I also collaborated as layoutist in other two projects realized with 28nm CMOS technology. The first one was the PRIN Brain28nm project that concerns the implementation of a neural signal acquisition chain. The goal of this work was the realization of a biosensor that uses the EOMOSFET structure with the 28nm CMOS technological node. The use of this technology makes this circuit more competitive when compared to the biosensors present in literature. The last one was Pignoletto project realized in collaboration with RedCat Devices. It concerns the implementation and theorical analysis of two different typologies of ICs measured under radiation: two digital cells and one Analog to Digital Converter. Under radiation measurements will be realize in January 2023. In the second part of my third year I started a work activity in Pavia site of AMS-Osram S.r.l as validation engineer. This company is a world leader in the field of optical sensors and the application of the latter in the automotive sector. The project I am carrying out involves the creation of a validation setup for an IC, in order to verify the correct performance of the multiple functions for which this chip is designed. A first analysis, useful for the preliminary study for the realization of the setup, was carried out through the use of an FPGA (Cyclone1000) on which the code that realizes the logic part of the IC was loaded using the Quartus software. Once the correct operation of the FPGA was validated, through the use of an STM32 micro-controller, various configurations and functions have been tested and correctly validated. The final purpose of this activity, which will continue in the coming months, is the validation of some communication methods between different devices, fundamental for the interface of the IC with automotive standards, and the creation of an updated version of the FPGA code and its subsequent verification. This activity appears to be a novelty in the field of integrated circuit design as it would allow to highlight problems and malfunctions of the circuit.

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O'Halloran, Micah G. (Micah Galletta) 1978. "A clock-based analog memory element for integrated circuits." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/87317.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
Includes bibliographical references (leaves 117-118).
by Micah G. O'Halloran.
S.M.

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El-Gamal, Mohamed A. "Fault location and parameter identification in analog circuits." Ohio : Ohio University, 1990. http://www.ohiolink.edu/etd/view.cgi?ohiou1172776742.

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Nalbantis, Dimitris. "World Wide Web based layout synthesis for analogue modules." Thesis, University of Kent, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.365218.

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Dai, Hong. "Development of a decomposition approach for testing large analog circuits." Ohio : Ohio University, 1989. http://www.ohiolink.edu/etd/view.cgi?ohiou1172006982.

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Dissertations / Theses on the topic 'Electric circuit analogie'

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