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Journal articles on the topic 'Efficient software implementation'

Author: Grafiati

Published: 25 May 2024

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1

Palsberg, Jens, Cun Xiao, and Karl Lieberherr. "Efficient implementation of adaptive software." ACM Transactions on Programming Languages and Systems 17, no. 2 (March 1995): 264–92. http://dx.doi.org/10.1145/201059.201066.

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2

Taghipour, Mohammad. "Implementation of Software-Efficient DES Algorithm." Advances in Networks 3, no. 3 (2015): 7. http://dx.doi.org/10.11648/j.net.s.2015030301.12.

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3

Shamsabad, Mohammad Reza Mirzaee, and Seyed Mojtaba Dehnavi. "Dynamic MDS diffusion layers with efficient software implementation." International Journal of Applied Cryptography 4, no. 1 (2020): 36. http://dx.doi.org/10.1504/ijact.2020.10029198.

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Shamsabad, Mohammad Reza Mirzaee, and Seyed Mojtaba Dehnavi. "Dynamic MDS diffusion layers with efficient software implementation." International Journal of Applied Cryptography 4, no. 1 (2020): 36. http://dx.doi.org/10.1504/ijact.2020.107164.

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5

Hernek, Diane, and David P. Anderson. "Efficient automated protocol implementation using RTAG." Software: Practice and Experience 20, no. 9 (September 1990): 869–85. http://dx.doi.org/10.1002/spe.4380200903.

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6

López-Parrado, Alexander, and Jaime Velasco Medina. "Efficient Software Implementation of the Nearly Optimal Sparse Fast Fourier Transform for the Noisy Case." Ingeniería y Ciencia 11, no. 22 (July 31, 2015): 73–94. http://dx.doi.org/10.17230/ingciencia.11.22.4.

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In this paper we present an optimized software implementation (sFFT-4.0)of the recently developed Nearly Optimal Sparse Fast Fourier Transform (sFFT) algorithm for the noisy case. First, we developed a modified versionof the Nearly Optimal sFFT algorithm for the noisy case, this modified algorithm solves the accuracy issues of the original version by modifying theflat window and the procedures; and second, we implemented the modifiedalgorithm on a multicore platform composed of eight cores. The experi-mental results on the cluster indicate that the developed implementation isfaster than direct calculation using FFTW library under certain conditions of sparseness and signal size, and it improves the execution times of previous implementations like sFFT-2.0. To the best knowledge ofthe authors,the developed implementation is the first one of the Nearly Optimal sFFT algorithm for the noisy case.

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Liu, Zhe, Reza Azarderakhsh, Howon Kim, and Hwajeong Seo. "Efficient Software Implementation of Ring-LWE Encryption on IoT Processors." IEEE Transactions on Computers 69, no. 10 (October 1, 2020): 1424–33. http://dx.doi.org/10.1109/tc.2017.2750146.

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Guajardo, Jorge, Sandeep S. Kumar, Christof Paar, and Jan Pelzl. "Efficient Software-Implementation of Finite Fields with Applications to Cryptography." Acta Applicandae Mathematicae 93, no. 1-3 (August 2, 2006): 3–32. http://dx.doi.org/10.1007/s10440-006-9046-1.

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9

del Campo, I., J. Echanobe, G. Bosque, and J. M. Tarela. "Efficient Hardware/Software Implementation of an Adaptive Neuro-Fuzzy System." IEEE Transactions on Fuzzy Systems 16, no. 3 (June 2008): 761–78. http://dx.doi.org/10.1109/tfuzz.2007.905918.

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10

Alpern, Bowen, Anthony Cocchi, Stephen Fink, and David Grove. "Efficient implementation of Java interfaces." ACM SIGPLAN Notices 36, no. 11 (November 2001): 108–24. http://dx.doi.org/10.1145/504311.504291.

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Alomar, M. L., Erik S. Skibinsky-Gitlin, Christiam F. Frasser, Vincent Canals, Eugeni Isern, Miquel Roca, and Josep L. Rosselló. "Efficient parallel implementation of reservoir computing systems." Neural Computing and Applications 32, no. 7 (December 6, 2018): 2299–313. http://dx.doi.org/10.1007/s00521-018-3912-4.

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12

Anikeev, F. A., G. O. Raiko, E. E. Limonova, M. A. Aliev, and D. P. Nikolaev. "Efficient Implementation of Fast Hough Transform Using CPCA Coprocessor." Programming and Computer Software 47, no. 5 (September 2021): 335–43. http://dx.doi.org/10.1134/s0361768821050029.

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Barladian, Boris, Vladimir Frolov, Vladimir Galaktionov, Vladimir Knyaz’, Igor Koverninskii, Lev Shapiro, Yuri Solodelov, and Alexey Voloboy. "Efficient Implementation of OpenGL SC for Avionics Embedded Systems." Программирование, no. 4 (2018): 3–10. http://dx.doi.org/10.31857/s013234740000519-5.

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Barladian, B. Kh, A. G. Voloboy, V. A. Galaktionov, V. V. Knyaz’, I. V. Koverninskii, Yu A. Solodelov, V. A. Frolov, and L. Z. Shapiro. "Efficient Implementation of OpenGL SC for Avionics Embedded Systems." Programming and Computer Software 44, no. 4 (July 2018): 207–12. http://dx.doi.org/10.1134/s0361768818040059.

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15

Kim, Hyunjun, Siwoo Eum, Minjoo Sim, and Hwajeong Seo. "Efficient Implementation of SPEEDY Block Cipher on Cortex-M3 and RISC-V Microcontrollers." Mathematics 10, no. 22 (November 13, 2022): 4236. http://dx.doi.org/10.3390/math10224236.

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The SPEEDY block cipher family announced at the CHES 2021 shows excellent performance on hardware architectures. Due to the nature of the hardware-friendly design of SPEEDY, the algorithm has low performance for software implementations. In particular, 6-bit S-box and bit permutation operations of SPEEDY are inefficient in software implementations, where it performs word-wise computations. We implemented the SPEEDY block cipher on a 32-bit microcontroller for the first time by applying the bit-slicing techniques. The optimized encryption performance results on ARM Cortex-M3 for SPEEDY-5-192, SPEEDY-6-192, and SPEEDY-7-192 are 65.7, 75.25, and 85.16 clock cycles per byte (i.e., cpb), respectively. It showed better performance than AES-128 constant-time implementation and GIFT constant-time implementation in the same platform. In RISC-V, the performance showed 81.9, 95.5, and 109.2 clock cycles per byte, which outperformed the previous works. Finally, we conclude that SPEEDY can show efficient software implementation on low-end embedded environments.

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Hung-Yu Chien, Hung-Yu Chien, and Pin-Ping Ciou Hung-Yu Chien. "Design and Implementation of Efficient IoT Authentication Schemes for MQTT 5.0." 網際網路技術學刊 24, no. 3 (May 2023): 665–74. http://dx.doi.org/10.53106/160792642023052403012.

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<p>MQTT (Message Queue Telemetry Transport) is one of the most popular Internet of Things (IoT) communication protocols, owing to its lightweight and easiness to use. The previous MQTT standards (including version 3.1 and its precedents) do not provide proper security functions; instead, they assume the adoption of SSL/TLS in the underlying layer. However, it not only incurs larger overhead but also hinders the development of suitable authentication/confidentiality protection to suit various MQTT deployment scenarios. The newest MQTT standard called MQTT 5.0 responds to these challenges by supporting the Enhanced Authentication framework in which designers can design and implement any secure authentication mechanisms within the framework. This paper designs and implements two efficient authentication protocols, using the MQTT 5.0 Enhanced Authentication framework. One is simple challenge-response authentication scheme, and the other is an anonymous challenge-response authentication scheme. We extend HiveMQ platform to implement the schemes and evaluate the performance. The results show that the proposed schemes demand only hundred few more milliseconds to achieve much robust authentication, compared to the simple identity-password authentication.</p> <p> </p>

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17

Yang, Jian Zhong, Tao Li, Qing Song, Dong Chen, and Ji Hong Chen. "Research and Implementation of OEM-Software for Pilger-Roller Processing." Applied Mechanics and Materials 437 (October 2013): 752–60. http://dx.doi.org/10.4028/www.scientific.net/amm.437.752.

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The processing of complicated surface is always a tough job in multi-axis machining. Pilger-roller is a kind of tool molds with complicated surface. To process the complicated grooved-surface of Pilger-roller, an algorithm, which included grooved-surface modeling, tool-path planning and cutter location (CL) computation, is proposed and implemented. The tool-path generated by this algorithm is smooth and has no interference. In order to meet the demand of Pilger-roller processing in efficiency and automation, automatically-processing software is developed based on Original Equipment Manufacturer (OEM). Compared with the conventional methods, this software makes the online programming visualized and efficient. This software has been applied to actual production and could meet the commercial requirement.

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18

Bernaschi, Massimo, Giulio Iannello, and Mario Lauria. "Efficient implementation of reduce-scatter in MPI." Journal of Systems Architecture 49, no. 3 (August 2003): 89–108. http://dx.doi.org/10.1016/s1383-7621(03)00059-6.

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19

Barreto, Paulo S. L. M., Ben Lynn, and Michael Scott. "Efficient Implementation of Pairing-Based Cryptosystems." Journal of Cryptology 17, no. 4 (September 2004): 321–34. http://dx.doi.org/10.1007/s00145-004-0311-z.

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20

Atri, Mohamed, Fatma Sayadi, Wajdi Elhamzi, and Rached Tourki. "Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications." Journal of Signal and Information Processing 03, no. 01 (2012): 122–29. http://dx.doi.org/10.4236/jsip.2012.31016.

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21

Delgado-Mohatar, Oscar, Amparo Fúster-Sabater, and José M. Sierra. "Performance evaluation of highly efficient techniques for software implementation of LFSR." Computers & Electrical Engineering 37, no. 6 (November 2011): 1222–31. http://dx.doi.org/10.1016/j.compeleceng.2011.04.002.

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22

Kamboj, Bindiya, and Rajesh Mehra. "Efficient FPGA Implementation of Direct Digital Frequency Synthesizer for Software Radios." International Journal of Computer Applications 37, no. 10 (January 28, 2012): 25–29. http://dx.doi.org/10.5120/4645-6714.

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23

NAKAJIMA, T., T. IZU, and T. TAKAGI. "Reduction Optimal Trinomials for Efficient Software Implementation of the T Pairing." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A, no. 9 (September 1, 2008): 2379–86. http://dx.doi.org/10.1093/ietfec/e91-a.9.2379.

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24

Mahdiani, H. R., A. Banaiyan, M. Haji Seyed Javadi, S. M. Fakhraie, and C. Lucas. "Defuzzification block: New algorithms, and efficient hardware and software implementation issues." Engineering Applications of Artificial Intelligence 26, no. 1 (January 2013): 162–72. http://dx.doi.org/10.1016/j.engappai.2012.07.001.

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25

Kumar, Nagendra J., Vasanth Asokan, Siddhartha Shivshankar, and Alexander G. Dean. "Efficient software implementation of embedded communication protocol controllers using asynchronous software thread integration with time- and space-efficient procedure calls." ACM Transactions on Embedded Computing Systems 6, no. 1 (February 2007): 2. http://dx.doi.org/10.1145/1210268.1210270.

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26

Hidayatullah, Kharisma Rizki, and Hadiq Hadiq. "Efficient Software Development Process Using Component-Based and ORM." CCIT Journal 17, no. 1 (February 29, 2024): 70–87. http://dx.doi.org/10.33050/ccit.v17i1.2822.

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The software development process has many variations. Each software development technique has its own advantages and disadvantages. There are efficient development processes and some could be more efficient. This research aims to build a web-based application efficiently utilizing component-based and ORM with a case study of financial management applications on community radio. This research begins with data collection through observations and interviews, requirement analysis, and system design, implementation, and testing. This research shows that combining component-based software development and object-relational mapping (ORM) can increase software development efficiency compared to non-component-based and pure SQL.

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27

Ramos, Jorge R., and Vernon Rego. "Efficient implementation of multiprocessor scheduling algorithms on a simulation testbed." Software: Practice and Experience 35, no. 1 (January 2005): 27–50. http://dx.doi.org/10.1002/spe.625.

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28

Nieminen, Janne, and Pekka Kilpeläinen. "Efficient implementation of Aho–Corasick pattern matching automata using Unicode." Software: Practice and Experience 37, no. 6 (2007): 669–90. http://dx.doi.org/10.1002/spe.785.

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29

Kermarrec, A. M., C. Morin, and M. Banâtre. "Design, implementation and evaluation of ICARE: an efficient recoverable DSM." Software: Practice and Experience 28, no. 9 (July 25, 1998): 981–1010. http://dx.doi.org/10.1002/(sici)1097-024x(19980725)28:9<981::aid-spe182>3.0.co;2-x.

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30

Narlikar, Girija J., and Guy E. Blelloch. "Space-efficient implementation of nested parallelism." ACM SIGPLAN Notices 32, no. 7 (July 1997): 25–36. http://dx.doi.org/10.1145/263767.263770.

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31

Ngan, N., E. Dokladalova, M. Akil, and F. Contou-Carrère. "Fast and efficient FPGA implementation of connected operators." Journal of Systems Architecture 57, no. 8 (September 2011): 778–89. http://dx.doi.org/10.1016/j.sysarc.2011.06.002.

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32

Johansson, Fredrik. "Efficient implementation of the Hardy–Ramanujan–Rademacher formula." LMS Journal of Computation and Mathematics 15 (October 1, 2012): 341–59. http://dx.doi.org/10.1112/s1461157012001088.

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AbstractWe describe how the Hardy–Ramanujan–Rademacher formula can be implemented to allow the partition function p(n) to be computed with softly optimal complexity O(n1/2+o(1)) and very little overhead. A new implementation based on these techniques achieves speedups in excess of a factor 500 over previously published software and has been used by the author to calculate p(1019), an exponent twice as large as in previously reported computations. We also investigate performance for multi-evaluation of p(n), where our implementation of the Hardy–Ramanujan–Rademacher formula becomes superior to power series methods on far denser sets of indices than previous implementations. As an application, we determine over 22 billion new congruences for the partition function, extending Weaver’s tabulation of 76 065 congruences. Supplementary materials are available with this article.

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33

Mazurkiewicz, Tomasz. "An efficient hardware implementation of a combinations generator." Technical Sciences 4, no. 20 (October 2, 2017): 405–13. http://dx.doi.org/10.31648/ts.5436.

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In this paper an area-efficient hardware implementation of a Bincombgen algorithm was presented. This algorithm generates all (n,k) combinations in the form of binary vectors. The generator was implemented using Verilog language and synthesized using Xilinx and Intel-Altera software. Some changes were applied to the original code, which allows our FPGA implementation to be more efficient than in the previously published papers. The usage of chip resources and maximum clock frequency for different values of n and k parameters are presented.

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34

Grineva, M. P., and M. N. Grinev. "Query triggers for XML DBMS: Efficient implementation based on shadow mechanism." Programming and Computer Software 33, no. 4 (July 2007): 204–13. http://dx.doi.org/10.1134/s0361768807040032.

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35

ISSAD, M., B. BOUDRAA, M. ANANE, and N. ANANE. "SOFTWARE/HARDWARE CO-DESIGN OF MODULAR EXPONENTIATION FOR EFFICIENT RSA CRYPTOSYSTEM." Journal of Circuits, Systems and Computers 23, no. 03 (March 2014): 1450032. http://dx.doi.org/10.1142/s0218126614500327.

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This paper presents an implementation of Rivest, Shamir and Adleman (RSA) cryptosystem based on hardware/software (HW/SW) co-design. The main operation of RSA is the modular exponentiation (ME) which is performed by repeated modular multiplications (MMs). In this work, the right-to-left (R2L) algorithm is used for the implementation of the ME as a programmable system on chip (PSoC). The processor MicroBlaze of Xilinx is used for flexibility. The R2L method is often suggested to improve the timing performance, since it is based on parallel computations of MMs. However, if the optimization of HW resources is a constraint, this method can be executed sequentially using a single modular multiplier as a custom intellectual property (IP). Consequently, the execution time of the ME becomes dependent of three factors, namely the capability of the custom IP to perform the MMs, the nonzero bit string of the exponent and the communication link between the processor and the custom IP. In order to achieve the best trade-off between area, speed and flexibility, we propose three implementations in this work. The first one is a pure software solution. The second one takes benefit of a HW accelerator dedicated to the MM execution. The last one is based on a dual strategy. Two parallel MMs are implemented within a custom IP and local memories are used close to the arithmetic units to minimize the communication link influence. The results show that in the application to RSA 1024-bits, the ME runs in 22,25 ms, while using only 1,848 slices.

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Gao, Pengfei, Hongyi Xie, Fu Song, and Taolue Chen. "A Hybrid Approach to Formal Verification of Higher-Order Masked Arithmetic Programs." ACM Transactions on Software Engineering and Methodology 30, no. 3 (May 2021): 1–42. http://dx.doi.org/10.1145/3428015.

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Side-channel attacks, which are capable of breaking secrecy via side-channel information, pose a growing threat to the implementation of cryptographic algorithms. Masking is an effective countermeasure against side-channel attacks by removing the statistical dependence between secrecy and power consumption via randomization. However, designing efficient and effective masked implementations turns out to be an error-prone task. Current techniques for verifying whether masked programs are secure are limited in their applicability and accuracy, especially when they are applied. To bridge this gap, in this article, we first propose a sound type system, equipped with an efficient type inference algorithm, for verifying masked arithmetic programs against higher-order attacks. We then give novel model-counting-based and pattern-matching-based methods that are able to precisely determine whether the potential leaky observable sets detected by the type system are genuine or simply spurious. We evaluate our approach on various implementations of arithmetic cryptographic programs. The experiments confirm that our approach outperforms the state-of-the-art baselines in terms of applicability, accuracy, and efficiency.

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37

Bagrodia, Rajive, and Sharad Mathur. "Efficient Implementation of high-level parallel programs." ACM SIGPLAN Notices 26, no. 4 (April 2, 1991): 142–51. http://dx.doi.org/10.1145/106973.376053.

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38

You, Cheng-Hwee, Jianying Zhou, and Kwok-Yan Lam. "On the efficient implementation of fair non-repudiation." ACM SIGCOMM Computer Communication Review 28, no. 5 (October 1998): 50–60. http://dx.doi.org/10.1145/303297.303305.

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39

STRUHARIK, RASTISLAV J. R., and LADISLAV A. NOVAK. "EVOLVING DECISION TREES IN HARDWARE." Journal of Circuits, Systems and Computers 18, no. 06 (October 2009): 1033–60. http://dx.doi.org/10.1142/s0218126609005526.

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This paper, according to the best of our knowledge, provides the very first solution to the hardware implementation of the complete decision tree inference algorithm. Evolving decision trees in hardware is motivated by a significant improvement in the evolution time compared to the time needed for software evolution and efficient use of decision trees in various embedded applications (robotic navigation systems, image processing systems, etc.), where run-time adaptive learning is of particular interest. Several architectures for the hardware evolution of single oblique or nonlinear decision trees and ensembles comprised from oblique or nonlinear decision trees are presented. Proposed architectures are suitable for the implementation using both Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Results of experiments obtained using 29 datasets from the standard UCI Machine Learning Repository database suggest that the FPGA implementations offer significant improvement in inference time when compared with the traditional software implementations. In the case of single decision tree evolution, FPGA implementation of H_DTS2 architecture has on average 26 times shorter inference time when compared to the software implementation, whereas FPGA implementation of H_DTE2 architecture has on average 693 times shorter inference time than the software implementation.

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Ramabhadran, Sriram, and George Varghese. "Efficient implementation of a statistics counter architecture." ACM SIGMETRICS Performance Evaluation Review 31, no. 1 (June 10, 2003): 261–71. http://dx.doi.org/10.1145/885651.781060.

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41

Chirilă, Ciprian C., and T. M. H. Ha. "FXRS: Fast X-Ray Spectrum-Simulator Theory and Software Implementation." Communications in Computational Physics 21, no. 5 (April 26, 2017): 1475–88. http://dx.doi.org/10.4208/cicp.oa-2015-0011.

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AbstractWe propose a simple, computationally efficient scheme for an X-ray spectrum simulator. The theoretical models describing the physical processes involved are employed in our Monte Carlo software in a coherent way, paving the way for straightforward future improvements. Our results compare satisfactorily to experimental results from literature and to results from dedicated simulation software. The simplicity, excellent statistical errors, and short execution time of our code recommend it for intensive use in X-ray generation simulations.

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42

Heredero, C. De Pablos, and D. López Berzosa. "Free Software Implementation Experiences for the Promotion of the Liquid Society." International Journal of Digital Literacy and Digital Competence 1, no. 3 (July 2010): 36–47. http://dx.doi.org/10.4018/jdldc.2010070104.

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Information and communication technologies have changed the way in which citizens interact with Public Administrations. Digital literacy is key for the development of the Liquid Society, and Public Administrations must take the lead in promoting more efficient, universal, and user oriented public services. The migration to open source standards allows Public Administration to offer more democratic, universal, and efficient channels for establishing relationships with citizens. In this article, the authors present international experiences that show how certain Public Administrations have migrated to open source software to promote digital literacy in the contexts they are operating. The final results depend on contextual and organizational factors, including the need to change, the political support and the existence of available technological resources, the organizational climate, motivation levels of human resources, and the kind of leadership for the project or the organizational complexity. Change efforts have strategic and organizational impacts that the organization must evaluate beforehand.

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43

Lei, Shanwen. "Analysis and Implementation of a Simple Database Management Software Based on Python and Excel." Academic Journal of Science and Technology 10, no. 3 (April 27, 2024): 99–105. http://dx.doi.org/10.54097/k9c58g42.

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This paper aims to address the challenges faced by small and medium-sized enterprises (SMEs) and individual users in database management. It adopts a combination of Python and Excel to simplify the operational process and enhance the user interface, thereby reducing the learning curve and technical requirements for managing databases. Users can effortlessly manage their databases, leading to improved work efficiency. This project breaks through the limitations of traditional database management software, offering a simple, efficient, and low-resource solution.

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44

Fuentes-Alventosa, Antonio, Juan Gómez-Luna, José Maria González-Linares, Nicolás Guil, and R. Medina-Carnicer. "CAVLCU: an efficient GPU-based implementation of CAVLC." Journal of Supercomputing 78, no. 6 (November 29, 2021): 7556–90. http://dx.doi.org/10.1007/s11227-021-04183-8.

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AbstractCAVLC (Context-Adaptive Variable Length Coding) is a high-performance entropy method for video and image compression. It is the most commonly used entropy method in the video standard H.264. In recent years, several hardware accelerators for CAVLC have been designed. In contrast, high-performance software implementations of CAVLC (e.g., GPU-based) are scarce. A high-performance GPU-based implementation of CAVLC is desirable in several scenarios. On the one hand, it can be exploited as the entropy component in GPU-based H.264 encoders, which are a very suitable solution when GPU built-in H.264 hardware encoders lack certain necessary functionality, such as data encryption and information hiding. On the other hand, a GPU-based implementation of CAVLC can be reused in a wide variety of GPU-based compression systems for encoding images and videos in formats other than H.264, such as medical images. This is not possible with hardware implementations of CAVLC, as they are non-separable components of hardware H.264 encoders. In this paper, we present CAVLCU, an efficient implementation of CAVLC on GPU, which is based on four key ideas. First, we use only one kernel to avoid the long latency global memory accesses required to transmit intermediate results among different kernels, and the costly launches and terminations of additional kernels. Second, we apply an efficient synchronization mechanism for thread-blocks (In this paper, to prevent confusion, a block of pixels of a frame will be referred to as simply block and a GPU thread block as thread-block.) that process adjacent frame regions (in horizontal and vertical dimensions) to share results in global memory space. Third, we exploit fully the available global memory bandwidth by using vectorized loads to move directly the quantized transform coefficients to registers. Fourth, we use register tiling to implement the zigzag sorting, thus obtaining high instruction-level parallelism. An exhaustive experimental evaluation showed that our approach is between 2.5$$\times$$ × and 5.4$$\times$$ × faster than the only state-of-the-art GPU-based implementation of CAVLC.

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45

Park, Sang-Hyeun, and Johannes Fürnkranz. "Efficient implementation of class-based decomposition schemes for Naïve Bayes." Machine Learning 96, no. 3 (January 1, 2014): 295–309. http://dx.doi.org/10.1007/s10994-013-5430-z.

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46

POWELL, D. G., and A. G. J. HOLT. "Hardware and software implementation of a hardware efficient beamformer for underwater acoustic communications." International Journal of Electronics 78, no. 1 (January 1995): 77–100. http://dx.doi.org/10.1080/00207219508926141.

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47

Hua, Shaoxiong, Gang Qu, and Shuvra S. Bhattacharyya. "Energy-efficient embedded software implementation on multiprocessor system-on-chip with multiple voltages." ACM Transactions on Embedded Computing Systems 5, no. 2 (May 2006): 321–41. http://dx.doi.org/10.1145/1151074.1151078.

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48

Domagała, Adam, Katarzyna Grobler-Dębska, Jarosław Wąs, and Edyta Kucharska. "Post-Implementation ERP Software Development: Upgrade or Reimplementation." Applied Sciences 11, no. 11 (May 27, 2021): 4937. http://dx.doi.org/10.3390/app11114937.

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The paper deals with problems in the post-implementation phase of management Enterprise Resource Planning (ERP) systems. Proper management of the system maintenance stage is a basis for efficient system development in terms of business needs. Based on the research and analysis of collected materials, it turns out that making a decision to upgrade the system is equally crucial. We present revealed mechanisms determining the post-implementation approach to upgrade or reimplement the ERP system. The main aim is to determine the methodology and difference understanding to achieve success in the post-implementation stage. The paper shows that the systemic approach to the maintenance stage of the ERP system affects its further decisions: upgrade or reimplement. It has a direct impact on future maintenance costs and the scope of new business demands. This research is an outcome of industry–academia collaboration and based on several developed implementation systems, achieved upgrade and reimplementation projects. Based on case study analysis, we show that reimplementation means an evolution of the current ERP processes rather than another attempt to “reimplement” an unsuccessful system implementation. On the other hand, upgrades are not only a tool or system actualization but the easiest way to bolster company sustainability and to have the information system up to date. The issues discussed in the article will be used to develop changes in the implementation methodology of ERP systems.

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Mileff, Péter, and Judit Dudra. "Effective Pixel Rendering in Practice." Production Systems and Information Engineering 10, no. 1 (2022): 1–15. http://dx.doi.org/10.32968/psaie.2022.1.1.

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The graphics processing unit (GPU) has now become an integral part of our lives through both desktop and portable devices. Thanks to dedicated hardware, visualization has been significantly accelerated, softwares today only use the GPU for rasterization. As a result of this development, now we use only triangle-based rendering, and pixel-based image manipulations can only be performed using shaders. It can be stated that today’s GPU pipeline cannot provide the same flexibility as the previous software implementation. This paper discusses an efficient software implementation of pixel-based rasterization. After reviewing the current GPU-based drawing process, we will show how to access pixel level drawing in this environment. Finally, a more efficient storage and display format than the classic solution is presented, which performance far exceeds the previous solution.

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Zhang, Weiguo, Shuanggen Liu, and Huawei Huang. "An efficient implementation algorithm for generating de Bruijn sequences." Computer Standards & Interfaces 31, no. 6 (November 2009): 1190–91. http://dx.doi.org/10.1016/j.csi.2008.12.001.

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