Dissertations / Theses on the topic 'Efficient implementation for HBVM'
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King, Myron Decker. "An efficient sequential BTRS implementation." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/46603.
Full textIncludes bibliographical references (leaves 73-74).
This thesis describes the implementation of BTRS, a language based on guarded atomic actions (GAA). The input language to the compiler which forms the basis of this work is a hierarchical tree of modules containing state, interface methods, and rules which fire atomically to cause state transitions. Since a schedule need not be specified, the program description is inherently nondeterministic, though the BTRS language does allow the programmer to remove nondeterminism by specifying varying degrees of scheduling constraints. The compiler outputs a (sequential) single-threaded C implementation of the input description, choosing a static schedule which adheres to the input constraints. The resulting work is intended to be used as the starting point for research into efficient software synthesis from guarded atomic actions, and ultimately a hardware inspired programming methodology for writing parallel software. This compiler is currently being used to generate software for a heterogeneous system in which the software and hardware components are both specified in BTRS.
by Myron Decker King.
S.M.
Patel, Nirav B. "Voronoi diagrams robust and efficient implementation /." Diss., Online access via UMI:, 2005.
Find full textStenman, Erik. "Efficient Implementation of Concurrent Programming Languages." Doctoral thesis, Uppsala University, Department of Information Technology, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-2688.
Full textDissertation in Computer Science to be publicly examined in Häggsalen, Ångströmlaboratoriet, Uppsala University, on Friday, November 1, 2002 at 1:00 pm for the degree of doctor of philosophy. The examination will be conducted in English.
This thesis proposes and experimentally evaluates techniques for efficient implementation of languages designed for high availability concurrent systems. This experimental evaluation has been done while developing the High Performance Erlang (HiPE) system, a native code compiler for SPARC and x86. The two main goals of the HiPE system are to provide efficient execution of Erlang programs, and to provide a research vehicle for evaluating implementation techniques for concurrent functional programming languages.
The focus of the thesis is the evaluation of two techniques that enable inter-process optimization through dynamic compilation. The first technique is a fast register allocator called linear scan, and the second is a memory architecture where processes share memory.
The main contributions of the thesis are:
An evaluation of linear scan register allocation in a different language setting. In addition the performance of linear scan on the register poor x86 architecture is evaluated for the first time.
A description of three different heap architectures (private heaps, shared heap, and a hybrid of the two), with a systematic investigation of implementation aspects and an extensive discussion on the associated performance trade-offs of the heap architectures. The description is accompanied by an experimental evaluation of the private vs. the shared heap setting.
A novel approach to optimizing a concurrent program, by merging code from a sender with code from a receiver, is presented together with other methods for reducing the overhead of context switching.
A description of the implementation aspects of a complete and robust native code Erlang system, which makes it possible to test compiler optimizations on real world programs.
ALVES, ROGERIO GUEDES. "EFFICIENT MULTI-RATE SYSTEM IMPLEMENTATION FORMS." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 1993. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=8692@1.
Full textInicialmente apresenta-se a estrutura de um sistema Multi- taxa, faz-se uma revisão teórica do mesmo, e descreve-se seu funcionamento. Posteriormente são apresentadas várias formas de implementar este sistema, como realizá-lo no domínio do tempo, parte no domínio do tempo e parte no domínio da freqüência e realizá-lo no domínio da freqüência. Nestas formas de implementação são considerados fatores como: emprego da técnica de overlap- save ou overlap-add para realização da convolução a ser implementada no sistema, e utilização de filtros do tipo IIR ou FIR para realizar o filtro de reconstrução. Nos sistemas implementados das diversas formas são analisados o atraso e a complexidade comparando-se os resultados teóricos obtidos. Nestas diferentes formas de implementação são mostrados sistemas com particularidades interessantes como: implementação da interpolação no domínio da freqüência e utilização de uma FFT inversa voltada para interpolação e decimação. Finalmente são apresentados resultados práticos dos sistemas realizados, sendo estes avaliados, comparados com os teóricos e comentados.
Firstly, a multi-rate system structure is presented, a theorical review is made and its behavior is described. Afterwards, many forms of its implementation are presented: in time domain, mixed time domain and frequency domain; and in the frequency domain only. In those implementation some factors are taken into account, such as the use of the overlap-save and overlap- add techniques for the convolution, and the utilization of IIR or FIR structures as reconstruction filters. In the system implemented, the delay and complexity are analised, by the comparing to the theorical results. Some interesting results are show, such as the implementation of the frequency domain interpolation and the use of an inverse FFT dedicated to decimation and interpolation. Finally, pratical results of the implemented system are presented. These are evaluated, compared to the theorical ones and commented upon.
Mahdi, Abdul-Hussain Ebrahim. "Efficient generalized transform algorithms for digital implementation." Thesis, Bangor University, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.277612.
Full textWojtczak, Dominik. "Recursive probabilistic models : efficient analysis and implementation." Thesis, University of Edinburgh, 2009. http://hdl.handle.net/1842/3217.
Full textTaylor, David Eirik. "Efficient Implementation of Cross-Correlation in Hardware." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2014. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-25839.
Full textAbdoel-Gawad, Farag Saleh. "Efficient hardware implementation of the CORDIC algorithm." Thesis, Liverpool John Moores University, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299066.
Full textFan, Yanan. "Efficient implementation of Markov chain Monte Carlo." Thesis, University of Bristol, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.343307.
Full textJerez, Juan Luis. "Custom optimization algorithms for efficient hardware implementation." Thesis, Imperial College London, 2013. http://hdl.handle.net/10044/1/12791.
Full textSustarsic, Alissa Michele. "An Efficient Implementation of the Transportation Problem." UNF Digital Commons, 1999. http://digitalcommons.unf.edu/etd/81.
Full textNau, Lee J. "A Scalable, Memory Efficient Multicore TEIRESIAS Implementation." Ohio University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1306856233.
Full textUlis, Bradley J. "Stereo image correspondence methods for efficient hardware implementation." Thesis, Monterey, California : Naval Postgraduate School, 2010. http://edocs.nps.edu/npspubs/scholarly/theses/2010/Jun/10Jun%5FUlis.pdf.
Full textThesis Advisor(s): Cristi, Roberto ; Second Reader: Fargues, Monique P. "June 2010." Description based on title screen as viewed on July 14, 2010. Author(s) subject terms: Stereo Correspondence, Ordinal Measures, 3D Reconstruction, Dynamic Programming. Includes bibliographical references (p. 75-77). Also available in print.
Johansson, John. "Efficient implementation of the Particle Level Set method." Thesis, Linköping University, Media and Information Technology, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-59579.
Full textThe Particle Level set method is a successful extension to Level set methods to improve thevolume preservation in fluid simulations. This thesis will analyze how sparse volume data structures can be used to store both the signed distance function and the particles in order to improve access speed and memory efficiency. This Particle Level set implementation will be evaluated against Digital Domains current Particle Level set implementation. Different degrees of quantization will be used to implement particle representations with varying accuracy. These particles will be tested and both visual results and error measurments will be presented. The sparse volume data structures DB-Grid and Field3D will be evaluated in terms of speed and memory efficiency.
Sims, Oliver. "Efficient implementation of video processing algorithms on FPGA." Thesis, University of Glasgow, 2007. http://theses.gla.ac.uk/4119/.
Full textWei, Dennis. "Design of discrete-time filters for efficient implementation." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66470.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (p. 325-333).
The cost of implementation of discrete-time filters is often strongly dependent on the number of non-zero filter coefficients or the precision with which the coefficients are represented. This thesis addresses the design of sparse and bit-efficient filters under different constraints on filter performance in the context of frequency response approximation, signal estimation, and signal detection. The results have applications in several areas, including the equalization of communication channels, frequency-selective and frequency-shaping filtering, and minimum-variance distortionless-response beamforming. The design problems considered admit efficient and exact solutions in special cases. For the more difficult general case, two approaches are pursued. The first develops low-complexity algorithms that are shown to yield optimal or near-optimal designs in many instances, but without guarantees. The second focuses on optimal algorithms based on the branch-and-bound procedure. The complexity of branch-and-bound is reduced through the use of bounds that are good approximations to the true optimal cost. Several bounding methods are developed, many involving relaxations of the original problem. The approximation quality of the bounds is characterized and efficient computational methods are discussed. Numerical experiments show that the bounds can result in substantial reductions in computational complexity.
by Dennis Wei.
Ph.D.
Honorato, Mauro Jacob. "Wam based space efficient Prolog implementation in Lisp." Universidade Federal de Uberlândia, 2015. https://repositorio.ufu.br/handle/123456789/17800.
Full textThis thesis proposes the implementation of a space efficient Prolog implementation based on the work of David H. D. Warren and Hassan Aït-Kaci. The Common Lisp is the framework used to the construction of the Prolog system, it was chosen both to provide a space efficient environment and a rich programming language in the sense that it supply the user with abstractions and new ways of thinking. The resulting system is a new syntax to the initial language that runs on top of the SBCL Common Lisp implementation and can abstract away or exploit the underlying system.
Tese (Doutorado)
Shuvo, Md Kamruzzaman. "Hardware Efficient Deep Neural Network Implementation on FPGA." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/theses/2792.
Full textAddluri, Ramya Krishna. "An Efficient Implementation of the Blowfish Encryption Algorithm." University of Cincinnati / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1406820252.
Full textSmith, Craig M. "Efficient software implementation of the JBIG compression standard /." Online version of thesis, 1993. http://hdl.handle.net/1850/11713.
Full textTurkyilmaz, Ogun. "Emerging 3D technologies for efficient implementation of FPGAs." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT091/document.
Full textThe ever increasing complexity of digital systems leads the reconfigurable architectures such as Field Programmable Gate Arrays (FPGA) to become highly demanded because of their in-field (re)programmability and low nonrecurring engineering (NRE) costs. Reconfigurability is achieved with high number of point configuration memories which results in extreme application flexibility and, at the same time, significant overheads in area, performance, and power compared to Application Specific Integrated Circuits (ASIC) for the same functionality. In this thesis, we propose to design FPGAs with several 3D technologies for efficient FPGA circuits. First, we integrate resistive memory based blocks to reduce the routing wirelength and widen FPGA employability for low-power applications with non-volatile property. Among many technologies, we focus on Oxide Resistive Memory (OxRRAM) and Conductive Bridge Resistive Memory (CBRAM) devices by assessing unique properties of these technologies in circuit design. As another solution, we design a new FPGA with 3D monolithic integration (3DMI) by utilizing high-density interconnects. Starting from two layers with logic-on-memory approach, we examine various partitioning schemes with increased number of integrated active layers to reduce the routing complexity and increase logic density. Based on the obtained results, we demonstrate that multi-tier 3DMI is a strong alternative for future scaling
Lewis, Gregory Paul. "Repeated Reading: Testing Alternative Models for Efficient Implementation." DigitalCommons@USU, 2012. https://digitalcommons.usu.edu/etd/1171.
Full textAxell, Christian, and Mikael Brogsten. "Efficient WiMAX Receiver Implementation on a Programmable Baseband Processor." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7684.
Full textWiMAX provides broadband wireless access and uses OFDM as the underlying modulation technique. In an OFDM based wireless communication system, the channel will distort the transmitted signal and the performance is seriously degraded by synchronization mismatches between the transmitter and receiver. Therefore such systems require extensive digital signal processing of the received signal for retrieval of the transmitted information.
In this master thesis, parts of an IEEE 802.16d (WiMAX) receiver have been implemented on a programmable baseband processor. The implemented parts constitute baseband algorithms which compensates for the effects from the channel and synchronization errors. The processor has a new innovative architecture with an instruction set optimized for baseband applications.
This report includes theory behind the baseband algorithms as well as a presentation of how they are implemented on the processor. An impartial evaluation of the processor performance with respect to the algorithms used in the reference model is also presented in the report.
Olgun, Muhammet Ertug. "Design And Fpga Implementation Of An Efficient Deinterleaving Algorithm." Master's thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/3/12609816/index.pdf.
Full textGunay, Hazan. "Efficient Fpga Implementation Of Image Enhancement Using Video Streams." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12611448/index.pdf.
Full textdisplaying an analog composite video input by via converting to digital VGA format, license plate localization on a video image and image enhancement on FPGA. Analog composite video input, either PAL or NTSC is decoded on a video decoder board
then on FPGA, video data is converted from 4:2:2 YCbCr format to RGB. To display RGB data on the screen, line doubling de-interlacing algorithm is used since it is efficient considering computational complexity and timing. When taking timing efficiency into account, image enhancement is applied only to beneficial part of the image. In this thesis work, beneficial part of the image is considered as numbered plates. Before image enhancement process, the location of the plate on the image must be found. In order to find the location of plate, a successful method, edge finding is used. It is based on the idea that the plate is found on the rows, where the brightness variation is largest. Because of its fast execution, band-pass filtering with finite response (FIR) is used for highlighting the high contrast areas. Image enhancement with rank order filter method is chosen to remove the noise on the image. Median filter, a rank order filter, is designed and simulated. To improve image quality while reducing the process time, the filter is applied only to the part of the image where the plate is. Design and simulation is done using hardware design language VHDL. Implementations of the chosen approaches are done on MATLAB and Xilinx Virtex-2 Pro FPGA. Improvement of the implementation considering speed and area is evaluated.
Li, Zhipeng Ph D. Massachusetts Institute of Technology. "Efficient baseband design and implementation for high-throughput transmitters." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/101465.
Full textThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 139-145).
Wireless communications are accelerating into the realm of higher data rates from hundreds of megabits to tens of gigabits per second. Increase in data rate requires higher throughput and higher utilization of spectral bandwidth. At the same time, we are seeing a demand for smaller chipsets with lower power budgets. Digital basebands with increased energy-efficiency are needed while fitting within tight area constraints. High spectral efficiency demands modulation schemes with high peak to average power ratio, increasing the precision requirements on the digital baseband circuitry. To enable a new class of energy-efficient millimeter wave communication systems based on outphasing power amplifiers (PAs), we have explored ways to implement high-throughput outphasing baseband functions with the smallest energy and area footprints. Aware of the limitations of field-programmable gate arrays (FPGA) in throughput and energy-efficiency, we have chosen to implement our digital baseband in application-specific integrated circuits to allow a truly integrated energy-efficient transmitter. By utilizing the changes in micro-architecture (parallelism and pipelining) and aggressive back-end power optimization techniques (noncritical path Vt re- placement and sizing reductions), we achieve a record energy-efficiency and through- put for asymmetric-multilevel-outphasing (AMO) signal component separator (SCS) of 32pJ/sample at 0.6V supply voltage and 400Msamples/s, with an area of 0.41mm². For high-throughput area-constrained applications, our static random-access memo- ries based AMO SCS design achieves 2× area reduction over the register-based design at the same throughput to allow more parallelism to meet the stringent throughput requirements. To compensate for system nonlinearity and memory effects, we implement a zero- avoidance shaping filter in place of the traditional shaping filter to improve con- vergence in model iterations of an outphasing transmitter, and design an energy- and area-efficient digital predistorter (DPD). We use this DPD architecture to compensate for nonideal phase modulation, preamplifier saturation, and many transmitter nonidealities. Applying this developed methodology in spice-level simulation, we improve adjacent-channel-power-ratio (ACPR) of the outphasing Q-band (45GHz) transmitter with 1.1Gsamples/s throughput from -30.6dB to -44.0dB and reduced error vector magnitude (EVM) from 4.5% down to 1.0% with 64-Quadrature-Amplitude-Modulation (64QAM) and real-time zero avoidance. The energy efficiency of this predistorter at a throughput of 1.1Gsamples/s (3.3Gbps data rate with 64QAM modulation and oversampling ratio of 2) is 1.5nJ/sample. To illustrate the wide applicability of this proposed linearization methodology, we applied it to compensate for distortion in a radio-frequency PA. We apply the off-line iterative compensation method to a PA with 1.97GHz carrier frequency and 737Mbps data throughput with 64QAM. We map the designed DPD structure onto FPGAs with a utilization of 144 DSP slices and an energy efficiency of 1.7nJ/sample. To meet an ACPR constraint of -48dB, the uncompensated PA has to back-off the input power by 12dB with 3.3% power efficiency. The compensated PA has to back-off by only 6dB with 9.2% overall transmitter power efficiency which includes the DPD power, almost 3× the efficiency of uncompensated PA.
by Zhipeng Li.
Ph. D.
Alam, Syed Asad. "Techniques for Efficient Implementation of FIR and Particle Filtering." Doctoral thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-124195.
Full textHosseini, Ehsan, and Gino Rea. "Hardware-Efficient Implementation of the SOVA for SOQPSK-TG." International Foundation for Telemetering, 2010. http://hdl.handle.net/10150/605932.
Full textIn this paper, we present a hardware-efficient architecture of a demodulator for shaped offset quadrature phase shift keying, telemetry group version (SOQPSK-TG). The demodulation is done using the soft-output Viterbi algorithm (SOVA), which is implemented by the two-step traceback method. In this method, two traceback operations are employed to find the maximum-likelihood (ML) path and the competing path. Using the proposed architecture, the tracebacks are done at the same time as the demodulator is generating output bits and their reliabilities. This method has been shown to require less storage than the well-known register-exchange method. Finally, we present the performance results from the FPGA implementation.
Maze, Sheldon. "Efficient implementation of the Heston-Hull & White model." Master's thesis, University of Cape Town, 2014. http://hdl.handle.net/11427/8521.
Full textA model with a stochastic interest rate process correlated to a stochastic volatility process is needed to accurately price long- dated contingent claims. Such a model should also price claims efficiently in order to allow for fast calibration. This dissertation explores the approximations for the characteristic function of the Heston-Hull&White model introduced by Grzelak and Oost- erlee (2011). Fourier-Cosine expansion pricing, due to Fang and Oosterlee (2008), is then used to price contingent claims under this model, which is implemented in MATLAB. We find that the model is efficient, accurate and has a relatively simple calibration procedure. In back-tests, it is determined that the Heston- Hull&White model produces better hedging profit and loss results than a Heston (1993) or a Black and Scholes (1973) model.
Lien, E.-Jen. "EFFICIENT IMPLEMENTATION OF ELLIPTIC CURVE CRYPTOGRAPHY IN RECONFIGURABLE HARDWARE." Case Western Reserve University School of Graduate Studies / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=case1333761904.
Full textChristman, Jordan Louis. "Efficient Digital Spotlighting Phase History Re-Centering Hardware Implementation." University of Dayton / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1480934083897465.
Full textHeyne, Benjamin. "Efficient CORDIC based implementation of selected signal processing algorithms." Aachen Shaker, 2008. http://d-nb.info/991790073/04.
Full textAlexander, Steven Wilson. "Efficient arithmetic for high speed DSP implementation on FPGAs." Thesis, Connect to e-thesis, 2007. http://theses.gla.ac.uk/856/.
Full textEng.D. thesis submitted to the Faculty of Engineering, Department of Civil Engineering, University of Glasgow, 2007. Includes bibliographical references. Print version also available.
Bak, Christopher. "GP 2 : efficient implementation of a graph programming language." Thesis, University of York, 2015. http://etheses.whiterose.ac.uk/12586/.
Full textKatreepalli, Raghava. "Efficient VLSI Implementation of Arithmetic Units and Logic Circuits." OpenSIUC, 2017. https://opensiuc.lib.siu.edu/dissertations/1471.
Full textNurrito, Eugenio. "Scattering networks: efficient 2D implementation and application to melanoma classification." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2016. http://amslaurea.unibo.it/12261/.
Full textLarsson, Fredrik. "Efficient implementation of model-checkers for networks of timed automata." Licentiate thesis, Uppsala universitet, Avdelningen för datorteknik, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-226511.
Full textBengtsson, Johan. "Efficient symbolic state exploration of timed systems : Theory and implementation." Licentiate thesis, Uppsala universitet, Avdelningen för datorteknik, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-86016.
Full textKwok, Hok-sum, and 郭學深. "The implementation of energy efficient strategies in Hong Kong buildings." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2001. http://hub.hku.hk/bib/B31254925.
Full textIntrachooto, Singh. "Technological innovation in architecture : effective practices for energy efficient implementation." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8513.
Full textSome ill. printed as leaves, numbered as pages, and folded.
Includes bibliographical references (p. 241-248).
The objective of this research is to simultaneously address the environmental concerns in building design and the urgency in the architectural, engineering, and construction industry (AEC) to advance technologically by providing specific responses to the following questions. What are the barriers that a design team faces when introducing environmental strategies and innovations into building projects? What are the mechanisms that can assist design teams to surpass industry standards or even break away from the limits of their own professional training? Ultimately, what is required to successfully implement environmentally sound and technologically innovative solutions in buildings? In order to gain a better insight into these issues, this research examines eight case studies and reconstructs their respective patterns of practices to discover how and why certain AEC teams successfully overcome design, development, and implementation barriers relating to energy efficient innovation (EEI) while most do not. The results of the study are categorized into four distinct, but related, components: (1) implementation techniques, (2) basic team attributes, (3) critical success factors, and (4) the implementation process. Contrary to popular belief, the findings suggest that technological innovation, specifically EEI, is best fostered by team members with prior work experience with each other, as opposed to an assembly of individuals selected solely on the basis of expertise. The repeated collaborations serve multiple functions: technical-risk reduction, financial security, and psychological assurance.
(cont.) In addition, six key factors of EEI implementation are isolated and organized into two groups: team dynamics and project logistics. Team dynamics encompasses concurrent collaboration, team relational competence, and commitment to environmental goals. Project logistics encompasses external funding; research collaboration; and technical evaluation, demonstration, and validation. A strong relationship was found between the integrated design process and the commitment to EEI. Specifically, contributors of EEI worked in parallel with an expedient feedback loop or explicit feedback period. Interestingly, financial contributions external to the clients' allocated budgets were consistently found and often related to the particular research of at least one member within the team. The direct relationship between research and the resultant innovation suggests that technological innovation is not random, but rather predictable and specific to team members' areas of expertise.
by Singh Intrachooto.
Ph.D.
Li, Tiancheng. "Efficient particle implementation of Bayesian and probability hypothesis density filtering." Thesis, London South Bank University, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.631738.
Full textFRASCA, CACCIA GIANLUCA. "A new efficient implementation for HBVMs and their application to the semilinear wave equation." Doctoral thesis, 2015. http://hdl.handle.net/2158/992629.
Full textLi, Yu-Lun, and 李有倫. "Efficient implementation of MP3 decoder." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/65766481241115154755.
Full text國立中正大學
資訊工程研究所
90
The Moving Picture Experts Group-1 / Layer3(MP3)algorithm on software application becomes more and more great. Therefore, to use hardware to implement MP3 obviously become a new field of course. In decoder section, because it needs to match the standard of real-time which makes it even better to present it by hardware. The objective for this thesis is to implement MP3 decoder by using hardware. Moreover, we decide to use Field Programmable Gate Array〈FPGA〉as for our design environment. We use software to do MP3 decode, because it is easier on calculation. Therefore, we don’t have any restriction on memory size. However, if we don’t consider this problem when we are designing our hardware, it would increase the price and the power consumption. That’s why we suggest a more effective memory management method according to some characteristic of MP3 decode. This method can reduce the memory size use and it can also maintain the real-time standard.
Wang, Guo-Ting, and 王國婷. "Efficient Implementation of FIDO UAF Client." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/22680485274516945129.
Full text國立臺灣大學
電子工程學研究所
104
With the popularity of mobile phones and tablets, more and more people surf the Internet with mobile devices. When users log in a website, in contrast to using traditional PCs, typing the password is very troublesome on mobile phones. However, the most commonly used authentication is still password-based. Thus, users usually record their password on browsers or apps after the first login. These security issues become apparent on mobile devices. Apart from using ”password”, there are several authentication solutions with higher security. For example, adding one-time password or hardware token for two-factor authentication are good choices. Most of those solutions are not adopted because of the cumbersome steps. FIDO Alliance is formed to address the problems of password and authentication. They develop specification of password-less solution. With biometric device, the ecosystem oflogin is secure and convenient. Users only need to pass identity verification,then they can successfully log in. There are few open resources related to standard published by FIDO except to the official documents. In this thesis, we implement the client part sothat more people can refer to it and pay attention to this issue.
Lu, Yi-shan, and 呂易珊. "Efficient Implementation of the Weil Pairing." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/q6664b.
Full text國立中山大學
資訊工程學系研究所
97
The most efficient algorithm for solving the elliptic curve discrete logarithm problem can only be done in exponential time. Hence, we can use it in many cryptographic applications. Weil pairing is a mapping which maps a pair of points on elliptic curves to a multiplicative group of a finite field with nondegeneracy and bilinearity. Pairing was found to reduce the elliptic curve discrete logarithm problem into the discrete logarithm problem of a finite field, and became an important issue since then. In 1986, Miller proposed an efficient algorithm for computing Weil pairings. Many researchers focus on the improvement of this algorithm. In 2006, Blake et al. proposed the reduction of total number of lines based on the conjugate of a line. Liu et al. expanded their concept and proposed two improved methods. In this paper, we use both NAF and segmentation algorithm to implement the Weil pairing and analyse its complexity.
Pahlevaninezhad, Hamid. "Design and implementation of efficient terahertz waveguides." Thesis, 2012. http://hdl.handle.net/1828/3977.
Full textGraduate
Gonçalves, Hélder José Alves. "Towards an efficient lattice basis reduction implementation." Master's thesis, 2016. http://hdl.handle.net/1822/47824.
Full textThe security of most digital systems is under serious threats due to major technology breakthroughs we are experienced in nowadays. Lattice-based cryptosystems are one of the most promising post-quantum types of cryptography, since it is believed to be secure against quantum computer attacks. Their security is based on the hardness of the Shortest Vector Problem and Closest Vector Problem. Lattice basis reduction algorithms are used in several fields, such as lattice-based cryptography and signal processing. They aim to make the problem easier to solve by obtaining shorter and more orthogonal basis. Some case studies work with numbers with hundreds of digits to ensure harder problems, which require Multiple Precision (MP) arithmetic. This dissertation presents a novel integer representation for MP arithmetic and the algorithms for the associated operations, MpIM. It also compares these implementations with other libraries, such as GNU Multiple Precision Arithmetic Library, where our experimental results display a similar performance and for some operations better performances. This dissertation also describes a novel lattice basis reduction module, LattBRed, which included a novel efficient implementation of the Qiao’s Jacobi method, a Lenstra-LenstraLovasz (LLL) algorithm and associated parallel implementations, a parallel variant of the ´ Block Korkine-Zolotarev (BKZ) algorithm and its implementation and MP versions of the the Qiao’s Jacobi method, the LLL and BKZ algorithms. Experimental performances measurements with the set of implemented modifications of the Qiao’s Jacobi method show some performance improvements and some degradations but speedups greater than 100 in Ajtai-type bases.
Atualmente existe um grande avanço tecnológico que poderá colocar em causa a segurança da maioria dos sistemas informáticos. Sistemas criptográficos baseados em reticulados são um dos mais promissores tipos de criptografia pós-quântica, uma vez que se acredita que estes sistemas são seguros contra possíveis ataques de computadores quânticos. A segurança destes sistemas está baseada na dificuldade de resolver o problema do vetor mais curto e o problema do vetor mais próximo. Algoritmos de redução de bases de reticulados são usados em muitos campos científicos, tais como criptografia baseada em reticulados. O seu principal objetivo e tornar o problema mais fácil de resolver, tornando a base do reticulado mais curta e ortogonal. Alguns casos de estudo requerem o uso de números com centenas de dígitos para garantir problemas mais difíceis. Portanto, é importante o uso de módulos de precisão múltipla. Esta dissertação apresenta uma nova representação de inteiros para aritmética de precisão múltipla e todas as respetivas funções de um módulo, ‘MpIM’. Também comparamos as nossas implementações com outras bibliotecas de precisão múltipla, tais como ‘GNU Multiple Precision Arithmetic Library’, em que obtivemos desempenhos semelhantes e em alguns casos melhores. A dissertação também apresenta um novo módulo para a redução de bases de reticulados, ‘MpIM’, que inclui uma nova e eficiente implementação do ‘Qiao’s Jacobi method’, o algoritmo ‘Lenstra-Lenstra-Lovasz’ (LLL) e respetiva implementação paralela, uma variante paralela do algoritmo ‘Block Korkine-Zolotarev’ (BKZ) e a sua versão sequencial e versões de precisão múltipla do ‘Qiao’s Jacobi method’, LLL e BKZ. Trabalhos experimentais mostraram que a versão do ‘Qiao’s Jacobi method’ que implementa todas as modificações sugeridas mostra ganhos e degradações de desempenho, contudo com aumentos de desempenho superiores a 100 vezes em bases ‘Ajtai-type’.
Wang, Te-Chuan, and 王得權. "Efficient FFT Implementation Using CORDIC-Based Arithmetic." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/43260882553028239700.
Full text國立中正大學
資訊工程研究所
90
This thesis presents an efficient implementation of the pipeline FFT processor based on radix-4 decimation-in-time algorithm with the use of CORDIC-based arithmetic units. By recombining the sequential input samples to parallel data streams, the proposed architecture can’t only achieve nearly fully hardware utilization, but also require much less memory compared with the previous FFT processor. In addition, in FFT processors, several modules of ROM are required for the storage of twiddle factors. Exploiting the redundancy of the factors and using the CORDIC control information instead of multiplicands can efficiently reduce the overall ROM size by a factor of 4.
Chen, Jian-Yu, and 陳建宇. "Efficient LDPC Decoder Implementation for IEEE 802.16e." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/23zfhb.
Full text國立中正大學
通訊工程研究所
100
Since the performance of Low-Density Parity Check (LDPC)codes is very close to Shannon limit, the related work has been widely discussed in the field of channel codes. LDPC codes are suitable for parallel decoding to achieve the high throughput due to the feature of highly parallelizable decoding architecture. Therefore, LDPC codes are preferable in many digital communication standards, such as the WiMax (802.16e) and Wi-Fi (802.11n). However, memory access conflict frequently occurred in the sub-matrices with same offsets when the fast decoding of Quasi-Cyclic low-density check (QC-LDPC) codes is applied with parallelization. This results in decoding latency and low throughput. In this thesis, we propose a efficient design of a parallel LDPC decoder, for 802.16e. In column-major decoding process, the storage of all check-to-variable messages in a row of parity check matrix is organized as an efficient chunk. This method should verify the offsets of all sub-matrices in a block row to prevent memory collisions. A pre-process is also proposed to indicate the degree of parallelization with the set of column. Each column set contains the columns which can be processed in parallel. Besides, decoding latency can be minimized. Experimental results in the hardware implementation show that the throughput of proposed LDPC decoder can be 241 Mbps in 184MHz.
Wan-TingWeng and 翁琬婷. "High Efficient VLSI Implementation of Canny Edge Detection." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/6898t2.
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