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Journal articles on the topic 'DYNAMIC COMPARATORS'

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Author: Grafiati

Published: 11 September 2023

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1

Song, Bangyu, and Yi Zhao. "A comparative research of innovative comparators." Journal of Physics: Conference Series 2221, no. 1 (May 1, 2022): 012021. http://dx.doi.org/10.1088/1742-6596/2221/1/012021.

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Abstract This paper studies four novel design comparators and gives a detailed analysis and summary of them. edge-pursuit comparator (EPC) improved energy efficiency and noise over conventional comparators by a circuit loop consisting of numbers of delay units. The triple-tail fully dynamic comparator minimizes the comparator’s total delay time and enhances the sample rate. The dynamic bias architecture of the double-tail latch-type comparator can provide a relatively high voltage gain while ensuring a low power consumption by stabilizing the static operating point. It also has advantages over conventional comparators in noise and delay. A triple-latch feedforward (TLFF) comparator improves on the triple-tail fully dynamic comparator. The triple-latch feedforward (TLFF) dynamic comparator consists of three-stage latches and a parallel feedforward path. It has a smaller delay time than other circuit designs, especially for large differential input signals.

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2

Liu, Yuchuan. "An Review of Dynamic CMOS Comparators." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 113–20. http://dx.doi.org/10.54097/hset.v44i.7273.

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CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.

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3

Du, Chengze. "Performance analysis of high-speed, low-power comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 292–301. http://dx.doi.org/10.54097/hset.v27i.3770.

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This article mainly presents a summary of development of dynamic comparators and the optimization to conventional comparator in recent years. By comparing the design of two different comparators, the design method of less power consumption, high speed or small delay, and low input referred noise can be concluded. The Dynamic comparator is designed to have small delay and less power consumption compared with two-stage comparator. The dynamic-bias comparator spends less power for operation the circuit compared with double-tail comparator. The FIA comparator operates under the controlling of logic NOR gate.

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4

Tang, Chengyun. "Performance analysis of comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 172–82. http://dx.doi.org/10.54097/hset.v27i.3742.

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This article reviews the innovative and improved structure of three comparators, and summarizes the optimization ideas to further optimize the design parameters of the comparators in the future. The Triple-Tail Dynamic Comparator proposes a multi-stage design to break connection between speed and noise. The Dynamic Bias Latch-Type (DB) Comparator takes an innovative approach to reducing energy consumption by stabilizing the source node voltage of the input pairs. The floating inverter amplififier (FIA)-based pre-amplififier further improves the energy efficiency based on the design of the low-power comparator, and also optimizes parameters such as common-mode output voltage and noise.

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5

Li, Yichen. "The Performance analysis of Low-Power High-Speed comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 72–82. http://dx.doi.org/10.54097/hset.v27i.3723.

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Comparators are the essential block for planning high-speed analog and. This paper presents three inventive designs of the comparators in recent years. First, innovated by classic two-stage comparator, the comparator with a transconductance-enhanced latching stage is suitable for low-power, high-speed operation. Second, triple-latch feed-forward(TLFF) fully dynamic comparator guarantees the maximum possible gain and speed for a specific power across the entire input range. Finally, the comparator with a dynamic floating inverter maximizes efficiency by reusing the current.

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6

Sun, Yuan. "A brief review on novel comparator design." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 418–27. http://dx.doi.org/10.54097/hset.v27i.3785.

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This paper reviewed three different kinds of comparators to show their respective advantage range. The Dynamic-bias comparator extends its pre-amplifier part with a capacitor and has a smaller power with a smaller input referred noise than Elzakker’s comparator but has a higher delay. The Quad high-speed comparator introduced the Quad into the comparator’s latch part. It has a lower delay and also make the calculation of the output voltage easier for it only depends on the skew factor. The low-power dynamic bias has a cross-couple device on its pre-amplifier part which slows down the discharge of the capacitors. It has a higher delay but lower the energy consumption by 30%.

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7

Wang, Sudong. "Review of Four Improving Designs of Dynamic Latch Comparator." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 129–37. http://dx.doi.org/10.54097/hset.v44i.7287.

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In this paper, four disparate designs of dynamic latch comparators are discussed consecutively. By improving the design of the pre-amplifier stage, the double tail comparator provides a good power-speed trade-off. Further, Differential pair amplifiers are implemented in the second design, which has better comparison speed and energy dissipation. Next, a bulk-driven structure is employed on the comparator design to improve the comparison speed. Finally, a dynamic comparator utilizes a floating reservoir capacitor and a positive feedback bulk structure is introduced to achieve higher energy efficiency. The overall performance of these comparators is evaluated in this paper.

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8

Fan, Jiangfeng. "Performance Analysis of Low-Power CMOS Dynamic Comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 62–71. http://dx.doi.org/10.54097/hset.v27i.3722.

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This paper studies four structures of CMOS dynamic comparators introduced in recent years. Based on conventional double-tail comparator, a comparator with a tail capacitor prevents output nodes of preamplifier from completely discharging to reduce energy consumption. Another comparator with a cross-coupled pairs achieves the same purpose of the first design. A comparator adds a floating inverter amplifier (FIA) to realize both dynamic bias and current reuse, achieve low energy consumption and be insensitive to the VCM. The triple-latch feed-forward (TLFF) comparator decreases delay conspicuously.

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9

sharma*, D. Pavan kumar, and P. Sreehari Rao. "A Low Input Referred Noise Dynamic Comparator for High Speed Applications." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 4 (November 30, 2019): 4768–72. http://dx.doi.org/10.35940/ijrted6881.118419.

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Comparators play a pivotal role in design of analog and mixed signal circuits. Comparators employ regenerative feedback both in input pre-amplifier stage and output stage. The designed comparator resolves 5mV with resolution of 8 bits and dissipates 11mW of power using 1.2V supply in 130nm CMOS technology while operating at clock frequency of 1.25 GHz.

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10

Chen, Zhenxiang, Yuheng Ni, and Zhenghao Xiong. "The Analysis of High-Speed Low-Power Dynamic Comparators." Journal of Physics: Conference Series 2187, no. 1 (February 1, 2022): 012022. http://dx.doi.org/10.1088/1742-6596/2187/1/012022.

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Abstract This article reviews 5 different articles on optimizing comparators and focuses on their innovations. Many innovative methods are used to get a higher comparison speed, lower power consumption and degraded noise comparator. Many novel methods such as connecting the conventional two-stage dynamic comparator to a transconductance-enhanced latching stage, adding a charge pump to the Miyahara’s comparator, engendering two propagating edges in two inverter loops and measuring the distance between the two edges to compare different input voltage and using an inverter-based input pair which is powered by a floating reservoir capacitor can significantly achieve these goals. What’s more, a three-stage feedforward fully dynamic comparator with an extra parallel feedforward path, which is a completely innovatory and newly designed comparator, is also proposed.

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11

Jin, Xin Yu, Cheng Li, Jun Biao Liu, Xiao Feng Jiang, and Xiang Bing Zeng. "Ternary Logic Dynamic CMOS Comparators." Advanced Materials Research 317-319 (August 2011): 1177–82. http://dx.doi.org/10.4028/www.scientific.net/amr.317-319.1177.

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In this paper, a new method of ternary logic circuit design is developed. It’s proposed that two types of static ternary CMOS comparators and three types of dynamic CMOS comparators, designed by new method, with low transistor count, high speed and low power consumption. The proposed comparators are the rearrangement and reordering of transistors in the evaluation block of a dynamic cell. These ternary comparators can be used as equality comparators, mutual comparators and zero/one/two detectors, which are widely used in build in self test and memory testing.

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12

Tang, Xiao-Bin, and Masayoshi Tachibana. "A BIST Scheme for Dynamic Comparators." Electronics 11, no. 24 (December 13, 2022): 4169. http://dx.doi.org/10.3390/electronics11244169.

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This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in dynamic comparators. In this scheme, a feedback loop is designed using the characteristics of the comparator; monitoring the voltage in the feedback loop can determine the presence of a circuit fault. The proposed BIST scheme and the circuit under testing are realized at the transistor level. The proposed BIST scheme was simulated using HSPICE. The simulated fault coverage is approximately 87.8% with 90 test circuits. To further verify the effectiveness of the proposed BIST scheme, six faults were injected into the real circuit. The test results were consistent with the simulation results.

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13

Du, Qinghang. "Analysis and comparison of several types of low-power, low offset comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 120–32. http://dx.doi.org/10.54097/hset.v27i.3728.

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This paper studies several excellent works of comparator constructions of comparators and compares them with the Double-tail latch-type comparator. Based on the Elzakker comparator, the comparator with a dynamic bias reduced the use of energy by partly discharging the preamplifier's output nodes. Edge-Pursuit Comparator(EPC) demonstrates a new approach to reducing energy consumption by automatic energy optimization. Apart from the designs that optimize energy consumption. Low-Noise Self-Calibrating Dynamic Comparator provides the low-offset feature while in relatively low power consumption.

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14

Zhang, Yuxin. "Design analyst of low energy, high gm/Id, and high sensitivity comparator." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 183–90. http://dx.doi.org/10.54097/hset.v27i.3745.

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This paper analyses three innovative designs of comparators and those structures have better performance than the traditional comparator. The dynamic floating inverter amplifier improves energy efficiency by preventing full discharging and charging. The Dynamic Bias Latch-Type Comparator used a double-tails latch to decrease energy consumption. The charge-injection compensations comparator has better sensitivity and less noise by utilizing the feedback loop. Those methods have greatly increased voltage gain, energy efficiency, and gm/Id

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15

Verma, Chanchal. "Dynamic Threshold MOSFET Based Comparators." International Journal for Research in Applied Science and Engineering Technology 9, no. 4 (April 30, 2021): 292–99. http://dx.doi.org/10.22214/ijraset.2021.33594.

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16

Gajawada, Varun sai, and Mohana J. "Construction of CMOS Logic Double Tail Comparator for Lower Power Consumption Compared with Dynamic Comparator." ECS Transactions 107, no. 1 (April 24, 2022): 13873–85. http://dx.doi.org/10.1149/10701.13873ecst.

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The aim of the study is to construct and analyze innovative CMOS based double tail comparators and compare them with a dynamic comparator using VLSI technology. Materials and methods: The comparator is designed by using the tanner tool for simulation and verification. By varying the length of a transistors the power values were obtained. There are two groups in the study. CMOS double tail comparator is the experimental group and dynamic tail comparator is the control group. This experiment is performed for 20 different values of length. Results: The power consumption of a CMOS logic double tail comparator is 0.38035 followed by the dynamic comparator is 0.4934. Insignificance of 0.150 was obtained which is greater than (p<0.05). Conclusion: The consumption of power by the constructed CMOS logic double tail comparator appears to be less than dynamic double tail comparator.

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17

Khanfir, Leïla, and Jaouhar Mouïne. "Systematic Hysteresis Analysis for Dynamic Comparators." Journal of Circuits, Systems and Computers 28, no. 06 (June 12, 2019): 1950100. http://dx.doi.org/10.1142/s0218126619501007.

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Comparator hysteresis is a memory phenomenon allowing outputs maintaining their past stable states until the input difference overcomes a given threshold voltage. In some applications, such as ADCs and memories, hysteresis is a deterministic error that should be minimized. In others, it can be considered as one of the design parameters, such as in implementing hysteresis control-based systems such as peak detectors and spectrum analyzers. In any case, the designer should be aware of how to estimate hysteresis to achieve the desired performances. This paper presents a mathematical approach to estimate hysteresis in clocked latch comparators. It has been demonstrated that hysteresis is not only sensitive to the clock frequency, but also to several design parameters including the transistors sizes, the common mode input voltage and the tracked input frequencies. The analysis results are validated through electrical simulations using a commercially available 0.18[Formula: see text][Formula: see text]m CMOS technology showing a maximum error of 8.6%.

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18

Cao, Menghua, and Weixun Tang. "The High-Speed Low-Power Dynamic Comparator." Journal of Physics: Conference Series 2113, no. 1 (November 1, 2021): 012064. http://dx.doi.org/10.1088/1742-6596/2113/1/012064.

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Abstract This paper comments on four works for the optimization of comparator design. Today, with the development of integrated circuits, the requirements for comparators about low power, low delay, few offset voltage, and low noise are highly desirable. Specifically, these works made progress in the conventional comparator, which comprises a preamplifier and a latch. They also solved some problems, such as decreasing power and delay. Some works employ a positive feedback cross-coupled pares to provide a larger gain in the preamplifier, use PMOS switch transistors to accelerate the definition phase, or a double-tail architecture to increase the latch regeneration speed. Other work designs a charge pump to improve speed.

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19

Chen, Yiming. "Innovative Techniques in Comparator Designs." Journal of Physics: Conference Series 2221, no. 1 (May 1, 2022): 012022. http://dx.doi.org/10.1088/1742-6596/2221/1/012022.

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Abstract This paper presents four innovative designs of comparators proposed these years. A latch-type dynamic bias adds a tail capacitor to prevent fully discharging at the pre-amplifier output nodes to reduce energy consumption. The comparator is analysed and then compared with floating inverter amplifier (FIA) type. The pre-amplifier of the FIA type adopts an inverter-based input pair by a floating reservoir capacitor, greatly boosting gm/Id and improving the energy efficiency. The edge-pursuit comparator (EPC) provides a new perspective when designing comparators. According to the input difference, it will automatically adjust the comparison energy, avoiding wasting unnecessary energy spent on coarse comparison. Finally, for the edge-race comparator (ERC), it further improves the performance of saving energy and addressing the relatively long comparison time in the EPC.

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20

Khorami, A., and M. Sharifkhani. "Low‐power technique for dynamic comparators." Electronics Letters 52, no. 7 (April 2016): 509–11. http://dx.doi.org/10.1049/el.2015.3805.

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21

Zhou, Yibo. "Analysis of the Improved Conventional Dynamic Comparator and the Edge-Pursuit Comparator." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 385–98. http://dx.doi.org/10.54097/hset.v27i.3782.

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In order to understand and learn the comparator in detail, three kinds of comparator are analyzed in this paper. An improvement of the traditional dynamic double-tailed comparator. So as to get fast operation and low power in low supply voltages, the circuit of the traditional double-tailed comparator is modulated. Another one is an improved low-power comparator. During evaluation, we can activate its latch delayed in order to avoid excess power consumption and get sufficient preamplification gain. The most innovative design is named edge-pursuit comparator (EPC) which is a new energy-efficient ring oscillator collapse-based comparator. With changing the comparison energy on the basis of input difference uncontrolled, it can automatically adjust its performance. It can also eliminate unnecessary energy which is spent on coarse comparisons. In addition, we get analysis of the design which is in the phase domain in detail. It presents that the energy efficiency can be improved over traditional comparators even out of energy scaling.

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22

Gupta, Anshu, Lalita Gupta, and R. K. Baghel. "Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator." International Journal of Engineering & Technology 7, no. 2.16 (April 12, 2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.16.11413.

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A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator’s delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

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23

Sharath kumar, L Yeshwanth, Nallam Balaji Ram Ganesh, and Voruganti Saketh. "Design of Area efficient comparator architecture using 5T XOR GATE." international journal of engineering technology and management sciences 7, no. 3 (2023): 494–98. http://dx.doi.org/10.46647/ijetms.2023.v07i03.69.

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The use of comparators in computation-based designs is extensive, making optimization crucial. While some comparator designs use dynamic logic to achieve low-power consumption, the limitations of low-speed and poor-noise margin make this approach challenging. The proposed comparator design offers a new solution that is both area-efficient and has a high operating speed while consuming low-power. It was designed using 180nm technology in Tanner Tool, and its results were observed. Overall, this work presents a promising new solution for optimizing digital comparators and improving the efficiency and speed of computation-based designs. This work presents a new solution for optimizing N-bit digital comparators in terms of area, power, and speed. The proposed comparator structure is a clever design that consists of two crucial modules - the comparison evaluation module (CEM) and the final module (FM). The CEM is responsible for evaluating the comparison, and it uses a regular structure of repeated logic cells to implement a parallel prefix tree structure. This approach is independent of input operand bit widths, which makes it highly versatile and adaptable to different applications. The FM, on the other hand, validates the final comparison based on the results obtained from the CEM. This ensures that the final output is accurate and reliable. By utilizing these two modules, the proposed comparator structure is able to achieve high-precision comparisons while maintaining a relatively simple and efficient design. Overall, this comparator structure is a promising development in the field of digital circuit design, and it has the potential to improve the performance and reliability of a wide range electronic systems.

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24

Sonar, S., D. Vaithiyanathan, and A. Mishra. "Performance analysis of double tail dynamic comparators." Journal of Physics: Conference Series 1706 (December 2020): 012058. http://dx.doi.org/10.1088/1742-6596/1706/1/012058.

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25

Boni, A., G. Chiorboli, and C. Morandi. "Dynamic characterisation of high-speed latching comparators." Electronics Letters 36, no. 5 (2000): 402. http://dx.doi.org/10.1049/el:20000369.

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26

González-Cueto, José Antonio, Zaid García Sánchez, Gustavo Crespo Sánchez, Hernan Hernandez, Jorge Iván Silva Ortega, and Vicente Leonel Martínez Díaz. "A mho type phase comparator relay guideline using phase comparison technique for a power system." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (April 1, 2021): 929. http://dx.doi.org/10.11591/ijece.v11i2.pp929-944.

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This paper presents a mho distance relay simulation based on the phase comparison technique using a typical electrical power systems analysis software for two cases: when the operation state is close to the static voltage limit and during a dynamic perturbation in the system. The paper evaluates the impedance variations caused by complex voltage values, the mho polarization, and the comparator operating region into the complex plane. In addition, the paper found the information for the dynamic perturbations from the outputs considering a mid-term stability program. The simulation of the mho-phase comparator in the static voltage proximity limit detects unit distance elements with impedance measured close to reach the threshold in the steady-state. Dynamic mho simulations in the complex plane are successfully tested by plotting time phase difference curves on the comparator input signals. Relay programmers can use these curves to analyze other phase comparators applications and the corresponding models in the complex plane.

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27

Deng, Ruichen. "Performance Analysis for Energy-Efficient Comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 94–105. http://dx.doi.org/10.54097/hset.v27i.3725.

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This work studies three different comparator proposed in recent years. Compared to the strnongARM latch as well as the Elzakker’s comparator, the dynamic comparator added cross-coupled devices that keeps the pre-amplifier’s integration nodes from fully discharge to the ground and thus improves energy performance. The dynamic bias latch-type comparator is an innovative design which added a tail capacitor to the pre-amplifier in order to block off the discharge route between the internal nodes and the ground. Though this design reduced the energy consumption significantly compared with the Elzakker’s comparator, it results in longer delay and only little improvement on the input-referred noise. The FIA dynamic comparator implemented a floating inverter amplifier (FIA) that utilizes a reservoir capacitor which cuts off its charging path and discharging path significantly reduced the energy consumption and improved noise performance to power itself.

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28

Zhu, Haomin. "Research on Four Different Designs of Comparator." Journal of Physics: Conference Series 2260, no. 1 (April 1, 2022): 012003. http://dx.doi.org/10.1088/1742-6596/2260/1/012003.

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Abstract Comparators contribute a significant role to analogue to digital converters (ADC). This paper describes and evaluates four excellent comparator optimisation schemes in recent years and analyses their advantages and disadvantages, providing ideas for the following comparator research direction. In addition, this paper introduces the design steps of each comparator optimisation scheme. It shows how the designer completes the final optimisation scheme step by step from the practical problems, which provides a specific reference for the comparator designers in the future. A double-tail latch-type comparator with dynamic bias adds a tail capacitor to the pre-amplifier to achieve low noise and high gain. Furthermore, a triple-tail dynamic comparator addresses a cascoded integrator. The new stage defines and attenuates the noise to achieve high speed and low noise. Compared to the triple-tail comparator, another design of a three-stage comparator is through adding a feedforward path between the first amplifier/latch and third latch to construct a triple-latch feedforward dynamic comparator. It is aimed to reduce delay and get low consumption in the region of the high voltage signal. Moreover, Edge-Pursuit Comparator (EPC) uses NAND gates and inverter delay cells to generate the comparison result between two input signals. Its circuit structure allows input noise tunability, automatic energy scaling, and low voltage tolerance.

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29

Sathishkumar, Arumugam, and Siddhan Saravanan. "A Low-Noise Dynamic Comparator with Offset Calibration for CMOS Image Sensor Architecture." Journal of Circuits, Systems and Computers 28, no. 02 (November 12, 2018): 1950022. http://dx.doi.org/10.1142/s0218126619500221.

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A low-noise, high-speed, low-input-capacitance switched dynamic comparator (SDC) CMOS image sensor architecture is presented in this paper. The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-power, area-efficient and high-speed flash analog-to-digital converters (ADCs) in many applications today motivated us to design a comparator for ADC. The rail-to-rail output swing is also improved. The input capacitance is reduced by using shared first-stage technique. The comparator is designed with constant [Formula: see text]/[Formula: see text] biasing to suppress the environmental drift. The simulation results from 45-nm and 65-nm CMOS technologies confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 3.5[Formula: see text]GHz and 2.2[Formula: see text]GHz at supply voltages of 1[Formula: see text]V and 0.6[Formula: see text]V, respectively. Simulations are carried out using predictive technology models for 45[Formula: see text]nm and 65[Formula: see text]nm in HSPICE.

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30

Jun He, Sanyi Zhan, Degang Chen, and R. L. Geiger. "Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators." IEEE Transactions on Circuits and Systems I: Regular Papers 56, no. 5 (May 2009): 911–19. http://dx.doi.org/10.1109/tcsi.2009.2015207.

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31

Khorami, Ata, and Mohammad Sharifkhani. "Excess power elimination in high-resolution dynamic comparators." Microelectronics Journal 64 (June 2017): 45–52. http://dx.doi.org/10.1016/j.mejo.2017.04.006.

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32

Zhang, Haoyue. "A Review of Innovative Comparator Designs." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 106–19. http://dx.doi.org/10.54097/hset.v27i.3726.

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Three papers on the optimal design of comparator circuits are further analyzed in this work. Each paper presents a method to improve the performance of comparators. Floating inverter amplifier applied an independent capacitor as the source of the preamplifier, which improves the overall performance of the circuit. In another design, a special local clock generator is proposed to control the input of both of the latch stage and the preampliﬁer, which makes it possible to adjust the speed and improve the energy efficiency. In dynamic bias circuit design, stabilized common-mode voltage is realized by adding a capacitor to the tail of the pre-amplifier of a latch-type comparator, optimizing the power and noise performance successfully.

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33

Asyaei, Mohammad. "New dynamic logic style for energy efficient tag comparators." Microprocessors and Microsystems 90 (April 2022): 104522. http://dx.doi.org/10.1016/j.micpro.2022.104522.

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34

Khorami, Ata, and Mohammad Sharifkhani. "A low-power technique for high-resolution dynamic comparators." International Journal of Circuit Theory and Applications 46, no. 10 (June 21, 2018): 1777–95. http://dx.doi.org/10.1002/cta.2500.

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35

Nguyen, Hoang Trong, and Trang Hoang. "A Novel Framework of Genetic Algorithm and Spectre to Optimize Delay and Power Consumption in Designing Dynamic Comparators." Electronics 12, no. 16 (August 9, 2023): 3392. http://dx.doi.org/10.3390/electronics12163392.

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In integrated circuit (IC) design, analog circuits contribute significantly as the interface between real and digital world signals. Although they make up a relatively small portion of the overall circuit, their design process is often most time-consuming, mostly from the phase of manual iteration of circuit parameters to meet design specifications. Therefore, the design automation of analog circuits with the help of efficient optimization techniques arises as a promising candidate to address the issue. Among optimization algorithms, while the genetic algorithm (GA) has been shown to be effective in finding near-optimal solutions, it has not been extensively applied to the field of analog circuit design. Hence, this paper proposes a method to utilize GA in the optimization of a widely used circuit topology, namely the comparator. The comparator is considered the fundamental block in the design of most analog-to-digital converters (ADCs). For high-speed ADCs, dynamic comparators are usually chosen for the purpose of high speed and power efficiency. In summary, this paper introduces an innovative GA-Spectre architecture to optimize the dynamic comparator with respect to delay and power consumption. The post-optimized results are optimistic with a 72.61 ps delay and 3.11 µW power dissipation.

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Gwóźdź, Michał. "Power Electronics Programmable Voltage Source with Reduced Ripple Component of Output Signal Based on Continuous-Time Sigma-Delta Modulator." Energies 14, no. 20 (October 18, 2021): 6784. http://dx.doi.org/10.3390/en14206784.

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In this work, an idea of a wideband, precision, power electronics programmable voltage source (PVS) is presented. One of the basic elements of the converter, the control section, contains a continuous-time sigma-delta modulator (SDM) with a pair of interconnected complementary comparators, which represents a new approach. In this case, the SDM uses comparators with a dynamic hysteresis loop (DHC) that includes an AC circuit rather than an R-R network. Dynamic hysteresis is a very effective way of eliminating parasitic oscillation during the signal transition at the input of the comparator; it also affects the frequency characteristics and, especially, the phase properties of the comparator, and this phenomenon is exploited in the proposed converter. The main disadvantage of all pulse-modulated converters is the presence of a ripple component in the output voltage (current), which reduces the quality of the output signal and may cause high-frequency disturbances. A basic feature of PVS is a lower RMS value for the pulse modulation component in the output voltage of the converter, compared to the typical value. Another important feature of the proposed converter is the ability of precise mapping of the output voltage to the reference (input) signal. The structure of the control circuit is relatively simple—no complex, digital components are used. Due to the high frequency of the SDM output bit-stream, the simulation model of the power stage of PVS is based on the power modules with gallium-nitride field effect transistors (GaN FETs). The work discusses the rules of PVS operations and the results from PVS simulation model studies as well as highlights the possible application fields for systems with a PVS.

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Khanfir, Leïla, and Jaouhar Mouïne. "Low-power latch comparator with accurate hysteresis control." Journal of Electrical Engineering 71, no. 6 (December 1, 2020): 379–87. http://dx.doi.org/10.2478/jee-2020-0052.

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Abstract Recent research has focused on finding ways to control hysteresis of dynamic comparators. The current proposed techniques are based on either geometrical dimension adjustment or digital control. The first case does not allow for post fabrication control, while the second has limited accuracy. This paper presents a new dynamic comparator design with external hysteresis adjustment using an analog voltage. This is achieved by proposing an architecture including control devices with a specific sizing. This is performed with no significant increase of the design complexity, keeping the power consumption as low as possible. The design is analyzed, showing that the proposed solution allows accurate hysteresis adjustment without affecting the inherent circuit properties. The dynamic comparator is also implemented using a 180 nm commercially available CMOS technology. The results show that a variation of 550 mV of the control voltage allows an accurate hysteresis adjustment ranging from 0 to 40 mV, according to the input conditions. Moreover, the simplicity of the circuit in conjunction with the use of dynamic technology have allowed the best performances to be achieved compared to the current state of the art, in terms of energy with an FoM equal to 116 fJ/decision and silicon area of 180 µm2 .

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Yang, Mingyu, Yi Qian, Tianlei Pu, Zhikun Sun, Weijian Lu, Jiarui Zhang, and Zhengqiang Liu. "Development of a shaper and discriminator chip with time walk compensation for HFRS-TPC detector." Journal of Instrumentation 18, no. 07 (July 1, 2023): P07040. http://dx.doi.org/10.1088/1748-0221/18/07/p07040.

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Abstract In this paper, a shaper and discriminator ASIC chip with time-walk compensation(TWC) is designed using 180 nm CMOS technology for a TPC detector which will be assembled on High energy FRagment Separator(HFRS) beamlines under construction. It comprises a fast CR-RC shaper, two comparators, and a TWC module. The peak time of the shaper is 30 ns, and the propagation delay of the comparator is 2.4 ns (25 mV Overdrive). When the dynamic range of the TPC output charge is from 10 fC to 1000 fC, the time error of the trigger signal produced by the ASIC was measured to be less than 2 ns.

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Barakauskas, A., Albinas Kasparaitis, Saulius Kausinis, and R. Lazdinas. "Analysis of Dynamic Method of Line Scales Detection." Solid State Phenomena 147-149 (January 2009): 576–81. http://dx.doi.org/10.4028/www.scientific.net/ssp.147-149.576.

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The main causes of uncertainty in measurement regarding long-stroke line scales are line detection errors and external factors, especially temperature effects. The number of calibration errors of this sort increases with the extension of calibration time. Therefore, a dynamic method of line scale detection for modern long-stroke line scale comparators is used [1, 2, 3]. The article discusses the dynamic method of line scale detection by means of an optical microscope equipped with a photosensitive cell matrix and a line scale detection algorithm. Advantages of the dynamic method of scale calibration in terms of rate, accuracy and throughput are presented. The method’s error (detection parameters) correlations with detection rate, number of nominal lines, measuring rate, exposition delay are analyzed and mathematical models are described. The optimal values of these parameters are estimated. We are particularly interested in the improvement of the dynamic calibration program algorithm and minimization of uncertainty in measurement. The method was implemented and tested on the long-stroke line scale comparator, which has been developed and realized by JSC Precizika Metrology [3, 4, 5] in cooperation with VGTU and KUT.

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Chua-Chin Wang, Po-Ming Lee, Chi-Feng Wu, and Hsin-Long Wu. "High fan-in dynamic cmos comparators with low transistor count." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 50, no. 9 (September 2003): 1216–20. http://dx.doi.org/10.1109/tcsi.2003.816338.

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Nichols, M. J., and D. L. Sparks. "Independent feedback control of horizontal and vertical amplitude during oblique saccades evoked by electrical stimulation of the superior colliculus." Journal of Neurophysiology 76, no. 6 (December 1, 1996): 4080–93. http://dx.doi.org/10.1152/jn.1996.76.6.4080.

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1. In early local feedback models for controlling horizontal saccade amplitude, a feedback signal of instantaneous eye position is continuously subtracted from a reference signal of desired eye position at a comparator. The output of the comparator is dynamic motor error, the remaining distance the eyes must rotate to reach the saccadic goal. When feedback reduces dynamic motor error to zero, the saccade stops on target. Two classes of local feedback model have been proposed for controlling oblique saccades (i.e., saccades with both horizontal and vertical components). In “independent comparator” models, separate horizontal and vertical comparators maintain independent representations of horizontal and vertical dynamic motor error. Thus, once an oblique desired displacement signal is established, the horizontal and vertical amplitudes of oblique saccades are under independent feedback control. In “vectorial comparator” models, output cells in the motor map of the superior colliculus act as site-specific vectorial comparators. For a given oblique desired displacement, a single comparator controls the amplitudes of both components. Because vectorial comparator models do not maintain separate representations of horizontal and vertical dynamic motor error, they cannot exert independent control over the component amplitudes of oblique saccades. 2. We tested differential predictions of these two types of models by electrically stimulating sites in the superior colliculus of rhesus monkey immediately after either vertical or horizontal visually guided saccades. We have shown previously that, despite the fixed site of collicular stimulation, the amplitude of the visually guided saccades systematically alters the amplitude of the corresponding component (horizontal or vertical) of stimulation-evoked saccades. However, in the present study, we examined the effect of the visually guided saccades on the amplitude of the orthogonal component of stimulation-evoked saccades. 3. For a fixed site of collicular stimulation, vectorial comparator models predict that the initial visually guided saccade will influence both components of the ensuing stimulation-evoked saccade via the single feedback comparator. By contrast, independent comparator models permit the independent manipulation of the horizontal and vertical amplitudes of these oblique stimulation-evoked saccades. 4. In total, we collected data from 15 collicular stimulation sites. Immediately after either horizontal or vertical visually guided saccades of different amplitudes, we measured the horizontal and vertical amplitudes of saccades evoked by stimulation of the intermediate or deep layers of the superior colliculus. For each site, the duration, frequency, and current of the stimulation train were held constant. 5. Under these conditions, stimulation-evoked saccades followed visually guided saccades with short latency (18.1 +/- 6.7 ms, mean +/- SD). For every stimulation site tested, although the amplitude of the component of stimulation-evoked saccades corresponding to the direction of the preceding saccade (horizontal or vertical) varied systematically, the amplitude of the orthogonal component was roughly constant. 6. Thus the horizontal and vertical amplitudes of oblique stimulation-evoked saccades can be manipulated independently. Moreover, the peak velocity-amplitude relationships, the instantaneous velocity profiles, and the ratio of horizontal and vertical velocities and durations were very similar to those of visually guided saccades. 7. Independent comparator models can readily account for the ability to manipulate the amplitude of one component of oblique saccades without affecting the other. However, two-dimensional local feedback models that cannot exert independent control over the horizontal and vertical amplitudes of oblique saccades should be carefully reevaluated.

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Shahpari, N., M. Habibi, and P. Malcovati. "An early shutdown circuit for power reduction in high-precision dynamic comparators." AEU - International Journal of Electronics and Communications 118 (May 2020): 153144. http://dx.doi.org/10.1016/j.aeue.2020.153144.

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Fan, Xiang Ning, Hao Zheng, Yu Tao Sun, and Xiang Yan. "Design and Implementation of a 12-Bit 100MS/s ADC." Applied Mechanics and Materials 229-231 (November 2012): 1507–10. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1507.

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In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

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Lin, Zepeng. "Principle and performance analysis of low-power, high-speed, low-noise comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 83–93. http://dx.doi.org/10.54097/hset.v27i.3724.

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This paper studies three different structures proposed in recent years and discusses their advantages and properties respectively. A modified strong-arm latch voltage comparator is adapted to 3GHz operating frequency through additional current paths in the pre-amplifier. A latch-type comparator with a dynamic-biased pre-amplifier (DA) greatly reduces energy and improves noise performance through the stabilization of the input common-mode voltage. An FIA comparator further reduces energy and noise and greatly enhances the delay performance and the robustness of the comparator against different input common-mode voltage.

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CAMPOS-CANTÓN, I., J. A. PECINA-SÁNCHEZ, E. CAMPOS-CANTÓN, and H. C. ROSU. "A SIMPLE CIRCUIT WITH DYNAMIC LOGIC ARCHITECTURE OF BASIC LOGIC GATES." International Journal of Bifurcation and Chaos 20, no. 08 (August 2010): 2547–51. http://dx.doi.org/10.1142/s0218127410027179.

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We report experimental results obtained with a circuit possessing dynamic logic architecture based on one of the theoretical schemes proposed by H. Peng and collaborators in 2008. The schematic diagram of the electronic circuit and its implementation to get different basic logic gates are displayed and discussed. In particular, we show explicitly how to get the electronic NOR, NAND and XOR gates. The proposed electronic circuit is easy to build because it employs only resistors, operational amplifiers and comparators.

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Babenko, Mikhail, Maxim Deryabin, Stanislaw J. Piestrak, Piotr Patronik, Nikolay Chervyakov, Andrei Tchernykh, and Arutyun Avetisyan. "RNS Number Comparator Based on a Modified Diagonal Function." Electronics 9, no. 11 (October 27, 2020): 1784. http://dx.doi.org/10.3390/electronics9111784.

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Number comparison has long been recognized as one of the most fundamental non-modular arithmetic operations to be executed in a non-positional Residue Number System (RNS). In this paper, a new technique for designing comparators of RNS numbers represented in an arbitrary moduli set is presented. It is based on a newly introduced modified diagonal function, whose strictly monotonic properties make it possible to replace the cumbersome operations of finding the remainder of the division by a large and awkward number with significantly simpler computations involving only a power of 2 modulus. Comparators of numbers represented in sample RNSs composed of varying numbers of moduli and offering different dynamic ranges, designed using various methods, were synthesized for the 65 nm technology. The experimental results suggest that the new circuits enjoy a delay reduction ranging from over 11% to over 75% compared to the fastest circuits designed using existing methods. Moreover, it is achieved using less hardware, the reduction of which reaches over 41%, and is accompanied by significantly reduced power-consumption, which in several cases exceeds 100%. Therefore, it seems that the presented method leads to the design of the most efficient current hardware comparators of numbers represented using a general RNS moduli set.

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Hosseini Asl, S. Ali, Reza E. Rad, Arash Hejazi, YoungGun Pu, and Kang-Yoon Lee. "A 64-MHz 2.15-µW/MHz On-Chip Relaxation Oscillator with 130-ppm/°C Temperature Coefficient." Electronics 12, no. 5 (February 27, 2023): 1144. http://dx.doi.org/10.3390/electronics12051144.

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This paper presents a 2.15 µW/MHz at the frequency of 64 MHz relaxation oscillator with a dynamic range of frequency from 47.5 MHz to 80 MHz. To reduce the power consumption and improve energy efficiency, this work employs only one comparator and one capacitor to generate the output clock in comparison with conventional relaxation oscillator structures. A total of 50% ± 5% of the duty cycle is obtained for the output clock by implementing an auxiliary comparator. The proposed relaxation oscillator uses the output voltages of an external low-dropout (LDO) voltage and bandgap reference (BGR) for the required supply and reference voltages, respectively. Two current sources are implemented to provide the required currents for trimming the output frequency and driving the comparators. Measurement results indicate that the relaxation oscillator achieves a temperature coefficient (TC) of 130 ppm/°C over a wide temperature range from −25 °C to 135 °C at the frequency of 64 MHz. The relaxation oscillator consumes 115 µA of current at the frequency of 64 MHz under a low-dropout (LDO) voltage of 1.2 V. The proposed relaxation oscillator is analyzed and fabricated in standard 90 nm complementary metal-oxide semiconductor (CMOS) process, and the die area is 130 µm × 90 µm.

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Kilikevicius, Arturas, Jonas Skeivalas, Mindaugas Jurevicius, Kristina Kilikeviciene, Vytautas Turla, Eligijus Tolocka, Olegas Cernasejus, and Raimonda Lukauskaite. "Theoretical and experimental analysis of dynamic parameters of the leveling and centering device." Measurement and Control 52, no. 3-4 (February 28, 2019): 222–28. http://dx.doi.org/10.1177/0020294019830109.

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The article analyzes vibrational oscillation’s strength dissemination and the parameters in the centering and leveling table using the covariance function theory. The implementation of measurement techniques requires to use most advanced ideas, and to seek and develop new tools, based on which the direction of angle calibration system’s development could be substantiated and calibration methodologies could be enabled. Vibrational oscillation strength measurements across fixed five ring points’ observations were recorded on a time scale in five vectors arrays (matrices). The covariance functions have enabled the evaluation of the influence of the vibrations of the corresponding rings on the accuracy of the measurement results. Expressions of auto-covariance and cross-covariance functions show the changes in the time scale of the interdependence between the parameters of the corresponding vibrations of the rings on the smoothing device. These changes significantly affect the measurement data errors. The digital vibrational strength measurement arrays’ reciprocal covariance functions were calculated, and estimates of individual arrays’ auto-covariance functions, by changing the quantization interval on the time scale. The covariance model proposed by the authors for the analysis of the dynamical parameters of the centering–leveling devices can be used to investigate the dynamic characteristics of the angular comparators containing the said devices and at the same time to determine the ways of improving the precision of these angular comparators. The calculations were carried out using the special computer program developed by the authors of the Matlab7 Operator Package (The MathWorks, Inc. R2012a 7.14.0.739 License Number 699298).

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Jnayah, Salma, Intissar Moussa, and Adel Khedher. "IM Fed by Three-Level Inverter under DTC Strategy Combined with Sliding Mode Theory." Electronics 11, no. 22 (November 9, 2022): 3656. http://dx.doi.org/10.3390/electronics11223656.

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The classical direct torque control (CDTC) of the induction motor (IM) drive is characterized by high ripples in the stator flux and the electromagnetic torque waveforms due to the use of hysteresis comparators. Furthermore, the motor speed in this control strategy is ensured through a proportional integral (PI) regulator, due to its simple structure. Nonetheless, this controller is sensitive to load disturbances. Hence, it is not robust against parameter variance, which can degrade the motor performance. To overcome this deficiency, many endeavors have been conducted in the literature to ensure a high dynamic response of the motor in all speed ranges, with minimum flux and torque undulations. Thus, the DTC of an IM associated with a three-level inverter based on sliding mode (SM) flux, torque and speed controllers was adopted to substitute the hysteresis comparators and the traditional PI regulator, since the SM speed controller is able to prevail against external disturbances. The second contribution of this manuscript is to develop the proposed DTC_SM approach using the Xilinx System Generator (XSG) in order to implement it on a field programmable gate array (FPGA) Virtex 5 on account of its ability to adopt parallel processing. The hardware co-simulation results verify clearly the merits of the suggested modified DTC strategy.

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An, Shengbiao, Shuang Xia, Yue Ma, Arfan Ghani, Chan Hwang See, Raed A. Abd-Alhameed, Chuanfeng Niu, and Ruixia Yang. "A Low Power Sigma-Delta Modulator with Hybrid Architecture." Sensors 20, no. 18 (September 16, 2020): 5309. http://dx.doi.org/10.3390/s20185309.

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Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

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