Dissertations / Theses on the topic 'DYNAMIC COMPARATORS'

In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. This thesis work initially investigates and compares different structures of SAR control logics including the conventional structures and the delay line based controller. Additionally, it focuses on selection of suitable dynamic comparator architecture.  Based on this analysis, dynamic two-stage comparator is selected due to its energy efficiency and capability of working in low supply voltages. Eventually, based on these studies an ultra-low power 10-bit SAR ADC in 65 nm technology is designed. Simulation results predict that the ADC consumes 12.4nW and achieves an energy efficiency of 14.7fJ/conversion at supply voltage of 1V and sampling frequency of 1kS/s. It has a signal-to-noise-and-distortion (SINAD) ratio of 60.29dB and effective-number-of-bits (ENOB) of 9.72 bits. The ADC is functional down to supply voltage of 0.5V with proper performance and minimal power consumption of 6.28nW.

The present study is divided in two differentiable but conceptually interrelated sections. Within the first section (Chapters I, II, and III), the focus is on the assessment of the argumentative logic behind the multiculturalist proposal for equally divided societies, among equally positioned ethno-cultural groups. A critical and analytical review of the multiculturalist argumentative constructions shows that its justification lies on the dogmatic assumption of the equal worth or dignity of cultures, which is ontologically incorrect. Cultures cannot be axiologically compared. Instead, this study proposes a new approach focused on the equal functional value of each culture vis-à-vis the cultural producer and beneficiary (the individual). Therefore, it is argued that multiculturalism plea for equal ethno-cultural partition of the public societal space is based on political aspirations and then subjected to –in open, pluralist and democratic societies– the dynamics and methodological procedures of the so-called ‘democratic game’. The second section of this work (Chapters IV, V, and VI) focuses on the specific case of indigenous peoples from both a theoretical and jurisprudential point of view. First, the very notion of indigenous peoples is deconstructed and critically examined. Their special relationship with their traditional lands has been identified as the main objective characteristic that sustains their claims for cultural distinctiveness and differential legal treatment. Then, Chapters V and VI refer to a critical legal analysis of the jurisprudence of the Inter-American Court of Human Rights in connection with indigenous peoples’ land claims, and the role that the element of ‘special relationship with traditional lands’ has played in the recognition of their right to communal property over traditional lands as protected by the American Convention on Human Rights (Article 21 ACHR). In this sense, special attention is given to the interpretative methods applied by the Court, and –in particular– its underlined ontological assumptions.

The present study is divided in two differentiable but conceptually interrelated sections. Within the first section (Chapters I, II, and III), the focus is on the assessment of the argumentative logic behind the multiculturalist proposal for equally divided societies, among equally positioned ethno-cultural groups. A critical and analytical review of the multiculturalist argumentative constructions shows that its justification lies on the dogmatic assumption of the equal worth or dignity of cultures, which is ontologically incorrect. Cultures cannot be axiologically compared. Instead, this study proposes a new approach focused on the equal functional value of each culture vis-à-vis the cultural producer and beneficiary (the individual). Therefore, it is argued that multiculturalism plea for equal ethno-cultural partition of the public societal space is based on political aspirations and then subjected to –in open, pluralist and democratic societies– the dynamics and methodological procedures of the so-called ‘democratic game’. The second section of this work (Chapters IV, V, and VI) focuses on the specific case of indigenous peoples from both a theoretical and jurisprudential point of view. First, the very notion of indigenous peoples is deconstructed and critically examined. Their special relationship with their traditional lands has been identified as the main objective characteristic that sustains their claims for cultural distinctiveness and differential legal treatment. Then, Chapters V and VI refer to a critical legal analysis of the jurisprudence of the Inter-American Court of Human Rights in connection with indigenous peoples’ land claims, and the role that the element of ‘special relationship with traditional lands’ has played in the recognition of their right to communal property over traditional lands as protected by the American Convention on Human Rights (Article 21 ACHR). In this sense, special attention is given to the interpretative methods applied by the Court, and –in particular– its underlined ontological assumptions.

2010 - 2011
La materia dei contratti internazionali è andata acquisendo sempre maggiore importanza e diffusione negli ultimi anni. Questo fatto costituisce, in qualche modo, la conseguenza dei profondi cambiamenti che hanno interessato il mondo delle relazioni commerciali. Oggigiorno, grazie alla creazione di un mercato unico europeo e, soprattutto, quale conseguenza diretta della globalizzazione, la gran parte dei businessmen tendono a spingere i propri affari ben oltre i confini nazionali, quando non accantonano addirittura la dimensione “geografica” e si avvalgono dei più moderni strumenti della comunicazione forniti dalla tecnologia (e-commerce). La categoria dei contratti internazionali dà vita, invero, a non pochi problemi: anzitutto, non è dato rinvenirne una specifica definizione e non è sempre facile stabilire quale regime normativo (nazionale) sia applicabile nel singolo caso, a prescindere dalle apposite regole già esistenti. Un altro aspetto molto rilevante è costituito dalla notevole complessità (spesso dovuta al valore economico dell’operazione commerciale) della fase delle negoziazioni durante la quale le parti, solitamente, si comunicano l’un l’altra la propria volontà e la misura entro la quale sono disposti a farsi reciproche concessioni, fissano i singoli steps attraverso cui addivenire al raggiungimento di un accordo, valutano la concreta fattibilità dell’affare. In un tale contesto complesso esse, spesso, fissano in appositi documenti i profili del futuro regolamento contrattuale su cui hanno già raggiunto un accordo e, nel far questo, non di rado escludono i lawyers dalla redazione degli stessi. Il risultato pratico è che, piuttosto frequentemente, le formulazioni di questi documenti danno vita a notevoli problemi interpretativi. La risoluzione di una controversia emersa dalla lettera di un contratto internazionale rende necessario che il giudice o, più spesso, l’arbitro tenga in debito conto gli sviluppi della legislazione in molti degli ordinamenti nazionali, degli strumenti normativi transnazionali e di ogni altra pratica emersa in tema di accordi commerciali. Giudici e arbitri, infatti, nel formulare le proprie decisioni non possono prescindere da tali sviluppi avutisi nella pratica del commercio, andando oltre i confini tracciati dalla normativa nazionale prescelta. Questa tesi si propone di analizzare gli effetti connessi al contenuto dei documenti pre-contrattuali, secondo quella che è la disciplina degli ordinamenti di Common Law e di Civil Law, nonché negli strumenti a vocazione transnazionale come, ad esempio, i Principi UNIDROIT, i Principles of European Contract Law, Draft Common Frame of Reference, U.N. Convention on the International Sales of Good (CISG) e, emenata recentemente, la proposta di regolamento Common European Sales Law. Più specificamente, due sono i profili presi in considerazione: anzitutto, ci si domanda fino a che punto una dichiarazione pre-contrattuale possa considerarsi vincolante in sé e per sé. In secondo luogo, si tratta di appurare fino a che punto una dichiarazione pre-contrattuale possa produrre effetti giuridici venendo incorporata nel futuro contratto o, comunque, inducendo alla stipula del contratto stesso. Il metodo d’indagine adottato consiste, anzitutto, nell’analisi delle regole sulla formazione dei contratti previste dagli ordinamenti più rappresentativi afferenti al Common Law ed al Civili Law, nonché dai documenti transazionali su menzionati. Segue, poi, uno studio sull’interpretazione e la qualificazione delle lettere di intenti e degli altri pre-contractual statements risultati di maggiore impiego nella prassi del commercio internazionale e, prima ancora, alla luce delle disposizioni normative riconducibili agli ordinamenti nazionali. La tesi si propone, in definitiva, di conseguire i seguenti obiettivi: 1) verificare quali siano gli eventuali riflessi sugli attuali trends relativi alla disciplina nazionale e transnazionale; 2) individuare quali fattori di policy incidono sulla evoluzione giuridica; 3) appurare se si venga a creare, o meno, una qualche interferenza tra diritto nazionale e transnazionale; 4) stabilire quale sia la relazione esistente tra Hard Law e Soft Law. [a cura dell'autore]
X n.s.

Il presente lavoro di tesi, svolto presso Xilinx in Irlanda, è focalizzato alla calibrazione e misura delle non idealità dinamiche presenti nei convertitori digitali-analogici (Digital to Time Converter) a radio frequenza, con architettura a Current-Steering. Questa architettura, controllata da una logica combinata di bit termometrici (6 MSB) e bit binari (10 LSB), permette di avere alte prestazioni di velocità. Le non idealità consistono nel disallineamento temporale di questi bit, che aumentano tanto più la frequenza del dato in ingresso aumenta. La necessità di metodi di calibrazione per questi effetti è necessaria al fine di ottenere delle prestazioni del convertitore accettabili per il mercato. In questa tesi viene quindi data una visione riguardante la calibrazione di questi errori temporali, forniti da un modello scritto in Verilog A, di un convertitore RFDAC a 16 bit operante con una frequenza di clock di 6.4GHz. In realtà, su silicio, questi errori temporali devono essere misurati con precisione da un sistema di misura. Si è contribuito al progetto e alla caratterizzazione, utilizzando librerie FinFET TSMC (Taiwan Semiconductor Manufacturing Company) in Cadence Virtuoso, di un sistema di misura integrato che consente di misurare il disallineamento temporale di questi bit, con una precisione di 150fs.

This dissertation is an initial study of how modern engineering control may be applied to reverse engineer homeostasis in metabolic pathways using high-throughput biological data. This attempt to reconcile differences between engineering control and biological homeostasis from an interdisciplinary perspective is motivated not only by the observation that robust behavior in metabolic pathways resembles stabilized dynamics in controlled systems, but also by the challenges forewarned in achieving a true meeting of minds between engineers and biologists. To do this, a comparator model is developed and applied to model the effect of single-gene (SPT) overexpression on C16:0 sphingolipid de novo biosynthesis in vitro, specifically to simulate and predict potential homeostatic pathway interactions between the sphingolipid metabolites. Sphingolipid de novo biosynthesis is highly regulated because its pathway intermediates are highly bioactive. Alterations in sphingolipid synthesis, storage, and metabolism are implicated in human diseases. In addition, when variation in structure is considered, sphingolipids are one of the most diverse and complex families of biomolecules. To complete the modeling paradigm, wild type cells are defi ned as the reference that exhibits the "desired" pathway dynamics that the treated cells approach. Key model results show that the proposed modern engineering control approach using a comparator to reverse engineer homeostasis in metabolic systems is: (a) eff ective in capturing observed pathway dynamics from experimental data, with no signifi cant di fference in precision from existing models, (b) robust to potential errors in estimating state-space parameters as a result of sparse data, (c) generalizable to model other metabolic systems, as demonstrated by testing on a separate independent dataset, and (d) biologically relevant in terms of predicting steady-state feedback as a result of homeostasis that is verifi ed in literature and with additional independent data from drug dosage experiments.

This diploma thesis deals with design methods and optimization techniques of dynamic latched comparators. It compares latched and continuous comparators and describes their principle. Then it analyses three popular latched comparator structures with respect to offset, speed and kickback noise. It shows practical comparator design focused on offset precision.

Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm

Il paradigma delle Reti Neurali Artificiali (ANN) consiste nell’applicazione del modello neurale “biologico” per la risoluzione di problemi che spesso sono troppo complessi per un’architettura di Von Neumann. La letteratura offre differenti approcci per l’implementazione di ANN. Qualche implementazione è di tipo software, altre sono soluzioni circuitali come circuiti digitali full-custom o FPGA (Field Programmable Gate Array), come pure circuiti analogici, e il tipo di implementazione di certo dipende dal tempo di esecuzione adeguato al tipo di applicazione. Questa tesi riguarda la progettazione di nuovi circuiti analogici adattati per le Reti Neurali. In particolare, saranno utilizzate le Reti Neurali Cellulari (CNN) proposte nel 1981 dal Prof. L.O.Chua (University of California – Berkeley). Il “Laboratorio di Circuiti” dell’Università di Roma “Tor Vergata” ha progettato e realizzato alcuni chip analogici dedicati a questo tipo di Reti Neurali. Questi chip appartengono alla famiglia “Digital Programmable CNN” (DPCNN) e presentano principalmente due caratteristiche: la programmabilità digitale dei pesi sinaptici come una particolare architettura orientata ad una struttura interconnessa (cioè connettendo tra loro più di questi chip è possibile realizzare reti di grande dimensione). In questa tesi viene data una visione di insieme sulle ANN, sulle CNN e sulle Star-CNN: cosa sono, come funzionano ed a cosa servono. In perticolare verrà descritta la famiglia DP-CNN. Questa tesi propone una nuova architettura chiamata TD-CNN (Time Division CNN), che sfrutta una particolare strategia mirata a ridurra l’area di occupazione su silicio di una cella elementare, per aumentare l’integrabilità della rete. Oltretutto la stessa strategia a divisione di tempo verrà applicata alle TD-Star CNN. In particolare questi circuiti sono le non-linerità digitalmente programmabili (cioè DPTA – Digital Programmable Transconductance Amplifier e DPTA – Digital Programmable Transconductance Comparator) e circuiti particolari per la multiplazione (DM-SH – Dynamic Mirror Sample and Hold e DM-MUX – Dynamic Mirror Multiplexer). Sono mostrate alcune simulazioni dei circuiti per permettere lo studio di queste nuove architetture, e la modifica delle dinamiche introdotte dalla strategia a divisione di tempo.
The Artificial Neural Network (ANN) paradigm consists of the application of biological “neural” models to the solution of particular problems that often are very hard to solve for the classical “Von Neumann” architectures. Different are the approaches proposed in literature for the implementation of an ANN. Some of them are software implementations only while, others are circuital solutions as full custom digital circuits or programmed FPGAs (Field Programmable Gate Array) as well as analogue circuits and the typology of the implementation certainly depends on the length of the processing time that you believe adequate for the particular application. This thesis is focused on the design of new analogue circuits well suited for Neural Network applications. In particular, the class of the Cellular Neural Networks (CNN), proposed in 1981 by Prof. L.O.Chua (University of California - Berkeley), will be exploited. In this area, the “Laboratorio Circuiti” at University of Rome “Tor Vergata” designed and manufactured several analogue chips devoted to this class of Neural Networks. These chips belong to the Digital Programmable CNN (DPCNN) chip family and present two main features: the digital programmability of the synaptic weights as well as a special architecture oriented to an interconnection structure (i.e. it is possible to carry out large network by connecting together more of these chips). In this thesis work you will find an overview about the Artificial Neural Network, the Cellular Neural Network and the Star Cellular Neural Network: what they are, how they work and why they are useful. In particular, the DP-CNN chip family will be deeply described. This thesis proposes the TD-CNN (Time Division CNN), a particular design strategy, devoted to reduce the silicon area occupation of the a elementary cell in order to improve the VLSI integrability of the network. Moreover, the same time-division strategy will be applied to TD-Star CNN. In particular, these circuits consist of the digitally programmable non-linearity circuits (i.e. the Digital Programmable Transconductance Amplifier - DPTA and Digital Programmable Transconductance Comparator – DTPC) and special circuit for to carry out the multiplexing feature (i.e. the Dynamic Mirror Sample and Hold – DM-SH and the Multiplexer – DM-MUX). Several circuital simulations will be shown in order to study the behavior of this modified architecture and the modifications on the dynamics introduced by the time division strategy.

L’utilisation de réseaux de neurones artificiels pour divers types de traitements d’information bio-inspirés est une technique de plus en plus répandue dans le domaine de l’intelligence artificielle. Leur fonctionnement diffère avantageusement de celui des ordinateurs conventionnels en permettant une plus grande parallélisation des calculs, ce qui explique pourquoi autant d’efforts sont déployés afin de réaliser une plate-forme matérielle dédiée à leur simulation. Pour ce projet, une architecture matérielle flexible simulant efficacement un réseau de neurones à décharges est présentée. Celle-ci se distingue des architectures existantes notamment parce qu’elle utilise une approche de simulation à événements discrets et parce qu’elle permet une détection efficace des événements simultanés. Ces caractéristiques en font une plate-forme de choix pour la simulation de réseaux de neurones à décharges de plus de 100 000 neurones où un niveau important de synchronie des décharges neuronales est atteint. Afin d’en démontrer les performances, une application en traitement d’images utilisant cette architecture a été réalisée sur FPGA. Cette application a permis de démontrer que la structure proposée pouvait simuler jusqu’à 2[indice supérieur 17] neurones et traiter des dizaines de millions d’événements par secondes lorsque cadencé à 100 MHz.

Organizzata in tre saggi, questa tesi si pone l’obiettivo di consentire una migliore comprensione del legame tra crescita e istituzioni, e dei meccanismi attraverso cui gli assetti istituzionali possono condizionare i sentieri economici. Riconoscendo, sulla base di considerazioni storiche, il potere esemplificativo delle ex Repubbliche Socialiste Sovietiche e della loro comune esperienza passata, questo lavoro fornisce, da un lato, una struttura empirica di riferimento per esaminare l’impatto sulla performance economica di un insieme di istituzioni, concretamente legate al funzionamento dell’attività economica; dall’altro, approfondisce lo studio degli effetti e delle determinanti delle azioni di policy. Il primo saggio offre una disamina della letteratura riguardante il legame crescita e istituzioni, fornendo un quadro esaustivo degli sviluppi teorici ed empirici, e illustra diversi aspetti che possono essere concepiti come obiettivi per la ricerca futura; il secondo, attraverso la costruzione di un modello statico e di un modello dinamico, quantifica l’impatto delle istituzioni economiche sui sentieri di crescita di questi paesi, impiegando e analizzando numerose tecniche di stima; il terzo saggio formula diverse specificazioni e affronta il tema rilevante del ruolo degli interventi di policy sullo sviluppo economico e dell’effetto delle istituzioni politiche su comportamenti e decisioni del governo.
Organized in three essays, this thesis aims at achieving a better understanding of the link between growth and institutions, and of the mechanisms through which the institutional arrangements affect the economic paths. Exploiting the past common experience of the Former Soviet Union economies, this work provides an empirical framework to examine the impact on the economic performance of a set of institutions concretely related to the “functioning” of the economic activity and offers a first attempt to include in this research program the study of the consequences of the government actions. The first essay offers a thorough review of the literature researching on the link between economic growth and institutions, and elucidates several issues that deserve further attention; the second develops a static and a dynamic approach to assess, using multiple estimation techniques, the impact of a set of economic institutions on the growth paths of these countries; the third essay, through several formal specifications, deals with the relevant issue of the role of policy measures and of the effect of the political institutions on the governments behaviour.

Organizzata in tre saggi, questa tesi si pone l’obiettivo di consentire una migliore comprensione del legame tra crescita e istituzioni, e dei meccanismi attraverso cui gli assetti istituzionali possono condizionare i sentieri economici. Riconoscendo, sulla base di considerazioni storiche, il potere esemplificativo delle ex Repubbliche Socialiste Sovietiche e della loro comune esperienza passata, questo lavoro fornisce, da un lato, una struttura empirica di riferimento per esaminare l’impatto sulla performance economica di un insieme di istituzioni, concretamente legate al funzionamento dell’attività economica; dall’altro, approfondisce lo studio degli effetti e delle determinanti delle azioni di policy. Il primo saggio offre una disamina della letteratura riguardante il legame crescita e istituzioni, fornendo un quadro esaustivo degli sviluppi teorici ed empirici, e illustra diversi aspetti che possono essere concepiti come obiettivi per la ricerca futura; il secondo, attraverso la costruzione di un modello statico e di un modello dinamico, quantifica l’impatto delle istituzioni economiche sui sentieri di crescita di questi paesi, impiegando e analizzando numerose tecniche di stima; il terzo saggio formula diverse specificazioni e affronta il tema rilevante del ruolo degli interventi di policy sullo sviluppo economico e dell’effetto delle istituzioni politiche su comportamenti e decisioni del governo.
Organized in three essays, this thesis aims at achieving a better understanding of the link between growth and institutions, and of the mechanisms through which the institutional arrangements affect the economic paths. Exploiting the past common experience of the Former Soviet Union economies, this work provides an empirical framework to examine the impact on the economic performance of a set of institutions concretely related to the “functioning” of the economic activity and offers a first attempt to include in this research program the study of the consequences of the government actions. The first essay offers a thorough review of the literature researching on the link between economic growth and institutions, and elucidates several issues that deserve further attention; the second develops a static and a dynamic approach to assess, using multiple estimation techniques, the impact of a set of economic institutions on the growth paths of these countries; the third essay, through several formal specifications, deals with the relevant issue of the role of policy measures and of the effect of the political institutions on the governments behaviour.

碩士
國立交通大學
電子研究所
101
This thesis presents two low voltage, high speed dynamic comparators. It improves the core circuit “latch architecture”, so the comparators can operate at low supply voltage. The comparators have the large enough overdrive voltage to keep the transconductance, so the comparators can maintain the high speed operation.And realizing comparators in 65nm CMOS. The first comparator operate at supply voltage is 0.6V, the operating speed is 1GHz, and the input referred offset(1&;#1049434;) is 6mV, the input referred noise(1&;#1049434;) is 0.65mV, and the sensitivity is 3mV to achieve the BER is 10-9. And the power consumption is only 38&;#1049221;W. The second comparator operate at supply voltage is 0.6V, the operating speed is 1.3GHz, and the input referred offset(1&;#1049434;) is 7.5mV, the input referred noise(1&;#1049434;) is 0.5mV, and the sensitivity is 4.2mV to achieve the BER is 10-9. And the power consumption is 64&;#1049221;W.

In many applications there is a growing demand for the development of low voltage and low power circuits and systems. Low power consumption is of great interest because it increases the battery lifetime. One of the main building blocks in many applications is the analogue-to-digital converter (ADC) which serves as an interface between the analogue world and the digital processing unit. In all these designs the comparator of the ADC, which is one the most power hungry blocks, is always on. In order to reduce the power consumption of the ADC it is possible to turn the comparator off when the decision is made and the comparator is not needed until the next clock cycle. This work provides a comprehensive review about a variety of comparator designs - in terms of performance, power and delay. The initial part of the work was working with static comparators architectures with different pre-amplifier modifications .Later part deals with two dynamic comparator architectures. The main components of such comparators are the preamplifier and latch circuit. Preamplifier is used for removing the kickback noise and the dc offset voltage while the latch is required for the comparison. The proposed architectures operate on three phases which are non-overlapping and dissipate 7ìW power when operated on a single 1V supply voltage. The latch is basically a back to back connected inverter circuit which inactivated only during the second phase.

In today's reality, where claim for versatile battery functioned gadgets is expanding, a noteworthy plunge is given in the direction of low power approaches for rapid applications. To reduce the feature size is the cause to reduce the power. The comparator is one of the most versatile circuits in analog circuit design. It serves as an input stage of most of the ADCs. The comparator has noteworthy effect on the execution of the objective application which depends on the architecture and form of it. In this thesis, a clock based comparator is analysed in terms of average power dissipation, delay power-delay product (PDP). An investigation of modified double tail dynamic comparator has been carried out using post layout simulations. Based on the analytical expressions, a new comparator circuit that consumes less power has been proposed. Simple modification has been done by adding MOS transistor that works as voltage variable resistor (MOSFET in triode region) to reduce power. The delay of the proposed circuit is also improved as the voltage variable resistor increases the differential voltage in pre amplifier stage. Post layout simulation of the design in 90nm CMOS technology is presented. The average power dissipations of the proposed comparator at two different supply voltages which is 0.6 and 1.2 V are 0.842 µW and 2.68 µW respectively. The clock frequency at which circuit gives proper output of the proposed circuit goes up to 1.33GHz and 1GHz at supply voltages of 1.2V and 0.6V.

碩士
國立東華大學
電機工程學系
103
Low supply voltage is a good way to achieve low power consumption. Besides, there are many applications about high-speed low-resolution analog-to-digital converter. For example: Disk Driver Front-end、High-speed Backplane、Ultrawideband Receiver and Millimeter-wave Receiver. The feature of ultra-low power is as needed as possible for portable devices. A Gm-enhancement low-voltage dynamic comparator is proposed. The speed can achieve 100 MHz at 0.6V in 0.18um CMOS process. And we realize a low-voltage low-power Flash ADC in UMC 180nm CMOS Logic &; Mixed Mode 1P6M Process. The simulation results shows Flash ADC sampled rate achieve 10MHz at 0.6V. The effective number of bit is 3.9, the power consumption of Flash ADC is 0.035mW, and the chip area is 0.057mm 2.

碩士
國立中山大學
電機工程學系研究所
88
Three different topics associated with their respective applications are proposed in this thesis. The first application is the implementation of a fast tagged sorter. A novel and high-speed realization of the tagged sorting algorithm is presented. Meanwhile, the problems to detect whether the queue is empty or full is also resolved without increasing any hardware cost. The second topic is focused on the implementation of a fast dynamic 64-bit comparator with small transistor count. The entire 64-bit comparator is composed of equality comparators and zero/one detectors, which are proposed by C.-F. Wu. The problem to handle a large fan-in requirement is also resolved in our design. The third topic is to carry out a power demand monitor system for factories. Not only can it monitor the factory’s power network with a graphical user interface, but also can turn off the unessential equipments automatically when the total power consumed by the factory is larger than what was expected.

A new fully differential CMOS dynamic comparator using positive feedback suitable for pipeline A/D converters with low power dissipation, low offset, low noise and high speed is proposed. Inputs are reconfigured from typical differential pair comparator such that near equal current distribution in the input transistors can be achieved for a meta stable point of the comparator. Restricted signal swing clock for the tail current is also used to ensure constant currents in the differential pairs. Nearly 18mV offset voltage is easily achieved with the proposed structure making it favorable for flash and pipeline data conversion applications. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources, has a small power dissipation, less hysteresis band, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Test structures of the comparators, designed in GPDK 90 nm are measured to determine offset power dissipation and speed with 1.8 V are compared and the superior features of the proposed comparator are established.

Low intrinsic transistor gain in nanometer CMOS technologies imposes implementation difficulties of switched-capacitor (SC) circuits based on a conventional OTA used in delta-sigma ADCs. Zero-crossing-based circuits (ZCBCs) have been proposed as replacements for conventional OTAs in SC circuits, but the efficiency of existing ZCBC-based delta-sigma ADCs trails that of state-of-art conventional delta-sigma ADCs. The dynamic comparator-based OTA (DCBOTA) is a novel circuit block that performs an equivalent operation of a conventional OTA in a SC circuit by repeatedly detecting the input (Vg) sign and applying output current pulses to move Vg toward zero. The current pulse amplitude, set to the maximum at the beginning of a charge transfer phase, is decremented each time Vg crosses zero. Once Vg crosses zero at the minimum current pulse amplitude, the operation above ceases. The discrete-time nature of Vg comparison and current pulse injection in the DCBOTA allows use of a dynamic regenerative comparator, which is fast and scaling friendly, instead of the slow scaling-unfriendly open-loop zero-crossing detector used in ZCBCs. A small final Vg step size is required for high settling accuracy, but it can result in a long settling time. Analysis reveals that the DCBOTA settling time is minimized with a current pulse scaling factor of 3.59 for any final Vg step size. The comparator and switch noise affects the settling DCBOTA settling accuracy. The relationship between the minimum Vg step size, comparator noise, and switch noise for a given input-referred noise is shown. The DCBOTA consists of a dynamic regenerative comparator, control logic, and current pulse driver. The comparator evaluates the Vg sign when enabled by the control logic. The control logic enables and resets the comparator, and controls the current pulse amplitude. The current pulse driver applies either a positive or negative output current pulse when triggered by the comparator output. A 1-1-1-1 MASH delta-sigma ADC using DCBOTAs fabricated in a 65-nm CMOS technology achieved 70.4 dB of peak SNDR over a 2.5-MHz bandwidth dissipating 3.89 mW of power from a 1.2-V supply. Measurements show linear ADC power scaling over sampling frequencies provided by the dynamic operation of the DCBOTAs.

A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to noise than the previous reported work is proposed. Backto- back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Previous reported comparators are designed and simulated their DC response and Transient response in Cadence® Virtuoso Analog Design Environment using GPDK 90nm technology. Layouts of the proposed comparator have been done in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS has been checked and compared with the corresponding circuits and RC extracted diagram has been generated. After that post layout simulation with 1V supply voltage has been done and compared the speed, power dissipation, Area, delay with the results before layout and the superior features of the proposed comparator are established.