Academic literature on the topic 'Dispositifs CMOS et integration'
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Journal articles on the topic "Dispositifs CMOS et integration":
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Yadav, Sachin, Pieter Cardinael, Ming Zhao, Komal Vondkar, Uthayasankaran Peralagu, Alireza Alian, Raul Rodriguez, et al. "(Digital Presentation) Substrate Effects in GaN-on-Si Hemt Technology for RF FEM Applications." ECS Meeting Abstracts MA2022-02, no. 32 (October 9, 2022): 1208. http://dx.doi.org/10.1149/ma2022-02321208mtgabs.
Abstract:
Abstract : GaN-on-Si HEMTs are emerging as a viable candidate for front-end-of-module (FEM) implementation in 5G and beyond user equipment and small-cell applications [1][2]. This is because GaN HEMTs based power amplifiers and switches have high power handling capability as well as excellent switch figure-of-merit (Ron × Coff). The cost-effective integration of GaN HEMTs on silicon substrates not only benefit from standard CMOS back-end-of-the-line processing but also wafer-level integration with Si-CMOS [1][3], enabling complex functionality and better performance than the standalone counterparts. An example can be a hybrid beamformer where GaN HEMTs can enable much smaller antenna array and therefore a smaller system form factor. For 5G wireless applications, standalone or co-integrated GaN HEMT based FEMs can lead to a more energy efficient and compact system as compared to standalone Si-CMOS technologies. However, for both amplifiers and switches, GaN-on-Si HEMTs present thermal management and substrate loss related issues. In this work, we study and model the impact of GaN HEMT integration on Si substrate on RF substrate losses and non-linearities. The growth of III-N buffer is the most significant factor in determining RF losses and harmonic distortion contribution from the substrate. High temperature annealing and ion implantation steps encountered during HEMT processing can also degrade the substrate performance. In addition, we demonstrate a direct co-relation between substrate losses and harmonic distortion analogous to silicon-on-insulator technologies (Figure 1). However, the bias dependence of RF losses and harmonics show a strong time dependence (memory effects) which is more complex to model [11]. We discuss the approaches to understand and model these effects. References: [1] H. W. Then et al, IEEE IEDM Tech. Dig., 2021, pp. 230-234. [2] B. Parvais et al, IEEE IEDM Tech. Dig., 2020, pp. 155-158. [3] W. E. Hoke et al, J. Vac. Sci. Technol. B 30, 02B101 (2012). [4] Drillet F et al, IJMWT 13, 517–522, 2021. [5] L. Cao et al, CSMANTECH conference Tech. Dig., 2020. [6] Roda Neve et al, IEEE TED, Vol. 59, NO. 4, pp. 924-932, 2012. [7] S. Yadav et al., in IEEE IEDM Tech. Dig., 2020, pp. 159-162. [8] Rack et al, ECS Trans., 92 (4), pp. 79-94, 2019. [9] Zhu et al, IEEE Microw. Wireless Compon. Lett., vol. 28, no. 8, pp. 377–379, 2018. [10] Raskin et al, IEEE SiRFIC, 2015. [11] P. Cardinael et al, IEEE ESSDERC 2021, pp. 303-306. Figure 1
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Mori, Takahiro. "(Invited, Digital Presentation) Silicon Compatible Quantum Computers: Challenges in Devices, Integration, and Circuits." ECS Meeting Abstracts MA2022-01, no. 29 (July 7, 2022): 1297. http://dx.doi.org/10.1149/ma2022-01291297mtgabs.
Abstract:
Quantum computers have been attractive because they could realize large-scale and highly complicated calculations that conventional computers cannot solve within a finite time. The large-scale integration of qubits, which are the building block of quantum computers, is required to realize their practical application. Indeed, fault-tolerant quantum computers require the integration of one million qubits. Therefore, silicon qubits is a high-profile candidate because they have advanced process and miniaturization technologies developed with VLSI. In addition, silicon qubits are advantageous in operation temperature. Superconductor qubits operate at the cryogenic temperature at around a few tens mK; in contrast, the operation principle of silicon qubits can operate at a much higher temperature over 1 K. The high-temperature operation can realize quantum computers with small and high-power refrigerators; therefore, we can expect desktop quantum computers instead of ongoing supercomputer-size ones. We must promote integration technology development for silicon qubits; however, the silicon qubit research was mainly in the physics field. Then, nowadays, the integration technology development is accelerated in the world. The challenges are in all conventional research fields: devices, integration, and circuits. We must re-develop the silicon technologies for quantum. For example, on the device design, now we do not have a good tool to design the qubits like TCAD; therefore, we must re-develop the TCAD technologies for quantum [1]. Actually, this is the starting point of our recent research activities; we are going to develop a quantum device simulator, clarify the requirements on the fabrication process of silicon qubits, and propose new technologies to reduce the variability to realize large-scale integration [2]. As for the integration, the quantum calculation circuits require several integrated items: qubits, qubit couplers, micro-magnets, and readout systems. The situation is quite different from the conventional VLSI case for which only the transistors should be integrated. Therefore, we must go re-developing new technologies to integrate all these items. Regarding the circuits, we must use CMOS circuits to generate input signals for qubits and readout the results of quantum calculation, which should be operated at cryogenic temperature. This is so-called “cryo-CMOS.” We must explore a new side of the transistor technologies, which is not investigated so far, because the physics of the MOSFET operation is quite different from the conventional room-temperature operation, hampering the circuit design due to the lack of the device operation model. In this situation, despite the long history of MOSFETs, new phenomena of transistor operation are discovered. For example, the low-frequency current noise increases at a low temperature. The origin of the noise is on the interface traps, instead of the fixed charges in the gate oxides as is the case for room temperature operation [3]. Therefore, we must re-developing CMOS circuit technologies from the bottom of the technologies, device physics. In this presentation, I’m going to overview the status of silicon technology developments for quantum from the viewpoints of devices, integration, and circuits. Also, we introduce some of our recent results to contribute to the developments. Acknowledgment: Our work is supported by MEXT Quantum Leap Flagship Program (Q-LEAP) JPMXS0118069228. [1] H. Asai et al., IEEE Electron Devices Technology and Manufacturing Conference 2021. [2] S. Iizuka et al., Tech. Dig. Symp. VLSI Technology 2021. [3] H. Oka et al., Tech. Dig. Symp. VLSI Technology 2020.
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Chaudhary, Mayur, and Yu-Lun Chueh. "Dual Threshold and Memory Switching Induced By Conducting Filament Morphology in Ag/WSe2 Based ECM Cell." ECS Meeting Abstracts MA2022-02, no. 36 (October 9, 2022): 1334. http://dx.doi.org/10.1149/ma2022-02361334mtgabs.
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In recent years, two-dimensional (2D) materials-based RRAMs have gained high importance because of their thermal and mechanical stability, and better potentiation-depression controllability. 2D materials based conductive bridge random access memory (CBRAM) has been considered as promising approach for neuromorphic and image processing technology [1]. Despite much progress in CMOS technology, the growth and deposition technology of 2D materials for semiconductor integrated circuit are much complex and is generally available at wafer scale [2]. In addition, high growth temperature for high quality of 2D materials complicates direct wafer growth and makes transfer process desirable. At the device level, challenges are linked to controlled and uniform growth of 2D material for high density electronic structure. Recently, discreet 2D based memristor have been used in crossbar structure as synapse for neuromorphic computing. However, the plasma-assisted chemical vapor reaction (PACVR) based memristor for neuromorphic application are rarely demonstrated. Here, we report the co-integration of plasma-assisted chemical vapor reaction (PACVR) with silicon CMOS technology to provide brain-inspired computing device. PACVR offers compatibility with temperature limited 3D integration process and also provides much better thickness control over a large area. Furthermore, it an easy platform for direct and controlled synthesis of TMDs compared to conventional CVD approach. The PACVR grown WSe2 layer (~2 nm) on silicon substrate is realized, which exhibits both threshold and bipolar switching. The threshold and bipolar switching emulate integrate-fire neuron function and is obtained by modulating the compliance current in the device. The dynamics of the switching is closely related to the diffusive dynamics of the active metal (Ag or Cu) which can be controlled by device current. As a result, the WSe2/Si memristor shows synaptic behavior for neuromorphic system with learning accuracy of 96%. References: Wang, C.-Y. et al. 2D layered materials for memristive and neuromorphic applications. Electron. Mater. 6, 1901107 (2020) Zhang, X. et al. Two-dimensional MoS2-enabled flexible rectenna for Wi-Fi-band wireless energy harvesting. Nature 566, 368–372 (2019). Figure 1
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Daszko, Sebastian, Carsten Richter, Jens Martin, Katrin Berger, Uta Juda, Christiane Frank-Rotsch, Patrick Steglich, and Karoline Stolze. "Transfer Printable Single-Crystalline Coupons for III-V on Si Integration." ECS Meeting Abstracts MA2022-02, no. 17 (October 9, 2022): 863. http://dx.doi.org/10.1149/ma2022-0217863mtgabs.
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The next-generation internet (6G) requires highly functional devices that e.g. realize frequencies in the THz range for higher data rates and lower latencies. Those requirements exceed the physical limits of established CMOS technologies based on silicon (Si). Hence, there is demand for other semiconductor materials with superior electronic and optical properties that complement Si. One of the key candidates is the III-V compound semiconductor, indium phosphide (InP). Due to its high electron mobility and direct band gap, InP-based devices allow access to frequencies >100 GHz and operate at the optical fibre compatible wavelength of 1.55 μm.1 With the perspective of leveraging the advantages of Si-based CMOS technology and III-V semiconductors, hetero-integration of III-V materials on Si is of great interest. However, existing integration approaches entail certain disadvantages: (i) High dislocation densities due to the lattice mismatch of InP and Si for integration via hetero-epitaxial growth;2 (ii) limited integration density and the requirement of accurate alignment for flip-chip integration; and (iii) high process-related losses of Si and III-V materials as well as thermal stress and low thermal conductivity of adhesive layers degrading device performance for wafer/die bonding technologies.3 Another promising approach for III-V-on-Si integration is micro-transfer-printing (μTP) that involves pick-up and transfer of µm-small chips from a source substrate to a target substrate with high alignment accuracy by using an elastomeric stamp. Advantages of μTP are high integration densities and efficient material use. The technique was already implemented for III-V-on-Si photonic integrated circuits by transfer of epitaxial III-V layers.4 However, using sacrificial III-V interlayers for release and adhesives for bonding still leads to transfer issues and low operation temperature for the devices, respectively. We pursue a new approach to hetero-integration of III-V on Si that aims at the transfer of single-crystalline InP coupons onto Si via μTP. This will be achieved by obtaining crystalline coupons with a thickness of d ≤ 10 µm and two polished surfaces that attain low roughness, needed i.a. for µTP. If the high structural quality of the single-crystalline InP source material can be maintained, this process will provide high quality templates for subsequent epitaxial growth. Towards this goal, we developed a sophisticated micro-preparation process in cooperation with the Leibniz Institute for High Performance Microelectronics IHP.5 Starting from 4-inch single crystals with homogeneous, low dislocation density of 2×103 cm- 2 grown at IKZ,6 thinned InP dies were obtained by sawing, grinding and employing an optimized two-step chemical mechanical polishing (CMP). In order to produce µm-sized transfer-printable coupons, the InP dies were micro structured by means of photolithography assisted patterning and wet (under-)etching (Fig. 1). The coupons can then be picked up with a stamp and transferred to the target wafer. Main innovation of this process is the resin which serves as low stress fixing layer for CMP as well as sacrificial layer for later release. The optimized CMP process with abrasive-free final polishing yielded InP platelets of the desired thickness below 10 μm with low thickness deviation < 1 µm and excellent surface roughness of S q ≈ 0.3 nm (Fig. 2a,b,d). This value even meets the requirements for adhesive-free bonding (S q ≤ 2 nm) and subsequent epitaxial growth (S q ≤ 0.5 nm). X-ray rocking curve mapping provides accurate spatial maps of lattice deformations in the material that may be a consequence of the mechanical processing. Rocking curve widths mappings of the 004 reflection of a (001) sample before and after thinning are homogeneous and below 25 arcsec in the majority of the sample area. Overall no signs of systematic crystal quality deterioration in the product platelets compared to bulk samples have been detected. In summary, the feasibility of μm-thin InP platelet fabrication was demonstrated. Final platelets meet the prerequisites of low and uniform thickness, high planarity, low roughness and little crystal quality deterioration. Furthermore, first InP platelets could successfully be patterned to 100–400 µm-sized coupons using optical lithography and wet etching (Fig. 2c). This opens a path to take the next steps towards hetero-integration on Si by means of µTP with high potential for adhesive-free bonding. References [1] J. C. Rode, et al. IEEE Trans. Electron Devices 2015, 62, 2779–2785. [2] Q. Li, K. M. Lau Prog. Cryst. Growth Charact. Mater. 2017, 63, 105–120. [3] X. Guo, et al. J. Semicond. 2019, 40, 101304. [4] J. Zhang, et al. APL Photonics 2019, 4, 110803. [5] IKZ-IHP Patent filed - DE 10 2022 100 661.1. [6] K. Giziewicz, et al. 51st Annual Meeting of the German Association of Crystal Growth, 2021, Berlin. Figure 1
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Nguyen, Ngoc-Anh, Olivier Schneegans, Jouhaiz Rouchou, Raphael Salot, Yann Lamy, Jean-Marc Boissel, Marjolaine Allain, Sylvain Poulet, and Sami Oukassi. "(G02 Best Presentation Award Winner) Elaboration and Characterization of CMOS Compatible, Pico-Joule Energy Consumption, Electrochemical Synaptic Transistors for Neuromorphic Computing." ECS Meeting Abstracts MA2022-01, no. 29 (July 7, 2022): 1293. http://dx.doi.org/10.1149/ma2022-01291293mtgabs.
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Non-Von Neumann computing application constituted by artificial synapses based on electrochemical random-access memory (ECRAM) has aroused tremendous attention owing to its capability to perform parallel operations, thus reducing the cost of time and energy spent [1-3]. Existing ECRAM synapses comprise two-terminal memristors and three-terminal synaptic transistors (SynT). While low cost, scalability, and high density are the highlights for memristors, their nonlinear, asymmetric state modulation, high ON current withdrawal, and sneak path in crossbar array integration prevent them from becoming the ideal synaptic elements for artificial neural networks (ANN) [4]. SynT configuration, on the other hand, offers an additional electrolyte-gated control from which ion doping content can be monitored via redox reactions, thus decoupling write-read actions and improving the linearity of programming states [5-6]. Nevertheless, existing SynTs suffer from different integration issues stemming from liquid-based ionic conductors and manually exfoliated channels. Moreover, several kinds of SynTs possess highly conductive channels in the range of µS to mS, significantly scaling up the energy spent for analog states reading. Despite having numerous communications on the performance of different ECRAM, a comprehensive electrochemical view of ion intercalation into the active material, the main root of conductance modulation, is clearly missing. In this work, we present the elaboration procedure of an all-solid-state synaptic transistor composed of nanoscale electrolyte and channel layers. The devices have been elaborated on 8’’ Silicon wafers using microfabrication processes compatible with conventional semiconductor technology and CMOS back end of line (BEoL) integration. (Figure 1a) We demonstrate the excellent synaptic plasticity properties of short-term potentiation (STP) and long-term potentiation (LTP) of our SynT. We performed tests to study the correlation between linearity, asymmetry, and the number of analog states. By averaging the amount of injected ions per write operation, we estimated the energy consumed for switching among adjacent states of this device is 22.5 pJ, yielding area-normalized energy of 4 fJ/µm2. In addition, operating in the range of nS, our SynTs meet the critical criteria of low energy consumption for both write and read operations. Endurance was highlighted by cycling in ambient conditions with 100 states of potentiation and depression for over 1000 cycles with only a slight variation of Gmax/Gmin ratio of 6.2 % (Figure 1b, c). Approximately 95 % accuracy in MNIST pattern recognition test on ANN in the crossbar array configuration has been obtained by simulation with SynTs as synaptic elements reassured SynT is a promising candidate for future neuromorphic computing hardware. To shed light on the properties of intercalation phenomena of Li ions into the TiO2 layer, a further electrochemical study on a cell comprising Ti/TiO2/LiPON/Li corresponding to the SynT gate stack was performed. This understanding will help to elucidate the correlation with conductance modulation characteristics for a synaptic transistor. Multiple tests were carried out, including cyclic voltammetry (CV) with different scan rates, rate capability with Galvanostatic cycling with potential limit (GCPL), and electrochemical impedance spectroscopy (EIS) on different states of charge. A circuit model was introduced to fit the frequency response of the cell, and it explained well the behavior of charging capability at different OCV (Figure 1d). References [1] P. Narayanan et al., “Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory,” IBM J. Res. Dev., vol. 61, no. 4/5, p. 11:1-11:11, Jul. 2017, doi: 10.1147/JRD.2017.2716579. [2] J. Tang et al., “ECRAM as Scalable Synaptic Cell for High-Speed, Low-Power Neuromorphic Computing,” in 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2018, p. 13.1.1-13.1.4. doi: 10.1109/IEDM.2018.8614551. [3] Y. Li et al., “In situ Parallel Training of Analog Neural Network Using Electrochemical Random-Access Memory,” Front. Neurosci., vol. 15, p. 636127, Apr. 2021, doi: 10.3389/fnins.2021.636127. [4] M. A. Zidan, H. A. H. Fahmy, M. M. Hussain, and K. N. Salama, “Memristor-based memory: The sneak paths problem and solutions,” Microelectron. J., vol. 44, no. 2, pp. 176–183, Feb. 2013, doi: 10.1016/j.mejo.2012.10.001. [5] Y. van de Burgt et al., “A non-volatile organic electrochemical device as a low-voltage artificial synapse for neuromorphic computing,” Nat. Mater., vol. 16, no. 4, pp. 414–418, Apr. 2017, doi: 10.1038/nmat4856. [6] E. J. Fuller et al., “Li-Ion Synaptic Transistor for Low Power Analog Computing,” Adv. Mater., vol. 29, no. 4, p. 1604310, Jan. 2017, doi: 10.1002/adma.201604310. Figure 1
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Pekarik, Jack, Vibhor Jain, Crystal Kenney, Judson Holt, Shweta Khokale, Sudesh Saroop, Jeffrey Johnson, et al. "Challenges for Sige Bicmos in Advanced-Node SOI." ECS Meeting Abstracts MA2022-02, no. 32 (October 9, 2022): 1196. http://dx.doi.org/10.1149/ma2022-02321196mtgabs.
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D-band (110-170GHz) spectrum is gaining attention for various applications, including 6G mm-Wave, sub-THz sensing, and radar. These systems require lattice spacing for antenna elements at sub-1mm and a very low loss signal path from antenna to integrated chip. A highly efficient front-end in a very small form factor will be required for these systems. This drives the requirement for a monolithically integrated high-gain, high-efficiency front-end that also leverages the benefits of a high-speed / high-density digital CMOS. Silicon germanium (SiGe) heterojunction bipolar transistors (HBT) integrated along with a high-density CMOS provide such an all-silicon monolithic solution. The US government is fostering the expansion of “unique and differentiated domestic manufacturing” with funding through DARPA’s Technologies for Mixed-mode Ultra Scaled Integrated Circuits (T-MUSIC) [1] program to enable disruptive RF mixed-mode technologies by developing high performance RF analog integrated with advanced digital CMOS. Through the T-MUSIC program, DARPA seeks to: 1) advance RF and mixed-mode devices to support ultra-wideband RF frontends from HF to 100 GHz; 2) integrate those devices with high density digital CMOS electronics at the wafer scale to enable embedded digital intelligence; 3) develop and explore ultra-high resolution broadband mixed-mode circuit building blocks for DoD-relevant applications; 4) explore innovative device topologies and materials to form THz devices in an advanced digital CMOS fabrication platform; and 5) establish a domestic ecosystem that facilitates enduring DoD access to differentiated capabilities for high performance RF mixed-mode SoCs. Under T-MUSIC, GlobalFoundries is demonstrating BiCMOS on 45nm PDSOI, which is the focus of this paper, and 22nm FDSOI CMOS with goals of increasing HBT performance of fT/fMAX from 350/500 GHz to 400/600 GHz and 600/700 GHz. HBTs with fT/fMAX of 380/550GHz GHz have been demonstrated building upon previously published results [2]. This paper will touch on some of the challenges that were encountered in achieving that result and discuss those anticipated in future work. Achieving these results required scaling transistor dimensions. Vertical scaling of the emitter, base and collector layers, with higher doping concentrations, reduces transit time but results in higher current densities and higher electric fields. Lateral scaling of the transistor structure reduces parasitic capacitance and resistance but concentrate the power dissipation in a smaller area. The thermal conductivity of silicon is 148W/m-K whereas that of silicon dioxide is ~1.4W/m-K. Even a thin layer of oxide will significantly increase the self-heating of the HBT. Therefore, we replace the SOI with coplanar epitaxy in regions where the HBTs are formed. The vertical scaling of the HBT requires limiting the thermal cycles that the HBT will experience during processing and suggests forming the HBT as late as possible in the CMOS process. However, the thermal cycles associate with the epitaxy and film depositions to form the HBT impact the CMOS transistors which suggests forming the HBT early in the process. We found a point in the process that offers the best compromise minimizing the impact to the doped-channel PDSOI CMOS while achieving the HBT performance goals. Work is just beginning on integration tradeoffs for FDSOI with metal gate and high-K dielectrics. Advanced-node CMOS processes can form components having smaller dimensions which offers advantages for lateral scaling but also presents challenges for forming the HBT. The contact height in 45nm is significantly less than the height of the HBT structure used in GF’s 9HP process. We changed the formation of the emitter and base so that the emitter and base contacts are almost coplanar in contrast to 9HP where the emitter was almost twice the height of the base. This problem is being further exasperated as we migrate to 22nm. The shrinking of BEOL wiring dimensions, along with the ability of the HBT to drive high currents, presents challenges in designing within limits imposed by electromigration. The use of wider wires is constrained by metal density rules. The use of stacked metal levels and redundant vias impact the parasitic capacitances and resistances of the interconnects. The paper and presentation will review these, and other challenges encountered in achieving BiCMOS integration of SiGe HBTs with fT/fMAX of 380/550GHz GHz [see figure] on a 45nm PDSOI CMOS and touch future work. This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA) and is Approved for Public Release, Distribution Unlimited. The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. [1] https://www.darpa.mil/attachments/T-MUSIC_Proposers%20Day_Presentations_Combined.pdf [2] J. Pekarik et al., 2021 IEEE BCICTS, 2021, pp. 1-4, Figure 1
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Kanyandekwe, Joël, Matthias Bauer, Tanguy Marion, Lazhar Saidi, Jean-Baptiste Pin, Jeremie Bisserier, Jérôme Richy, et al. "Very Low Temperature Tensile and Selective Si:P Epitaxy for Advanced CMOS Devices." ECS Meeting Abstracts MA2022-02, no. 32 (October 9, 2022): 1190. http://dx.doi.org/10.1149/ma2022-02321190mtgabs.
Abstract:
Nowadays, “more Moore” and “more than Moore” device architectures are becoming more and more complex. In CEA-Leti, we work on the “CoolCubeTM” 3D sequential integration which is based on the stacking of FDSOI devices [1]. We present solutions, at T<500°C, for the integration of SiP Raised Sources & Drains (RSD) in the upper devices without degrading the electrical performances of the bottom ones. We also target a lowering of the RSD resistance and an increase of the electron mobility in the channel of NMOS devices thanks to tensile strain [2]. Such a know-how will be useful to minimize the contact resistance and fabricate other types of devices such as FINFETs or h-GAA (e.g. nano-sheet devices) with Si (110) surfaces. Experiments were carried out in an Applied Materials epitaxy reactor featuring (i) liquid precursor delivery, together with H2, N2 or He carrier gas capability, enabling the use of Cl2; (ii) “High Precision Temperature Control (HPTC)”, allowing excellent LT control and enabling flexible rotation speeds; (iii) “precision flow distribution PFD-III”, enhancing uniformity performances. Selective Epitaxial Growth (SEG) is usually obtained with “co-flow” processes at rather high temperatures (>600°C). Chlorinated precursors (SiH2Cl2 (+ GeH4) + HCl, typically) are then sent simultaneously into the growth chamber. At LT (<500C°C), HCl cannot decompose, however. To overcome those limitations, we used a Cyclic Deposition Etch (CDE) strategy, with non-selective depositions followed by selective chemical vapor etches, to obtain SiP SEG. This strategy allowed us to obtain high quality films, as shown in Fig.1. The Omega-2Theta scans around the (004) X-Ray Diffraction order for tensile SiP (t-SiP) layers grown at T < 500°C with different Phosphorus concentrations were indeed typical of monocrystalline layers, with well-defined and intense peaks together with numerous thickness fringes. The substitutional P contents in those ~ 60 nm thick t-SiP layers were in the 1.02% - 5.42% range. The good layer uniformity in terms of thickness and P content, over a 300mm wafer radius, is shown in figure Fig.2. These layers grown at T <500°C were smooth, as shown in Fig.3, with a 0.21 nm Root Mean Square (RMS) roughness for a 60nm thick Si:P layer, i.e. a value close to the typical RMS roughness for t-SiP layers grown at high temperature with a chlorinated chemistry. The electrical resistivity in various t-SiP layers is plotted in Fig.4 as function of the substitutional phosphorus concentration and for various growth temperatures in the 450°C – 525°C range. Reducing the temperature by 75°C halved the electrical resistivity. We were able to achieve a resistivity as low as 0.21 mOhm.cm for a t-SiP layer with 5.8% of P grown at 450°C. We then evaluated, at first on tests structures without gates, our process selectivity. A top view Scanning Electron Microscopy image of a t-SiP layer grown non-selectively, with numerous amorphous SiP nuclei on SiO2, is shown in Fig 5.a. After some careful optimization, we succeeded in having fully selective processes versus SiO2, as shown in Fig 5.b. We then tested such optimized processes on low density FD-SOI devices with 28 nm design rules. A top-view SEM image of transistors after such a growth is shown in Fig.6. The growth selectivity was excellent, with nitride spacers and hard masks as well as isolations free of a-SiP nuclei for 31 nm of t-SiP with 4.5% of P deposited in the Sources/Drains. The surface was smooth, with a RMS roughness as low as 0.30nm on active areas, as shown in Fig.7. Thanks to High Resolution Reciprocal Space Maps (HR-RSM), we measured a Phosphorus concentration of 4.5% for that SiP layer grown on SOI. The very high quality of that epitaxy layer, with well-defined thickness fringes, is obvious in Fig.8. Cross-sectional Transmission Electron Microscopy (TEM) images such as the one shown in Fig. 9 enabled us to confirm, at the nanoscale, the excellent quality of such layers in RSDs. To sum up, we were able to develop a tensile Si:P process which was shown to be selective, at a temperature lower than 500°C, against SiO2 and SiN. Such t-SiP layers were successfully integrated in the Sources/Drains regions of FD-SOI 28nm devices. The very low material resistivity and the high phosphorus content should yield, notably because of tensile strain, performant NMOS devices in the near future. [1] C. Fenouillet-Beranger et al., IEEE TED 68, 3142-3148 (2021) [2] V. Chan et al., IEEE 2005 Custom Integrated Circuits Conference 2005, pp. 667-674 Figure 1
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Lamy, Yann, Florian Dupont, Guillaume Rodriguez, Messaoud Bedjaoui, Pierre Perreau, Marie Bousquet, Alexandre Reinhardt, and Sami Oukassi. "(Invited) Lithium-Based Components Integrated on Silicon: Disruptive, Promising and Credible Solutions for 5G & Beyond." ECS Meeting Abstracts MA2022-01, no. 29 (July 7, 2022): 1286. http://dx.doi.org/10.1149/ma2022-01291286mtgabs.
Abstract:
Following a trend similar to Moore’s low which prevailed for decades for active circuits, RF integrated passive components have reinvented themselves over the years in order to sustain continuous performance and size requirements. Their roadmap is still unrolling, thanks to a wide variety of new materials integration: high-k dielectrics for capacitors[1] ,[2] , magnetic material for inductors [3], aluminium nitride[4] (now scandium doped) for RF filters, or more recently phase-change materials for RF switches[5]. In the last few years, RF integrated passives built upon Lithium-based materials have attracted strong attention because of their state-of-the-art performances and their direct integration on silicon wafers. Lithium-based piezoelectric materials are used since 40 years by the SAW filters industry, which processes LiTaO3 (LTO) or LiNbO3 (LNO) bulk wafers in dedicated fabs. Recently, however, layered SAW devices exploiting thin films of these materials directly on a silicon wafer have exhibited dramatically improved performances. These devices leverage the latest developments in single crystal Li-based layer transfer, or in deposition techniques (PVD, ALD[6], Pulse-Laser-Deposition, ...) of epitaxial, textured, or amorphous Li-based thin films, all of which achievable in industrial grade semiconductor equipments. In this presentation, we will give an overview of the potential of integrating lithium-based materials on silicon through different examples of promising RF components for 5G. First, we will show how the availability of Li-based Piezoelectric-on-Insulator (POI) wafers[7] is a game changer for 5G filtering. We will present very promising perspectives regarding the development of LNO-based Bulk Acoustics Wave filters (BAW)[8] ,[9],[10] which aim at extending the application space of POI SAW filters towards the upper 5G bands and even Wi-Fi 6E [5-7 GHz] . Different examples of Li-based materials integrations will be given3,4,5,[11] . Secondly, we will discuss the potential of a new type of Li-based hybrid micro supercapacitors integrated on silicon. LiPON thin films offer a unique combination of dual properties, being both a dielectric and an electrolyte[12]. Their integration on silicon is not only bringing potentially ultra-high capacitance densities, but also local on-chip energy storage for 5G components, opening a new paradigm in use of the device in a system[13] ,[14] . After that, we will open the horizon of the potential of Li-based materials integration towards other types of RF devices, like RF switchs, and elaborate on their synergy with Li-transistors for neuromorphic applications[15] and with more conventional lithium microbatteries integrated on silicon[16]. Finally, the integration of Lithium in a silicon industrial environment and the remaining challenges will be discussed. The similarities and discrepancies of the different Li-based processes will be analyzed as well as the compatibility with a silicon CMOS and/or microsystem fab, and the potential for wafers size scaling. Risks like sensitivity to humidity and potential Li contamination will be outlined with some relevant preventive protocols in order to make the Lithium integration on silicon a real and credible disruptive solution regarding 5G challenges. [1] F. Roozeboom, et al. ECS 2007 [2] M. Bousquet et al., ECAPD 2014 [3] J. P. Michel et al., IEEE Trans. Magnetics 55, n°7, pp. 1-7 (2019) » [4] A. Reinhardt et al., IFCS 2011 [5] A. Leon et al., IEEE Trans. Microwave Theory and Techniques, vol. 68, n°1, pp. 60-73 (2020)” [6] M. Bedjaoui et al. ECS Meeting (October 10-14, 2021). [7] E. Butaud et al. IEDM 2020 [8] M. Bousquet et al., Proc. IEEE International Ultrasonics Symposium 2019. [9] M. Bousquet et al., Proc. IEEE International Ultrasonics Symposium 2020. [10] A. Reinhardt et al., Proc. Joint Conference of EFTF & IFCS 2021 [11] L. Sauze et al, Thin solid films, 726, may 2021 [12] L. Le Van-Jodin et al, Solid State ionic, 2013 [13] V. Sallaz et al, Journal of Power Source, 2020 [14] V. Sallaz et al. submitted to ECS 2021 [15] N-A Ngyuen et al,” submitted to ECS 2021 [16] S. Oukassi et al, IEDM 2019
9
Xu, Xiaopeng, Xi-Wei Lin, Youxin Gao, and Soren Smidstrup. "(Invited) 3DIC Hierarchical Thermal and Mechanical Analysis with Continuum and Atomistic Modeling." ECS Meeting Abstracts MA2022-02, no. 17 (October 9, 2022): 845. http://dx.doi.org/10.1149/ma2022-0217845mtgabs.
Abstract:
3D IC heterogeneous integration technologies employ numerous materials with widely varying thermal and mechanical properties and distinct deformation behaviors. During 3D integration processes, the constituent materials undergo various thermal cycles. Because of thermal expansion coefficient mismatch, the materials are essentially subject to mechanical loadings for these thermal ramps. The resulting chip, package, and board interactions lead to 3D stack warpage, silicon mobility variation, and material damage. Under operation conditions, heat can be trapped between insulation layers and leads to nonuniform temperature rises. Elevated local temperatures can change carrier mobility, relax mechanical stress, and affect material deformation behaviors. Consequently, these local temperature rises can affect device performance, structure integrity, and material reliability. To accurately assess these thermal and mechanical effects, extract design rules, optimize designs, and develop performance and reliability mitigation methodologies, it is of paramount importance to characterize material deformation and interface de-bonding behaviors, map chip temperature distributions, and analyze stress hotspot evolutions during integration process and under operation conditions while developing 3D IC integration technologies [1]. In this study, a multiscale hierarchical modeling approach is assembled to analyze thermal, mechanical, and material deformation and interface de-bonding behaviors under 3D integration process and operation conditions for a newly designed 3D IC package with a 2nm SOC die copper-bonded on an RDL interposer [2]. The 3DIC structures are constructed directly using GDSII design and ITF technology data [3]. Each structural layer is divided into small smear tiles. Each tile is represented by anisotropic thermal and mechanical properties that depend on local feature patterns in the tile. Under given operation conditions, power grids are generated and used as heat sources for thermal analysis. For multiscale hierarchical modeling, the global thermal and mechanical analyses that call for coarse grain resolution are first performed. The subsequent local analyses that provide fine grain resolution in areas of interests utilize boundary conditions that are extracted from the global analyses. The material deformation and interface de-bonding behaviors are simulated using molecular dynamics [4]. Several 3D integration design options are explored. The 3D configuration effects on chip temperature distributions during operations, stack warpages, silicon mobility variations, and chip package interaction induced stress hotspots are examined. The elevated temperature impacts on material deformation and de-bonding process are also investigated. References: “Heterogenous Integration Roadmap”, 2022, https://eps.ieee.org/hir “Heterogeneous Integration Enabled by the State-of-the-Art 3DIC and CMOS Technologies: Design, Cost, and Modeling”, X. Lin et al., International Electron Devices Meeting, IEDM Technical Dig., 2021 “Sentaurus Interconnect User Guide”, 2022, https://www.synopsys.com/silicon/tcad “Quantum ATK: An integrated platform of electronic and atomic-scale modelling tools”, S. Smidstrup et al., J. Phys.: Condens. Matter 32, 015901, 2020
10
Quay, Ruediger, Arnulf Leuther, Sebastien Chartier, Laurenz John, and Axel Tessmann. "(Invited) III-V Integration on Silicon for Resource-Efficient Sensor-Technology." ECS Meeting Abstracts MA2023-01, no. 33 (August 28, 2023): 1853. http://dx.doi.org/10.1149/ma2023-01331853mtgabs.
Abstract:
This work deals with the wafer-level integration of advanced group III-V devices and integrated circuits on silicon substrate for RF-sensor integration, such as radar functions a very high frequencies beyond 300 GHz [1]. The aim is to achieve both performance improvements on device level, co-integration with digital functions, and advanced integration to achieve a greener usage of material critical to the environment. Submillimeter-Wave frequency bands beyond 300 GHz allow for broadband transmit and receive windows, serviceable to both communications and radar-based applications—increasing data rates and imaging resolutions, respectively. On the other hand, CMOS co-integration is called for by the data acquisition- and other mixed-mode- and fast digital functions. As examples of the integration schemes Terahertz Monolithic Integrated Circuit amplifiers (TMICs) are implemented in an advanced transferred-substrate InGaAs-channel HEMT technology with 20-nm gate length on silicon. The inverted III-V HEMT heterostructure is grown by molecular beam epitaxy (MBE) on 100-mm semi-isolating GaAs wafers and transferred to silicon substrates by using a SiO2-based wafer bond process with subsequent wafer thinning and removal of the GaAs substrate. Thus, only a 100-nm-thick III-V heterostructure layer is remaining on the Si substrate. This advanced transferred-substrate technology also offers the implementation of HEMT devices with backside gate [2,3] to achieve better sub-threshold slope, or field plates to increase both channel confinement and higher breakdown voltages. The 20-nm InGaAs-OI HEMT technology features typical values for the OFF-state breakdown voltage of 5 V and and maximum drain-current density of 1200 mA/mm, respectively. A maximum transconductance of 2400 mS/mm is achieved. The expected cutoff frequency values fT and fmax are above 500 GHz and 1 THz, respectively [4]. A fully passivated back-end-of-line (BEOL) process is used, including three metal layers (MET1–MET3). A NiCr 50 Ohm sq thin-film-resistor layer, as well as an SiN layer for the implementation of MIM capacitors between MET2 andMET3. S-parameter characteristics of a six-stage and nine-stage TMIC amplifiers in the frequency band from 620 to 730 GHz are given as examples. During the on-wafer characterization, the HEMT devices in cascode configuration have been biased at VD= 2 V (1 V drain–source voltage per device) and a current of 350 mA/mm. The measured small-signal gain of the six-stage cascode TMIC amplifier is in the range of 22–25 dB over the frequency range from 670 to above 700 GHz. This corresponds to 4 dB of gain per cascode stage around the 670-GHz frequency range. A nine-stage TMIC amplifier, on the other hand, achieves at least 30 dB of measured gain from 660 to about 700 GHz. This again corresponds to a gain per stage below 4 dB. Such results prove both the advancements in integration as well as state-of-the-art circuit performance co-integrated on silicon. References: [1] B. Gashi et al., "Broadband 400 GHz On-Chip Antenna With a Metastructured Ground Plane and Dielectric Resonator," in IEEE Transactions on Antennas and Propagation, vol. 70, no. 10, pp. 9025-9038, Oct. 2022, doi: 10.1109/TAP.2022.3177527. [2] A. Tessmann et al., "20-nm In0.8Ga0.2As MOSHEMT MMIC Technology on Silicon," in IEEE Journal of Solid-State Circuits, vol. 54, no. 9, pp. 2411-2418, Sept. 2019, doi: 10.1109/JSSC.2019.2915161. [3] A. Leuther et al., "InGaAs HEMT MMIC Technology on Silicon Substrate with Backside Field-Plate," 2020 50th European Microwave Conference (EuMC), 2021, pp. 187-190, doi: 10.23919/EuMC48046.2021.9337957. [4] L. John, et al., "High-Gain 670-GHz Amplifier Circuits in InGaAs-on-Insulator HEMT Technology," in IEEE Microwave and Wireless Components Letters, vol. 32, no. 6, pp. 728-731, June 2022, doi: 10.1109/LMWC.2022.3160093.
Dissertations / Theses on the topic "Dispositifs CMOS et integration":
1
Dubreuil, Théophile. "Architecture 3D 1T1R innovante à base de RRAMs pour le calcul hyperdimensionnel." Electronic Thesis or Diss., Université Grenoble Alpes, 2023. http://www.theses.fr/2023GRALT085.
Abstract:
Dans les prochaines années, en raison des besoins toujours plus grands des applications d'apprentissage machine dans le domaine de l'intelligence artificielle, une augmentation soutenue de la capacité de calcul est nécessaire pour faire face à un véritable "déluge de données". Pour relever ce défi, les architectures de calcul immergé en mémoire (IMC) à haute performance nécessitent le développement de nouvelles technologies adaptées à la fois au calcul local et au stockage. Dans ce contexte, ce travail de thèse présente de nouvelles matrices mémoire 3D 1T1R qui sont dérivées des transistors à nanofeuillés empilés. Cette nouvelle technologie est associée au calcul hyperdimensionnel (HDC), un paradigme inspiré du cerveau qui est à la fois résistant à l’erreur et facilement parallélisable. Tout d’abord, nous montrons que l’IMC peut largement bénéficier des architectures 3D basées sur les mémoires non volatiles (NVM) pour augmenter la densité et les performances de calcul. Toutefois, les difficultés de fabrication et les résistances et capacités parasites inhérentes aux structures 3D limitent parfois considérablement les performances de ces architectures pour l’IMC. Grâce à la technologie 3D 1T1R proposée dans ce travail, qui combine des nanofeuillés empilés comportant des grilles indépendantes avec une RRAM insérée dans le drain des transistors, nous montrons qu’il est possible de s’affranchir, en partie, de ces problèmes. Nous présentons, fabriquons et caractérisons électriquement plusieurs modules technologiques essentiels à la fabrication de structures 1T1R 3D. Nous démontrons également la fonctionnalité de cellules mémoires 1T1R pour lesquelles le point RRAM est intégré dans le drain de différents types de sélecteurs avec une électrode inférieure faite de Si dopé. Enfin, nous proposons d’implémenter l’algorithme HDC en mémoire pour tirer profit de notre structure 3D 1T1R. Différentes implémentations sont explorées et leurs performances sont évaluées à l’aide de simulations SPICE. Nous montrons également à l'aide de simulations logicielles que la classification de langages et la reconnaissance de gestes, basées sur le calcul hyperdimensionnel, peuvent être implémentées à l’aide de notre structure 3D 1T1R de façon réalisteIn the years to come, due to the insatiable need for data-intensive machine learning applications, a drastic expansion of computing power is required to confront a veritable “data deluge”. To meet this challenge, high-performance In-Memory-Computing (IMC) architectures require the development of novel storage devices that are also suited for local computations. In this context, this thesis work presents a novel 3D 1T1R memory array derived from vertically stacked-nanosheet technology, which is used for Hyperdimensional Computing (HDC), an error-resilient and highly parallel brain-inspired computing paradigm. Firstly, the IMC paradigm can greatly benefit from novel 3D non-volatile memory (NVM) architectures which increase the density and the computing performances. However, the fabrication challenges and parasitics can greatly limit the potential benefits of these architectures. With the 3D 1T1R technology, made by coupling new disruptive gate-independent stacked-nanosheets with drain-based RRAM cells, we show that some of these issues can be overcome, thus leading to high-density 3D NVM arrays. We demonstrate various technological modules necessary for the fabrication of 3D 1T1R structures. Devices are fabricated and electrically characterized for both storage and computing applications. In particular, functional MEOL drain-based RRAM cells are demonstrated with a doped-Si bottom electrode for various types of selector technologies. Finally, we propose a full-IMC architecture of HDC to take advantage of the 3D 1T1R structure. Different hardware implementations are proposed and compared with SPICE simulations. We also show with software-based simulations that language and gesture recognition can be realistically performed with our 3D 1T1R implementation
2
Charbonneau, Micaël. "Etude et développement de points mémoires résistifs polymères pour les architectures Cross-Bar." Thesis, Grenoble, 2012. http://www.theses.fr/2012GRENT116/document.
Abstract:
Ces dix dernières années, les technologies de stockage non-volatile Flash ont joué un rôle majeur dans le développement des appareils électroniques mobiles et multimedia (MP3, Smartphone, clés USB, ordinateurs ultraportables…). Afin d’améliorer davantage les performances, augmenter les capacités et diminuer les coûts de fabrication, de nouvelles solutions technologiques sont aujourd’hui étudiées pour pouvoir compléter ou remplacer la technologie Flash. Citées par l’ITRS, les mémoires résistives polymères présentent des caractéristiques très prometteuses : procédés de fabrication à faible coût et possibilité d’intégration haute densité au dessus des niveaux d’interconnexions CMOS ou sur substrat souple. Ce travail de thèse a été consacré au développement et à l'étude des mémoires résistifs organiques à base de polymère de poly-méthyl-méthacrylate (PMMA) et de molécules de fullerènes (C60). Trois axes de recherche ont été menés en parallèle: le développement et la caractérisation physico-chimique de matériaux composites, l’intégration du matériau organique dans des structures de test spécifiques et la caractérisation détaillée du fonctionnement électrique des dispositifs et des performances mémoiresOver the past decade, non-volatile Flash storage technologies have played a major role in the development of mobile electronics and multimedia (MP3, Smartphone, USB, ultraportable computers ...). To further enhance performances, increase the capacity and reduce manufacturing costs, new technological solutions are now studied to provide complementary solutions or replace Flash technology. Cited by ITRS, the polymer resistive memories present very promising characteristics: low cost processing and ability for integration at high densities above CMOS interconnections or on flexible substrate. This PhD specifically focused on the development and study of composite material made of Poly-Methyl-Methacrylate (PMMA) polymer resist doped with C60 fullerene molecules. Studies were carried out on three different axes in parallel: Composite materials development & characterization, integration of the organic material in specific test structure and advanced devices and finally detailed electrical characterization of memory cells and performances analysis
3
Cassé, Mikaël. "Caractérisation Électrique et Modélisation du Transport dans les Dispositifs CMOS Avancés." Habilitation à diriger des recherches, Université de Grenoble, 2014. http://tel.archives-ouvertes.fr/tel-00974652.
Abstract:
La micro-électronique est considérée comme une technologie révolutionnaire compte-tenu de la dynamique qu'elle a insufflée à l'économie mondiale depuis l'invention du circuit intégré dans les années 50. Jusqu'à récemment, les défis technologiques relevés ont consisté à conserver une ligne directrice de développement fondée sur une simple réduction des dimensions du transistor MOS, faisant basculer la micro-électronique dans l'ère de la nanoélectronique. Industriels et chercheurs tentent aujourd'hui de repousser les limites physiques imposées par la réduction d'échelle en agissant sur différents leviers technologiques, afin d'améliorer les performances des dispositifs sans avoir à en réduire les dimensions. Les travaux présentés résument mon activité de recherche menée au CEA-Léti depuis 2001, dans le contexte général du développement des technologies CMOS pour les noeuds avancés (i.e. le 65nm pour le début des années 2000, le 14nm et en deçà à l'heure actuelle), avec un focus plus particuliers sur l'étude du transport dans le canal des transistors MOS. Trois voies principales ont été explorées, et seront analysées et commentées : * les nouveaux matériaux de grille, avec l'introduction des oxydes à forte permittivité (high-κ) et des grilles métalliques. * l'ingénierie de la mobilité, avec entre autres l'utilisation de matériaux à plus forte mobilité comme les alliages SiGe, ou encore l'exploitation des contraintes. * les nouvelles architectures de transistor, avec la réalisation de films minces et de transistors multi-grilles ou à grille enrobante.
4
Lee, Sang Bruno. "Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS." Thèse, Université de Sherbrooke, 2016. http://hdl.handle.net/11143/8955.
Abstract:
Résumé : Le transistor monoélectronique (SET) est un dispositif nanoélectronique très attractif à cause de son ultra-basse consommation d’énergie et sa forte densité d’intégration, mais il n’a pas les capacités suffisantes pour pouvoir remplacer complètement la technologie CMOS. Cependant, la combinaison de la technologie SET avec celle du CMOS est une voie intéressante puisqu’elle permet de profiter des forces de chacune, afin d’obtenir des circuits avec des fonctionnalités additionnelles et uniques.
Cette thèse porte sur l’intégration 3D monolithique de nanodispositifs dans le back-end-of-line (BEOL) d’une puce CMOS. Cette approche permet d’obtenir des circuits hybrides et de donner une valeur ajoutée aux puces CMOS actuelles sans altérer le procédé de fabrication du niveau des transistors MOS. L’étude se base sur le procédé nanodamascène classique développé à l’UdeS qui a permis la fabrication de dispositifs nanoélectroniques sur un substrat de SiO2.
Ce document présente les travaux réalisés sur l’optimisation du procédé de fabrication nanodamascène, afin de le rendre compatible avec le BEOL de circuits CMOS. Des procédés de gravure plasma adaptés à la fabrication de nanostructures métalliques et diélectriques sont ainsi développés. Le nouveau procédé nanodamascène inverse a permis de fabriquer des jonctions MIM et des SET métalliques sur une couche de SiO2. Les caractérisations électriques de MIM et de SET formés avec des jonctions TiN/Al2O3 ont permis de démontrer la présence de pièges dans les jonctions et la fonctionnalité d’un SET à basse température (1,5 K). Le transfert de ce procédé sur CMOS et le procédé d’interconnexions verticales sont aussi développés par la suite. Finalement, un circuit 3D composé d’un nanofil de titane connecté verticalement à un transistor MOS est réalisé et caractérisé avec succès.
Les résultats obtenus lors de cette thèse permettent de valider la possibilité de co-intégrer verticalement des dispositifs nanoélectroniques avec une technologie CMOS, en utilisant un procédé de fabrication compatible.Abstract : The single electron transistor (SET) is a nanoelectronic device very attractive due to its ultra-low power consumption and its high integration density, but he is not capable of completely replace CMOS technology. Nevertheless, the hybridization of these two technologies is an interesting approach since it combines the advantages of both technologies, in order to obtain circuits with new and unique functionalities. This thesis deals with the 3D monolithic integration of nanodevices in the back-end-ofline (BEOL) of a CMOS chip. This approach gives the opportunity to build hybrid circuits and to add value to CMOS chips without fundamentally changing the process fabrication of MOS transistors. This study is based on the nanodamascene process developed at UdeS, which is used to fabricate nanoelectronic devices on a SiO2 layer. This document presents the work done on the nanodamascene process optimization, in order to make it compatible with the BEOL of CMOS circuits. The development of plasma etching processes has been required to fabricate metallic and dielectric nanostructures useful to the fabrication of nanodevices. MIM junctions and metallic SET have been fabricated with the new reverse nanodamascene process on a SiO2 substrate. Electrical characterizations of MIM devices and SET formed with TiN/Al2O3 junctions have shown trap sites in the dielectric and a functional SET at low temperature (1.5 K). The transfer process on CMOS substrate and the vertical interconnection process have also been developed. Finally, a 3D circuit consisting of a titanium nanowire connected to a MOS transistor is fabricated and is functional. The results obtained during this thesis prove that the co-integration of nanoelectronic devices in the BEOL of a CMOS chip is possible, using a compatible process.
5
Lim, Tek Fouy. "Dispositifs de protection contre les décharges électrostatiques pour les applications radio fréquences et millimétriques." Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENT033/document.
Abstract:
Ces travaux s'inscrivent dans un contexte où les contraintes vis-à-vis des décharges électrostatiques sont de plus en plus fortes, les circuits de protection sont un problème récurrent pour les circuits fonctionnant à hautes fréquences. La capacité parasite des composants de protection limite fortement la transmission du signal et peut perturber fortement le fonctionnement normal d'un circuit. Les travaux présentés dans ce mémoire font suite à une volonté de fournir aux concepteurs de circuits fonctionnant aux fréquences millimétriques un circuit de protection robuste présentant de faibles pertes en transmission, avec des dimensions très petites et fonctionnant sur une très large bande de fréquences, allant du courant continu à 100 GHz. Pour cela, une étude approfondie des lignes de transmission et des composants de protection a été réalisée à l'aide de simulations électromagnétiques et de circuits. Placés et fragmentées le long de ces lignes de transmission, les composants de protection ont été optimisés afin de perturber le moins possible la transmission du signal, tout en gardant une forte robustesse face aux décharges électrostatiques. Cette stratégie de protection a été réalisée et validée en technologies CMOS avancées par des mesures fréquentielles, électriques et de courant de fuiteAdvanced CMOS technologies provide an easier way to realize radio-frequency integrated circuits (RFICs). However, the lithography dimension shrink make electrostatic discharges (ESD) issues become more significant. Specific ESD protection devices are embedded in RFICs to avoid any damage. Unfortunately, ESD protections parasitic capacitance limits the operating bandwidth of RFICs. ESD protection size dimensions are also an issue for the protection of RFICs, in order to avoid a significant increase in production costs. This work focuses on a broadband ESD solution (DC-100 GHz) able to be implemented in an I/O pad to protect RFICs in advanced CMOS technologies. Thanks to the signal transmission properties of coplanar / microstrip lines, a broadband ESD solution is achieved by implementing ESD components under a transmission line. The silicon proved structure is broadband; it can be used in any RF circuits and fulfill ESD target. The physical dimensions also enable easy on-chip integration
6
Le, Goulven Katell. "Dispositifs institutionnels et integration des marches la commercialisation du porc au vietnam." Montpellier, ENSA, 2000. http://www.theses.fr/2000ENSA0012.
Abstract:
L'objet de la these est d'analyser le fonctionnement d'un marche agricole -celui du porc- dans un pays en transition -le vietnam. Dans le cadre de la nouvelle economie institutionnelle et en partant de l'hypothese qu'il n'existe pas une forme universelle de marche, nous montrons que la diversite des marches est expliquee par la nature des arrangements institutionnels qui structurent les echanges et par les regles sociales qui supportent la mise en application de ces arrangements. Nous developpons d'abord une grille de lecture des niveaux institutionnels dans lesquels s'inscrivent les transactions. Ensuite nous mettons en evidence l'existence de deux marches dont les logiques de formation et de transmission des prix sont differentes. Finalement nous demontrons que ces differences resultent de structures institutionnelles specifiques. Les travaux conduisent a des resultats parfois paradoxaux. Au nord vietnam, le plus longtemps soumis a la collectivisation, les transactions marchandes sont structurees par des institutions informelles privees. Cette organisation entrainent des phenomenes collusifs et de concentration qui affectent la formation concurrentielle des prix et les incitations a la production. Au sud du pays, les institutions publiques legales ont un role central dans la coordination economique. Les mecanismes de fixation des prix y sont plus concurrentiels et la production mieux stimulee. Nous montrons que ces differences, heritees de l'histoire, correspondent a des ancrages des marches dans des valeurs morales particulieres. L'apport theorique de la these est de proposer le couplage d'outils dont l'un est exhaustif mais descriptif - la modelisation des prix - et l'autre est analytique mais monographique - l'analyse de donnees d'enquetes - dans un meme cadre d'analyse. L'apport empirique consiste en la production de donnees de terrain detaillees, collectees a tous les niveaux de la filiere porc au cours de trois sejours sur le terrain dans neuf provinces du pays.
7
Maggioni, Mezzomo Cécilia. "Caractérisation et modélisation des fluctuations aléatoires des paramètres électriques des dispositifs en technologies CMOS avancées." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00987632.
Abstract:
Ce travail porte sur la caractérisation et la modélisation des fluctuations aléatoires des paramètres électriques des transistors MOS avancées. La structure de test utilisée est validée expérimentalement au moyen de la méthode de mesure de Kelvin. Pour comprendre le comportement des fluctuations, un modèle est d'abord proposé pour le régime linéaire. Il permet de modéliser les fluctuations de la tension de seuil des transistors avec implants de poche pour toutes les longueurs de transistor et aussi pour toute la gamme de tension de grille. Ensuite, l'appariement du courant de drain est caractérisé et modélisé en fonction de la tension de drain. Pour modéliser les caractéristiques réelles de transistors sans implants de poche, il est nécessaire de considérer la corrélation des fluctuations de la tension de seuil et celles de la mobilité. De plus, des caractérisations sur des transistors avec implants de poche montrent un nouveau comportement de l'appariement du courant de drain. Des caractérisations ont aussi été menées pour analyser l'impact des fluctuations de la rugosité de grille.
8
Maggioni, Mezzomo Cecilia. "Caractérisation et modélisation des fluctuations aléatoires des paramètres électriques des dispositifs en technologies CMOS avancées." Thesis, Grenoble, 2011. http://www.theses.fr/2011GRENT044/document.
Abstract:
Ce travail porte sur la caractérisation et la modélisation des fluctuations aléatoires des paramètres électriques des transistors MOS avancées. La structure de test utilisée est validée expérimentalement au moyen de la méthode de mesure de Kelvin. Pour comprendre le comportement des fluctuations, un modèle est d’abord proposé pour le régime linéaire. Il permet de modéliser les fluctuations de la tension de seuil des transistors avec implants de poche pour toutes les longueurs de transistor et aussi pour toute la gamme de tension de grille. Ensuite, l’appariement du courant de drain est caractérisé et modélisé en fonction de la tension de drain. Pour modéliser les caractéristiques réelles de transistors sans implants de poche, il est nécessaire de considérer la corrélation des fluctuations de la tension de seuil et celles de la mobilité. De plus, des caractérisations sur des transistors avec implants de poche montrent un nouveau comportement de l’appariement du courant de drain. Des caractérisations ont aussi été menées pour analyser l’impact des fluctuations de la rugosité de grilleThis research characterizes and models the mismatch of electrical parameters in advanced MOS transistors. All characterizations are made through a test structure, which is experimentally validated using a structure based on Kelvin method. A model, valid in the linear region, is proposed. It is used for modeling the threshold voltage fluctuations of the transistors with pocket-implants, for any transistor length and gate voltage. It gives a deep understanding of the mismatch, especially for devices with non-uniform channel. Another study analyzes the mismatch of the drain current by characterizing and modeling in terms of the drain voltage. A second model is then proposed for transistors without pocket-implants. In order to apply this model, the correlation of threshold voltage fluctuations and mobility fluctuations must be considered. Characterizations are also performed on transistors with pocket-implants, showing a new drain current mismatch behavior for long transistors. Finally, characterizations are made to analyze the impact of gate roughness fluctuations on mismatch
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Hossri, Nabil al. "Etude du phénomène métastable dans les dispositifs bistables de technologie CMOS modélisation, caractérisation et simulation." Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37598345s.
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Hossri, Nabil al. "Etude du phénomène métastable dans les dispositifs bistables de technologie CMOS : modélisation, caractérisation et simulation." Bordeaux 1, 1986. http://www.theses.fr/1986BOR10868.
Abstract:
Elaboration de modeles reels des elements logiques cmos a partir desquels on parvient a une formulation complete du fonctionnement des bistables elementaires en regime metastable. Expression theorique de la courbe d'incertitude en fonction des parametres technologiques et extrinseques du dispositif etudie. On en deduit les regles d'optimisation des performances de ces circuits vis a vis des declenchements marginaux
Books on the topic "Dispositifs CMOS et integration":
1
Solans, Henri. Faire société sans faire souffrir?: Les dispositifs vecteurs de cohésion sociale et leurs victimes. Paris: Harmattan, 2005.
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Haskard, Malcolm R., and Ian C. May. Analog Vlsi Design: Nmos and Cmos (Silicon Systems Engineering Series). Prentice Hall, 1988.
3
Dhiman, Rohit, and Rajeevan Chandel. VLSI and Post-CMOS Electronics: Devices, Circuits and Interconnects. Institution of Engineering & Technology, 2019.
4
Dhiman, Rohit, and Rajeevan Chandel. VLSI and Post-CMOS Electronics: Design, Modelling and Simulation. Institution of Engineering & Technology, 2019.
5
Dhiman, Rohit, and Rajeevan Chandel. VLSI and Post-CMOS Electronics: Devices, Circuits and Interconnects, Volume 2. Institution of Engineering & Technology, 2019.
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Dhiman, Rohit, and Rajeevan Chandel. VLSI and Post-CMOS Electronics: Design, Modelling and Simulation, Volume 1. Institution of Engineering & Technology, 2019.
Book chapters on the topic "Dispositifs CMOS et integration":
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VUILLAUME, Dominique. "Électronique moléculaire : transport d’électrons, de spins et de chaleur." In Au-delà du CMOS, 259–300. ISTE Group, 2024. http://dx.doi.org/10.51926/iste.9127.ch7.
Abstract:
Après une brève description de la technologie des jonctions moléculaires, suivie d'une introduction à la physique de base du transport des électrons, plusieurs sections passent en revue des résultats sélectionnés sur le transport dépendant du spin, la plasmonique, les interférences quantiques, le transport thermique et le bruit électronique dans les dispositifs de l’électronique moléculaire.
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VITALE, Steven A. "Valléetronique dans les matériaux 2D." In Au-delà du CMOS, 215–57. ISTE Group, 2024. http://dx.doi.org/10.51926/iste.9127.ch6.
Abstract:
Les matériaux 2D ouvrent la possibilité d'aborder et de manipuler le pseudospin de vallée au sein du matériau, ainsi permettant la réalisation de dispositifs de valléetronique. Ce chapitre présente le contexte nécessaire pour comprendre ces phénomènes au niveau théorique et expérimental, et les perspectives et les défis dans le domaine de l'informatique.
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CAO, Wei, and Kaustav BANERJEE. "Transistors à effet de champ à capacité négative." In Au-delà du CMOS, 83–111. ISTE Group, 2024. http://dx.doi.org/10.51926/iste.9127.ch3.
Abstract:
Le FET à capacité négative est prometteur grâce à la diminution de sa tension d'alimentation. Cependant, l'authenticité de la capacité négative dans différentes conditions d'essai reste controversée. Après l'introduction de ses principes fondamentaux, ce chapitre se concentre sur les défis et opportunités du point de vue de la physique des dispositifs, et présente un aperçu des progrès expérimentaux.
Conference papers on the topic "Dispositifs CMOS et integration":
1
Pu, R., R. Jurrat, E. M. Hayes, C. W. Wilmsen, K. D. Choquette, and K. M. Geib. "Optical processing arrays based on VCSELs bonded directly to GaAs smart pixels." In Spatial Light Modulators. Washington, D.C.: Optica Publishing Group, 1997. http://dx.doi.org/10.1364/slmo.1997.smb.4.
Abstract:
VCSELs are near ideal light sources for free space, parallel optical interconnects since they are highly efficient, can be fabricated into 2D arrays and emit a low divergence column of light normal to the surface. However, integrating the VCSELs into smart pixels introduces fabrication problems since they can not be grown on foundry fabricated Si CMOS or GaAs MESFET circuits. Thus, the fabrication of complex pixels is difficult. Three methods of electrically connecting VCSELs to electronic chips have been discussed by Bryan et al. [1]; wire bonding, bridge bonding, and flip chip bonding to the whole VCSEL chip to a separate area of the electronic chip. Unfortunately none of these techniques are suitable for large-high speed arrays since they involve excessive numbers of long electrical lead wires or thin film traces which occupy a large area and add significantly to the capacitance and inductance of the circuit. Recently Goosen et al. [2] have developed a co-planar flip-chip bonding process for the attachment of SEED devices to CMOS chips. Their process has been shown to be both scalable and reliable [3]. This technique significantly increases the combined array size and decreases the interconnect capacitance and inductance allowing for much faster operation. The present paper reports the development of a co-planar bonding technique for VCSELs onto prefabricated pixel chips. This paper presents the details of this flip-chip bump-bonding integration.