Dissertations / Theses on the topic 'Discrete cosine transform'
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Yu, Sungwook. "VLSI implementation of multidimensional discrete Fourier transform and discrete cosine transform /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
Full textHu, Ta-Hsiang. "Discrete cosine transform implementation in VHDL." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA245791.
Full textThesis Advisor(s): Lee, Chin-Hwa ; Yang, Chyan. "December 1990." Description based on title screen as viewed on March 29, 2010. DTIC Identifier(s): Fast Fourier Transform, High Level Languages, CHIPS (Electronics), Computerized Simulation, Signal Processing, Theses, Algorithms, Floating Point Operation, VHDL (Vhsic Hardware Description Language). Author(s) subject terms: FFT System, DCT System Implementation. Includes bibliographical references (p. 152). Also available in print.
Jin, Chengzhou. "Discrete Cosine Transform for Pre-coded EGPRS." Thesis, KTH, Signalbehandling, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-98761.
Full textAbedi, Safdar Ali Syed. "Exploring Discrete Cosine Transform for Multi-resolution Analysis." Digital Archive @ GSU, 2005. http://digitalarchive.gsu.edu/cs_theses/12.
Full textHaque, S. M. Rafizul. "Singular Value Decomposition and Discrete Cosine Transform based Image Watermarking." Thesis, Blekinge Tekniska Högskola, Avdelningen för för interaktion och systemdesign, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5269.
Full textPhone number: +88041730212
Chua, Doi-eng, and 蔡岱榮. "Some variations on Discrete-Cosine-Transform-based lossy image compression." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2000. http://hub.hku.hk/bib/B31222523.
Full textDeng, An-Te. "VHDL behavioral description of Discrete Cosine Transform in image compression." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/28641.
Full textHantehzadeh, Neda. "3-D Face Recognition using the Discrete Cosine Transform (DCT)." Available to subscribers only, 2009. http://proquest.umi.com/pqdweb?did=1964658571&sid=3&Fmt=2&clientId=1509&RQT=309&VName=PQD.
Full textScargall, Lee David. "Very low bit-rate digital video coding." Thesis, University of Newcastle Upon Tyne, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299046.
Full textBhardwaj, Divya Anshu. "Inverse Discrete Cosine Transform by Bit Parallel Implementation and Power Comparision." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2447.
Full textThe goal of this project was to implement and compare Invere Discrete Cosine Transform using three methods i.e. by bit parallel, digit serial and bit serial. This application describes a one dimensional Discrete Cosine Transform by bit prallel method and has been implemented by 0.35 ìm technology. When implementing a design, there are several considerations like word length etc. were taken into account. The code was implemented using WHDL and some of the calculations were done in MATLAB. The VHDL code was the synthesized using Design Analyzer of Synopsis; power was calculated and the results were compared.
Shah, Rajul R. (Rajul Ramesh) 1979. "Hardware implementation of a low-power two-dimensional discrete cosine transform." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/16859.
Full textIncludes bibliographical references (p. 143-144).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
In this project, a JPEG compliant, low-power dedicated, two-dimensional, Discrete Cosine Transform (DCT) core meeting all IBM Softcore requirements is developed. Power is optimized completely at the algorithmic, architectural, and logic levels. The architecture uses row-column decomposition of a fast 1-D algorithm implemented with distributed arithmetic. It features clock gating schemes as well as power-aware schemes that utilize input correlations to dynamically scale down power consumption. This is done by eliminating glitching in the ROM Accumulate (RAC) units to effectively stop unnecessary computation. The core is approximately 180K transistors, runs at a maximum of 100MHz, is synthesized to a .18[mu]m double-well CMOS technology with a 1.8V power supply, and consumes between 63 and 87 mW of power at 100MHz depending on the image data. The thesis explores the algorithmic evaluations, architectural design, development of the C and VHDL models, verification methods, synthesis operations, static timing analysis, design for test compliance, power analysis, and performance comparisons for the development of the core. The work has been completed in the ASIC Digital Cores I department of the IBM Microelectronics Division in Burlington, Vermont as part of the third assignment in the MIT VI-A program.
by Rajul R. Shah.
M.Eng.
Mclean, Ivan Hugh. "An adaptive discrete cosine transform coding scheme for digital x-ray images." Thesis, Rhodes University, 1989. http://hdl.handle.net/10962/d1002032.
Full textBanham, Benjamin E. "An Evolutionary Approach to Image Compression in the Discrete Cosine Transform Domain." DigitalCommons@USU, 2008. https://digitalcommons.usu.edu/etd/5.
Full textPagliari, Carla Liberal. "Perspective-view image matching in the DCT domain." Thesis, University of Essex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.298594.
Full textMurali, Swetha. "Design of Assistive Human-Machine-Interface control signal classifiers using the Discrete Cosine Transform." Available to subscribers only, 2008. http://proquest.umi.com/pqdweb?did=1674094141&sid=8&Fmt=2&clientId=1509&RQT=309&VName=PQD.
Full textLeBlanc, Lawrence. "Image Completion: Comparison of Different Methods and Combination of Techniques." ScholarWorks@UNO, 2011. http://scholarworks.uno.edu/td/1326.
Full textTsai, Hsing-Juan, and 蔡幸娟. "A Parameterizable Architecture for Two-Dimensional Discrete Cosine Transform and Inverse Discrete Cosine Transform." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/66341916946119230484.
Full text逢甲大學
資訊工程所
93
The Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transforms (IDCT) are widely used in various audio and image processing applications. Because of the computation complexity of these algorithms, the dedicated hardware is usually required to achieve the performance of real-time applications. This thesis presents an efficient implementation of a two-dimensional DCT/IDCT processor using a serial-parallel systolic array architecture. The data transfer between processing elements is propagated serially in order to reduce the data communication cost. The data within the processing element is computed in a parallel manner to make the architecture high-speed. By carefully collocating the propagate data in the register of processing element, the transposition operation can be eliminated in this architecture. The block size of 2-D DCT/IDCT and the bit-width of computation data are extracted as parameters that can easily and systematically be adapted to conform to the various imaging coding standard. The behavior and structure model in C language is used to verify the correctness of the 2-D DCT/IDCT computation and the parameterizable implementation. The precision analysis of the 2-D DCT/IDCT implementation was performed by MatLab. The DCT design cost about 14K gate counts when block size is 8 and bit width is 6. The numbers of gate count increase 4 times when block size increases 2 times and those increase about 1.5 times when bit width increases 2 times.
Das, Swastik, and Rasmi Ranjan Sethy. "Image Compression using Discrete Cosine Transform & Discrete Wavelet Transform." Thesis, 2009. http://ethesis.nitrkl.ac.in/1119/1/Image_Compression_using_DCT_%26_DWT.pdf.
Full textBhawna, Gauatm. "Image compression using discrete cosine transform and discrete wavelet transform." Thesis, 2010. http://ethesis.nitrkl.ac.in/1731/1/project.pdf.
Full textHwang, Jen-Jyh, and 黃仁志. "Digital Watermarking by Discrete Cosine Transform." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/99105407359663155102.
Full text世新大學
資訊管理學研究所(含碩專班)
98
With the rapid development and extensive use of multimedia and network technology, multimedia protection such as image, audio, video is an urgent issue. It has been widely concerned to view watermarking technology as a powerful tool for copyright protection and safety certification. The paper is based on watermarks hiding creation by Discrete Cosine Transform (DCT) to analyze the robustness of the watermarked images. By not affecting the visually indistinguishable, this research hopes to provide bigger help for the area of watermarks hiding and digital documents.
Chen, Chingson, and 陳慶勳. "Design and Implementation of Discrete Cosine Transform." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/38242894398568802620.
Full text國立交通大學
電子研究所
83
Discrete Cosine Transform (DCT) is now used in many communication standards for the removal of redundancies of correlation in random sequences. A random sequence with less correlation could be well compressed after quantisation and entropy coding. Since DCT and its inverse (IDCT) cost much computation power, the design of DCT or IDCT is important in overall system consideration. Traditionally, ROM-Based Distributed Arithmetic (DA) architecture has been used in many commercial systems. Since ROMs cost much area in ROM-Based DA, a new architecture named Adder-Based DA replacing ROMs with serial adders is proposed in this thesis. This new architecture cost much less area than traditionally ROM-Based DA since the ROMs are all replaced by small serial adders. An IDCT chip with 16 mm^2 core area by CCL CMOS standard cells is designed and implemented in this thesis and speed of 98 M pels/ sec is achieved in simulation of VERILOG.
Liu, Chun-Wen, and 劉仲文. "Adaptive Voltage Scaling for Discrete Cosine Transform." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/00937421266683497648.
Full text國立交通大學
電子工程系所
96
In the modern digital IC system, adaptive voltage scaling is the most efficient technology for low power design. A new variable voltage generator (VVG) has been proposed in this paper. Five voltage levels ranged from 0.8V to 1.2V can be generated. An adaptive voltage scaling controller has been developed to fit the VVG to form an adaptive voltage scaling control system. In stead of the off-chip DC-DC converter which is often used in voltage regulation, the on-chip VVG takes an important roll in this system. Discrete Cosine Transform (DCT) has become one of the widely used transform techniques in digital signal processing. The adaptive voltage scaling system has been applied to DCT and reduces at most 45% power consumption of DCT. All simulations are implemented in TSMC0.13-μm CMOS technology.
Tsai, Ya-Ting, and 蔡雅婷. "Object Detection with Integer Discrete Cosine Transform." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/40998194573150464909.
Full text中華大學
資訊工程學系碩士班
100
Multimedia technologies, including those for video- and image-related applications, are widely used in various fields, such as security surveillance, medical diagnosis, education, entertainment, and business presentations. Moving objects are of significant interest in surveillance applications. Therefore, detecting the moving objects and identifying their moving trajectories may provide useful information for assuring the security of the monitored site. However, many lighting conditions cause video cameras to record the shadows of moving objects in video images. To identify accurate moving trajectories, the shadows associated with moving objects need to be removed from the recorded video images. Otherwise, false alarm may be triggered, or miscalculation may result. In this thesis, we propose a real-time method for verifying a block belonging to a moving object block or a shadow block. The method includes the following phases. First, we simplify the DCT transformation to construct a novel integer DCT transformation. Second, based on the integer DCT transformed DC and AC coefficients, the background variations are modeled via the GMM probabilistic models. Third, by analyzing the respective variances of the DC and the AC coefficients we can determine the foreground as a moving object or a shadow region. Experimental results show that our method outperforms the conventional methods in terms of accuracy and efficiency.
Chung, Ming-Shen, and 鐘明聲. "FPGA Implementation of the Discrete Fourier Transform (DFT) and the Discrete Cosine Transform (DCT)." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/01456280849939764692.
Full text國立高雄第一科技大學
電腦與通訊工程所
90
The Discrete Fourier Transform(DFT)has been widely applied in communcation, speech processing, image processing, radar and sonar systems, etc. The architecture of DFT implement can be classified into two fields:(1)one is a pipelined systolic architecture,(2)the other is a memory-based architecture. Discrete Cosine Transform(DCT)has been commonly adopted in the various atandardsfor image compression while FPGA has become a new trend of ASIC design, so we will apply FPGA techinque to implement the DFT and the DCT. This thesis deals with how to use FPGA techinque to implement: (1)the pipelined systolic array architecture that requires log2N complex multipliers, 2log2N complex adders, 2log2N multiplexers, N delay elements and is able to provide a throughput of one transform sample per clock cycle; (2)the memory-based architecture that consists of three two-port RAM’s, one ROM, one complex multiplier, two complex adders, one multiplexer, and has capability of computing one transform sample every log2N+1 clock cycles on average; (3)Improved architecture in(2)under increasing little hardware that spends half of run time, i.e.N(log2N)/2; (4)2D-DFT that use architecture in(2)of 1D-DFT; (5)DCT operation and 2D-DCT operation.
Poplin, Dwight. "Distributed arithmetic architecture for the discrete cosine transform." Thesis, 1997. http://hdl.handle.net/1957/34243.
Full textGraduation date: 1997
Liu, Jian-Cheng, and 劉建成. "Multi-dimentional Discrete Cosine Transform (DCT) Chip Design." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/56071432152209136424.
Full textHuang, Mu-Chang, and 黃牧常. "3D Face Recognition Using Discrete Cosine Transform Approach." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/67021825468958961692.
Full text義守大學
電機工程學系
92
It is found that the feature extraction is important in recognition systems, such as faces recognition systems. This thesis studies a 3D face recognition system using the height information in the 3D face as the features. The 3D face database is built up by our 3D reconstruction system. The difference between 3D faces and 2D faces is that the variable in a 3D face including height information rather than the grey level in a 2D face image. The well known Discrete Cosine Transform and Principle Components Analysis method express very good performance in the image compression and faces recognition respectively. In this thesis, we propose the approach which combines DCT and PCA in forming face characteristic coefficient extraction, and compare the results with that using PCA and Wavelet Transform in the 3D face and the 2D face recognition. Our experimental results shows that the combined DCT and PCA approach has outstanding performance. The Nearest Feature Line, Linear Discriminant Analysis and Euclidean Distance are also incorporated into the process to improve the stability and robustness in the recognition system.
LIN, RUI-QI, and 林瑞琦. "A study of discrete cosine and hartley transform." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/63434531522833015784.
Full textShan, Yi-Chia, and 單益嘉. "ASYNCHRONOUS TWO-DIMENSION DISCRETE COSINE TRANSFORM CIRCUIT DESIGN." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/92076365087289606386.
Full text大同大學
通訊工程研究所
96
This thesis proposes an asynchronous two-dimension discrete cosine transform (2-D DCT) processor. In asynchronous design, we used Sutherland’s Micropipelines to implement handshake pipeline. In DCT process, we adopt row-column decomposition method to separate 2-D DCT into two one-dimensional discrete cosine transform (1-D DCT) and a transpose memory. In order to realize the matrix calculation easily, multiplier and accumulator method has been adapted. We implement 2-D DCT function with Field Programable Gate Array (FPGA), and verify the design by the function simulation and timing simulation. FPGA has the programble property, so it’s very convient to be used in design level. We design asynchronous circuit which is based on FPGA architecture. The proposed circuit has asynchronous design spirit, but not completely followed the asynchronous design of the reference paper. The timing simulation result of 2-D DCT is not satisfied, the reason is related with FPGA architecture and the compile tool. Because we can not control the placement and routing of the circuit very well, the programs are auto compiled by FPGA tool, so it could cause the circuit failed. Although we met many challenges in FPGA design, but these experiences can be refered in the future ASIC asynchronous design.
Lao, Hsing-Sheng, and 勞杏生. "Two-Dimension Interpolation Scheme Using Discrete Cosine Transform." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/10377114762758902394.
Full text大同大學
通訊工程研究所
92
The interpolation of an image provides an approach to sample an image at a low rate for transmission or storage and then increase the sampling rate later. Some basic properties of an interpolator must satisfy these zero crossings guarantee that the image is not modified if it is resampled on the same grid. In addition to, the complexity of the interpolation algorithm is needed to be considered. Based on the above principles, a DCT (Discrete Cosine Transform) is proposed to do two-dimensional interpolation. We compare the results of using DCT with those of conventional using DFT (Discrete Fourie Transform) interpolation scheme and Wang’s DFT interpolation scheme. The experiment results show that no matter with human subjective perception to observe or with PSNR(Peak Signal - to - Noise Ratio)error metrics to measure, the results of two-dimensional DCT interpolation scheme are better than those of two-dimensional conventional DFT interpolation scheme and there is no big difference between the methods of two-dimensional DCT interpolation and Wang’s improved two-dimensional DFT interpolation scheme. And the complexity of the two-dimensional DCT interpolation algorithm is simpler than that of two-dimensional DFT one.
Lin, You-Chung, and 林友中. "Design and Test of Discrete Cosine Transform Circuits." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/24801626295131883922.
Full text國立成功大學
電機工程學系碩博士班
91
We present three testable 2-D Discrete Cosine Transform (DCT) circuits with high fault coverage and short test application time. The three DCT circuits are implemented with the row-column decomposition method, the direct method, and the folded direct method, respectively. We do some modifications when designing these DCT circuits to improve their fault coverage. These modifications include scan design, ad hoc design, and pipeline design, which are used according to different circumstances of these DCT circuits. After the modifications on these circuits, their fault coverage can reach 100% or near 100%. However, inserting scan design and pipeline design into the circuits would substantially increase the test application time. To overcome this defect, we apply two testing methods, namely the input reduction testing method and the broadcasting scan method, to these circuits. With these methods the test application time can be reduced to 0.647%~15.48% of those of the original circuits with single full scan design, and the area overhead is 5.84%~9.16% of those of the original circuits.
Zheng, Rui Huang, and 鄭瑞煌. "Design and analysis of inverse discrete cosine transform." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/56157583926065706078.
Full textZHENG, BO-WEN, and 鄭博文. "Design of three dimension discrete cosine transform coder." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/86282721872260597212.
Full textLIN, GUO-ZHEN, and 林國楨. "VLSI implementation of 2-dimensional discrete cosine transform." Thesis, 1991. http://ndltd.ncl.edu.tw/handle/86587200420273634574.
Full textWu, Yung-Gi, and 吳永基. "Finite State Discrete Cosine Transform for Image Compression." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/68322478679918275389.
Full text國立成功大學
電機工程研究所
82
In this thesis,a new image compression method is devised. Discrete Cosine Transform is the kernel of the compressor. The new technique classifies the image subblock into eights classes by their characteristics which can be got from the transfomed domain.Four edge classes,three texture classes ,one smooth class.This kind of classification is called Three Model Classification.As to the overhead of classification ,finite state concept is used to reduce the overhead by predicting the current block's class from the previously blocks. In order to promote the correct ratio of prediction,edge orientation should be considered.We exploit the relationship between the transformed domain and edge orientation.As we know, the smooth regions occupy most part of a natual images.Larger coding size can get higher compression ratio in the smooth regions. But this will sacrifice the quality of complicated regions.In order to solve this deficiency.We devised a variable block coding size algorithm.The edge blocks use the fixed 8*8 block to keep the detailed parts and the variable block size segmentation scheme is applied to texture and smooth regions. The new segmentation method is called "class driven segmentation" The overhead of the segmention is zero. The simulation results show good quality for the decoded images.
Hsieh, Yen-Long, and 謝顏隆. "Architecture Design of H.264 Discrete Cosine Transform." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/74024470056539167481.
Full text國立成功大學
電機工程學系碩博士班
97
This thesis proposes a Discrete Cosine Transform architecture with high throughput and low area. This architecture can be applied in H.264 High Definition (HD) resolution video products. In H.264, the block sizes of the Discrete Cosine Transform are 4×4 and 8×8. The 8×8 block size transform is mainly used in Standard Definition resolution, High Definition resolution, and above Definition resolution. This thesis implements an 8×8 transform architecture. For application in HD resolution video products, the proposed architecture supplies enough high throughput, but a big area should also be associated with a high throughput. Through some property of the DCT, this thesis shows that the area can be reduced and then a high throughput and small area architecture can be implemented. In the proposed architecture, the specification of proposed architecture is 1080p and 60 frames per second. The proposed architecture is synthesized with TSMC 0.18 μm technology cell library and the operating speed is 81 MHz. In this operation speed, the proposed architecture has smaller area when compared with other architectures which also implement H.264 8×8 DCT architecture recently.
Lin, Chen-Chieh, and 林成頡. "A Unified Architecture Design of Recursive Discrete Fourier Transform and Inverse Modified Discrete Cosine Transform." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/53681842824278817088.
Full text國立成功大學
電機工程學系碩博士班
97
The thesis presents a novel unified architecture of the recursive Discrete Fourier Transform (DFT) and the Inverse Modified Cosine Transform (IMDCT) algorithms. The proposed design is supporting multi-formats and multi-length frames, such as MP3, AAC, AAC in DRM, AC3, VQ, Ogg (N=12, 36, 64, 128, 240, 256, 512, 1024, 1920, 2048, 4096 and 8192 points) of IMDCT and DFT in DRM (N=288, 256, 176, 112 points). In order to implement the unified architecture, the kernel of the proposed design is adpoted the recursive DFT algorithm. Due to the limit of speed of the recursive DFT architecture, we used 2-D algorithm to improve this problem. Trandicitonally, the coefficients are implemented by lookup table, but the method will cost large chip area. Thus, we use a memory-free algorithm to solve this problem. The proposed design not only reduces amounts of the coefficients greatly but also supports the multi-format for various audio codecs, if it is built in a media platform. For those of implementation, the proposed architecture only costs five multipliers. The cycle counts of the proposed architecture are 242 times improvement, and then the proposed design are lower than other existing literature of the recursive architecture. TSMC 0.18μm CMOS 1P6M technology is used to implement the proposed design. The chip can be operated at the frequency of 25MHz, the core size iii is 2 0.94�e0.99mm , and the power consummation is 22.97mW. Therefore, it is more suitable for multi-format of audio codecs.
Wu, Yung-Gi, and 吳永基. "New Image Compression Algorithms Based on Discrete Cosine Transform." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/98511424272795876877.
Full text國立成功大學
電機工程學系
88
Due to the progress of multimedia technologies, the demands of various types of information from users become huge so as to lead to the shortage of transmission bandwidth and storage space. The technologies of network and storage devices have been improving as well; however, the users'' desires always exceed the provided services currently. Therefore, data must be compressed before transmission or storage to achieve the needed quality under the circumstance of limited bandwidth. Among all kinds of media, video and image data occupy immense volume. Thus, the compression technologies of them have been intensively exploited in academy and industry. Discrete Cosine Transform (DCT) is an efficient and effective compression tool, which compacts the spatial energy into few coefficients in frequency domain. In addition, there are many fast algorithms for hardware realizations to speed up processing time. DCT has been employed in the compressions of image, video and speech, etc. In this dissertation, new algorithms based on DCT are developed to raise the compression performance of nature and medical images. The first part in this dissertation concentrates on the exploration of compression dimension (size). Here, a 2x2 block based DCT is proposed to compress image. It has the advantage of fast implementation and the compression ratio achieved by our method is better than other block based coding schemes. In addition, a 3D-DCT coder is proposed by us. It can not only attain very high compression ratio but also decrease blocky phenomena. The second part is to explore the processing of DCT coefficients. Conventional block based coding schemes do not consider the correlation among inter-blocks. Proposed spectral analysis strategy takes the correlation into account so as to raise the compression ratio significantly. Another new method is a sampling algorithm used to record the significant DCT coefficients and discard insignificant coefficients. Simulation demonstrates that proposed method is better than conventional coefficient processing method. Finally, a hybridization-coding scheme that combines DCT and Vector Quantization (VQ) is proposed in the last part of this dissertation. DCT is a post processing of VQ. It can decrease 50% bit rate compared to conventional VQ scheme.
Cheng, Wen-Chu, and 鄭文珠. "A Robust Watermarking Method on Discrete Cosine Transform Domain." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/07301667868891898797.
Full text國立清華大學
資訊工程學系
87
A novel image watermarking method with desired picture quality is proposed in this thesis. As usual, the watermark information is a long sequence of random values of normal distribution with zero mean and unity variance. The embedding process operates on the DCT domain as well as the spatial domain regarding the promotion of robustness and invisibility together. First, we understand that the quantity of embedding information is limited by the quantity of the corresponding DCT coefficient, especially for the low quantity coefficient the capability of robustness is declining. Conversely, it can sustain large quantity of information with pleasing level of robustness no matter how the postprocessing is done. Accordingly, our watermarking method adopts multiple and adaptive scaling factors to effectively embed the watermarking information with larger capacity relative to the other methods can do. These scaling factors are guided by desired image quality also. Besides, we superimpose a JND visual model on our method in spatial domain to guarantee the invisibility of watermarks. Furthermore, after the destructive postprocessing such as cropping or resizing, the current similarity measurement is useless. We propose an interesting similarity measurement that can truthfully reflect the similarity using the partial set of watermarks we only have. Finally, we conducted several experiments to justify the proposed method. The simulation results show that it surely prevent the original quality and against the JPEG compressing, cropping and resizing.
Wu, Dong-yang, and 吳東洋. "STUDY OF RESIZING IMAGE BY USING DISCRETE COSINE TRANSFORM." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/3c2835.
Full text大同大學
通訊工程研究所
102
The interpolation is be widely used by digital image process, e.g. Polynomial Interpolation, DFT with zero-padding, etc. The polynomial interpolation increase accuracy at the cost of increasing computation complexity. In frequency domain, the DFT with zero-padding induces inaccurate estimates for edge of image. Discrete Cosine Transform Type-II (DCT-II) is popularly used in digital image process and signal process. Now, some successful literatures use the DCT-II with zero-padding to resize image, but it has an important defect. When the magnification factor is even, the original data would change. The original image data is the important reference, and therefore the current method is not applicable when the magnification is even. As current DCT-II interpolation method has this flaw, so our team revised the procedure of DCT-II interpolation a. It can guarantee the original value will not change when the magnification factor is even. This thesis tries to use the proposed DCT-II interpolation for resizing image with reduction of the computation complexity to improves well known defect. Compared with previous methods, the method used in this thesis can ensure that the most important original data value will not change no matter the magnification factor is odd or even, In addition artificial block edge can be removed by operation of sub-block. The proposed approach can achieve lower the operation time of the processing, and obtain better image quality.
Tseng, Chao-Hsuing, and 曾昭雄. "Designs of Discrete Cosine Transform for Advanced Video Coding." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/60264778611132717506.
Full text國立成功大學
電機工程學系碩博士班
94
In the dissertation, we proposed several fast discrete cosine transform algorithms and integer transforms to reduce the computational complexity and achieve better energy compaction of video coders. First, the fast two-dimensional discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) algorithms were proposed to reduce computational complexity with regular and modular architecture. Then, a systematic design procedure of integer discrete cosine transforms (integer DCTs) and integer orthogonal discrete cosine transforms (IODCTs) was proposed to achieve better energy compaction and improve video coder performance. Finally, an enhanced rate-distortion cost function was proposed to improve the coding performance for H.264/AVC intra mode decision. The detailed discussions are addressed in the following: The proposed fast DCT and IDCT algorithms by using the direct computation approach are based on regular quad-matrix process. Since the algorithms through decomposition and reconstruction procedures can be repeatedly performed, we can easily extend them for the higher-dimension DCT and IDCT computations. With regularized procedures, all the heavy computations can be realized by the same computational kernel, which demands three multiplications and eight additions for each kernel. With high regular architecture and low computational complexity, the proposed algorithms after feasibility design show their advantages in both software and hardware implementation. The integer transform without drifting problems has been widely investigated. Among these researches, the integer transforms in various versions of H.264/AVC are the most attractive. We proposed a systematic design procedure of integer discrete cosine transforms (integer DCTs) and integer orthogonal discrete cosine transforms (IODCTs). Based on the proposed methods, we can design optimal integer transforms with better compaction ability and less computational complexity. With recursive design method, we can get many IODCTs and their reduced computations. The IODCTs depend on selections of normalization factors and cosine kernel integers. We use the compaction coding gain as the criterion to verify the performance of energy compaction to select a proper discrete transform. We found the famous integer transforms which achieve good approximations of the original DCT suggested in H.264/AVC coder all belong to IODCTs. Simulations show that the proposed IODCTs achieve better energy compaction and coding performances than the original DCT and integer transforms in H.264 coder. With advantages of computational efficiency and energy compaction, we believe that the proposed IODCTs could be efficiently and effectively used in advanced video coding systems. In H.264 advanced video coding (AVC) standard, the intra prediction plays an important role in compression of intraframes by referring surrounding coded blocks. It is obvious that either the SAD or SATD criterion suggested in the reference software will cause the worse coding performance compare to RD-optimized criterion. We first propose an enhanced cost function for intra 4x4 mode decision in H.264/AVC and then develop fast computation algorithms of the SATD and the SAITD to reduce the computation by using the property of linear transform and fixed spatial relation of predicted pixels in each intra mode. Simulation results show that when we adopt the enhanced cost function to select the best mode, the coding performance is better than the SAD (or SATD) criterion and is very similar to the RD optimized criterion in low bit rate. Moreover, with the developing fast algorithm of the SATD, we can reduce about 54% computation of the original SATD algorithm for intra 4x4 mode decision. And we can further reduce about 30% the computation of the original SAITD algorithm when computing the enhanced cost function.
Hsieh, Wen-Han, and 謝文漢. "A New Recursive Structure for the Discrete Cosine Transform." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/79359310501168742655.
Full text大同工學院
電機工程學系
84
In this thesis, a new recursive algorithm for the computation of the discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) is proposed. The algorithm is derived by the method that regards the DCT/IDCT as a filter type directly, so it does not need complex or dedicated mathematics like existing algorithms. Therefore, the derived processes of the proposed algorithm are easy to understand and to derive for other transforms. At the same time, the corresponding recursive filters, permitting an arbitrary-length input in natural order, are simpler and more regular than some other existing algorithms. Besides, the distribution of upper-bound values in the recursive structure for each DCT value is derived in this thesis. This distribution is used to add extra bits in the accumulator to process overflow. Finally, the roundoff error analysis for the proposed structure is presented in this thesis and some results by software simulation provide the analysis to be usful.
Cheng, Je-Yuan, and 鄭傑元. "PAPR Reduction For OFDM By Using Discrete Cosine Transform." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/30572659501326670891.
Full text大同大學
通訊工程研究所
92
OFDM (Orthogonal Frequency Division Multiplexing) is using multi-carries to transmit data. The transmitted data are separated into many sub-carriers as parallel transmission, instead of one carrier. Only a small amount of the data is transported on each sub-carrier, and by this lowering of the bit rate per sub-carrier. OFDM can be seen as a parallel data transmission and frequency multiplexing techniques (FDM). The approach can increase robustness against frequency selective fading and multipath immunity. OFDM is used for Terrestrial Digital TV broadcasting in Europe, Japan and Taiwan. In addition, OFDM is used in high-speed telephone line communications such as ADSL, and wireless LAN such as IEEE802.11a/g. Although OFDM has many advantages, it has a problem which is high Peak-to-average power ratio (PAPR). OFDM has high peak more than the average signal level because OFDM is composed of thousands of orthogonal waves. It is a serious defect. The defect results in these serious problems such as nonlinear distortion and increases bit error rate (BER) of receiver, next-channel Interference, etc. We must use a high-level transmitter, an high-resolution A/D and D/A converter, etc. to overcome these defects. It will increase equipment and business capital. The main purpose of this thesis is to discuss how to use discrete cosine transform (DCT) to reduce PAPR and improve application capital of OFDM.
趙廣元. "Multiplication-Free Approximate Algorithms for the Discrete Cosine Transform." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/24726606331906210059.
Full text國立暨南國際大學
資訊工程學系
92
In these years, Hand-held devices such as mobile phone, PDA, etc. are given the capability to capture images. Hence, embedding the function of video or image compression in those devices by using the technique of chip design is getting more and more popular. During the process of design, the high computational complexity of the Discrete Cosine Transform (DCT) is usually the challenge under the condition of limited CPU speed and power. For the sake of reducing the computational complexity, the approximated DCT will be adopted in conjunction with some pruning skill. In this paper, the algorithms of DCT which is extensively used in video and image compression are introduced first. Then, we discuss the approximated DCT and explore how to use the pruning skill to further make this transform faster. In the first part, we focus on the DCT algorithms respectively proposed by Winograd, Chen, and Loeffler. How to use Lifting Scheme to further refine the Chen and Loeffler methods is deeply discussed and some improvement is pointed out also. In the second part, we introduce the approximated algorithms such as Dyadic, Sum-Of-Power-Of-Two (SOPOT), and J.Q.Trelewicz’s method. We use the”Minimum-Adder Multiplications” and “Brute-Force” schemes to further improve the Dyadic and SOPOT algorithms. We also propose a simpler and efficient pruning scheme. In the third part, we show the performance of the J.Q.Trelewicz and our proposed pruning schemes.
Lee, Shiuh-Ming, and 李旭明. "Block-Adaptive Discrete Cosine Transform with Rate-Distortion Control." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/76454073717365139363.
Full text國立清華大學
資訊工程學系
86
Block-Adaptive Discrete Cosine Transform with Rate-Distortion ControlDiscrete Cosine Transform (DCT) has been used for many image or video coding standards such as JPEG, H.261/3, MPEG-1/2/4, etc. In this paper, a block adaptive DCT coder by using a quadtree-based variable blocksize DCT is proposed. It can achieve the best trade-off between the bitrate and the image quality by using the Lagrange multiplier λ merge rate and distortion. By using the quantization matrix generated by the visual model, our performance has a significant improvement on image quality. Simulation resultsshow that our coding scheme outperforms the standard JPEG coder about 1-2 dB at typical bit rates. It can compete with other coding schemes like embedded zerotree wavelet (EZW) and embedded zerotree DCT(EZDCT).
Lee, Yung-Pin, and 李永斌. "Architecture Design for Video Deccoder and Discrete Cosine Transform." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/67437645166483116122.
Full text國立臺灣大學
電機工程學系
85
In this dissertation, both architectures for a 2-D DCT/IDCT using direct approach and an MPEG-2 MP@ML video decoder are proposed. Firstly, a novel 8x8 2-D DCT/IDCT architecture based on the direct 2-Dapproach and the rotation technique is developed. The computational complexity is reduced by taking advantage of the special attribute of complex number. Both the parallel and the folded architectures is proposed. Unlike other approach, the proposed architecture is regular, and economically-allowable for VLSI implementation. Compared to the row-column method, less internal wordlength is needed in order to meet the error requirement of IDCT, and the throughput of the proposed architecture can achieve two times that of the row- column method with 30% hardware increased.The folded 8x8 IDCT architecture is also implemented as a VLSI chip. Secondly, in the MPEG-2 video decoder, the bitstream isfirst surveyed, and, accroding to the bitstream, a suitable variable length decoder (VLD) for such application is designed. Based on the proposedarchitecture for the MPEG-2 decoder, the off-chip memory configuration and the decoding process are analyzed, and the decoding process, which includes VLD,inverse scan, inverse quantization, inverse DCT, and motion compensation, is implemented by VLSI with 27 MHz to satisfy the requirement of the MP@ML.
Chang, Chi Lun, and 張祺崙. "Discrete Cosine Transform Program Generator and its Related Research." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/83882237642740715101.
Full textHui, Yu Rong, and 于榮輝. "Adaptive Discrete Cosine Transform Coding of Gray-Scale Images." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/15830412519295635772.
Full text國立中央大學
資訊及電子工程研究所
82
An adaptive cosine transform coding scheme for gray-scale images based on HVS is proposed in this thesis. Ngan, Leong, and Singh's approach is adopted in this paper. In our block adaptive scheme, a new range scale factor function is proposed to improve the subjective quality of those blocks which contain edges. Besides, we will propose a new adaptive block-effect redunction method to reduce the block effect resulting from block transform coding schemes. This scheme is combined with perceptual distortion minimization and two-dimensional block distortion equalization algorithms. Experimental results show that the subjective quality of the reconstructed images at a bit rate of 0.4 bit/pixel is very appealing.
HONG, SI-BO, and 洪嗣博. "VLSI implementation of 8 X 8 discrete cosine transform." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/68263704895133235828.
Full text杜維洲. "Novel Convolution-Based computations of the discrete cosine transform." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/63817327093807243898.
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