Academic literature on the topic 'Direct Interconnection Technique (DIT)'
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Journal articles on the topic "Direct Interconnection Technique (DIT)"
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Ebrahimi Salari, Mahdi, Joseph Coleman, and Daniel Toal. "Power Control of Direct Interconnection Technique for Airborne Wind Energy Systems." Energies 11, no. 11 (November 13, 2018): 3134. http://dx.doi.org/10.3390/en11113134.
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In this paper, an offshore airborne wind energy (AWE) farm consisting of three non-reversing pumping mode AWE systems is modelled and simulated. The AWE systems employ permanent magnet synchronous generators (PMSG). A direct interconnection technique is developed and implemented for AWE systems. This method is a new approach invented for interconnecting offshore wind turbines with the least number of required offshore-based power electronic converters. The direct interconnection technique can be beneficial in improving the economy and reliability of marine airborne wind energy systems. The performance and interactions of the directly interconnected generators inside the energy farm internal power grid are investigated. The results of the study conducted in this paper, show the directly interconnected AWE systems can exhibit a poor load balance and significant reactive power exchange which must be addressed. Power control strategies for controlling the active and reactive power of the AWE farm are designed, implemented, and promising results are discussed in this paper.
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Salari, Mahdi Ebrahimi, Joseph Coleman, Cathal O'Donnell, and Daniel Toal. "Experimental rig investigation of a direct interconnection technique for airborne wind energy systems." International Journal of Electrical Power & Energy Systems 123 (December 2020): 106300. http://dx.doi.org/10.1016/j.ijepes.2020.106300.
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Salari, Mahdi Ebrahimi, Joseph Coleman, and Daniel Toal. "Analysis of direct interconnection technique for offshore airborne wind energy systems under normal and fault conditions." Renewable Energy 131 (February 2019): 284–96. http://dx.doi.org/10.1016/j.renene.2018.07.045.
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Savtchouk, Alexander, Marshall Wilson, Carlos Almeida, Dmitriy Marinskiy, Robert Hillard, and Jacek Lagowski. "Accurate Dopant and Interface Characterization in Oxidized SiC with Refined Non-Contact C-V Technique." Materials Science Forum 963 (July 2019): 189–93. http://dx.doi.org/10.4028/www.scientific.net/msf.963.189.
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The non-contact C-V technique has been recently gaining interest as a precise, cost and time effective metrology for wide-bandgap semiconductors. Originally focused on dopant measurement, non-contact C-V has been expanding to encompass wide-bandgap surface and interface characterization, including complex reliability issues critical for the future of power devices. In this work, we report progress achieved using a new direct method for determining the flatband voltage, VFB, and capacitance, CFB. Experimental results are presented for n-type oxidized epitaxial 4-H SiC. They demonstrate the approach and the unique self-consistent measurement producing an entire set of pertinent electrical parameters, including the interface trap density, Dit.
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Li, Jinying, Jiaming Xu, and Xin Tan. "Dynamic Comprehensive Benefit Evaluation of the Transnational Power Grid Interconnection Project Based on Combination Weighting and TOPSIS Grey Projection Method." Sustainability 10, no. 12 (December 7, 2018): 4672. http://dx.doi.org/10.3390/su10124672.
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With the rapid development of the global economy, the interconnection of power grids has become an objective law and a trend of the power industry development. The implementation of power grid interconnection projects, especially transnational power grid interconnection projects, will bring us substantial benefits. To demonstrate these benefits comprehensively, we designed a comprehensive evaluation index system with multiple international engineering characteristics. The index system takes the influencing factors of economic, social, environmental and technical benefits into account. In order to improve the rigidity and power of weight determination, we proposed the least squares method which combines the order relation method and the factor analysis method. Furthermore, the limitation of the one-way evaluation was effectively overcome by combining TOPSIS (Technique for Order Preference by Similarity to an Ideal Solution), grey relation analysis method and vector projection method. In addition, we adjusted the potential impact of the time on evaluation by using the quadratic weighted algorithm, so that we can dynamically evaluate the comprehensive benefits. Finally, we verified the established index system and evaluation model through an example of eight different investment plans of a transnational high voltage direct current (HVDC) transmission project. Altogether, results from this paper will provide a guidance reference and decision support for the grid corporation to invest in transnational power grid interconnection projects.
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CHENG, EDDIE, KE QIU, and ZHIZHANG SHEN. "A GENERATING FUNCTION APPROACH TO THE SURFACE AREAS OF SOME INTERCONNECTION NETWORKS." Journal of Interconnection Networks 10, no. 03 (September 2009): 189–204. http://dx.doi.org/10.1142/s0219265909002510.
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An important and interesting parameter of an interconnection network is the number of vertices of a specific distance from a specific vertex. This is known as the surface area or the Whitney number of the second kind. In this paper, we give explicit formulas for the surface areas of the (n, k)-star graphs and the arrangement graphs via the generating function technique. As a direct consequence, these formulas will also provide such explicit formulas for the star graphs, the alternating group graphs and the split-stars since these graphs are related to the (n, k)-star graphs and the arrangement graphs. In addition, we derive the average distances for these graphs.
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Yu, Zhiqiang, Qing Shi, Huaping Wang, Junyi Shang, Qiang Huang, and Toshio Fukuda. "Controllable Melting and Flow of Ag in Self-Formed Amorphous Carbonaceous Shell for Nanointerconnection." Micromachines 13, no. 2 (January 29, 2022): 213. http://dx.doi.org/10.3390/mi13020213.
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Nanointerconnection has been selected as a promising method in the post-Moore era to realize device miniaturization and integration. Even with many advances, the existing nanojoining methods still need further developments to meet the three-dimensional nanostructure construction requirements of the next-generation devices. Here, we proposed an efficient silver (Ag)-filled nanotube fabrication method and realized the controllable melting and ultrafine flow of the encapsulated silver at a subfemtogram (0.83 fg/s) level, which presents broad application prospects in the interconnection of materials in the nanometer or even subnanometer. We coated Ag nanowire with polyvinylpyrrolidone (PVP) to obtain core–shell nanostructures instead of the conventional well-established nanotube filling or direct synthesis technique, thus overcoming obstacles such as low filling rate, discontinuous metalcore, and limited filling length. Electromigration and thermal gradient force were figured out as the dominant forces for the controllable flow of molten silver. The conductive amorphous carbonaceous shell formed by pyrolyzing the insulative PVP layer was also verified by energy dispersive spectroscopy (EDS), which enabled the continued outflow of the internal Ag. Finally, a reconfigurable nanointerconnection experiment was implemented, which opens the way for interconnection error correction in the fabrication of nanoelectronic devices.
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Sidauruk, Paston, Satrio Satrio, Evarista Ristin Pujiindiyati, and Barokah Aliyanta. "Upstream Hydraulic Interconnection Study of Gunungkidul Karst Area Underground Rivers." EKSPLORIUM 38, no. 2 (November 30, 2017): 81. http://dx.doi.org/10.17146/eksplorium.2017.38.2.3715.
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AbstractHydraulic interconnection of Jomblangan cave (Petung) with other caves and water discharges in Gunungkidul karst area has been investigated using tracer techniques and variationof stable isotopes and hydrochemical data interpretation from water samples near the cave. Many studies related to the interconnections of underground rivers around Gunungkidul Karst area have been conducted, most of them, however, focused on the area around Bribin and Seropan caves. This is because of the development activites of microhydro turbines to lift the water from underground river were still focused around Bribin and Seropan caves. Petung cave, located in the north of Bribin and Seropan caves, was believed to be one of the caves at the upstream river system of Bribin and Seropan, however, there is no evidence yet of the hydraulic interconnection between Petung cave with either Bribin or Seropan caves. The results of tracer technique at the current study showed that there was no hydraulic interconnection between Petung cave with either Bribin and Seropan caves.On the other hand, the study showed an indication of a direct flow from Petung cave to Sriti and Beton springs. The travel times from Petung to Sriti and Beton springs were found to be around 2 and 10 hours, respectively. This finding is also in agreement with the results of chemical and stable isotopes analysis from the research location. AbstrakPenelitian keterhubungan Gua Jomblangan (Petung) dengan gua lainnya dan keluaran air di sekitar daerah karst Gunungkidul telah dilakukan dengan menggunakan teknik perunut dan variasi kandungan isotop stabil serta hidrokimia sampel air di sekitar gua. Penelitian yang berkaitan dengan keterhubungan antara sistim aliran bawah tanah di sekitar daerah karst Gunungkidul telah banyak dilakukan, namun sebagian besar dari penelitian tersebut hanya berpusat pada gua di sekitar Bribin dan Seropan. Hal ini terjadi karena kegiatan pembangunan turbin-turbin mikrohidro untuk mengangkat air dari sungai bawah permukaan tanah masih terfokus di daerah gua Bribin dan Seropan. Gua Petung, yang berada di sebelah utara gua Bribin dan Seropan, dipercaya merupakan salah satu gua yang berada di hulu sistim sungai bawah tanah Bribin dan Seropan, namun, sampai sekarang belum ada bukti keterhubungan hidrolika antara gua Petung dengan gua Bribin maupun dengan gua Seropan.Hasil uji perunut dalam penelitian ini menunjukkan bahwa aliran air bawah tanah di gua Petung tidak berhubungan langsung dengan aliran bawah tanah di gua Bribin maupun di gua Seropan. Sebaliknya, hasil penelitian ini menunjukkan adanya aliran langsung dari gua Petung ke mata air Sriti dan Beton. Waktu tempuh yang dibutuhkan dari gua Petung ke mata air Sriti adalah sekitar 2 jam dan ke mata air Beton adalah sekitar 10 jam. Temuan ini sangat bersesuaian dengan hasil analisis kimia air dan isotop stabil dari lokasi penelitian.
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Ngamroo, I. "Design of A Hvdc-Based Controller for Load Change Compensation and Stabilization of Inter-Area Oscillations." ASEAN Journal on Science and Technology for Development 20, no. 3&4 (December 27, 2017): 187–202. http://dx.doi.org/10.29037/ajstd.356.
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As an interconnected power system via a High-Voltage Direct Current (HVDC) link is subjected to a rapid load change with the frequency of inter-area oscillation mode, system frequency and tie line power may be severely disturbed and oscillate. To compensate for the rapid load change and stabilize both frequency and tie line power oscillations due to the inter-area mode, the dynamic power flow control via a HVDC link can be exploited. To implement this concept, a new design method of HVDC-based controller is proposed. To grasp a physical characteristic of the inter-area oscillation frequency, the technique of overlapping decompositions is employed to achieve the subsystem embedded with the inter-area mode. Consequently, the second-order lead/lag controller of HVDC link can be designed in this subsystem. To acquire the desired overshoot of frequency oscillations, the parameters of the controller are automatically optimized by the Tabu Search (TS) algorithm. The effectiveness of the designed controller is investigated in a three-area longitudinal interconnected power system which represents the interconnection between the south of Thailand and Malaysia power systems.
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Lei, Thomas G., Jesus Calata, Shu Fang Luo, Guo Quan Lu, and Xu Chen. "Low-Temperature Sintering of Nanoscale Silver Paste for Large-Area Joints in Power Electronics Modules." Key Engineering Materials 353-358 (September 2007): 2948–53. http://dx.doi.org/10.4028/www.scientific.net/kem.353-358.2948.
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Today, reflow soldering is a commonly used technique to establish large-area joints in power electronics modules. These joints are needed to attach large-area (>1 cm2) power semiconductor chips to the substrate, e.g., a direct-bond copper substrate, and the multichip module substrate to a copper base plate for heat spreading. Thermal performance, specifically thermal conductivity and thermomechanical reliability, of these large-area joints are critical to the electrical performance and lifetime of the power modules. Soft solder alloys, including the lead-tin eutectic and lead-free alternatives, have low thermal conductivities and are highly susceptible to fatigue failure. As demands mount for higher power density, higher junction temperature, and longer lifetime out of the power modules, reliance on solder-based joining is becoming a barrier for further advancement in power electronics systems. Recently, we successfully demonstrated lowtemperature sintering of nanoscale silver paste as a lead-free solution for achieving highperformance, high-reliability, and high-temperature interconnection of small devices (<0.09 cm2). In this paper, we report the results of our study to extend the low-temperature sintering technique to large-area joints. The study involved redesigning the organic and inorganic components of the nanoscale silver paste, analyzing the burnout kinetics of the various organic species sandwiched between large-area plates, and developing desirable temperature-time profile to improve sintering and bonding strength of the joints.
Dissertations / Theses on the topic "Direct Interconnection Technique (DIT)"
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Mouawad, Bassem. "Assemblages innovants en électronique de puissance utilisant la technique de " Spark Plasma Sintering "." Phd thesis, INSA de Lyon, 2013. http://tel.archives-ouvertes.fr/tel-00943438.
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L'augmentation des températures de fonctionnement est une des évolutions actuelles de l'électronique de puissance. Ce fonctionnement entraine d'une part des changements de la structure des modules de puissance notamment des structures " 3D " pour assurer un refroidissement double face des composants de puissance, et d'autre part l'utilisation de matériaux qui permettent de réduire des contraintes thermomécaniques, liées à la différence de coefficient de dilatation des matériaux, lors d'une montée en température. Le travail réalisé au cours de cette thèse consiste à développer une nouvelle structure " 3D " basée sur une technique de contact par des micropoteaux en cuivre, élaborés par électrodéposition et ensuite assemblés à un substrat céramique métallisé (notamment, un DBC : Direct Bonding Copper). Pour réaliser ce contact, une technique de frittage par SPS (Spark Plasma Sintering) est utilisée. Nous étudions dans un premier temps le collage direct de cuivre sur des massifs, puis effectuons dans un deuxième temps le collage de cuivre entre les micropoteaux et le DBC. Cette technique SPS est aussi utilisée pour la réalisation d'un nouveau substrat céramique métallisé basé sur des matériaux avec des coefficients de dilatation thermique accordés, pour les applications à haute température.
Conference papers on the topic "Direct Interconnection Technique (DIT)"
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Malba, Vincent, Leland B. Evans, Christopher D. Harvey, and Anthony F. Bernhardt. "V-PAC: Vertical Packaging for Assembly-Compatible Chip Stacks." In ASME 2003 International Electronic Packaging Technical Conference and Exhibition. ASMEDC, 2003. http://dx.doi.org/10.1115/ipack2003-35194.
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A new process for making high-density memory stacks which are completely compatible with typical electronic assembly techniques is presented. The process uses PECVD-SiO2 passivation, laser direct-writing, electrodeposited photoresist, and metal electroplating to form a reroute pattern extending from the input/output (I/O) pads on top of the chip directly onto the chip sidewalls. With the I/O available for interconnection on the side of the chip, four memory chips are stacked together with one silicon reroute chip. A high-temperature compatible anisotropically conductive adhesive is used to connect a flex circuit to the sidewall I/O pads of the memory chips and the reroute die. The reroute die’s sidewall pads connect to a pattern on the die surface which redistributes the I/O for connection to a leadframe. The lead frame is epoxied to the reroute die, and wirebonded to complete the electrical connection. The leadframe/stack assembly is then encapsulated with an epoxy potting compound, and the leads are formed and trimmed, creating a chip stack which is indistinguishable from a standard IC package.
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Adanur, Emir, Charles Ellis, Robert N. Dean, Eric Tuck, and Derek Strembicke. "A Novel Plating Technique for Realizing Copper Filled TSVs in Silicon Wafers." In ASME 2011 International Mechanical Engineering Congress and Exposition. ASMEDC, 2011. http://dx.doi.org/10.1115/imece2011-63689.
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Through-Silicon-Vias (TSVs) continue to stand out as the most promising technology for electrical interconnections in the microelectronics industry. As package size continues to decrease, TSVs offer an elegant and robust solution for vertical interconnects. They facilitate 3D die stacking while minimizing or even eliminating area consuming planar packaging, allowing for direct signal and power paths through the substrate itself. TSVs can also be fabricated from different materials to desired dimensions to handle the required current level. Plated copper is emerging as the material of choice for TSVs. In this work, electroplated copper TSVs were fabricated successfully and evaluated using cutting and polishing techniques in preparation for image capture. The detailed fabrication process and analysis of the resulting TSVs are presented in this work.
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Tumne, Pushkraj, Vikram Venkatadri, Santosh Kudtarkar, Michael Delaus, Daryl Santos, Ross Havens, and Krishnaswami Srihari. "Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages (WLCSP)." In ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems. ASMEDC, 2011. http://dx.doi.org/10.1115/ipack2011-52078.
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Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.
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Kim, Houngkyung, Jun Yeob Song, Jae Hak Lee, Seungman Kim, and Yongjin Kim. "Face-up Interconnection Technique Using Direct Image Writing for Three-Dimensional Heterogeneous Flexible Electronics." In 2018 IEEE 20th Electronics Packaging Technology Conference (EPTC). IEEE, 2018. http://dx.doi.org/10.1109/eptc.2018.8654284.
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Mohammed, Ilyas, and Young-Gon Kim. "Design Features of Compliant Packages and Their Impact on Reliability." In ASME 2001 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2001. http://dx.doi.org/10.1115/imece2001/epp-24705.
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Abstract It is well-known that the main cause of mechanical failure in electronic packages is due to the difference in the Coefficients of Thermal Expansion (CTE) of the silicon and the organic board. There are many packaging technologies that try to overcome this limitation; ranging from making curved connection pins (gull-wing leads) from the package to the board, as in the case of Thin Small Outline Package (TSOP), to using hard epoxy to rigidly adhere the die to the board as in the case of flip-chip packages. This paper illustrates a compliant packaging concept that minimizes the effect of the CTE mismatch between the silicon die and the board. A summary of different packaging techniques that address the CTE mismatch problem is presented. From this summary, it is apparent that many of these techniques do not provide as high reliability as the compliant packages do, especially when the electrical connections from the package to the board (solder balls) are present directly under the silicon die as in the case of chip scale packages. As the compliant package isolates the effect of the silicon die from the substrate, the silicon has some motion relative to the substrate. This means that the interconnections from the silicon to the substrate must be designed to withstand this motion. Hence the design of these interconnections is key to maximizing the reliability of the compliant packages. A detailed design and reliability analysis of compliant packages for different applications is presented. The design highlights the main parameters that have an effect on reliability of the package. Reliability simulation and analysis using finite element techniques is presented for different designs to highlight the key parameters that govern the reliability of compliant packages. Finally, reliability testing data is presented for different packages.
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Lee, James, and Tony Rogers. "Hermetic Packaging Technique Featuring Through-Wafer Interconnects and Low Temperature Direct Bond." In 2008 Second International Conference on Integration and Commercialization of Micro and Nanosystems. ASMEDC, 2008. http://dx.doi.org/10.1115/micronano2008-70288.
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A novel wafer level packaging method suitable for low production volumes, R&D, and multi-project wafers is presented, providing a hermetic seal suitable for vacuum encapsulation with wafers bonded at a low temperature. Hermetic through-wafer interconnects are bump bonded to a CMOS chip encapsulated by bonding a cap wafer after activating surfaces with free radicals, the Silicon-Silicon direct bond is then annealed to a high strength at 200°C to avoid chip damage. The application for which this system is proposed is an implantable multi-contact active nerve electrode for the treatment of epilepsy via vagus nerve stimulation. Although intended for human implantation of integrated systems, this technology may be applied across a range of devices requiring hermetic or vacuum sealing and through-wafer interconnection. Solid electroplated through-wafer interconnects (aspect ratio 5) enable hermetic interconnection of direct bonded packages with low connection impedance, offering benefits across a range of packaging applications. A key feature of this packaging method is it’s versatility, the proposed embodiment features chip to wafer bonding with an ASIC, but the package is equally suitable for MEMS devices and also for wafer to wafer bonding.
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Prchlik, Lubos, Tomas Misek, Zdenek Kubin, and Karel Duchek. "The Measurement of Dynamic Vibration Modes and Frequencies of a Large LP Bladed Disc." In ASME Turbo Expo 2009: Power for Land, Sea, and Air. ASMEDC, 2009. http://dx.doi.org/10.1115/gt2009-60002.
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A new 48″ steam turbine last stage blade (LSB) has been developed by the common effort of Skoda Power and Ansaldo Energia. The successful detuning of eigen-frequencies with respect to the basic rotational frequency has been achieved by using interconnecting elements near the mid-span and at the shroud of blades. Friction forces among the contact elements resulted from the constraint blade untwist generated by the centrifugal-force. FEM calculation of the Campbell and interference diagrams was followed by a detailed measurement in a specialized vacuum testing rig with strain gages located near the blade root. The excitation was performed by a high-power variable-frequency magnet. For the critical 0-node “umbrella” shape frequency both the axial magnetic excitation and the direct torsional excitation with AC driving motor were applied. Nearly forty different bladed-disc frequencies grouped into five families were identified by the FFT analysis. The corresponding modal shapes were indentified from the relationship between the excitation and resonance frequencies using the time offset of the signal from strain gages distributed along the disc perimeter. An excellent agreement between calculated and measured frequencies and nodal shapes was observed. A typical difference between the predicted and actually measured critical frequencies did not exceed 3% of the nominal value for the relevant frequencies. A complementary measurement using tip-timing technique is currently underway.
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Lueg, Raymond T., James W. Rose, and James E. Simpson. "A Reliability Study of a Novel Type of Solder-Less Interconnection." In ASME 2010 International Mechanical Engineering Congress and Exposition. ASMEDC, 2010. http://dx.doi.org/10.1115/imece2010-37680.
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The reliability of a novel type of solder-less electrical interconnection has been investigated. The technique is known as Compressive Displacement (CD). CD is the mechanical bonding of flex to a printed circuit board (PCB) using an adhesive layer under specified temperature, pressure and time process parameters. Unlike the more commonly used anisotropic conductive film (ACF) attach process; CD does not require electrically conductive spheres dispersed in the adhesive. The metal features on the flex and the mating PCB pads are designed to displace the adhesive from between them during processing, resulting in a direct metal-to-metal electrical interconnection between the two and robust mechanical adhesion in the regions other than the metal features. Reliability experiments were performed on specially-designed test assemblies which incorporated a variety of component footprints, including 1206, 0805, 0603, 0402 and 0201 types from the IPC-SM-782 standard. Process parameters and adhesives were varied between test boards in order to evaluate the effect of these parameters on reliabilty. The assemblies were subjected to 3,700 temperature cycles of −45°C to +125°C and a 2,400 hr soak test at 85°C / 85% RH. Continuity tests were performed every 100 cycles / 100 hours. The resulting failure data indicated very few failures for many component footprint types under these conditions and indicated which process parameters had the most influence on life. Analysis of the reliability data also indicated that the CD connections for most component footprints greatly exceed the ten-year service life requirement of the intended application.
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Soto, Paola Rivera, Pedro O. Quintero, Mellyssa Mulero, and Dimeji Ibitayo. "Microstructural Stability of Au-Sn SLID Joints for Harsh Environments." In ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels. American Society of Mechanical Engineers, 2015. http://dx.doi.org/10.1115/ipack2015-48323.
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Solid liquid inter diffusion (SLID) is an interconnection technique for electronic packaging, particularly beneficial for high power and harsh environments conditions. It consists of the bonding of two materials with different melting points at a low processing temperature to achieve a high melting point interconnection. The materials investigated in this work are a gold-tin bond attaching a SiC diode to an AlN direct-bond-copper (DBC) substrate. Gold (Au) is the high melting point constituent while the eutectic gold-tin (80 wt.% Au-20 wt.%Sn) offers the low melting point (280°C). This work is aimed at the microstructural evaluation of the joints at different bonding and aging conditions in an effort to get the insights of this interconnection technology from a metallurgical perspective. Four different bonding conditions were used: 315°C-5min, 315°C-10min, 340°C-1min and 340°C-5min; from which a base-line as built condition was assessed by means of metallographical analysis. Furthermore, the samples were aged at 250°C from 1000 to 4000 hours in increments of 1000hrs to study and quantify the microstructural stability and intermetallic (IMC) growth at the interface. This aging experiment has been designed to obtain accelerated information on the kinetics of this reaction so that predictive models can be developed for the real application conditions. The samples were diced, polished and analyzed following standard metallographical techniques; both optical and electronic microscopy (SEM-EDS) was employed. The as-built samples, for the four bonding conditions, presented differences in IMC growth with the thickest layers appearing at the harshest processing conditions. After aging the IMC kept growing and the formation of a new IMC layer was discovered and investigated, furthermore, cracks started to show in some of the samples. It was observed that after 4000 hours some of the cracks extended across the whole interface.