Dissertations / Theses on the topic 'Digital time constant regulator'

This thesis presents the fundamental issues of the digital controlled DC/DC converter. A lot of challenges exist when you introduce the digital control technique into the control of the DC/DC converter, especially with regards to the voltage regulator module. One issue is the limit cycle oscillation problem caused by the quantization effect from the ADC and DPWM of the digital control chip. Another issue is the delay problem coming from the sample-hold effect. In this thesis, the modeling, analysis and design methodology for the constant frequency voltage-mode control is reviewed. A DPWM (Digital Pulse Width Modulator) model is verified in simulation, which shows what effects the digital control brings to the conventional Pulse Width Modulator. In CPES, the constant on-time control concept is introduced into the digital control of the voltage regulator module. This provides a high resolution of DPWM and allows the digital constant on-time voltage-mode control architecture to be proposed. To limit the oscillation amplitude in the digital control structure, the digital constant on-time current-mode control w/ external ramp is further proposed in CPES. To analyze this structure, a describing function model is proposed for the digital constant on-time current-mode control, which takes both the sample-hold effect and the quantization effect into consideration. This model clearly shows the stability problem caused by the sample-hold effect in the current loop. Using larger rampâ s slope values, this stability issue can be alleviated. Based on this model, a design methodology is introduced. By properly designing the current loopâ s ADC resolution and the voltage loopâ s ADC resolution, the limit cycle oscillation in this structure can be minimized: the digital constant on-time current-mode control will only have the oscillation coming from the sample-hold effect in the current loop, which can be greatly reduced by adding the large slopeâ s external ramp to this structure. Simulation verification for this design methodology is provided to prove the concepts. Based on the proposed model, the compensator design is performed. The motivation for the compensator design is to push the bandwidth while satisfying the stability condition and the dynamic no-limit-cycle oscillation condition. When analyzing the case of one sample per switching cycle, there is a certain amount of delay, which compromises the phase characteristics. Our design also requires a large external ramp because it will reduce the oscillation amplitude in our system. From our model, it is quite obvious that the external ramp must have a slope larger than one time that of inductor current down slope. A slope that is too larger will weaker the phase and limit the bandwidth. When using the normal current-mode compensator, like the 1-pole 1-zero compensator, the phase is dropped too much and the bandwidth will be limited too low. If we use a 2-pole 2-zero compensator, the phase can be boosted. However, in this case, the gain margin requirement from the dynamic no-limit-cycle oscillation condition will make the further improvements on bandwidth impossible. In our design, the one sixth of the switching frequency is achieved.
Master of Science

One of the fundamental characteristics of the microprocessor application is its property of dynamic load change. Although idle most of the time, it wakes up in nanoseconds to support sudden workload demands, which are becoming increasingly severe in today's multi-core processors with large core count. From the standpoint of its voltage regulator (VR) design, it must have very good efficiency at light loads, while also supporting a very fast transient response. Thus, the variable-frequency constant on-time current-mode (COTCM) control scheme is widely used in the VRs, as it can automatically reduce its switching frequency during light-load conditions. But, from transient point of view, it has some limitations in response to heavy-load demands by microprocessors; this is resolved by adding different nonlinear controls in state-of-the-art control schemes. These nonlinear controls are difficult to optimize for the widely variable transient conditions in processors. Another major issue for this ripple-based COTCM control is that when the combined inductor-current ripple in multiphase operation becomes zero because of the ripple-cancellation effect, COTCM loses its controllability. Therefore, the goal of this research is to discover a new adaptive COT control scheme that is concurrently very efficient at light-load conditions and also provides a fast and optimized transient response without adding any nonlinear control; hence providing a complete solution for today's high-performance microprocessors. Firstly, the overview of state-of-the-art COTCM control is discussed in detail, and its limitations are analyzed. Analysis shows that one issue plaguing the COTCM control is its slow transient response in both single and multiphase operation. In this context, two methods have been proposed to improve the transient performance of conventional COTCM control in single and multiphase operations. These two methods can effectively reduce the output capacitor count in system, but the ripple-cancellation and phase overlapping issues in multiphase operation are yet to be improved. This provides motivation to search for a new COT control technique that can resolve all these problems together. Therefore, a new concept of inverse charge constant on-time (IQCOT) control is proposed to replace the conventional ripple-based COTCM; the goals are to improve noise immunity at the ripple-cancellation point without adding any external ramp into the system, and to improve the load step-up transient performance in multiphase operation by achieving natural and linear pulse overlapping without adding any nonlinear control. Additionally, the transient performance of the proposed IQCOT has been further improved by naturally increasing or decreasing the TON time during the load step-up or step-down transient period without adding any nonlinear control. As this transient property is inherent in proposed IQCOT control, it is adaptive to the widely variable transient requirements of processors, and always produces an optimized transient response. In order to design the proposed control with high bandwidth for supporting fast transient response, an accurate high-frequency small-signal model needs to be derived. Therefore, a high-frequency model for the proposed IQCOT control is derived using the describing function method. The model is also verified by simulation and hardware results in different operating conditions. From the derived model it is found that the quality factor (Q) of one double-pole set varies with changes in duty cycle. To overcome this challenge, an auto-tuning method for Q-value control is also proposed in this dissertation.
Ph. D.

Recently, constant-on-time V2 control is more and more popular in industry products due to features of high light load efficiency, simple implementation and fast transient response. In many applications such as cell phone, camera, and other portable devices, low-ESR capacitors such as ceramic caps are preferred due to small size and small output voltage ripple requirement. However, for the converters with ceramic caps, the conventional V2 control suffers from the sub-harmonic oscillation due to the lagging phase of the capacitor voltage ripple relative to the inductor current ripple. Two solutions to eliminate sub-harmonic oscillations are discussed in [39] and the small-signal models are also derived based on time-domain describing function. However, the characteristic of constant-on-time V2 with external ramp is not fully understood and no explicit design guideline for the external ramp is provided. For digital constant on-time V2 control, the high resolution PWM can be eliminated due to constant on-time modulation scheme and direct output voltage feedback [43]. However, the external ramp design is not only related to the amplitude of the limit-cycle oscillation, but also very important to the stability of the system. The previous analysis is not thorough since numerical solution is used. The primary objective of this work is to gain better understanding of the small-signal characteristic for analog and digital constant-on-time V2 with ramp compensations, and provide the design guideline based on the factorized small-signal model. First, constant on-time current-mode control and constant on-time V2 control are reviewed. Generally speaking, constant-on-time current mode control does not have stability issues. However, for constant-on-time V2 control with ceramic caps, sub-harmonic oscillation occurs due to the lagging phase of the capacitor voltage ripple. External ramp compensation and current ramp compensation are two solutions to solve the problem. Previous equivalent circuit model extended by Ray Ridleyâ s sample-and-hold concept is not applicable since it fails to consider the influence of the capacitor voltage ripple. The model proposed in [39] successfully considers the influence from the capacitor voltage ripple by using time-domain describing function method. However, the characteristic of constant-on-time V2 with external ramp is not fully understood. Therefore, more research focusing on the analysis is needed to gain better understanding of the characteristic and provide the design guideline for the ramp compensations. After that, the small-signal model and design of analog constant on-time V2 control is investigated and discussed. The small-signal models are factorized and pole-zero movements are identified. It is found that with increasing the external ramp, two pairs of double poles first move toward each other at half of switching frequency, after meeting at the key point, the two double poles separate, one pair moves to a lower frequency and the other moves to a higher frequency while keeping the quality factor equal to each other. For output impedance, with increasing the external ramp, the low frequency magnitude also increases. The recommended external ramp is around two times the magnitude at the key point K. When Duty cycle is larger, the damping performance is not good with only external ramp compensation, unless very high switching frequency is used. With current ramp compensation, it is recommended to design the current ramp so that the quality factor of the double pole is around 1. With current ramp compensation, the damping can be well controlled regardless of the circuit parameters. Next, the small-signal analysis and design strategy is also extended to digital constant on-time V2 control structure which is proposed in [43]. It is found that the scenario is very similar as analog constant on-time V2 control. The external ramp should be designed around the key point to improve the dynamic performance. The sampling effects of the output voltage require a larger external ramp to stabilize digital constant-on-time V2 control while suffers only a little bit of damping performance. One simple method for measuring control-to-output transfer functions in digital constant-on-time V2 control is presented. The experimental results verify the small-signal analysis except for the high frequency phase difference which reveals the delay effects in the circuit. Load transient experimental results prove the proposed design guideline for digital constant on-time V2 control. As a conclusion, the characteristics of analog and digital constant-on-time V2 control structures are examined and design guidelines are proposed for ramp compensations based on the factorized small-signal model. The analysis and design guideline are verified with simplis simulation and experimental results.
Master of Science

Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells. The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.

Диссертация на соискание научной степени кандидата технических наук по специальности 05.11.13 – приборы и методы контроля и определения состава веществ. – Национальный технический университет "Харьковский политехнический институт", Харьков, 2016. Диссертация посвящена разработке метода контроля кратковременной перегрузочной способности высоковольтного силового кабеля в условиях производства и необходимый комплекс аппаратуры для его экспериментального подтверждения. Предложена модель нагрева жилы в начальный период нагрева кабеля, которая является решением дифференциального уравнения второй степени для теплового баланса в течение адиабатного нагрева кабеля. Модель позволила количественно характеризовать кратковременную перегрузочную способность кабеля и сравнивать ее с кратковременной перегрузочной способностью, полученной с помощью известных моделей нагрева кабеля. Предложен количественный показатель кратковременной перегрузочной способности высоковольтного кабеля со сшитой полиэтиленовой изоляцией для контроля изготовленных кабелей в условиях производства. Данный показатель не зависит от условий окружающей среды, а значит, является качественной характеристикой самого кабеля. Создан и опробован комплекс аппаратуры для определения показателя кратковременной перегрузочной способности высоковольтного кабеля в условиях производства. Проверен разработанный метод оперативного неразрушающего контроля показателей кратковременной перегрузочной способности на примере СПЭ-кабеля на напряжение 35 кВ.
Dissertation for the degree of Ph. D. in Engineering Science, specialty 05.11.13 – Devices and methods of testing and materials structure determination. – National Technical University "Kharkov Polytechnic Institute", Kharkov, 2016. The thesis is devoted to the developing of control method of the short-term over-load capacity of high voltage cable in the conditions of production and the required complex of equipment for the verification of method. It was proposed the quantitative criterion of the short-term overload capacity of high voltage cable with cross linked polyethylene insulation for the control of the manufacturing cables in the conditions of production. It was created and proofed the complex of equipment for determination the criterion of the short-term overload capacity of high voltage cable in the conditions of production. The developed prompt method of the nondestructive testing of the quantitative criteria of the short-term overload capacity was tested on the 35 kV XLPE-cable.

Дисертація на здобуття наукового ступеня кандидата технічних наук за спеціальністю 05.11.13 – прилади і методи контролю та визначення складу речовин. – Національний технічний університет "Харківський політехнічний інститут", Харків, 2016 р. Дисертація присвячена розробці методу контролю короткочасної перевантажувальної здатності високовольтного силового кабелю в умовах виробництва та необхідний комплекс апаратури для його експериментального підтвердження. Запропоновано модель нагріву жили в начальний період нагріву кабелю. Модель дозволила кількісно характеризувати короткочасну перевантажувальну здатність кабелю і порівнювати її з короткочасною перевантажувальною здатністю, одержаною за допомогою відомих моделей нагріву кабелю. Виконано теоретичні та експериментальні дослідження для визначення теплофізичних параметрів відведення тепла з поверхні кабелю в приміщенні та дослідження залежності нагріву кабелю від відстані між фазами при прокладанні в площині. Запропоновано кількісний показник короткочасної перевантажувальної здатності високовольтного кабелю зі зшитою поліетиленовою ізоляцією для контролю виготовлених кабелів в умовах виробництва. Перевірено розроблений метод оперативного неруйнівного контролю показників короткочасної перевантажувальної здатності на прикладі ЗПЕ-кабелю на напругу 35 кВ.
Dissertation for the degree of Ph. D. in Engineering Science, specialty 05.11.13 – Devices and methods of testing and materials structure determination. – National Technical University "Kharkov Polytechnic Institute", Kharkov, 2016. The thesis is devoted to the developing of control method of the short-term over-load capacity of high voltage cable in the conditions of production and the required complex of equipment for the verification of method. It was proposed the quantitative criterion of the short-term overload capacity of high voltage cable with cross linked polyethylene insulation for the control of the manufacturing cables in the conditions of production. It was created and proofed the complex of equipment for determination the criterion of the short-term overload capacity of high voltage cable in the conditions of production. The developed prompt method of the nondestructive testing of the quantitative criteria of the short-term overload capacity was tested on the 35 kV XLPE-cable.

Vodní energie se nyní stala nejlepším zdrojem elektrické energie na zemi. Vyrábí se pomocí energie poskytované pohybem nebo pádem vody. Historie dokazuje, že náklady na tuto elektrickou energii zůstávají konstantní v průběhu celého roku. Vzhledem k mnoha výhodám, většina zemí nyní využívá vodní energie jako hlavní zdroj pro výrobu elektrické energie.Nejdůležitější výhodou je, že vodní energie je zelená energie, což znamená, že žádné vzdušné nebo vodní znečišťující látky nejsou vyráběny, také žádné skleníkové plyny jako oxid uhličitý nejsou vyráběny, což činí tento zdroj energie šetrný k životnímu prostředí. A tak brání nebezpečí globálního oteplování. Použití internetové techniky k ovladání několika vodních elektráren má velmi významné výhody, jako snížení provozních nákladů a flexibilitu uspokojení změny poptávky po energii na straně spotřeby. Také velmi efektivně čelí velkým narušením elektrické sítě, jako je například přidání nebo odebrání velké zátěže, a poruch. Na druhou stranu, systém získávání dat poskytuje velmi užitečné informace pro typické i vědecké analýzy, jako jsou ekonomické náklady, predikce poruchy systémů, predikce poptávky, plány údržby, systémů pro podporu rozhodování a mnoho dalších výhod. Tato práce popisuje všeobecný model, který může být použit k simulaci pro sběr dat a kontrolní systémy pro vodní elektrárny v prostředí Matlab / Simulink a TrueTime Simulink knihovnu. Uvažovaná elektrárna sestává z vodní turbíny připojené k synchronnímu generátoru s budicí soustavou, generátor je připojen k veřejné elektrické síti. Simulací vodní turbíny a synchronního generátoru lze provést pomocí různých simulačních nástrojů. V této práci je upřednostňován SIMULINK / MATLAB před jinými nástroji k modelování dynamik vodní turbíny a synchronního stroje. Program s prostředím MATLAB SIMULINK využívá k řešení schematický model vodní elektrárny sestavený ze základních funkčních bloků. Tento přístup je pedagogicky lepší než komplikované kódy jiných softwarových programů. Knihovna programu Simulink obsahuje funkční bloky, které mohou být spojovány, upravovány a modelovány. K vytvoření a simulování internetových a Real Time systémů je možné použít bud‘ knihovnu simulinku Real-Time nebo TRUETIME, v práci byla použita knihovna TRUETIME.

Studying the dynamic behaviour of non-linear complex power systems in a laboratory is very challenging. Early experimental platforms used micro-alternators to emulate the behaviour of fixed steam and hydro turbine models. The micro-alternator is a three-phase synchronous generator with similar electrical constants (in per unit on machine rating) as those typically found in alternators in large power stations. It is an electrical scaled-down model of machines up to 1000 MW rating and is rated between 1 to 10 kVA. Researchers used these micro-machines up to the 90s to study large electric generators’ transient and steady-state performance. The department of electrical engineering at the Indian Institute of Science (IISc) was also very active in experimental research in power engineering. The department still retained two-three kVA and one ten kVA micro-machine sets, but the control panels of these machines became obsolete as the manufacturer of these machines Mawdsley, London, doesnt exist anymore. Advancements in simulation software packages and real-time simulators have primarily replaced the experimental models of electric power systems worldwide. The push for green energy technologies worldwide due to climate concerns has increased the presence of power electronic converters in the power grids. Reduction of overall inertia, frequent occurrence of electromechanical oscillations, electromagnetic transients, and control interaction modes has become a concern for the power grid operators. The need for understanding the physical insights of the oscillatory modes introduced by fast-acting power electronic converters, the need for developing practically feasible control algorithms for mitigating the interaction modes, and the need for developing dispatchability and grid support features like conventional generation sources have triggered the development of laboratory-scale experimental power grids across the world in the past decade. In this thesis, initially, an attempt is made to revive the old 3 kVA micro alternator controls. An IGBT-based buck converter static excitation system has been developed for the micro-alternator. This exciter also incorporates several limiters which were non-existent in the old analog control panels. An under-excitation limiter, overexcitation limiter, and V/Hz limiter as per IEEE standard 421.5 have been designed to protect the micro-alternator during abnormal conditions such as overloading, overheating, and over-fluxing of the machine. A digital time constant regulator (TCR) is incorporated to modify the micro-alternator field’s time constant to mimic large synchronous machines’ dynamics as micro-machine time constants are very small. The detailed tuning procedure of limiters and TCR is discussed to comply with IEEE STD 421.2 and IEEE STD 421.5. Overheating of old micro-machines was observed due to the creation of multiple shortcircuit faults. Hence, a custom 5 kVA micro-alternator is manufactured through a local vendor having parameters like the old machines. A single micro-alternator can represent only one large alternator dynamics, thereby limiting the scalability of the platform. Emulating machines of different ratings using a single micro-machine would undoubtedly boost the capabilities of experimental platforms for investigating conventional and non-conventional source interactions in laboratories. To the best of our knowledge, only one such attempt was made in the literature, where a model reference control algorithm is proposed to mimic any rating alternator dynamics using a doubly excited laboratory micro-alternator. However, doubly excited micro-alternators are non-existent today. A reconfigurable experimental single machine infinite bus testbed using the 5 kVA singly excited micro-alternator is developed reconfigurable options to emulate different types of IEEE Standard excitation systems, standard turbine governor models and different machine parameters. A non-linear output matching control based on the dynamic inversion technique is proposed for emulating the synchronous generators of different ratings with the IEEE standard excitation system and governor turbine models using a single micro-alternator. IEEE Model 1.1 is used for representing the behaviour of large alternators. The singlemachine infinite bus (SMIB) experimental testbed has been used to validate the proposed emulation approach. The dynamics of the synchronous generator model in per unit corresponding to 128 MVA and 192 MVA machines have been physically emulated on the 5 kVA laboratory micro-alternator. Good tracking performance is obtained with the proposed approach under small and large disturbances in MATLAB simulations and experimental evaluations. Using a systematic scaling procedure the proposed emulation approach has been extended to evaluate the possibility of emulating the WSCC 3 machine 9 bus system in the laboratory using MATLAB simulations. The simulation results are found to be very promising in replicating the dynamics of WSCC system using the 5 kVA micro-machines. Emulation of large machine dynamics with different types of turbines, governors, and excitation controls using a singly excited micro-alternator enabling a generalized synchronous machine emulation platform is a first-of-its-kind effort in the literature to the best of our knowledge.

碩士
國立成功大學
電機工程學系碩博士班
100
This thesis presents a sensorless digital regulator with dead-time self-exploration. The dead-time controller utilizes the relationship between duty-cycle command and power-loss to find the optimized dead-time without sensing any of the power-stage signals. A exploration algorithm with delay-line circuits instead of high frequency is used to accelerate the optimized dead-time searching and provides high quantization resolution with dead-time step. This approach is well suited for digital IC implementation. The FPGA experimental results show that the proposed architecture can quickly search the optimization of the dead-time and improve efficiency. After FPGA prototyping, the proposed DC-DC converter has been implemented in TSMC 1P6M 0.18μm CMOS technology. The chip size is 1.3 mm2 and the experimental results proved the same with FPGA experimental results.

abstract: Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required. The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking. The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.
Dissertation/Thesis
Doctoral Dissertation Electrical Engineering 2019

碩士
國立臺灣大學
電機工程學研究所
101
In the past, the DC-DC converters used for computer power applications usually employ a constant-frequency variable-duty-cycle controller. This type of control, however, often causes low conversion efficiency under light-load conditions. In recent years, light-load efficiency has become a major design consideration for the reason that most of the electronic devices, whether for desk-top or hand-held applications, are most of the time operated under light-load conditions. Therefore, a new controller type, the constant-on-time controller, has been proposed and adopted in many applications recently. DC converters employing such a control scheme features relatively high light-load efficiency, compared to a conventional constant frequency converter, while maintaining good heavy-load efficiency. In this thesis, a tolerance analysis of a converter using a constant-on-time controller will be performed. More specifically, a multi-phased buck converter with adaptive-voltage positioning (AVP) feature employing a constant on-time controller will be analyzed. Two performance features of the converter will be the focus. One is the converter output load line with AVP feature, and the other is the feedback stability performance. The three traditional tolerance analysis methods are used. There are the extreme value analysis, the root-mean-square analysis, and the Monte-Carlo analysis. Sensitivity analysis is also performed that provides an insight into the sensitivity of the converter performances to component value tolerance. The results of these analyses provide useful design information in a high-volume production situation.

碩士
國立臺灣大學
電機工程學研究所
102
In recent years, the ripple-based constant on-time (RBCOT) control scheme for voltage regulators has been adopted in many applications because of its high efficiency feature under both the heavy-load and the light-load conditions. However, the basic RBCOT control suffers from output-voltage offset problem. Therefore, an offset correcting circuit (OC) is sometimes added to the basic RBCOT scheme to correct the problem for the applications in which output voltage precision is critical. This control scheme is abbreviated as OCRBCOT in this thesis. The main focus of this thesis is on the stability issue of a buck converter regulator using the OCRBCOT control scheme. Traditional low-frequency small-signal average models cannot be applied to the basic RBCOT due to inaccuracy [1]. A describing function approach was proposed and applied to model the behavior of a buck converter regulator employing the basic RBCOT scheme [2]. To model the conventional regulator using describing function approach is mathematically too complicated to be feasible. In this thesis, a time-domain analysis approach with a semi-empirical observation is used to address this issue. Experimental and simulation results are given to verify the stability criterion derived. The result obtained in the thesis, while not analytically proved, provides a useful tool for addressing the stability issue of a buck regulator with OCRBCOT control scheme. It also provides a way to eliminate the proper RC value of the offset correcting circuit to minimize the chip area of the OCRBCOT controller integrated circuit.

碩士
國立臺灣大學
電機工程學研究所
102
In recent years, there have been two technical trends for the DC converters for powering computer central process units (CPUs). One of the trends is to push up conversion efficiency not only for the heavy-load condition but also for the light- load condition. The other trend is to interleave multi-channel converter to achieve high load current at low voltage output. For the reasons, current-mode (C.M) constant on-time (COT) control scheme has been widely adopted by industry in recent year. For CPU power converter applications, the average output voltage is usually required to provide adaptive voltage position (AVP) feature. The ripple voltage magnitude must also be keep within tight range, usually in the range of 30 mV, when the CPU load current is changing with time. To emulate the CPU current, a large square-wave load current ranging from several kilohertz to megahertz is usually imposed on the DC converter and tests the output voltage ripple voltage. The focus of the thesis is to investigate the AC loading effects on output ripple voltage. In this thesis, a qualitative analysis of the issue is first given using duty-cycle VI modulation spectrum theory. This analysis provides insight into the complexity of the issue. Then a quantitative analysis based on a time-domain approach is used to derive converter output voltage ripple in terms of the converter load current excitation. A solution is established for estimating the worst-case output ripple voltage due to repetitive large-step AC load current excitation of wide-range frequencies. The results are verified experimentally. A parametric sensitivity analysis for a practical converter is also provided to give an idea about the sensitivity of each parameter variation on the overall ripple magnitude. The analytical results obtained, although complicated, are useful to the designers.

碩士
國立交通大學
電子研究所
107
In this thesis, a digitally controlled linear voltage regulator is proposed using monolithic 3DIC multi-FET BEOL circuits. The PMOS switch array which originally occupied the majority of the area of the digitally controlled voltage regulator is implemented between top metal layers for power grids using monolithic 3DIC BEOL technique for reducing the cost of silicon area. 　　In thr proposed digital voltage regulator, a comparator-based error detector is used instead of an analog amplifier. Compared to the conventional digitally controlled linear voltage regulator, a comparator triggered at the positive and negative edges is utilized to achieve a fast response for the proposed digital voltage regulator. The time sharing method is also used in the shift register to reduce the power consumption due to the double edge triggered comparator. The proposed voltage regulator can adjust the PMOS strength by itself under different PVT and load variations, and achieves settling time by 200ns, quiescent current by 7.4μs and FOM 0.089ps. Furthermore, the total power efficiency is 99.94%.

In this thesis, the possibility of applying digital current mode control on multiple-input (MI) converters is studied. As for MI topologies having a central energy transfer inductor, the predictive constant on-time current-mode control can greatly reduce both the design and digital realization efforts needed. By doing digital constant on-time current-mode control, the control of MI buck and MI buck-boost converters can be simplified into an equivalent-single-input converter control problem. The small signal models of digital constant on-time controlled single-input (SI), MI buck and SI, MI buck-boost converters in both CCM and DCM are proposed. Simulations and experiments were built to verify the proposed models.
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Dissertação de mestrado integrado em Engenharia Física (área de especialização em Dispositivos, Microssistemas e Nanotecnologias)
The core focus of the work reported herein is the fulfillment of a functional Light Detection and Ranging (LiDAR) sensor to validate the direct Time-of-Flight (ToF) ranging concept and the acquisition of critical knowledge regarding pivotal aspects jeopardizing the sensor’s performance, for forthcoming improvements aiming a realistic sensor targeted towards automotive applications. Hereupon, the ToF LiDAR system is implemented through an architecture encompassing both optical and electronical functions and is subsequently characterized under a sequence of test procedures usually applied in benchmarking of LiDAR sensors. The design employs a hybrid edge-emitting laser diode (pulsed at 6kHz, 46ns temporal FWHM, 7ns rise-time; 919nm wavelength with 5nm FWHM), a PIN photodiode to detect the back-reflected radiation, a transamplification stage and two Time-to-Digital Converters (TDCs), with leading-edge discrimination electronics to mark the transit time between emission and detection events. Furthermore, a flexible modular design is adopted using two separate Printed Circuit Boards (PCBs), comprising the transmitter (TX) and the receiver (RX), i.e. detection and signal processing. The overall output beam divergence is 0.4º×1º and an optical peak power of 60W (87% overall throughput) is realized. The sensor is tested indoors from 0.56 to 4.42 meters, and the distance is directly estimated from the pulses transit time. The precision within these working distances ranges from 4cm to 7cm, reflected in a Signal-to-Noise Ratio (SNR) between 12dB and 18dB. The design requires a calibration procedure to correct systematic errors in the range measurements, induced by two sources: the timing offset due to architecture-inherent differences in the optoelectronic paths and a supplementary bias resulting from the design, which renders an intensity dependence and is denoted time-walk. The calibrated system achieves a mean accuracy of 1cm. Two distinct target materials are used for characterization and performance evaluation: a metallic automotive paint and a diffuse material. This selection is representative of two extremes of actual LiDAR applications. The optical and electronic characterization is thoroughly detailed, including the recognition of a good agreement between empirical observations and simulations in ZEMAX, for optical design, and in a SPICE software, for the electrical subsystem. The foremost meaningful limitation of the implemented design is identified as an outcome of the leading-edge discrimination. A proposal for a Constant Fraction Discriminator addressing sub-millimetric accuracy is provided to replace the previous signal processing element. This modification is mandatory to virtually eliminate the aforementioned systematic bias in range sensing due to the intensity dependency. A further crucial addition is a scanning mechanism to supply the required Field-of-View (FOV) for automotive usage. The opto-electromechanical guidelines to interface a MEMS micromirror scanner, achieving a 46º×17º FOV, with the LiDAR sensor are furnished. Ultimately, a proof-of-principle to the use of polarization in material classification for advanced processing is carried out, aiming to complement the ToF measurements. The original design is modified to include a variable wave retarder, allowing the simultaneous detection of orthogonal linear polarization states using a single detector. The material classification with polarization sensing is tested with the previously referred materials culminating in an 87% and 11% degree of linear polarization retention from the metallic paint and the diffuse material, respectively, computed by Stokes parameters calculus. The procedure was independently validated under the same conditions with a micro-polarizer camera (92% and 13% polarization retention).
O intuito primordial do trabalho reportado no presente documento é o desenvolvimento de um sensor LiDAR funcional, que permita validar o conceito de medição direta do tempo de voo de pulsos óticos para a estimativa de distância, e a aquisição de conhecimento crítico respeitante a aspetos fundamentais que prejudicam a performance do sensor, ambicionando melhorias futuras para um sensor endereçado para aplicações automóveis. Destarte, o sistema LiDAR é implementado através de uma arquitetura que engloba tanto funções óticas como eletrónicas, sendo posteriormente caracterizado através de uma sequência de testes experimentais comumente aplicáveis em benchmarking de sensores LiDAR. O design tira partido de um díodo de laser híbrido (pulsado a 6kHz, largura temporal de 46ns; comprimento de onda de pico de 919nm e largura espetral de 5nm), um fotodíodo PIN para detetar a radiação refletida, um andar de transamplificação e dois conversores tempo-digital, com discriminação temporal com threshold constante para marcar o tempo de trânsito entre emissão e receção. Ademais, um design modular flexível é adotado através de duas PCBs independentes, compondo o transmissor e o recetor (deteção e processamento de sinal). A divergência global do feixe emitido para o ambiente circundante é 0.4º×1º, apresentando uma potência ótica de pico de 60W (eficiência de 87% na transmissão). O sensor é testado em ambiente fechado, entre 0.56 e 4.42 metros. A precisão dentro das distâncias de trabalho varia entre 4cm e 7cm, o que se reflete numa razão sinal-ruído entre 12dB e 18dB. O design requer calibração para corrigir erros sistemáticos nas distâncias adquiridas devido a duas fontes: o desvio no ToF devido a diferenças nos percursos optoeletrónicos, inerentes à arquitetura, e uma dependência adicional da intensidade do sinal refletido, induzida pela técnica de discriminação implementada e denotada time-walk. A exatidão do sistema pós-calibração perfaz um valor médio de 1cm. Dois alvos distintos são utilizados durante a fase de caraterização e avaliação performativa: uma tinta metálica aplicada em revestimentos de automóveis e um material difusor. Esta seleção é representativa de dois cenários extremos em aplicações reais do LiDAR. A caraterização dos subsistemas ótico e eletrónico é minuciosamente detalhada, incluindo a constatação de uma boa concordância entre observações empíricas e simulações óticas em ZEMAX e elétricas num software SPICE. O principal elemento limitante do design implementado é identificado como sendo a técnica de discriminação adotada. Por conseguinte, é proposta a substituição do anterior bloco por uma técnica de discriminação a uma fração constante do pulso de retorno, com exatidões da ordem sub-milimétrica. Esta modificação é imperativa para eliminar o offset sistemático nas medidas de distância, decorrente da dependência da intensidade do sinal. Uma outra inclusão de extrema relevância é um mecanismo de varrimento que assegura o cumprimento dos requisitos de campo de visão para aplicações automóveis. As diretrizes para a integração de um micro-espelho no sensor concebido são providenciadas, permitindo atingir um campo de visão de 46º×17º. Conclusivamente, é feita uma prova de princípio para a utilização da polarização como complemento das medições do tempo de voo, de modo a suportar a classificação de materiais em processamento avançado. A arquitetura original é modificada para incluir uma lâmina de atraso variável, permitindo a deteção de estados de polarização ortogonais com um único fotodetetor. A classificação de materiais através da aferição do estado de polarização da luz refletida é testada para os materiais supramencionados, culminando numa retenção de polarização de 87% (tinta metálica) e 11% (difusor), calculados através dos parâmetros de Stokes. O procedimento é independentemente validado com uma câmara polarimétrica nas mesmas condições (retenção de 92% e 13%).