Relevant bibliographies by topics / DIGITAL SYSTEM DESIGN TEST AND VERIFICATION

Academic literature on the topic 'DIGITAL SYSTEM DESIGN TEST AND VERIFICATION'

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Published: 14 March 2023

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Journal articles on the topic "DIGITAL SYSTEM DESIGN TEST AND VERIFICATION"

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Wei, Chi Pin, Zhao Lin Li, Hao Liu, and Zhi Xiang Chen. "Design of a Random Test Platform for DSP Serials Used in Embedded Systems." Advanced Materials Research 267 (June 2011): 98–103. http://dx.doi.org/10.4028/www.scientific.net/amr.267.98.

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Embedded systems with digital signal processor (DSP) become more and more popular for the increasing requirement of supercomputing these days. Efficient development of DSP serials used in embedded systems shortens the embedded system R&D cycle. Functional verification is one of the most complex and expensive tasks during DSP serials design process. A random test platform which is urged for DSP serials verification is proposed in this paper. The platform can automatically generate the random test program. The platform also realized the recording and checking of simulation results, which make the verification more effective. In order to improve the efficiency of DSP verification, a testing experience library has been generated through the testing procedure. This platform can be transplanted for different DSP models easily by updating few modules. According to the verification results, this platform has satisfactory coverage of DSP models.
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Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (March 25, 2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increase in hard & fast circuits, delay also increases simultaneously. That’s the reason these Carry look ahead adders (CLA) are used. The carry look ahead adder speeds up the addition by reducing the amount of time required to determine carry bits. It uses two blocks, carry generator (Gi) and carry propagator (Pi) which finds the carry bit in advance for each bit position from the nearest LSB, if the carry is 1 then that position is going to propagate a carry to next adder.
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Sharma, N., P. Kumar, N. Singh, and U. Mehta. "Digital energy monitor: design, simulations and prototype." South Pacific Journal of Natural and Applied Sciences 35, no. 2 (2017): 45. http://dx.doi.org/10.1071/sp17005.

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This paper demonstrates the design and implementation of a GSM based digital energy monitoring device. Firstly fuzzy based model is developed to replicate the characteristic of current and voltage sensors. The entire system is also studied and simulated in terms of utility side supply, load, microcontroller digitization and GSM communication. A virtual data sharing technic is also studied for the proposed system using state flow logic. A prototype system is verified real-time with its test and verification phase results. In this work, remote monitoring of electricity has been made easier for the utility. Demand side management is also presented as customers can instantly get their electricity consumptions when requested. Further, an effective overcurrent monitoring system has been embedded along with a backup battery source. Results obtained from the experiments prove that with this emerging technology it is possible to move towards a smarter grid at a rapid and cost effective way.
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Chen, Fu Long, Zhao Xia Zhu, and Xiao Ya Fan. "FPGA-Based In-Circuit Verification of Digital Systems." Advanced Materials Research 187 (February 2011): 362–67. http://dx.doi.org/10.4028/www.scientific.net/amr.187.362.

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In general hardware designers design integrated circuit with hardware description languages or schematic diagram. However the growth of circuit complexity makes circuit design error prone and time consuming. The resulting descriptions tend to be lengthy and hard to reason about. Therefore functional simulation, timing simulation and in-circuit test are three essential steps to ensure that the designed circuit is correct. This paper presents a method of in-circuit verification on FPGA using UART communication between the computer and the FPGA board. Through UART, designers can convert the parallel input vector into a set of serial stimulus signals and send them to the FPGA board, and also can receive the feedback serial signals from the FPGA board and reconvert them into a parallel output vector. Given the input and output ports of the verified circuit component, a verification platform based on UART communication will be customized automatically by the in-circuit verification platform generator. This breaks the constraint of the FPGA board's limited pins and supports wide-scale input/output vectors and can be applied in in-circuit test of digital circuit.
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Zhang, Xu, Zhiguang Deng, Jun Li, Youwei Yang, Quan Ma, and Mingming Liu. "Design and Verification of Reactor Power Control Based on Stepped Dynamic Matrix Controller." Science and Technology of Nuclear Installations 2019 (November 3, 2019): 1–11. http://dx.doi.org/10.1155/2019/4973120.

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As key equipment in nuclear power plant, the reactor power control system is adopted to strictly control and regulate the reactor power of a PWR (pressurized water reactor) in a nuclear power plant. A well-optimized predictive control algorithm based on SDMC (stepped dynamic matrix controller) is developed and introduced in this paper and applied to the power regulation of a reactor power model. In addition, the test and verification of this application is conducted by two different methods and devices: the virtual verification platform and the physical DCS (digital control system). The result of the verification suggests that the application of SDMC gains a better performance in the maximum dynamic deviation, adjustment time, overshoot, and so on.
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Zhu, Pengcheng, and Haojie Li. "Design of Aeronautical Digital Video and Communication Bus Processing System." Journal of Physics: Conference Series 2252, no. 1 (April 1, 2022): 012044. http://dx.doi.org/10.1088/1742-6596/2252/1/012044.

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Abstract With the development of avionics systems, Avionics Digital Video Bus (ARINC 818) and Digital Information Transmission System (Arinc429) have become a new generation of aviation video transmission and communication bus standard respectively. Aiming at the characteristics of ARINC 818 and Arinc429, an aeronautical digital video and communication bus processing system is designed. First, the ARINC 818 aviation video transmission bus and the Arinc429 communication bus standard are introduced. Then, the design principles of the aeronautical digital video and communication bus processing system are described according to this standard, and the design scheme of each system component is introduced in detail. Finally, build a hardware test platform for testing and verification. The system development follows an integrated and modular design, with the Application Processing Unit (APU) main processor and Field Programmable Gate Array (FPGA) as the core, which realizes the superposition of 1-channel input ARINC 818 video with internally generated characters, and then outputs 1-channel ARINC 818 to the function displayed on the display. At the same time, it supports 7-channel Electronic Industries Association-422 (EIA-422) and 4-channel Arinc429 bus communication. In addition, the system supports the processing of 22 input discrete quantities and 7 input analog quantities. The design has been successfully used in a certain type of aircraft display control management system.
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Zhu, Pengcheng, and Haojie Li. "Design of Aeronautical Digital Video and Communication Bus Processing System." Journal of Physics: Conference Series 2252, no. 1 (April 1, 2022): 012044. http://dx.doi.org/10.1088/1742-6596/2252/1/012044.

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Abstract With the development of avionics systems, Avionics Digital Video Bus (ARINC 818) and Digital Information Transmission System (Arinc429) have become a new generation of aviation video transmission and communication bus standard respectively. Aiming at the characteristics of ARINC 818 and Arinc429, an aeronautical digital video and communication bus processing system is designed. First, the ARINC 818 aviation video transmission bus and the Arinc429 communication bus standard are introduced. Then, the design principles of the aeronautical digital video and communication bus processing system are described according to this standard, and the design scheme of each system component is introduced in detail. Finally, build a hardware test platform for testing and verification. The system development follows an integrated and modular design, with the Application Processing Unit (APU) main processor and Field Programmable Gate Array (FPGA) as the core, which realizes the superposition of 1-channel input ARINC 818 video with internally generated characters, and then outputs 1-channel ARINC 818 to the function displayed on the display. At the same time, it supports 7-channel Electronic Industries Association-422 (EIA-422) and 4-channel Arinc429 bus communication. In addition, the system supports the processing of 22 input discrete quantities and 7 input analog quantities. The design has been successfully used in a certain type of aircraft display control management system.
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Sun, Peng, Qi Shao, Ying Yu Liu, and Wei Ping Chen. "A New Method of Design and Verification of Digital Silicon Gyroscopes Closed-Loop Driving System Based on MicroBlaze." Key Engineering Materials 645-646 (May 2015): 771–76. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.771.

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The article brings out a digital silicon gyroscopes closed-loop driving system using the phase relationship of the input driving signal and the signal of the forced motion of the mass block in sensor structure based on analyzing the working principle and phase characters of digital silicon gyroscopes. We make a low-cost, simple and high precision measurement technique for resonant frequency of silicon micro-machinery gyroscopes by the whole digital locked loop system designed with MicroBlaze method. Dichotomy and Fourier transform spectrometry method constitute the algorithm of the system and the solution precision can be determined by the number of the times of approximation. Under the control of the MicroBlaze softcore, the system realizes the realization of the digital signal, the high speed frequency transformation, the acquisition of mass block response signal and the calculation of phase difference. Lastly, each module of the system and the whole system are simulated, the whole system is approved on the test broad.
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Rakic, Aleksandar, Sasa Zivanovic, Zoran Dimic, and Mladen Knezevic. "Digital twin control of multi-axis wood CNC machining center based on LinuxCNC." BioResources 16, no. 1 (December 18, 2020): 1115–30. http://dx.doi.org/10.15376/biores.16.1.1115-1130.

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This paper presents an application of an open architecture control system implemented on a multi-axis wood computer numerical control milling machining center, as a digital twin control. The development of the digital twin control system was motivated by research and educational requirements, especially in the field of configuring a new control system by “virtual commissioning”, enabling the validation of the developed controls, program verification, and analysis of the machining process and monitoring. The considered wood computer numerical control (CNC) machining system is supported by an equivalent virtual machine in a computer-aided design and computer-aided manufacturing (CAD/CAM) environment, as well as in the control system, as a digital twin. The configured virtual machines are used for the verification of the machining program and programming system via machining simulation, which is extremely important in multi-axis machining. Several test wood workpieces were machined to validate the effectiveness of the developed control system based on LinuxCNC.
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Hudson, Jeffrey A., Aernout Oudenhuijzen, and Gregory F. Zehner. "Digital Human Modelling Systems: A Procedure for Verification and Validation Using the F-16 Crew Station." Proceedings of the Human Factors and Ergonomics Society Annual Meeting 44, no. 38 (July 2000): 723–26. http://dx.doi.org/10.1177/154193120004403810.

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Digital Human Modelling Systems (HMS's) are considered a basic element in the cockpit design process. Their bio-fidelity has yet to be fully demonstrated, however. Currently, a joint project, undertaken by the Air Force Research Lab (AFRL/HECP) and the Netherlands (TNO HFRI), is addressing this issue. This effort will help improve methods for controlling and assuring anthropometric accommodation of crew systems in military aircraft. A verification and validation procedure is being developed as a part of this project and has been implemented for several commercially available HMS's. The two phases of the procedure are: 1. Anthropometric Verification: Quantify and compare a set of anthropometric values measured on 8 test subjects with the same set measured on their corresponding digital manikins (their human models), and 2. F-16 Cockpit Validation: Quantify and compare field test results (involving reaches, clearance, vision) of the same 8 test subjects in an F-16 cockpit, to the digital test results obtained with the HMS's using digital models of the subjects placed in an F-16 CAD drawing. The digital tests are conducted without knowledge of the field data results. The ultimate goal of this project is to set the standard for verification and validation of Human Modelling Systems to ensure their bio-fidelity. A complete discussion of the methods is provided below. The results, however, were not available at the time this manuscript was submitted, but will be covered in the oral presentation.
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Dissertations / Theses on the topic "DIGITAL SYSTEM DESIGN TEST AND VERIFICATION"

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VALLERO, ALESSANDRO. "Cross layer reliability estimation for digital systems." Doctoral thesis, Politecnico di Torino, 2017. http://hdl.handle.net/11583/2673865.

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Forthcoming manufacturing technologies hold the promise to increase multifuctional computing systems performance and functionality thanks to a remarkable growth of the device integration density. Despite the benefits introduced by this technology improvements, reliability is becoming a key challenge for the semiconductor industry. With transistor size reaching the atomic dimensions, vulnerability to unavoidable fluctuations in the manufacturing process and environmental stress rise dramatically. Failing to meet a reliability requirement may add excessive re-design cost to recover and may have severe consequences on the success of a product. %Worst-case design with large margins to guarantee reliable operation has been employed for long time. However, it is reaching a limit that makes it economically unsustainable due to its performance, area, and power cost. One of the open challenges for future technologies is building ``dependable'' systems on top of unreliable components, which will degrade and even fail during normal lifetime of the chip. Conventional design techniques are highly inefficient. They expend significant amount of energy to tolerate the device unpredictability by adding safety margins to a circuit's operating voltage, clock frequency or charge stored per bit. Unfortunately, the additional cost introduced to compensate unreliability are rapidly becoming unacceptable in today's environment where power consumption is often the limiting factor for integrated circuit performance, and energy efficiency is a top concern. Attention should be payed to tailor techniques to improve the reliability of a system on the basis of its requirements, ending up with cost-effective solutions favoring the success of the product on the market. Cross-layer reliability is one of the most promising approaches to achieve this goal. Cross-layer reliability techniques take into account the interactions between the layers composing a complex system (i.e., technology, hardware and software layers) to implement efficient cross-layer fault mitigation mechanisms. Fault tolerance mechanism are carefully implemented at different layers starting from the technology up to the software layer to carefully optimize the system by exploiting the inner capability of each layer to mask lower level faults. For this purpose, cross-layer reliability design techniques need to be complemented with cross-layer reliability evaluation tools, able to precisely assess the reliability level of a selected design early in the design cycle. Accurate and early reliability estimates would enable the exploration of the system design space and the optimization of multiple constraints such as performance, power consumption, cost and reliability. This Ph.D. thesis is devoted to the development of new methodologies and tools to evaluate and optimize the reliability of complex digital systems during the early design stages. More specifically, techniques addressing hardware accelerators (i.e., FPGAs and GPUs), microprocessors and full systems are discussed. All developed methodologies are presented in conjunction with their application to real-world use cases belonging to different computational domains.
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Zhou, Jing 1959. "LOVERD--a logic design verification and diagnosis system via test generation." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/291686.

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The development of cost-effective circuits is primarily a matter of economy. To achieve it, design errors and circuit flaws must be eliminated during the design process. To this end, considerable effort must be put into all phases of the design cycle. Effective CAD tools are essential for the production of high-performance digital systems. This thesis describes a CAD tool called LOVERD, which consists of ATPG, fault simulation, design verification and diagnosis. It uses test patterns, developed to detect single stuck-at faults in the gate-level implementation, to compare the results of the functional level description and its gate-level implementation. Whenever an error is detected, the logic diagnosis tool can be used to provide useful information to designers. It is shown that certain types of design errors in combinational logic circuits can be detected and allocated by LOVERD efficiently.
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Kim, Seokjin. "High-speed analog-to-digital converters for modern satellite receivers design verification test and sensitivity analysis /." College Park, Md.: University of Maryland, 2008. http://hdl.handle.net/1903/7864.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2008.
Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Bougan, Timothy B. "Flexible Intercom System Design for Telemetry Sites and Other Test Environments." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611449.

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International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California
Testing avionics and military equipment often requires extensive facilities and numerous operators working in concert. In many cases these facilities are mobile and can be set up at remote locations. In almost all situations the equipment is loud and makes communication between the operators difficult if not impossible. Furthermore, many sites must transmit, receive, relay, and record telemetry signals. To facilitate communication, most telemetry and test sites incorporate some form of intercom system. While intercom systems themselves are a not a new concept and are available in many forms, finding one that meets the requirements of the test community (at a reasonable cost) can be a significant challenge. Specifically, the test director must often communicate with several manned stations, aircraft, remote sites, and/or simultaneously record all or some of the audio traffic. Furthermore, it is often necessary to conference all or some of the channels (so that all those involved can fully follow the progress of the test). The needs can be so specialized that they often demand a very expensive "custom" solution. This paper describes the philosophy and design of a multi-channel intercom system specifically intended to support the needs of the telemetry and test community. It discusses in detail how to use state-of-the-art field programmable gate arrays, relatively inexpensive computers and digital signal processors, and some other new technologies to design a fully digital, completely non-blocking intercom system. The system described is radically different from conventional designs but is much more cost effective (thanks to recent developments in programmable logic, microprocessor performance, and serial/digital technologies). This paper presents, as an example, the conception and design of an actual system purchased by the US government.
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Ruddy, Marcus A. "Pico-Satellite Integrated System Level Test Program." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/688.

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Testing is an integral part of a satellite’s development, requirements verification and risk mitigation efforts. A robust test program serves to verify construction, integration and assembly workmanship, ensures component, subsystem and system level functionality and reduces risk of mission or capability loss on orbit. The objective of this thesis was to develop a detailed test program for pico-satellites with a focus on the Cal Poly CubeSat architecture. The test program established a testing baseline from which other programs or users could tailor to meet their needs. Inclusive of the test program was a detailed decomposition of discrete and derived test requirements compiled from the CubeSat and Launch Vehicle communities, military guidelines, and industry standards. The test requirements were integrated into a methodical, efficient and risk adverse test flow for verification.
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Aalto, Alve, and Ali Jafari. "Automatic Probing System for PCB : Analysis of an automatic probing system for design verification of printed circuit boards." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-174865.

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The purpose of this thesis is to conduct an analysis of whether the printed circuit boards from Ericsson can be tested using an automatic probing system or what changes in the design are required, to be a viable solution. The main instrument used for analyzing the printed circuit board was an oscilloscope. The oscilloscope was used to get the raw data for plotting the difference between the theoretical and actual signals. Connected to the oscilloscope was a 600A-AT probe from LeCroy. The programs used for interpreting the raw data extracted from the oscilloscope included Python, Matlab and Excel. For simulations on how an extra via in the signal path would affect the end results we used HFSS and ADS. The results were extracted into different Excel sheets to get an easier overview of the results. The results showed that the design of a board must almost become completely rebuilt for the changes, and it is therefore better to implement in a new circuit board rather than in an already existing one. Some of the components have to either be smaller or placed on one side of the board, where they cannot be in the way of the probe. The size of the board will become larger since the rules of via placements will be limited compared to before. The most time demanding part was the simulations of the extra via in the signal path, and the results showed that if a single-ended signal is below two gigahertz the placing of the via does not make a big difference, but if the signal has a higher frequency the placement is mostly dependent on the type of the signal. The optimal placement is generally around four millimeters away from the receiving end.
Målet med detta examensarbete är att göra en analys av huruvida Ericssons kretskort kan testas med hjälp av ett automatiskt probe system eller om det kräver stora förändringar i designdelen av kretskorten och om, vad för förändringar det i sådant fall kan vara. Till hjälp att analysera kretskorten har vi haft oscilloskop för att få ut rådata om skillnaderna mellan de teoretiska och verkliga signalerna. För att kunna tyda oscilloskopets samplade signaler har olika programmeringsspråk som Python, Matlab samt Excel använts. En extra via i signalens väg har även simulerats i HFSS och ADS med olika sorts probar för att se hur signalens beteende påverkas. Resultaten extraherades sedan in i olika Excel ark för att få en lätt överskådlig bild av resultaten. Resultatet vi fick visade att utformningen av ett kretskort med ändringarna skulle vara lättare att göra med en ny design istället för en redan existerande då större delar av kortet skulle behöva göras om. Vissa stora komponenter behöver antingen göras om, hitta mindre men likvärdiga eller sättas på ena sidan av kortet där de inte är i vägen för proben. Kretskorten som kommer använda flygande probesystem kommer antagligen bli lite större då viornas placering är mer begränsade än tidigare. Det mest tidskrävande arbetet var att simulera olika placeringar av en extra via i signalens väg. Detta visade att på en single ended signal under två gigahertz så gör det ingen större skillnad vart i signalens väg som den extra vian placeras. Då en högre frekvens används så är själva signalens karaktär det viktigaste än placeringen av en via, men om man inte vet den exakta karaktären så är fyra millimeter bort från mottagarens sida att rekommendera då närmare placering av viorna gör att signalerna börjar störa varandra.
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Ioannides, Charalambos. "Investigating the potential of machine learning techniques for feedback-based coverage-directed test genreation in simulation-based digital design verification." Thesis, University of Bristol, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.618315.

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A consistent trend in the semiconductor industry has been the increase of embedded functionality in new designs. As a result, the verification process today requires significant resources to cope with these increasingly complex designs. In order to alleviate the problem, industrialists and academics have proposed and improved on many formal, simulation-based and hybrid verification techniques. To dale, none of the approaches proposed have been ab le to present a convincing argument warranting their unconditional adoption by the industry. In an attempt to further automate design verification (DV), especially in simulation-based and hybrid approaches, machine learning (ML) techniques have been exploited to close the loop between coverage feedback and test generation ; a process also known as coverage directed test generation (COG). Although most techniques in the literature are reported to help in constructing minimal tests that exercise most, if not the entire design under verification, a question remains on their practical usefulness when applied in real-world industry-level verification environments. The aim of this work was to answer the following questions: I. What would constitute a good ML-COG solution? What would be its characteristics? 2. 00 existing ML-CDG technique(s) scale to industrial designs and verification environments? 3. Can we develop an ML-based system that can attempt functional coverage balancing? This work answers these questions having gathered requirements and capabilities from earlier academic work and having filtered them through an industrial perspective on usefulness and practicality. The main metrics used to evaluate these were effectiveness in terms of coverage achieved and effort in terms of computation time. A coverage closure effective and easy to use genetic programming technique has been applied on an industrial level verification project and the poor results obtained show that the particular technique does not scale well. Linear regress ion has been attempted for feature extraction as part of a larger and novel stochastic ML-CDG model. The results on the capability of these techniques were again below expectations thus showing the ineffectiveness of these algorithms on larger datasets. Finally, learning classifier systems, specifically XCS, have been used to discover the cause-effect relationships between test generator biases and coverage. The results obtained pointed to a problem with the learning mechanism in XCS, and a misconception held by academics on its capabilities. Though XCS at its current state is not an immediately exploitable ML~CDG technique, it shows the necessary potential for later adoption once the problem discovered here is resolved through further research. The outcome of this research was the realisation that the contemporary ML methodologies that have been experimented with fall short of expectations when dealing with industry-level simulation-based digital design verification. In addition, it was discovered that design verification constitutes a problem area that can stress these techniques to their limits and can therefore indicate areas for further improvement and academic research.
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Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.

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The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.
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Qiang, Qiang. "FORMAL a sequential ATPG-based bounded model checking system for VLSI circuits /." online version, 2006. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=case1144614543.

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Larsson, Erik. "An Integrated System-Level Design for Testability Methodology." Doctoral thesis, Linköpings universitet, ESLAB - Laboratoriet för inbyggda system, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4932.

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HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems. The main objective of this thesis is to address test problems faced by the designer at the system level. Considering the testability issues at early design stages can reduce the test problems at lower abstraction levels and lead to the reduction of the total test cost. The objective is achieved by developing several new methods to help the designers to analyze the testability and improve it as well as to perform test scheduling and test access mechanism design. The developed methods have been integrated into a systematic methodology for the testing of system-on-chip. The methodology consists of several efficient techniques to support test scheduling, test access mechanism design, test set selection, test parallelization and test resource placement. An optimization strategy has also been developed which minimizes test application time and test access mechanism cost, while considering constraints on tests, power consumption and test resources. Several novel approaches to analyzing the testability of a system at behavioral level and register-transfer level have also been developed. Based on the analysis results, difficult-to-test parts of a design are identified and modified by transformations to improve testability of the whole system. Extensive experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodology and techniques. The experimental results show clearly the advantages of considering testability in the early design stages at the system level.
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Books on the topic "DIGITAL SYSTEM DESIGN TEST AND VERIFICATION"

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Navabi, Zainalabedin. Digital System Test and Testable Design. Boston, MA: Springer US, 2011. http://dx.doi.org/10.1007/978-1-4419-7548-5.

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Verilog digital system design: RT level synthesis, testbench, and verification. 2nd ed. New York: McGraw-Hill, 2006.

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Rashinkar, Prakash. System-On-A-Chip verification: Methodology and techniques. New York: Kluwer Academic Publishers, 2002.

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1959-, Lavagno Luciano, Scheffer Lou, and Martin Grant, eds. EDA for IC system design, verification, and testing. Boca Raton, FL: Taylor & Francis, 2005.

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1955-, Paterson Peter, and Singh Leena 1971-, eds. System-On-A-Chip verification: Methodology and techniques. Boston, MA: Kluwer Academic Publishers, 2001.

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Rashinkar, Prakash. System-On-A-Chip verification: Methodology and techniques. Boston, MA: Kluwer Academic Publishers, 2001.

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Jean-Michel, Bergé, Levia Oz, and Rouillard Jacques, eds. Hardware/software co-design and co-verification. Boston: Kluwer Academic Publishers, 1997.

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Navabi, Zainalabedin. Digital System Test and Testable Design: Using HDL Models and Architectures. Boston, MA: Springer Science+Business Media, LLC, 2011.

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Bergé, Jean-Michel. Hardware/Software Co-Design and Co-Verification. Boston, MA: Springer US, 1997.

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IEEE International High-Level Design Validation and Test Workshop (6th 2001 Monterey, Calif.). Sixth IEEE International High-Level Design Validation and Test Workshop: Proceedings : 7-9 November, 2001. Los Alamitos, Calif: IEEE Computer Society, 2001.

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Book chapters on the topic "DIGITAL SYSTEM DESIGN TEST AND VERIFICATION"

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Navabi, Zainalabedin. "Test Compression." In Digital System Test and Testable Design, 345–73. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_10.

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Navabi, Zainalabedin. "Deterministic Test Generation Algorithms." In Digital System Test and Testable Design, 175–212. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_6.

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Snider, Ross. "Chapter 8: Introduction to Verification." In Advanced Digital System Design using SoC FPGAs, 93–124. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-15416-4_8.

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Navabi, Zainalabedin. "Standard IEEE Test Access Methods." In Digital System Test and Testable Design, 261–94. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_8.

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Navabi, Zainalabedin. "Logic Built-in Self-test." In Digital System Test and Testable Design, 295–344. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_9.

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Navabi, Zainalabedin. "Verilog HDL for Design and Test." In Digital System Test and Testable Design, 21–62. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_2.

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Navabi, Zainalabedin. "Test Pattern Generation Methods and Algorithms." In Digital System Test and Testable Design, 143–74. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_5.

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Navabi, Zainalabedin. "Design for Test by Means of Scan." In Digital System Test and Testable Design, 213–59. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_7.

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Navabi, Zainalabedin. "Basics of Test and Role of HDLs." In Digital System Test and Testable Design, 1–20. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_1.

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Navabi, Zainalabedin. "Memory Testing by Means of Memory BIST." In Digital System Test and Testable Design, 375–91. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_11.

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Conference papers on the topic "DIGITAL SYSTEM DESIGN TEST AND VERIFICATION"

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Xiong, Huasheng, Duo Li, and Liangju Zhang. "Test Facility Design for Integrated Digital Nuclear Reactor Protection System." In 18th International Conference on Nuclear Engineering. ASMEDC, 2010. http://dx.doi.org/10.1115/icone18-29286.

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Reactor protection system is one of the most important safety systems in nuclear power plant and shall be designed with very high reliability. Digital computer-based Reactor Protection System (RPS) takes great advantages over its conventional counterpart based on analog technique and faces the issues how to effectively demonstrate and confirm the completeness and correctness of the software that performs reactor safety functions in the same time. It is commonly accepted that the essential way to solve safety software issues in a digital RPS is to pass a strict and independent Verification and Validation (V&V) process, in which integrated RPS testing play an important role to form a part of the overall system validation. Integrated RPS testing must be carried out rigorously before the system is delivered to nuclear power plant. The integrated testing are often combined with the factory acceptance test (FAT) to form a single testing activity, during which the RPS is excited by emulated static and dynamic input signals. The integration testing should simulate normal operation, anticipated operational occurrences and accident conditions, as well as anticipated faults on the inputs to the DRPS such as sensors out of range or ambiguous input readings. All safety function requirements of digital RPS should be confirmed by representative testing. The design and development of a test facility to carry out the integrated RPS testing are covered in this paper, which is merged in the research on a digital RPS engineering prototype for a nuclear power plant. The test facility is based on PXI platform and LabVIEW software development environment and its architecture design also takes into account the test functions future extensions such as hardware upgrades and software modules enhancement. The test facility provides the digital RPS with redundant, synchronized and multi-channel emulated signals that are produced to emulate all protection signals from 1E class sensors and transmitters with time varied value within their possible ranges, which would put integrated RPS testing into practice to confirm the digital RPS has fully met its predefined safety functionality requirements. The designed test facility can provide an independent verification and validation process for the research of digital RPS with scientific methods and authentic data to evaluate the RPS performance thoroughly and effectively, such as measuring threshold precision and trip response time, analyzing system statistical reliability and so on.
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Reza Kakoee, Mohammad, M. H. Neishaburi, and Siamak Mohammadi. "Functional Test-Case Generation by a Control Transaction Graph for TLM Verification." In 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). IEEE, 2007. http://dx.doi.org/10.1109/dsd.2007.4341464.

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Hanada, Satoshi, Koji Ito, and Kenji Mashio. "US-APWR Human System Interface System Verification and Validation Program for Digital I&C Design." In 18th International Conference on Nuclear Engineering. ASMEDC, 2010. http://dx.doi.org/10.1115/icone18-29928.

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The US-APWR, currently under Design Certification review by the U.S. Nuclear Regulatory Commission, is a four loop evolutionary pressurized water reactor with a four train active safety system applied by Mitsubishi Heavy Industries. The digital Instrumentation and Control (I&C) System and Human Systems Interface (HSI) system are to be applied to the US-APWR. This design is currently being applied to the latest Japanese PWR plant and to nuclear power plant I&C modernization program in Japan. The US-APWR digital I&C and HSI system (HSIS) utilizes computerized systems, including computer-based procedures and alarm prioritization, relying principally on an HSIS with soft controls, console based visual display units (VDUs) and a large, heads up, overview display panel. Conventional hard-wired controls are limited to system level manual actions and a Diverse Actuation System (DAS). The overall design philosophy of the US-APWR is based on the concept that operator performance will be enhanced through the integration of safety and non-safety display and control systems in a robust digital environment. This philosophy is augmented, for diversity, by the application of independent safety soft displays and controls. In addition, non-digital diverse automatic and manual actuation system is introduced. As with all the advanced designs, the digital systems open as many questions as they answer. To address these new questions, for an eight week period during the months of July and August 2008, an extensive verification and validation (V&V) program was completed with the objective of assessing US operators’ performance in this digital design environment. (Robert E. Hall et al., 2008, “US-APWR Human Systems Interface System V&V Results: Impact on Digital I&C Design”, 17th International Conference on Nuclear Engineering, ICONE17-75176) [1] Over this time period, U.S. operating crews were subjected to exercise in Mitsubishi dynamic simulator. To follow up above mentioned V&V activities, additional test during the months of this spring in 2009 has been carried out to resolve human engineering discrepancies (HEDs) induced from the previous evaluation and the participants’ comments and performance. Subjective and objective data were collected on each crew for each scenario and an extensive convergent measures analysis was performed, resulting in the identification of both specific design as well as generic conclusions. This paper discusses the digital HSIS of the US-APWR design, the V&V program data collection and analysis, and the study results related to the ongoing discussion of the impacts of digital systems on human performance, such as workload, navigation, situation awareness, operator training and licensing.
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Kadlubowski, Lukasz A., and Piotr Kmon. "Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array." In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2021. http://dx.doi.org/10.1109/ddecs52668.2021.9417054.

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Zak, P., and V. Dynybyl. "Design and Testing of Gears With Non-Standard Profile." In ASME 2007 International Mechanical Engineering Congress and Exposition. ASMEDC, 2007. http://dx.doi.org/10.1115/imece2007-41027.

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This paper introduces a sophisticated methodology that guides the design of the non-standard geometry of cylindrical gearwheels, methodology for the evaluation of operation life depending on flank damage (pitting) in shortened lifetime tests of gearwheels and also number of other research results. The methodology for the design of gearwheels modifications is solved by using FEM system and takes into account real geometry of the whole gearbox and its component. Processed samples designs are tested in experimental testing stand and compared with samples which are designed using DIN 3990 standard Method B. The test results serves for verification of created designs. The back-to-back test-rig allowing smooth control of virtual power up to 785 kW (1053 HP) is also described. The methodology for evaluation of pitting area is solved by using digital documentation and automatic evaluation of damaged tooth flank surface.
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Sheng, Xin, Xiaojin Huang, Zhencai An, and Yin Guo. "Study on an Optimization Algorithm of Generating Test Vectors for Digital Reactor Protection System Testing." In 16th International Conference on Nuclear Engineering. ASMEDC, 2008. http://dx.doi.org/10.1115/icone16-48098.

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As a safety-critical system for the NPP, the digital Reactor Protection System (RPS) has replaced the traditional analog Reactor Protection System in the most newly-built NPPs. A new type digital RPS developed by INET, Tsinghua University, must pass the hardware qualification and software Verification & Validation (V&V) to satisfy the requirements of quality criterion and safety laws. The stimulation/response testing method is always used in the integration testing phase of software V&V. The test vectors group would be very large if the digital RPS has many input variables. Therefore, In order to find out all of the failure of software, the less testing vectors would be benefit to limit the testing time and cost. A black box model is always be used for those systems with few known information for the Conner. All testing vectors would be generated by nature sequence. The black box model has good features. It does not rely on any prior knowledge about the objective system. However, the black box model may increase the average number of test vectors and average time to find out all of the failure. If a grey box model can be adopted in the testing process, a lot of known information of the objective system can be used and the test time would be saved prominently. As independent developed digital RPS by INET, there is enough information of the testing objects, which can be used to apply the grey box model on the digital RPS testing procedure and to generate the test vectors. An optimization algorithm of test vectors generating is as follows: a) Firstly, a different weight factors would be set to different combination of input variables by expert knowledge and logic design rules; b) Secondly, a particle movement algorithm is used to optimize, compare and select random test vectors by weight factors. The primary simulation results indicate that the average testing time and the number of test vectors are both less than the normal test strategy which based on the black box model. The optimization algorithm of test vectors generating based on the particle movement may be more efficient to find out all of the failure. Therefore, the testing cost and time would be saved in consequence.
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Endo, Yui, Satoshi Kanai, Takeshi Kishinami, Miyata Natsuki, Makiko Kouchi, and Masaaki Mochimaru. "An Ergonomic Assessment System Using a Digital Hand for Designing Handheld Information Appliances." In ASME 2006 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2006. http://dx.doi.org/10.1115/detc2006-99114.

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Recently, as handheld information appliances, such as mobile phones, PDAs, have widely spread, the development of these appliances should pay more attention in their ergonomic design. However, the user tests for developing the “ergonomic” appliances are usually done by many real subjects testing a variety of these physical mockups, and the process of these tests usually requires the expensive cost and has to take a long time. So, we propose a software system of an automatic ergonomic assessment system for designing handheld information appliances by integrating the digital hand model with the product model of the appliance. Our system has the following four feature functions for ergonomic assessment: 1) Generation of kinematically and geometrically accurate digital hand models with rich dimensional variation, 2) automatic evaluation of the grasp posture stability by estimating the force-closure and the grasp quality, 3) automatic evaluation of ease of the finger motion in operating the user interface, 4) aiding the designers to re-design the housing shapes and user-interfaces in the product model. In this paper, we describe the 1) and 2) of the above functions. Moreover, we also describe the verification results of our system by comparing estimated grasp postures and these stability given from the system with the ones from experiments by real subjects.
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Guzas, Emily L., Stephen E. Turner, Matthew Babina, Brandon Casper, Thomas N. Fetherston, and Joseph M. Ambrico. "Validation of a Surrogate Model for Marine Mammal Lung Dynamics Under Underwater Explosive Impulse." In ASME 2019 Verification and Validation Symposium. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/vvs2019-5143.

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Abstract Primary blast injury (PBI), which relates gross blast-related trauma or traces of injury in air-filled tissues or those tissues adjacent to air-filled regions (rupture/lesions, contusions, hemorrhaging), has been documented in a number of marine mammal species after blast exposure [1, 2, 3]. However, very little is known about marine mammal susceptibility to PBI except in rare cases of opportunistic studies. As a result, traditional techniques rely on analyses using small-scale terrestrial mammals as surrogates for large-scale marine mammals. For an In-house Laboratory Independent Research (ILIR) project sponsored by the Office of Naval Research (ONR), researchers at the Naval Undersea Warfare Center, Division Newport (NUWCDIVNPT), have undertaken a broad 3-year effort to integrate computational fluid-structure interaction techniques with marine mammal anatomical structure. The intent is to numerically simulate the dynamic response of a marine mammal thoracic cavity and air-filled lungs to shock loading, to enhance understanding of marine mammal lungs to shock loading in the underwater environment. In the absence of appropriate test data from live marine mammals, a crucial part of this work involves code validation to test data for a suitable surrogate test problem. This research employs a surrogate of an air-filled spherical membrane structure subjected to shock loading as a first order approximation to understanding marine mammal lung response to underwater explosions (UNDEX). This approach incrementally improves upon the currently used one-dimensional spherical air bubble approximation to marine mammal lung response by providing an encapsulating boundary for the air. The encapsulating structure is membranous, with minimal simplified representation not accounting for marine mammal species-specific and individual animal differences in tissue composition, rib mechanics, and mechanical properties of interior lung tissue. NUWCDIVNPT partnered with the Naval Submarine Medical Research Laboratory (NSMRL) to design and execute a set of experiments to investigate the shock response of an air-filled rubber dodgeball in a shallow underwater environment. These tests took place in the 2.13 m (7-ft) diameter pressure tank at the University of Rhode Island, with test measurements including pressure data and digital image correlation (DIC) data captured with high-speed cameras in a stereo setup. The authors developed 3-dimensional computational models of the dodgeball experiments using Dynamic System Mechanics Advanced Simulation (DYSMAS), a Navy fluid-structure interaction code. DYSMAS models of a variety of different problems involving submerged pressure vessel structures responding to hydrostatic and/or UNDEX loading have been validated against test data [4]. Proper validation of fluid structure interaction simulations is quite challenging, requiring measurements in both the fluid and structure domains. This paper details the development of metrics for comparison between test measurements and simulation results, with a discussion of potential sources of uncertainty.
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Davies, William J., Charlie L. Jones, and Robert A. Noonan. "Real Time Simulators for Use in Design of Integrated Flight and Propulsion Control Systems." In ASME 1988 International Gas Turbine and Aeroengine Congress and Exposition. American Society of Mechanical Engineers, 1988. http://dx.doi.org/10.1115/88-gt-24.

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The introduction of Full Authority Digital Electronic Controls (FADEC) to both commercial and military aircraft gas turbine engines provides significant operational benefits. FADEC’s are reliable and more maintainable than the hydromechanical controls they have replaced. The next significant change in their use will be integration with the flight control, particularly in military applications, to provide reduced fuel consumption in cruise and rapid, accurate engine transients for increased maneuverability. Integration with the flight control system requires another level of control system testing beyond verification that the FADEC will perform it’s principle functions-control and protection of the engine. This new testing requires that the FADEC be tested in unison with the flight control to verify total control system capability and safety throughout the flight envelope. These testing requirements have been addressed at Pratt & Whitney and various airframers through application of the same simulation tools which have been in use to verify FADEC hardware and software capability prior to engine test. These test systems and their application to advanced integrated control systems are described herein to provide insight into both their operation and application.
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El-Shafei, A., and M. El-Hakim. "Development of a Test Rig and Experimental Verification of the Performance of HSFDs for Active Control of Rotors." In ASME 1995 International Gas Turbine and Aeroengine Congress and Exposition. American Society of Mechanical Engineers, 1995. http://dx.doi.org/10.1115/95-gt-256.

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This paper summarizes the experimental development of hybrid squeeze film dampers (HSFDs) for active control of rotor vibrations. In a recent paper (El-Shafei and Hathout, 1994) it was shown that the automatically controlled HSFD can be a very useful device for the active control of rotors. A complete mathematical model of the open-loop system was developed. An on-off control strategy based on speed feedback was proposed and was shown by the simulation results to be quite effective in controlling the rotor vibrations. In this paper, the development of a test rig for the experimental investigation of the HSFD-rotor system is presented. The design of the test rig, the HSFD and the rotor system are discussed. The experimental set-up consists of the rotor-HSFD system controlled through a pressure control servovalve for controlling the pressure in the sealing chambers. The hydraulic circuit is controlled through a digital computer with a data acquisition and control system. The on-off control strategy with feedback on speed is implemented on the computer control system and is shown to be quite effective in controlling the first mode of vibration of the rotor system.
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Reports on the topic "DIGITAL SYSTEM DESIGN TEST AND VERIFICATION"

1

Korsah, K., G. W. Turner, and J. A. Mullens. Environmental testing of a prototypic digital safety channel, Phase I: System design and test methodology. Office of Scientific and Technical Information (OSTI), April 1995. http://dx.doi.org/10.2172/90921.

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