Journal articles on the topic 'Digital processor architectures'
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Lee, Jongbok. "Performance Study of Multicore Digital Signal Processor Architectures." Journal of the Institute of Webcasting, Internet and Telecommunication 13, no. 4 (August 31, 2013): 171–77. http://dx.doi.org/10.7236/jiibc.2013.13.4.171.
Full textShirai, Katsuhiko, and Toshiyuki Takezawa. "Expert system for designing digital signal processor architectures." Microprocessors and Microsystems 12, no. 2 (March 1988): 83–91. http://dx.doi.org/10.1016/0141-9331(88)90046-4.
Full textShirai, K., and T. Takezawa. "Expert system for designing digital signal processor architectures." Computer-Aided Design 20, no. 7 (September 1988): 423. http://dx.doi.org/10.1016/0010-4485(88)90220-5.
Full textVehlies, Uwe. "Stepwise Transformation of Algorithms into Array Processor Architectures by the DECOMP." VLSI Design 3, no. 1 (January 1, 1995): 67–80. http://dx.doi.org/10.1155/1995/76861.
Full textBakó, László, Szabolcs Hajdú, and Fearghal Morgan. "Evaluation and Comparison of Low FPGA Footprint, Embedded Soft-Core Processors." MACRo 2015 2, no. 1 (October 1, 2017): 23–30. http://dx.doi.org/10.1515/macro-2017-0003.
Full textHasler, Jennifer. "Analog Architecture Complexity Theory Empowering Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems." Journal of Low Power Electronics and Applications 9, no. 1 (January 21, 2019): 4. http://dx.doi.org/10.3390/jlpea9010004.
Full textFahmy, M. M., and Y. Wan. "New array processor architectures for two-dimensional FIR digital filters." IEE Proceedings E Computers and Digital Techniques 136, no. 4 (1989): 234. http://dx.doi.org/10.1049/ip-e.1989.0032.
Full textLee, Jongbok. "A Performance Study of Asymmetric Multi-core Digital Signal Processor Architectures." Journal of The Institute of Internet, Broadcasting and Communication 15, no. 5 (October 31, 2015): 219–24. http://dx.doi.org/10.7236/jiibc.2015.15.5.219.
Full textPadma, Chennagiri Rajarao, and Dr K. M. Ravikumar. "Low-cost Magnetic Resonance Console Architecture using an Open Source for Laboratory Scale Systems." International Journal of Innovative Technology and Exploring Engineering 12, no. 2 (January 30, 2023): 26–32. http://dx.doi.org/10.35940/ijitee.b9413.0112223.
Full textL. M. Hassan, S., N. Sulaiman, S. S. Shariffudin, and T. N. T. Yaakub. "Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor." Bulletin of Electrical Engineering and Informatics 7, no. 2 (June 1, 2018): 230–35. http://dx.doi.org/10.11591/eei.v7i2.1167.
Full textDawwd, Shefa, and Suha Nori. "Reduced Area and Low Power Implementation of FFT/IFFT Processor." Iraqi Journal for Electrical and Electronic Engineering 14, no. 2 (December 1, 2018): 108–19. http://dx.doi.org/10.37917/ijeee.14.2.3.
Full textLarrabee, Allan R. "The P4 Parallel Programming System, the Linda Environment, and Some Experiences with Parallel Computation." Scientific Programming 2, no. 3 (1993): 23–35. http://dx.doi.org/10.1155/1993/817634.
Full textVASSILIADIS, STAMATIS, GERALD G. PECHANEK, and JOSÉ G. DELGADO-FRIAS. "SPIN: THE SEQUENTIAL PIPELINED NEUROEMULATOR." International Journal on Artificial Intelligence Tools 02, no. 01 (March 1993): 117–32. http://dx.doi.org/10.1142/s0218213093000084.
Full textSchneider, M., H. Blume, and T. G. Noll. "Power estimation on functional level for programmable processors." Advances in Radio Science 2 (May 27, 2005): 215–19. http://dx.doi.org/10.5194/ars-2-215-2004.
Full textKhan, Burhan Khalid. "A High-Performance On-Chip Memory Module for Image Processing Applications." International Journal for Research in Applied Science and Engineering Technology 10, no. 2 (February 28, 2022): 146–56. http://dx.doi.org/10.22214/ijraset.2022.40178.
Full textShakor Moghee, Hussein. "A New Technology for Reducing Power Consumption in Synchronous Digital Design Using Tri-State Buffer." Diyala Journal of Engineering Sciences 11, no. 2 (June 1, 2018): 60–66. http://dx.doi.org/10.24237/djes.2018.11208.
Full textKonguvel, Elango, and Muniandi Kannan. "A Survey on FFT/IFFT Processors for Next Generation Telecommunication Systems." Journal of Circuits, Systems and Computers 27, no. 03 (October 30, 2017): 1830001. http://dx.doi.org/10.1142/s0218126618300015.
Full textKondapalli, Soumya, Arjuna Madanayake, and Len Bruton. "Digital Architectures for UWB Beamforming Using 2D IIR Spatio-Temporal Frequency-Planar Filters." International Journal of Antennas and Propagation 2012 (2012): 1–19. http://dx.doi.org/10.1155/2012/234263.
Full textZafra, Eduardo, Sergio Vazquez, Hipolito Guzman Miranda, Juan A. Sanchez, Abraham Marquez, Jose I. Leon, and Leopoldo G. Franquelo. "Efficient FPSoC Prototyping of FCS-MPC for Three-Phase Voltage Source Inverters." Energies 13, no. 5 (March 1, 2020): 1074. http://dx.doi.org/10.3390/en13051074.
Full textMeena, Nitish, and Nilesh Parihar. "Real-Time Algorithms and Architectures for several user Channel Detection in Wireless Base Station Receivers." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 2 (July 1, 2015): 82. http://dx.doi.org/10.11591/ijres.v4.i2.pp82-98.
Full textNARAYANAN, P. J., and LARRY S. DAVIS. "REPLICATED IMAGE ALGORITHMS AND THEIR ANALYSES ON SIMD MACHINES." International Journal of Pattern Recognition and Artificial Intelligence 06, no. 02n03 (August 1992): 335–52. http://dx.doi.org/10.1142/s0218001492000217.
Full textFeldkaemper, H. T., H. Blume, and T. G. Noll. "Study of heterogeneous and reconfigurable architectures in the communication domain." Advances in Radio Science 1 (May 5, 2003): 165–69. http://dx.doi.org/10.5194/ars-1-165-2003.
Full textSideris, Argyrios, Theodora Sanida, and Minas Dasygenis. "High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor." Technologies 8, no. 1 (February 10, 2020): 15. http://dx.doi.org/10.3390/technologies8010015.
Full textTrunov, Artem S., Vyacheslav I. Voronov, and Lilia I. Voronova. "Integration of legacy applications into "Eni" scientific research ecosystem." T-Comm 14, no. 8 (2020): 33–41. http://dx.doi.org/10.36724/2072-8735-2020-14-8-33-41.
Full textSolomon, Merrin Mary, Neeraj Gupta, and Rashmi Gupta. "HIGH SPEED ADDER USING GDI TECHNIQUE." International Journal of Engineering Technologies and Management Research 5, no. 2 (April 30, 2020): 130–36. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.634.
Full textDahnoun, N., and J. Brand. "Teaching DSP Implementation: The Big Picture." International Journal of Electrical Engineering & Education 49, no. 3 (July 2012): 202–9. http://dx.doi.org/10.7227/ijeee.49.3.2.
Full textIslam, Md Mainul, Md Selim Hossain, Moh Khalid Hasan, Md Shahjalal, and Yeong Min Jang. "Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve." Sensors 20, no. 18 (September 10, 2020): 5148. http://dx.doi.org/10.3390/s20185148.
Full textPOPLI, SANJAY P., MAGDY A. BAYOUMI, and AKASH TYAGI. "A RECONFIGURATION TECHNIQUE FOR RELIABLE VLSI DSP ARRAY PROCESSORS." Journal of Circuits, Systems and Computers 02, no. 03 (September 1992): 281–304. http://dx.doi.org/10.1142/s0218126692000180.
Full textWei, Wei, Dexiang Deng, Lin Zeng, Chen Zhang, and Wenxuan Shi. "Classification of foreign fibers using deep learning and its implementation on embedded system." International Journal of Advanced Robotic Systems 16, no. 4 (July 2019): 172988141986760. http://dx.doi.org/10.1177/1729881419867600.
Full textGrout, Ian Andrew, and Lenore Mullin. "Realizing Mathematics of Arrays Operations as Custom Architecture Hardware-Software Co-Design Solutions." Information 13, no. 11 (November 4, 2022): 528. http://dx.doi.org/10.3390/info13110528.
Full textSingh, Pankaj Kumar. "Performance Analysis of Associate Radix-2, Radix- 4 and Radix-8 based FFT using Folding Technique." International Journal for Research in Applied Science and Engineering Technology 9, no. 10 (October 31, 2021): 1489–94. http://dx.doi.org/10.22214/ijraset.2021.38649.
Full textMartínez Ramírez, Marco A., Emmanouil Benetos, and Joshua D. Reiss. "Deep Learning for Black-Box Modeling of Audio Effects." Applied Sciences 10, no. 2 (January 16, 2020): 638. http://dx.doi.org/10.3390/app10020638.
Full textLubaszewski, Marcelo, and Marcelo Antonio Pavanello. "Table of Contents and Foreword." Journal of Integrated Circuits and Systems 7, no. 1 (December 27, 2012): 1–6. http://dx.doi.org/10.29292/jics.v7i1.350.
Full textUngerboeck, G., D. Maiwald, H. P. Kaeser, P. R. Chevillat, and J. P. Beraud. "Architecture of a digital signal processor." IBM Journal of Research and Development 29, no. 2 (March 1985): 132–39. http://dx.doi.org/10.1147/rd.292.0132.
Full textVENKATESWARAN, N., S. PATTABIRAMAN, R. DEVANATHAN, B. KUMARAN, ASHRAF AHMED, and SANKARA NARAYANAN. "A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS—PART 1: GIPOP PROCESSOR ARRAY." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (April 1995): 231–62. http://dx.doi.org/10.1142/s0218001495000122.
Full textMego, Roman, and Tomas Fryza. "Instruction mapping techniques for processors with very long instruction word architectures." Journal of Electrical Engineering 73, no. 6 (December 1, 2022): 387–95. http://dx.doi.org/10.2478/jee-2022-0053.
Full textKumar, Sandeep, Munish Verma, Vijay K. Lamba, Susheel Kumar, and Avinash Mehta. "IMPLEMENTATION AND ANALYSIS OF FIR FILTER USING TMS 320C6713 DSK." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 3, no. 2 (October 30, 2012): 266–70. http://dx.doi.org/10.24297/ijct.v3i2b.2873.
Full textGabrielli, A., and E. Gandolfi. "A fast digital fuzzy processor." IEEE Micro 19, no. 1 (1999): 68–79. http://dx.doi.org/10.1109/40.748798.
Full textMandolesi, P. S., P. Julian, and A. G. Andreou. "A Scalable and Programmable Simplicial CNN Digital Pixel Processor Architecture." IEEE Transactions on Circuits and Systems I: Regular Papers 51, no. 5 (May 2004): 988–96. http://dx.doi.org/10.1109/tcsi.2004.827626.
Full textAono, K., M. Toyokura, T. Araki, A. Ohtani, H. Kodama, and K. Okamoto. "A video digital signal processor with a vector-pipeline architecture." IEEE Journal of Solid-State Circuits 27, no. 12 (1992): 1886–94. http://dx.doi.org/10.1109/4.173119.
Full textWalravens, Cedric, and Wim Dehaene. "Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 2 (February 2014): 313–21. http://dx.doi.org/10.1109/tvlsi.2013.2238645.
Full textKENNEDY, MICHAEL PETER, CHAI WAH WU, STANLEY PAU, and JAMES TOW. "DIGITAL SIGNAL PROCESSOR-BASED INVESTIGATION OF CHUA'S CIRCUIT FAMILY." Journal of Circuits, Systems and Computers 03, no. 02 (June 1993): 269–92. http://dx.doi.org/10.1142/s0218126693000204.
Full textKloker, Kevin. "The Motorola DSP56000 Digital Signal Processor." IEEE Micro 6, no. 6 (December 1986): 29–48. http://dx.doi.org/10.1109/mm.1986.304807.
Full textBeaumont-Smith, A., M. Liebelt, C. C. Lim, K. To, and W. Marwood. "Digital signal multi-processor for matrix applications." Computer Standards & Interfaces 20, no. 6-7 (March 1999): 439. http://dx.doi.org/10.1016/s0920-5489(99)90897-8.
Full textBattilotti, S., and G. Ulivi. "An architecture for high performance control using digital signal processor chips." IEEE Control Systems Magazine 10, no. 6 (October 1990): 20–23. http://dx.doi.org/10.1109/37.60447.
Full textDasiewicz, P., P. F. Corbett, and R. E. Seviora. "A VLSI architecture for the Central Processor of a digital switch." Microprocessing and Microprogramming 18, no. 1-5 (December 1986): 591–95. http://dx.doi.org/10.1016/0165-6074(86)90095-5.
Full textTarasov, I. E., D. S. Potekhin, and O. V. Platonova. "Prospects for using soft processors in systems-on-a-chip based on field-programmable gate arrays." Russian Technological Journal 10, no. 3 (June 8, 2022): 24–33. http://dx.doi.org/10.32362/2500-316x-2022-10-3-24-33.
Full textShen, Zheng, Hu He, Yanjun Zhang, and Yihe Sun. "A Video Specific Instruction Set Architecture for ASIP design." VLSI Design 2007 (November 15, 2007): 1–7. http://dx.doi.org/10.1155/2007/58431.
Full textChance, Jim. "TMS320 digital signal processor development system." Microprocessors and Microsystems 9, no. 2 (March 1985): 50–56. http://dx.doi.org/10.1016/0141-9331(85)90414-4.
Full textTseng, Chien Hsun. "Analysis of Parallel Multidimensional Wave Digital Filtering Network on IBM Cell Broadband Engine." Journal of Computational Engineering 2014 (February 17, 2014): 1–13. http://dx.doi.org/10.1155/2014/793635.
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