Journal articles: 'Digital processor architectures'

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Lee, Jongbok. "Performance Study of Multicore Digital Signal Processor Architectures." Journal of the Institute of Webcasting, Internet and Telecommunication 13, no. 4 (August 31, 2013): 171–77. http://dx.doi.org/10.7236/jiibc.2013.13.4.171.

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Shirai, Katsuhiko, and Toshiyuki Takezawa. "Expert system for designing digital signal processor architectures." Microprocessors and Microsystems 12, no. 2 (March 1988): 83–91. http://dx.doi.org/10.1016/0141-9331(88)90046-4.

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Shirai, K., and T. Takezawa. "Expert system for designing digital signal processor architectures." Computer-Aided Design 20, no. 7 (September 1988): 423. http://dx.doi.org/10.1016/0010-4485(88)90220-5.

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Vehlies, Uwe. "Stepwise Transformation of Algorithms into Array Processor Architectures by the DECOMP." VLSI Design 3, no. 1 (January 1, 1995): 67–80. http://dx.doi.org/10.1155/1995/76861.

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A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers the complete design flow from algorithmic specifications in a high-level programming language to architecture descriptions in a hardware description language. The transformation itself is divided into manageable design steps and implemented in the CAD-tool DECOMP which allows the exploration of different architectures in a short time. With the presented approach data independent algorithms can be mapped onto array processor architectures. To allow this, a known mapping methodology for array processor design is extended to handle inhomogeneous dependence graphs with nonregular data dependences. The implementation of the formal approach in the DECOMP is an important step towards design automation for massively parallel systems.

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Bakó, László, Szabolcs Hajdú, and Fearghal Morgan. "Evaluation and Comparison of Low FPGA Footprint, Embedded Soft-Core Processors." MACRo 2015 2, no. 1 (October 1, 2017): 23–30. http://dx.doi.org/10.1515/macro-2017-0003.

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AbstractThe paper presents three embedded soft-core processor architectures, developed by the authors to be easily implementable while yielding low digital resource usage. These architectures will be compared and contrasted between each-other by introducing a special testing method, based on control algorithm implementations. For reference, the same testing and comparison has been implemented on a well established architecture, too, on the Xilinx PicoBlaze processor. Measurement results and application suggestion are given in the concluding section.

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Hasler, Jennifer. "Analog Architecture Complexity Theory Empowering Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems." Journal of Low Power Electronics and Applications 9, no. 1 (January 21, 2019): 4. http://dx.doi.org/10.3390/jlpea9010004.

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This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption. As in digital systems, a strong architecture theory, based on experimental results, is essential for these opportunities. The recent availability of programmable and configurable analog technologies, as well as the start of analog numerical analysis, makes considering scaling of analog computation more than a purely theoretical interest. Although some aspects nicely parallel digital architecture concepts, analog architecture theory requires revisiting some of the foundations of parallel digital architectures, particularly revisiting structures where communication and memory access, instead of processor operations, that dominates complexity. This discussion shows multiple system examples from Analog-to-Digital Converters (ADC) to Vector-Matrix Multiplication (VMM), adaptive filters, image processing, sorting, and other computing directions.

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Fahmy, M. M., and Y. Wan. "New array processor architectures for two-dimensional FIR digital filters." IEE Proceedings E Computers and Digital Techniques 136, no. 4 (1989): 234. http://dx.doi.org/10.1049/ip-e.1989.0032.

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Lee, Jongbok. "A Performance Study of Asymmetric Multi-core Digital Signal Processor Architectures." Journal of The Institute of Internet, Broadcasting and Communication 15, no. 5 (October 31, 2015): 219–24. http://dx.doi.org/10.7236/jiibc.2015.15.5.219.

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Padma, Chennagiri Rajarao, and Dr K. M. Ravikumar. "Low-cost Magnetic Resonance Console Architecture using an Open Source for Laboratory Scale Systems." International Journal of Innovative Technology and Exploring Engineering 12, no. 2 (January 30, 2023): 26–32. http://dx.doi.org/10.35940/ijitee.b9413.0112223.

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MRI systems with proprietary hardware must use pulse programming, which is less expensive. Pulse programming consoles use Digital Signal Processor, Complex Programming Logic Device, and microcontrollers, which are typically restricted to particular architectures. General–purpose, extremely affordable electronics board featuring these architectures are now capable enough to be directly implemented in MRI consoles. Here we present the architectural details of various consoles with novel designs and their limitations. Finally, we propose a console design which was created utilising widely accessible Arduino Boards to connect to Pulseq-GPI implementations at a reduced cost of $225

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L. M. Hassan, S., N. Sulaiman, S. S. Shariffudin, and T. N. T. Yaakub. "Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor." Bulletin of Electrical Engineering and Informatics 7, no. 2 (June 1, 2018): 230–35. http://dx.doi.org/10.11591/eei.v7i2.1167.

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Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.

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Dawwd, Shefa, and Suha Nori. "Reduced Area and Low Power Implementation of FFT/IFFT Processor." Iraqi Journal for Electrical and Electronic Engineering 14, no. 2 (December 1, 2018): 108–19. http://dx.doi.org/10.37917/ijeee.14.2.3.

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The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.

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Larrabee, Allan R. "The P4 Parallel Programming System, the Linda Environment, and Some Experiences with Parallel Computation." Scientific Programming 2, no. 3 (1993): 23–35. http://dx.doi.org/10.1155/1993/817634.

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The first digital computers consisted of a single processor acting on a single stream of data. In this so-called "von Neumann" architecture, computation speed is limited mainly by the time required to transfer data between the processor and memory. This limiting factor has been referred to as the "von Neumann bottleneck". The concern that the miniaturization of silicon-based integrated circuits will soon reach theoretical limits of size and gate times has led to increased interest in parallel architectures and also spurred research into alternatives to silicon-based implementations of processors. Meanwhile, sequential processors continue to be produced that have increased clock rates and an increase in memory locally available to a processor, and an increase in the rate at which data can be transferred to and from memories, networks, and remote storage. The efficiency of compilers and operating systems is also improving over time. Although such characteristics limit maximum performance, a large improvement in the speed of scientific computations can often be achieved by utilizing more efficient algorithms, particularly those that support parallel computation. This work discusses experiences with two tools for large grain (or "macro task") parallelism.

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VASSILIADIS, STAMATIS, GERALD G. PECHANEK, and JOSÉ G. DELGADO-FRIAS. "SPIN: THE SEQUENTIAL PIPELINED NEUROEMULATOR." International Journal on Artificial Intelligence Tools 02, no. 01 (March 1993): 117–32. http://dx.doi.org/10.1142/s0218213093000084.

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This paper proposes a novel digital neural network architecture referred to as the Sequential PIpelined Neuroemulator or Neurocomputer (SPIN). The SPIN processor emulates neural networks producing high performance with minimum hardware by sequentially processing each neuron in the modeled completely connected network with a pipelined physical neuron structure. In addition to describing SPIN, performance equations are estimated for the ring systolic, the recurrent systolic array, and the neuromimetic neurocomputer architectures, three previously reported schemes for the emulation of neural networks, and a comparison with the SPIN architecture is reported.

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Schneider, M., H. Blume, and T. G. Noll. "Power estimation on functional level for programmable processors." Advances in Radio Science 2 (May 27, 2005): 215–19. http://dx.doi.org/10.5194/ars-2-215-2004.

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Abstract. In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW)-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA). Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW) -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA). This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated the input parameters of the Correspondence to: H. Blume (blume@eecs.rwth-aachen.de) arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. This approach is exemplarily demonstrated and evaluated applying two modern digital signal processors and a variety of basic algorithms of digital signal processing. The resulting estimation values for the inspected algorithms are compared to physically measured values. A resulting maximum estimation error of 3% is achieved.

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Khan, Burhan Khalid. "A High-Performance On-Chip Memory Module for Image Processing Applications." International Journal for Research in Applied Science and Engineering Technology 10, no. 2 (February 28, 2022): 146–56. http://dx.doi.org/10.22214/ijraset.2022.40178.

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Abstract: To actualize numerous image processing applications, today's technology revolution in portable electronic devices necessitates significant amounts of data processing power, area, and time. Approximate data computing has been demonstrated to be a viable solution for picture processing. In real-time digital data computing applications, achieving high precision or fulfilling a variable accuracy requirement of up to 100 percent has become a crucial design goal. As a result, very large-scale integration (VLSI) architectures with excellent performance are critical in the design of digital signal processors. The use of high-performance adders and on-chip memory structures has also been a focus of recent breakthroughs in processor design Stability and dependability are crucial design factors that contribute to a reduction in worst-case error and the use of a hybrid application in real time. High precision, high speed, low power, and area efficiency are achieved by balancing the restrictions of high performance. The processor core's performance is determined by the configuration, design parameters, and efficient use of the data channel and on-chip memory structures. As a result, high-performance adders and on-chip memory architecture were used in this study. To provide superior quantitative computation for human perception, the suggested design is included into image processing applications such as image approximation, canny edge detection, and noise reduction approaches. Berkeley, medical, and satellite image samples were used..

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Shakor Moghee, Hussein. "A New Technology for Reducing Power Consumption in Synchronous Digital Design Using Tri-State Buffer." Diyala Journal of Engineering Sciences 11, no. 2 (June 1, 2018): 60–66. http://dx.doi.org/10.24237/djes.2018.11208.

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This research paper deals with design and implementation of low power 8-bit arithmetic logic units. The main part of power consumption is consumed in ALU in any processor. Therefore, reducing power dissipation in ALU should be requiring. The proposed technique disabled one of the main block of ALU using tri-state logic which is not necessary to use, except the required processes. In this work, the suggested design is realized by using ASIC methodologies. In order to implement the arithmetic and logic architectures, 130 nm standard cell libraries are used for ASIC execution. The architecture of the design has been created using Verilog HDL language. In addition, it is simulated using ModelSim-Altera 10.3c (Quartus II 14.1) tools. By using tri-state technique, dynamic power and total power are decreased

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Konguvel, Elango, and Muniandi Kannan. "A Survey on FFT/IFFT Processors for Next Generation Telecommunication Systems." Journal of Circuits, Systems and Computers 27, no. 03 (October 30, 2017): 1830001. http://dx.doi.org/10.1142/s0218126618300015.

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The Fast Fourier Transform and Inverse Fast Fourier Transform (FFT/IFFT) are the most significant digital signal processing (DSP) techniques used in Orthogonal Frequency Division Multiplexing (OFDM)-based applications which include day-to-day wired/wireless communications, broadband access, and information sharing. The advancements in telecommunication technologies require an efficient FFT/IFFT processing device to meet the necessary specifications which depend on the particular application. A real-time implementation of high-speed FFT/IFFT processor with less area that operates in minimal power consumption is essential in designing an OFDM integrated chip. A comparative study of efficient algorithms and architectures for FFT chip design is presented in this paper. It is also recommended that mixed-radix/higher-radix algorithm combined with Single-path Delay Commutator (SDC) architecture is appropriate for massive MIMO in 5G, optical OFDM, cooperative MIMO and multi-user MIMO-based applications.

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Kondapalli, Soumya, Arjuna Madanayake, and Len Bruton. "Digital Architectures for UWB Beamforming Using 2D IIR Spatio-Temporal Frequency-Planar Filters." International Journal of Antennas and Propagation 2012 (2012): 1–19. http://dx.doi.org/10.1155/2012/234263.

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A design method and an FPGA-based prototype implementation of massively parallel systolic-array VLSI architectures for 2nd-order and 3rd-order frequency-planar beam plane-wave filters are proposed. Frequency-planar beamforming enables highly-directional UWB RF beams at low computational complexity compared to digital phased-array feed techniques. The array factors of the proposed realizations are simulated and both high-directional selectivity and UWB performance are demonstrated. The proposed architectures operate using 2's complement finite precision digital arithmetic. The real-time throughput is maximized using look-ahead optimization applied locally to each processor in the proposed massively-parallel realization of the filter. From sensitivity theory, it is shown that 15 and 19-bit precision for filter coefficients results in better than 3% error for 2nd- and 3rd-order beam filters. Folding together with Ktimes multiplexing is applied to the proposed beam architectures such that throughput can be traded forK-fold lower complexity for realizing the 2-D fan filter banks. Prototype FPGA circuit implementations of these filters are proposed using a Virtex 6 xc6vsx475t-2ff1759 device. The FPGA-prototyped architectures are evaluated using area (A), critical path delay (T), and metricsATandAT2. TheL2error energy is used as a metric for evaluating fixed-point noise levels and the accuracy of the finite precision digital arithmetic circuits.

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Zafra, Eduardo, Sergio Vazquez, Hipolito Guzman Miranda, Juan A. Sanchez, Abraham Marquez, Jose I. Leon, and Leopoldo G. Franquelo. "Efficient FPSoC Prototyping of FCS-MPC for Three-Phase Voltage Source Inverters." Energies 13, no. 5 (March 1, 2020): 1074. http://dx.doi.org/10.3390/en13051074.

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This work describes an efficient implementation in terms of computation time and resource usage in a Field-Programmable System-On-Chip (FPSoC) of a Finite Control Set Model Predictive Control (FCS-MPC) algorithm. As an example, the FCS-MPC implementation is used for the current reference tracking of a two-level three-phase power converter. The proposed solution is an enabler for using both complex control algorithms and digital controllers for high switching frequency semiconductor technologies. An original HW/SW (hardware and software) system architecture for an FPSoC is designed to take advantage of a modern operating system, while removing time uncertainty in real-time software tasks, and exploiting dedicated FPGA fabric for the most complex computations. In addition, two different architectures for the FPGA-implemented functionality are proposed and compared in order to study the area-speed trade-off. Experimental results show the feasibility of the proposed implementation, which achieves a speed hundreds of times faster than the conventional Digital Signal Processor (DSP)-based control platform.

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Meena, Nitish, and Nilesh Parihar. "Real-Time Algorithms and Architectures for several user Channel Detection in Wireless Base Station Receivers." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 2 (July 1, 2015): 82. http://dx.doi.org/10.11591/ijres.v4.i2.pp82-98.

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In this paper presents algorithms and architecture designs that can meet real-time requirements of for several user channel estimation and detection in code-division multiple-access-based wireless base-station receivers. Entangled algorithms proposed to implement several user channel assessment and demodulation make their real-time execution difficult on current digital signal processor-based receivers. A based several user channel assessment scheme requiring matrix conversion is draft again from an demodulation perspective for a reduced intricacy, repetitive scheme with a simple fixed-point very large scale integration architecture. A reduced-intricacy, bit-streaming several user demodulation algorithm that avoids the need for demodulation is also developed for a simple, pipelined VLSI architecture. Thus, we develop real-time solutions for several user channel assessment and demodulation for third-generation wireless systems by: 1) designing the algorithms from a fixed-point execution perspective, without significant loss in error rate performance; 2) task partitioning; and 3) designing bit-streaming fixed-point VLSI architectures that explore pipelining, correspondence, and bit-level computations to achieve real-time with minimum area overhead.

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NARAYANAN, P. J., and LARRY S. DAVIS. "REPLICATED IMAGE ALGORITHMS AND THEIR ANALYSES ON SIMD MACHINES." International Journal of Pattern Recognition and Artificial Intelligence 06, no. 02n03 (August 1992): 335–52. http://dx.doi.org/10.1142/s0218001492000217.

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Data parallel processing on processor array architectures has gained popularity in data intensive applications, such as image processing and scientific computing, as massively parallel processor array machines became feasible commercially. The data parallel paradigm of assigning one processing element to each data element results in an inefficient utilization of a large processor array when a relatively small data structure is processed on it. The large degree of parallelism of a massively parallel processor array machine does not result in a faster solution to a problem involving relatively small data structures than the modest degree of parallelism of a machine that is just as large as the data structure. We presented data replication technique to speed up the processing of small data structures on large processor arrays. In this paper, we present replicated data algorithms for digital image convolutions and median filtering, and compare their performance with conventional data parallel algorithms for the same on three popular array interconnection networks, namely, the 2-D mesh, the 3-D mesh, and the hypercube.

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Feldkaemper, H. T., H. Blume, and T. G. Noll. "Study of heterogeneous and reconfigurable architectures in the communication domain." Advances in Radio Science 1 (May 5, 2003): 165–69. http://dx.doi.org/10.5194/ars-1-165-2003.

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Abstract. One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an appropriate trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future communication systems include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. These will be integrated as a System-on-Chip (SoC). For such a heterogeneous architecture a design space exploration and an appropriate partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. A factor of about seven orders of magnitude spans between a physically optimised implementation and an implementation on a programmable DSP kernel. An implementation on an embedded FPGA kernel is in between these two representing an attractive compromise with high flexibility and low power consumption. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for the appropriate partitioning of heterogeneous systems.

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Sideris, Argyrios, Theodora Sanida, and Minas Dasygenis. "High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor." Technologies 8, no. 1 (February 10, 2020): 15. http://dx.doi.org/10.3390/technologies8010015.

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Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak algorithm is the winner of the NIST competition for the adoption of the new standard SHA-3 hash algorithm. In this work, we present hardware throughput optimization techniques for the SHA-3 algorithm using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) programming language for all output lengths in the Keccak hash function (224, 256, 384 and 512). Our experiments were performed with the Nios II processor on the FPGA Arria 10 GX (10AX115N2P45E1SG). We applied two architectures, one without custom instruction and one with floating point hardware 2. Finally, we compare the results with other existing similar designs and found that the proposed design with floating point 2 optimizes throughput (Gbps) compared to existing FPGA implementations.

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Trunov, Artem S., Vyacheslav I. Voronov, and Lilia I. Voronova. "Integration of legacy applications into "Eni" scientific research ecosystem." T-Comm 14, no. 8 (2020): 33–41. http://dx.doi.org/10.36724/2072-8735-2020-14-8-33-41.

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The article describes the development of a digital platform for the Eni research ecosystem, based on a microservice approach that automatically scales the computing resources of the system when working with big data. A brief description of the structure of the digital platform, its main components and the functionality of the basic subsystems is provided. Two types of digital platform consumers are presented - legacy and platform applications. Their capabilities and limitations are shown. The subsystem of distributed computing is described, which provides continuous management and monitoring of the microservice architecture of the platform, in particular, it is responsible for: load balancing, service discovery, system recovery after failures, end-to-end authentication, "canary rollouts", access control. The high-performance computing subsystem is presented. It includes models and methods for organizing parallel calculations on various hardware devices, such as a multiprocessor system, a cluster of computing devices connected by a local network, and a graphics processor. As software solutions for organizing parallel computing, multithreaded data processing technologies, MPI messaging interface, and CUDA technology are used. Also described is a data mining subsystem designed to deploy different types of neural networks with different architectures, including direct distribution, convolutional, recurrent and generative neural networks. The integration of the legacy application MD-SLAG-MELT v13.0 into the ecosystem of scientific research using platform integration adapters is presented. The architectures and the main components of the original software package and the integrated software package MD-SLAG-MELT v14.0 are presented. The results of load testing with the analysis of performance metrics and response time of an inherited application, when processing big data, are presented.

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Solomon, Merrin Mary, Neeraj Gupta, and Rashmi Gupta. "HIGH SPEED ADDER USING GDI TECHNIQUE." International Journal of Engineering Technologies and Management Research 5, no. 2 (April 30, 2020): 130–36. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.634.

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Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.

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Dahnoun, N., and J. Brand. "Teaching DSP Implementation: The Big Picture." International Journal of Electrical Engineering & Education 49, no. 3 (July 2012): 202–9. http://dx.doi.org/10.7227/ijeee.49.3.2.

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Starting a digital signal processing (DSP) implementation course can be a daunting task, especially with the advanced DSP algorithms, complex DSP processor architectures and sophisticated development tools that are developed to satisfy consumer demands. These courses can be split into disciplines such as control, audio and video. In this paper the authors are addressing the concerns associated with fast-growing DSP chips and tools and the impact they have on teaching DSP implementation. The authors also provide solutions, advice and suggestions on how to select a DSP, set a DSP implementation course and the associated laboratory hardware and software that fit a specific application.

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Islam, Md Mainul, Md Selim Hossain, Moh Khalid Hasan, Md Shahjalal, and Yeong Min Jang. "Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve." Sensors 20, no. 18 (September 10, 2020): 5148. http://dx.doi.org/10.3390/s20185148.

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With the swift evolution of wireless technologies, the demand for the Internet of Things (IoT) security is rising immensely. Elliptic curve cryptography (ECC) provides an attractive solution to fulfill this demand. In recent years, Edwards curves have gained widespread acceptance in digital signatures and ECC due to their faster group operations and higher resistance against side-channel attacks (SCAs) than that of the Weierstrass form of elliptic curves. In this paper, we propose a high-speed, low-area, simple power analysis (SPA)-resistant field-programmable gate array (FPGA) implementation of ECC processor with unified point addition on a twisted Edwards curve, namely Edwards25519. Efficient hardware architectures for modular multiplication, modular inversion, unified point addition, and elliptic curve point multiplication (ECPM) are proposed. To reduce the computational complexity of ECPM, the ECPM scheme is designed in projective coordinates instead of affine coordinates. The proposed ECC processor performs 256-bit point multiplication over a prime field in 198,715 clock cycles and takes 1.9 ms with a throughput of 134.5 kbps, occupying only 6543 slices on Xilinx Virtex-7 FPGA platform. It supports high-speed public-key generation using fewer hardware resources without compromising the security level, which is a challenging requirement for IoT security.

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POPLI, SANJAY P., MAGDY A. BAYOUMI, and AKASH TYAGI. "A RECONFIGURATION TECHNIQUE FOR RELIABLE VLSI DSP ARRAY PROCESSORS." Journal of Circuits, Systems and Computers 02, no. 03 (September 1992): 281–304. http://dx.doi.org/10.1142/s0218126692000180.

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Real-time digital signal processing (DSP) applications require high performance parallel architectures that are also reliable. VLSI arrays are good candidates for providing the required high throughput for these applications. These arrays which consist of a number of regularly interconnected processing elements (PEs) will not function correctly in the presence of even a single fault in any of the PEs. Fault tolerance has therefore become a vital design criterion for VLSI arrays. In this paper, a fault tolerance strategy for VLSI arrays is proposed, which significantly improves the reliability of the system. The fault tolerance scheme is composed of two phases: testing and locating faults (fault detection and diagnosis), and reconfiguration. The first phase employs an on-line error detection technique which achieves a compromise between the space and time redundancy approaches. This concurrent error detection technique reduces the rollback time considerably. The reconfiguration phase is achieved by using a global control responsible for changing the states of the switches in the interconnection network. Backtracking is introduced into the algorithm for maximizing the processor utilization, at the same time keeping the complexity of the interconnection network as simple as possible. Finally, a reliability analysis of this scheme using a Markov model and a comparison with some previous schemes are given.

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Wei, Wei, Dexiang Deng, Lin Zeng, Chen Zhang, and Wenxuan Shi. "Classification of foreign fibers using deep learning and its implementation on embedded system." International Journal of Advanced Robotic Systems 16, no. 4 (July 2019): 172988141986760. http://dx.doi.org/10.1177/1729881419867600.

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In recent years, the foreign fibers in cotton lint significantly affect the quality of the final cotton textile products. It remains a challenging task to accurately distinguish foreign fibers from cotton. This article proposes an embedded system based on field programmable gate array (FPGA) + digital signal processor (DSP) to recognize and remove foreign fibers mixed in cotton. With substantial tests of this system, we collect massive samples of foreign fibers and fake foreign fibers. Based on these samples, a convolution neural network mode is developed to validate the classification of the suspected targets from the detection subsystem, to improve the detection reliability. After training several model architectures, we find a model with the best balance between performance and computation. The high success rate (up to 96% in the validation set) demonstrates the effectiveness of the model. Moreover, the computation time (5 ms on a single image based on an eight-core DSP) indicates the efficiency of the detection, which ensures the real-time application of the system.

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Grout, Ian Andrew, and Lenore Mullin. "Realizing Mathematics of Arrays Operations as Custom Architecture Hardware-Software Co-Design Solutions." Information 13, no. 11 (November 4, 2022): 528. http://dx.doi.org/10.3390/info13110528.

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In embedded electronic system applications being developed today, complex datasets are required to be obtained, processed, and communicated. These can be from various sources such as environmental sensors, still image cameras, and video cameras. Once obtained and stored in electronic memory, the data is accessed and processed using suitable mathematical algorithms. How the data are stored, accessed, processed, and communicated will impact on the cost to process the data. Such algorithms are traditionally implemented in software programs that run on a suitable processor. However, different approaches can be considered to create the digital system architecture that would consist of the memory, processing, and communications operations. When considering the mathematics at the centre of the design making processes, this leads to system architectures that can be optimized for the required algorithm or algorithms to realize. Mathematics of Arrays (MoA) is a class of operations that supports n-dimensional array computations using array shapes and indexing of values held within the array. In this article, the concept of MoA is considered for realization in software and hardware using Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) technologies. The realization of MoA algorithms will be developed along with the design choices that would be required to map a MoA algorithm to hardware, software or hardware-software co-designs.

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Singh, Pankaj Kumar. "Performance Analysis of Associate Radix-2, Radix- 4 and Radix-8 based FFT using Folding Technique." International Journal for Research in Applied Science and Engineering Technology 9, no. 10 (October 31, 2021): 1489–94. http://dx.doi.org/10.22214/ijraset.2021.38649.

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Abstract : In recent years, as a result of advancing VLSI technology, Orthogonal Frequency Division Multiplexing (OFDM) has received a great deal of attention and has been adopted in many new generation wideband data communication systems such as IEEE 802.11a, IEEE 802.16e, HiPerLAN/2, Digital Audio/Video Broadcasting (DAB/DVB), and for 4G Radio mobile communications. This is because of its high bandwidth efficiency as the use of orthogonal waveforms with overlapping spectra. The immunity to multipath fading channel and the capability for parallel signal processing make it a promising candidate for the next generation mobile communication systems. The modulation and demodulation of OFDM based communication systems can be efficiently implemented with an FFT and IFFT, which has made the FFT valuable for those communication systems. The complexity of an OFDM system highly depends upon the computation of Fast Fourier Transform (FFT) algorithm. With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well-known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day.

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Martínez Ramírez, Marco A., Emmanouil Benetos, and Joshua D. Reiss. "Deep Learning for Black-Box Modeling of Audio Effects." Applied Sciences 10, no. 2 (January 16, 2020): 638. http://dx.doi.org/10.3390/app10020638.

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Virtual analog modeling of audio effects consists of emulating the sound of an audio processor reference device. This digital simulation is normally done by designing mathematical models of these systems. It is often difficult because it seeks to accurately model all components within the effect unit, which usually contains various nonlinearities and time-varying components. Most existing methods for audio effects modeling are either simplified or optimized to a very specific circuit or type of audio effect and cannot be efficiently translated to other types of audio effects. Recently, deep neural networks have been explored as black-box modeling strategies to solve this task, i.e., by using only input–output measurements. We analyse different state-of-the-art deep learning models based on convolutional and recurrent neural networks, feedforward WaveNet architectures and we also introduce a new model based on the combination of the aforementioned models. Through objective perceptual-based metrics and subjective listening tests we explore the performance of these models when modeling various analog audio effects. Thus, we show virtual analog models of nonlinear effects, such as a tube preamplifier; nonlinear effects with memory, such as a transistor-based limiter and nonlinear time-varying effects, such as the rotating horn and rotating woofer of a Leslie speaker cabinet.

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Lubaszewski, Marcelo, and Marcelo Antonio Pavanello. "Table of Contents and Foreword." Journal of Integrated Circuits and Systems 7, no. 1 (December 27, 2012): 1–6. http://dx.doi.org/10.29292/jics.v7i1.350.

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This issue of the Journal of Integrated Circuits and Systems (JICS) features a very broad content, including papers on analog and digital design, presenting novel solutions for circuit synthesis, energy efficiency, memory architectures and processor modeling and also proposing new approaches for wireless communication, motion estimation and neural networks applications. Six of these papers have been selected from the presentations given at SBCCI2011 (24th Symposium on Integrated Circuits and Systems Design), which has been held in João Pessoa, Brazil in 2011. Among the contributions presented at the Symposium, only a few best rated were selected by the JICS Editorial Board and have been invited to submit an extended version to the Journal. These papers have been reviewed by external experts and have been accepted for the special section on best SBCCI2011 papers. In addition to the best papers presented at the conference, one spontaneous submission passed through the usual reviewing process and has been accepted as a regular paper. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection, which guarantees the scientific level of this issue.We sincerely hope that JICS readers will enjoy these contributions.Marcelo Lubaszewski - JICS Editor-in-chief Marcelo Antonio Pavanello - JICS Co-Editor

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Ungerboeck, G., D. Maiwald, H. P. Kaeser, P. R. Chevillat, and J. P. Beraud. "Architecture of a digital signal processor." IBM Journal of Research and Development 29, no. 2 (March 1985): 132–39. http://dx.doi.org/10.1147/rd.292.0132.

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VENKATESWARAN, N., S. PATTABIRAMAN, R. DEVANATHAN, B. KUMARAN, ASHRAF AHMED, and SANKARA NARAYANAN. "A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS—PART 1: GIPOP PROCESSOR ARRAY." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (April 1995): 231–62. http://dx.doi.org/10.1142/s0218001495000122.

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Very Large Array Processors (VLAP) will be the need of the future for solving computationally intense Very Large Problems (VLP) common in pattern recognition, image processing and other related areas of digital signal processing. Design methodology of such VLAPs for massively parallel dedicated/general purpose applications is highly complex. Two companion papers (Part 1 and Part 2) on VLAP are presented in this issue. In Part 1, we propose a VLAP called Reconfigurable GIPOP Processor Array (RGPA). The RGPA is made up of high performance processing elements called the Generalized Inner Product Outer Product (GIPOP) processor. Unlike the traditional special/general purpose processors, ours has a totally different and new architecture and organization involving higher level functional units to match with the complex computational structures of numeric algorithms and suitable for massively parallel processing. We also present a strategy for mapping VLPs on VLAPs. In Part 2, we propose a novel VLSI design methodology for implementing cost effective and very high performance processors meant for special purpose applications and in particular, for VLAPs.

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Mego, Roman, and Tomas Fryza. "Instruction mapping techniques for processors with very long instruction word architectures." Journal of Electrical Engineering 73, no. 6 (December 1, 2022): 387–95. http://dx.doi.org/10.2478/jee-2022-0053.

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Abstract This paper presents an instruction mapping technique for generating a low-level assembly code for digital signal processing algorithms. This technique helps developers to implement retargetable kernel functions with the performance benefits of the low-level assembly languages. The approach is aimed at exceptionally long instruction word (VLIW) architectures, which benefits the most from the proposed method. Mapped algorithms are described by the signal-flow graphs, which are used to find possible parallel operations. The algorithm is converted into low-level code and mapped to the target architecture. This process also introduces the optimization of instruction mapping priority, which leads to the more effective code. The technique was verified on selected kernels, compared to the common programming methods, and proved that it is suitable for VLIW architectures and for portability to other systems.

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Kumar, Sandeep, Munish Verma, Vijay K. Lamba, Susheel Kumar, and Avinash Mehta. "IMPLEMENTATION AND ANALYSIS OF FIR FILTER USING TMS 320C6713 DSK." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 3, no. 2 (October 30, 2012): 266–70. http://dx.doi.org/10.24297/ijct.v3i2b.2873.

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In most of the applications, analog signals are produced in response to some physical phenomenon or activity. But it is quite difficult to process that analog signal; here comes the need to convert an analog signal to a digital signal. For this purpose specific digital signal processors (DSPâ€™s) are developed. TMS 320C6713 is one of such type of processors that can be used to process or handle the signals in a variety of ways. In the current report, basically the architecture of this processor is studied. Along with the processor architecture, the hardware portion DSK (Digital Starter Kit) and the software portion CCS (Code Composer Studio) is also studied. Digital filters are very commonly found in everyday life and include a variety of applications. Mainly they are used for two major purposes: signal separation and signal restoration. Signal separation is needed when a signal has been contaminated with interference, noise, or other signals. Signal restoration is used when a signal has been distorted in some way. So, various programs have been analyzed in this work to implement efficiently those FIR filter structures on TMS 320C6713 DSK. Characteristics of FIR filters are studied in frequency domain.

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Gabrielli, A., and E. Gandolfi. "A fast digital fuzzy processor." IEEE Micro 19, no. 1 (1999): 68–79. http://dx.doi.org/10.1109/40.748798.

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Mandolesi, P. S., P. Julian, and A. G. Andreou. "A Scalable and Programmable Simplicial CNN Digital Pixel Processor Architecture." IEEE Transactions on Circuits and Systems I: Regular Papers 51, no. 5 (May 2004): 988–96. http://dx.doi.org/10.1109/tcsi.2004.827626.

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Aono, K., M. Toyokura, T. Araki, A. Ohtani, H. Kodama, and K. Okamoto. "A video digital signal processor with a vector-pipeline architecture." IEEE Journal of Solid-State Circuits 27, no. 12 (1992): 1886–94. http://dx.doi.org/10.1109/4.173119.

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Walravens, Cedric, and Wim Dehaene. "Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 2 (February 2014): 313–21. http://dx.doi.org/10.1109/tvlsi.2013.2238645.

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KENNEDY, MICHAEL PETER, CHAI WAH WU, STANLEY PAU, and JAMES TOW. "DIGITAL SIGNAL PROCESSOR-BASED INVESTIGATION OF CHUA'S CIRCUIT FAMILY." Journal of Circuits, Systems and Computers 03, no. 02 (June 1993): 269–92. http://dx.doi.org/10.1142/s0218126693000204.

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This paper is concerned with exploiting the architecture of a single-chip digital signal processor for integrating piecewise-linear ODEs. We show that DSPs can be usefully applied in the study of Chua's circuit family provided that one chooses a multistep integration algorithm which exploits their unique single-instruction multiply-and-accumulate feature.

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Kloker, Kevin. "The Motorola DSP56000 Digital Signal Processor." IEEE Micro 6, no. 6 (December 1986): 29–48. http://dx.doi.org/10.1109/mm.1986.304807.

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Beaumont-Smith, A., M. Liebelt, C. C. Lim, K. To, and W. Marwood. "Digital signal multi-processor for matrix applications." Computer Standards & Interfaces 20, no. 6-7 (March 1999): 439. http://dx.doi.org/10.1016/s0920-5489(99)90897-8.

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Battilotti, S., and G. Ulivi. "An architecture for high performance control using digital signal processor chips." IEEE Control Systems Magazine 10, no. 6 (October 1990): 20–23. http://dx.doi.org/10.1109/37.60447.

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Dasiewicz, P., P. F. Corbett, and R. E. Seviora. "A VLSI architecture for the Central Processor of a digital switch." Microprocessing and Microprogramming 18, no. 1-5 (December 1986): 591–95. http://dx.doi.org/10.1016/0165-6074(86)90095-5.

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Tarasov, I. E., D. S. Potekhin, and O. V. Platonova. "Prospects for using soft processors in systems-on-a-chip based on field-programmable gate arrays." Russian Technological Journal 10, no. 3 (June 8, 2022): 24–33. http://dx.doi.org/10.32362/2500-316x-2022-10-3-24-33.

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Objectives. Developing the element base of field-programmable gate arrays (FPGA) may significantly affect the design of electronic devices due to the enhanced logical capacity of such chips and the general tendency towards increased subsystem integration. The system-on-a-chip (SoC) concept is aimed at combining receiving, processing, and exchange subsystems onto a single chip, as well as at implementing control, diagnostic, and other auxiliary subsystems. The study aimed at developing a method for soft processor applications, i.e., processors based on configurable logical resources, for implementing control functions in an FPGA-based SoC.Methods. A digital system design methodology was used.Results. For soft processors, a unified design route based on selecting architectural parameters qualitatively corresponding to control tasks was considered. In particular, such parameters as instruction set addressness, number of pipeline cycles, and arithmetic logic unit configuration are adjustable at the design stage to allow the optimization of the soft processor in the discrete parameter space. An approach to rapid prototyping of the assembler based on stack-oriented programming language with regular grammar was also considered. The control of digital signal processing hardware as part of an SoC is the promising application area for soft processors. An implementation is considered on the example of an SoC based on Xilinx Virtex-7 FPGA containing several processor cores developed using the proposed methodology.Conclusions. The considered approaches to soft processor design allow the rapid prototyping of the control processor core for operation as part of an FPGA-based SoC.

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Shen, Zheng, Hu He, Yanjun Zhang, and Yihe Sun. "A Video Specific Instruction Set Architecture for ASIP design." VLSI Design 2007 (November 15, 2007): 1–7. http://dx.doi.org/10.1155/2007/58431.

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This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.

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Chance, Jim. "TMS320 digital signal processor development system." Microprocessors and Microsystems 9, no. 2 (March 1985): 50–56. http://dx.doi.org/10.1016/0141-9331(85)90414-4.

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Tseng, Chien Hsun. "Analysis of Parallel Multidimensional Wave Digital Filtering Network on IBM Cell Broadband Engine." Journal of Computational Engineering 2014 (February 17, 2014): 1–13. http://dx.doi.org/10.1155/2014/793635.

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As an alternative approach for the numerical integration of physical systems, the MDWDF technique has become of importance in the field of numerical analysis due to its attractive features, for example, massive parallelism and high accuracy both inherent in nature. In this study, speed-up efficiencies of a MDWDF network are studied for the linearized shallow water system, which plays an important role in fluid dynamics. To achieve the goal, the full parallelism of the MDWDF network is established in the first place based on the chained MD retiming technique. Following the implementation on the IBM Cell Broadband Engine (Cell/BE), excellent performance of the full parallel architecture is revealed. The IBM Cell/BE containing 1 power processor element (PPE) and 8 synergistic processor elements (SPEs) perfectly fits the architecture of the retimed MDWDF model. Empirical results have demonstrated that the full parallelized model with 8 processors (1PPE + 7SPEs) outperforms the other three models: partial right/left-loop retimed models and the full sequential model with 4× improvements for scheduled grids 51×51. In addition, for scheduled fine grids 201×201, the full parallel model is shown to possess significant performance over these models by up to 7× improvements.

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Journal articles on the topic 'Digital processor architectures'

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