Relevant bibliographies by topics / Digital processor architectures

Academic literature on the topic 'Digital processor architectures'

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Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Digital processor architectures"

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Lee, Jongbok. "Performance Study of Multicore Digital Signal Processor Architectures." Journal of the Institute of Webcasting, Internet and Telecommunication 13, no. 4 (August 31, 2013): 171–77. http://dx.doi.org/10.7236/jiibc.2013.13.4.171.

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Shirai, Katsuhiko, and Toshiyuki Takezawa. "Expert system for designing digital signal processor architectures." Microprocessors and Microsystems 12, no. 2 (March 1988): 83–91. http://dx.doi.org/10.1016/0141-9331(88)90046-4.

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Shirai, K., and T. Takezawa. "Expert system for designing digital signal processor architectures." Computer-Aided Design 20, no. 7 (September 1988): 423. http://dx.doi.org/10.1016/0010-4485(88)90220-5.

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Vehlies, Uwe. "Stepwise Transformation of Algorithms into Array Processor Architectures by the DECOMP." VLSI Design 3, no. 1 (January 1, 1995): 67–80. http://dx.doi.org/10.1155/1995/76861.

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A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers the complete design flow from algorithmic specifications in a high-level programming language to architecture descriptions in a hardware description language. The transformation itself is divided into manageable design steps and implemented in the CAD-tool DECOMP which allows the exploration of different architectures in a short time. With the presented approach data independent algorithms can be mapped onto array processor architectures. To allow this, a known mapping methodology for array processor design is extended to handle inhomogeneous dependence graphs with nonregular data dependences. The implementation of the formal approach in the DECOMP is an important step towards design automation for massively parallel systems.
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Bakó, László, Szabolcs Hajdú, and Fearghal Morgan. "Evaluation and Comparison of Low FPGA Footprint, Embedded Soft-Core Processors." MACRo 2015 2, no. 1 (October 1, 2017): 23–30. http://dx.doi.org/10.1515/macro-2017-0003.

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AbstractThe paper presents three embedded soft-core processor architectures, developed by the authors to be easily implementable while yielding low digital resource usage. These architectures will be compared and contrasted between each-other by introducing a special testing method, based on control algorithm implementations. For reference, the same testing and comparison has been implemented on a well established architecture, too, on the Xilinx PicoBlaze processor. Measurement results and application suggestion are given in the concluding section.
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Hasler, Jennifer. "Analog Architecture Complexity Theory Empowering Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems." Journal of Low Power Electronics and Applications 9, no. 1 (January 21, 2019): 4. http://dx.doi.org/10.3390/jlpea9010004.

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This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption. As in digital systems, a strong architecture theory, based on experimental results, is essential for these opportunities. The recent availability of programmable and configurable analog technologies, as well as the start of analog numerical analysis, makes considering scaling of analog computation more than a purely theoretical interest. Although some aspects nicely parallel digital architecture concepts, analog architecture theory requires revisiting some of the foundations of parallel digital architectures, particularly revisiting structures where communication and memory access, instead of processor operations, that dominates complexity. This discussion shows multiple system examples from Analog-to-Digital Converters (ADC) to Vector-Matrix Multiplication (VMM), adaptive filters, image processing, sorting, and other computing directions.
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Fahmy, M. M., and Y. Wan. "New array processor architectures for two-dimensional FIR digital filters." IEE Proceedings E Computers and Digital Techniques 136, no. 4 (1989): 234. http://dx.doi.org/10.1049/ip-e.1989.0032.

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Lee, Jongbok. "A Performance Study of Asymmetric Multi-core Digital Signal Processor Architectures." Journal of The Institute of Internet, Broadcasting and Communication 15, no. 5 (October 31, 2015): 219–24. http://dx.doi.org/10.7236/jiibc.2015.15.5.219.

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Padma, Chennagiri Rajarao, and Dr K. M. Ravikumar. "Low-cost Magnetic Resonance Console Architecture using an Open Source for Laboratory Scale Systems." International Journal of Innovative Technology and Exploring Engineering 12, no. 2 (January 30, 2023): 26–32. http://dx.doi.org/10.35940/ijitee.b9413.0112223.

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MRI systems with proprietary hardware must use pulse programming, which is less expensive. Pulse programming consoles use Digital Signal Processor, Complex Programming Logic Device, and microcontrollers, which are typically restricted to particular architectures. General–purpose, extremely affordable electronics board featuring these architectures are now capable enough to be directly implemented in MRI consoles. Here we present the architectural details of various consoles with novel designs and their limitations. Finally, we propose a console design which was created utilising widely accessible Arduino Boards to connect to Pulseq-GPI implementations at a reduced cost of $225
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L. M. Hassan, S., N. Sulaiman, S. S. Shariffudin, and T. N. T. Yaakub. "Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor." Bulletin of Electrical Engineering and Informatics 7, no. 2 (June 1, 2018): 230–35. http://dx.doi.org/10.11591/eei.v7i2.1167.

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Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.
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Dissertations / Theses on the topic "Digital processor architectures"

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Omundsen, Daniel (Daniel Simon) Carleton University Dissertation Engineering Electrical. "A pipelined, multi-processor architecture for a connectionless server for broadband ISDN." Ottawa, 1992.

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Patel, Dipesh Ishwerbhai. "Architectural considerations for a control system processor." Thesis, Loughborough University, 1996. https://dspace.lboro.ac.uk/2134/11075.

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Modern design methodologies for control systems create controllers with dynamics which are of a similar order to the physical system being controlled. When these are implemented digitally as Infinite Impulse Response (HR) filters the processing requirements are extensive, in particular when high sample rates are necessary to minimise the detrimental effects of sample delay. The aim of the research was to apply signal processing techniques to facilitate the implementation of control algorithms in digital form, with the principal objective of maximising the computational efficiency, either to achieve the highest possible sample rates using a given processor, or to minimise the processor complexity for a given requirement. One of the approaches is to design a fixed point processor whose architecture is optimised to meet the computational requirements of signal processing for control, thereby maximising what can be achieved with a single processor. Hence the aim of the research was to head towards a processor architecture optimised for Control System Processing. The design of this processor is based on a unified structural form and it will be shown that controllers, represented either in state space form or as transfer functions, can be implemented using this unified structure. The structure is based on the σ-operator, which has been shown to be robust to changes in coefficients and hence require shorter coefficient wordlength to achieve a comparable performance to traditional z-operator based structures. Additionally, the σ-operator structures are also shown to have lower wordlength requirements for the internal variables. Also presented is a possible architecture for a Control System Processor and a model for the processor is developed and constructed using VHDL. This is simulated on a test bench, also designed in VHDL. The results of implementing a phase advance controller on the processor are then compared with those obtained from a MATLAB simulation.
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Vermillion, Joshua D. "The digital craftsperson : an investigation into digital tools/processes/craft." Virtual Press, 2005. http://liblink.bsu.edu/uhtbin/catkey/1318944.

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One potential role for the architect of the future will be that of the digital craftsperson. Digital technology is allowing the designer to take control of and retool the entire design I fabrication I assembly process. With this new power, architects are crafting the digital tools and processes required to make architecture for the digital age.First, this thesis examines the notion of craft in the traditional way—how it has applied to architecture and building for most of history. This story recounts the architect's role in the designing and making of architecture, from the medieval master mason to the present-day architect. Craft, it is argued, is based on an understanding and skillful application of tools and processes as they relate to designing and making.The second part of this thesis applies this definition of craft to a new set of digital skills, tools, and processes. Digital craft is a combination of the skills of the architect, augmented by computers and computer-driven machines. Designing and making with digital tools is very dependent on a feedback loop driven process centered around a digital master model, into which, design information and data is input, and direct fabrication information and representation is output.The third part of this thesis describes the digital craftsperson through three case studies. The first case study recounts the process of digital tool-making. The second, describes the development of innovative fabrication and assembly techniques using digital tools and unconventional materials. The last case study recounts the design and fabrication process of a full-scale prototype by the author and a team of students.
Department of Architecture
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Runyon, Ginger R. "Parallel processor architecture for a digital beacon receiver." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/41422.

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Singer, Jonathan Noam. "A shared bus architecture for a digital signal processor and a microcontroller." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/38810.

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Netzer, Gilbert. "Efficient LU Factorization for Texas Instruments Keystone Architecture Digital Signal Processors." Thesis, KTH, Skolan för datavetenskap och kommunikation (CSC), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-170445.

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The energy consumption of large-scale high-performance computer (HPC) systems has become one of the foremost concerns of both data-center operators and computer manufacturers. This has renewed interest in alternative computer architectures that could offer substantially better energy-efficiency.Yet, the for the evaluation of the potential of these architectures necessary well-optimized implementations of typical HPC benchmarks are often not available for these for the HPC industry novel architectures. The in this work presented LU factorization benchmark implementation aims to provide such a high-quality tool for the HPC industry standard high-performance LINPACK benchmark (HPL) for the eight-core Texas Instruments TMS320C6678 digitalsignal processor (DSP). The presented implementation could perform the LU factorization at up to 30.9 GF/s at 1.25 GHz core clock frequency by using all the eight DSP cores of the System-on-Chip (SoC). This is 77% of the attainable peak double-precision floating-point performance of the DSP, a level of efficiency that is comparable to the efficiency expected on traditional x86-based processor architectures. A presented detailed performance analysis shows that this is largely due to the optimized implementation of the embedded generalized matrix-matrix multiplication (GEMM). For this operation, the on-chip direct memory access (DMA) engines were used to transfer the necessary data from the external DDR3 memory to the core-private and shared scratchpad memory. This allowed to overlap the data transfer with computations on the DSP cores. The computations were in turn optimized by using software pipeline techniques and were partly implemented in assembly language. With these optimization the performance of the matrix multiplication reached up to 95% of attainable peak performance. A detailed description of these two key optimization techniques and their application to the LU factorization is included. Using a specially instrumented Advantech TMDXEVM6678L evaluation module, described in detail in related work, allowed to measure the SoC’s energy efficiency of up to 2.92 GF/J while executing the presented benchmark. Results from the verification of the benchmark execution using standard HPL correctness checks and an uncertainty analysis of the experimentally gathered data are also presented.
Energiförbrukningen av storskaliga högpresterande datorsystem (HPC) har blivit ett av de främsta problemen för såväl ägare av dessa system som datortillverkare. Det har lett till ett förnyat intresse för alternativa datorarkitekturer som kan vara betydligt mer effektiva ur energiförbrukningssynpunkt. För detaljerade analyser av prestanda och energiförbrukning av dessa för HPC-industrin nya arkitekturer krävs väloptimerade implementationer av standard HPC-bänkmärkningsproblem. Syftet med detta examensarbete är att tillhandhålla ett sådant högkvalitativt verktyg i form av en implementation av ett bänkmärkesprogram för LU-faktorisering för den åttakärniga digitala signalprocessorn (DSP) TMS320C6678 från Texas Instruments. Bänkmärkningsproblemet är samma som för det inom HPC-industrin välkända bänkmärket “high-performance LINPACK” (HPL). Den här presenterade implementationen nådde upp till en prestanda av 30,9 GF/s vid 1,25 GHz klockfrekvens genom att samtidigt använda alla åtta kärnor i DSP:n. Detta motsvarar 77% av den teoretiskt uppnåbara prestandan, vilket är jämförbart med förväntningar på effektivteten av mer traditionella x86-baserade system. En detaljerad prestandaanalys visar att detta tillstor del uppnås genom den högoptimerade implementationen av den ingående matris-matris-multiplikationen. Användandet av specialiserade “direct memory access” (DMA) hårdvaruenheter för kopieringen av data mellan det externa DDR3 minnet och det interna kärn-privata och delade arbetsminnet tillät att överlappa dessa operationer med beräkningar. Optimerade mjukvaruimplementationer av dessa beräkningar, delvis utförda i maskinspåk, tillät att utföra matris-multiplikationen med upp till 95% av den teoretiskt nåbara prestandan. I rapporten ges en detaljerad beskrivning av dessa två nyckeltekniker. Energiförbrukningen vid exekvering av det implementerade bänkmärket kunde med hjälp av en för ändamålet anpassad Advantech TMDXEVM6678L evalueringsmodul bestämmas till maximalt 2,92 GF/J. Resultat från verifikationen av bänkmärkesimplementationen och en uppskattning av mätosäkerheten vid de experimentella mätningarna presenteras också.
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Nascimento, Anelise Ventura. "Fronteiras permeáveis entre a arquitetura e a biologia: processos de projeto digital." Universidade de São Paulo, 2015. http://www.teses.usp.br/teses/disponiveis/102/102132/tde-31082015-155107/.

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A pesquisa visa a estudar as inter-relações1 entre os processos de projeto da arquitetura contemporânea, mediados por tecnologia computacional, e os processos da biologia, com o olhar sob os conceitos da ecologia, apoiados na teoria dos sistemas e na cibernética. As análises pretendem relacionar questões de âmbitos teórico e prático, dentro da observação dos processos de projeto, por meio das seguintes etapas: 1. Introdução e compreensão das atuais mudanças de paradigma nas áreas da biologia, ecologia e ciência da computação, que influenciam diretamente os modos de produção de informação nos processos de projeto digital em arquitetura; 2. Reflexões sobre a teoria da cibernética e sistemas complexos como costuradores dos processos biológicos aos processos de projeto de arquitetura, com implicações em emergência e inovação em arquitetura e 3. Análises práticas da integração de processos de projeto e produção digitais recorrentes das interrelações da arquitetura com a biologia.
The research aims to study the interrelationship between the contemporary architecture design processes, mediated by computer technology and the biology processes, with a view under the concepts of ecology, supported on system theory and cybernetics. The analyzes aim to relate issues on the spheres of theory and practice, within the observation of design processes, through the following steps: 1. Introduction and understanding of the current paradigm shifts in biology, ecology and computer science, which directly holds the modes of producing information in architecture digital design processes; 2. Thoughts on cybernetic theory and complex systems like links between biological processes and architectural design processes, with implications in emergence and innovation in architecture 3. Analyses of study cases about design processes and digital production integration recurrent from the interrelationship between architecture and biology.
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Alves, Gilfranco Medeiros. "Cibersemiótica e processos de projeto: metodologia em revisão." Universidade de São Paulo, 2014. http://www.teses.usp.br/teses/disponiveis/102/102132/tde-07012015-105828/.

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A tese propõe uma abordagem cibersemiótica para processos de projeto a partir da perspectiva da mediação digital e de suas relações com a arquitetura contemporânea. Apresenta uma revisão dos processos digitais de projeto, com base na constatação de que a atuação de arquitetos e designers, em função dos modos de vida contemporâneos, passa a exigir atualmente uma postura diferenciada em relação ao gerenciamento das informações, assim como uma reflexão crítica em relação ao método projetivo utilizado na arquitetura da era digital. A tese utiliza como fundamentação teórica, os principais referenciais que tratam da Cibersemiótica, conforme proposta pelo filósofo dinamarquês Søren Brier, e de suas duas bases conceituais: a Semiótica de Charles Sanders Peirce e a Cibernética de Segunda Ordem, proposta por Heinz von Foerster. A tese propõe uma estrutura (framework) para análise de projetos a partir do olhar cibersemiótico, assim como propõe também uma estrutura (framework) para os próprios processos digitais de projeto. O trabalho é dividido em duas partes. A primeira parte, aborda processos de concepção e de produção digitais e as teorias utilizadas como fundamentação. Também define o quadro contextual que compara alguns projetos selecionados no recorte proposto e propõe uma estrutura de análise cibersemiótica destas referências. A segunda parte, apresenta estratégias para projeto digitais e propõe uma estrutura cibersemiótica para processos digitais de projeto. Acredita-se que a relevância da contribuição da tese se dá na direção da expansão do paradigma teórico cibersemiótico assim como na sua capacidade de potencializar processos digitais de projeto. Se outras espacialidades e interconexões deverão surgir a partir da atualização dos níveis de comunicação estabelecidos entre os diferentes sistemas, e de novos desafios sociais e culturais, é imprescindível que os arquitetos estejam atentos à compreensão das teorias e dos processos que estão disponíveis, para a otimização de todo o seu potencial de projeto na busca por ampliar as possibilidades para a Arquitetura e Urbanismo.
The thesis explores the Cibersemiotic approach to design processes from the perspective of digital mediation and its relationship with contemporary architecture. It presents a review of existing digital design processes, based on the assumption that the practice of architects and designers, according to the contemporary modes of life, currently requires a different position in relation to the management of information, as well as a critical reflection on the design methods used in the architecture of the digital age. The thesis\' theoretical foundation is based on the Cibersimiotic work produced by the Danish philosopher Søren Brier, which unifies two important conceptual frameworks: the Semiotics by Charles Sanders Peirce and the Second Order Cybernetics proposed by Heinz von Foerster. The thesis proposes a structure (or framework) to analyze existing designs from the cibersemiotic point of view, as well as a structure (or framework) for the digital design processes themselves. The work is presented in two parts. The first examines the digital processes and production as well as the theories they are based on. This part also presents the theoretical context for the structure (or framework) used to analyse selected existing designs and introduces the framework. The second part presents strategies for digital design and proposes the cibersemiotic framework for digital design processes. It is believed the thesis contributes towards the expansion of the Cibersemiotic theoretical paradigm as well as provides a working framework for the increasingly complex processes of digital design. Assuming other spatialities and interconnections will arise from the update levels established from communication between different systems as well as new social and cultural challenges, it is essential that architects are aware of available theories and processes for optimizing design potential and expand the possibilities for Architecture and Urbanism.
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Gambarato, Roberto Rampazzo. "A linguagem do movimento na arquitetura contemporânea." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/16/16136/tde-26052010-111343/.

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Esta pesquisa caracteriza-se como um estudo de análise gráfico-conceitual acerca da importância de processos de ação criadora referenciáveis à questão do movimento por meio de formas de representação e de exploração do espaço e do tempo na Arquitetura. Aborda a questão da representação na linguagem arquitetônica, entendida como meio de relação entre tempo e espaço. Investiga como o movimento sendo uma possível síntese desta equação pode ser percebido, representado e interpretado na geração de um projeto arquitetônico. Reflete sobre a mudança de paradigmas que caracterizam a transição dos meios de representação e identifica as expressões de movimento na linguagem arquitetônica, assim como novos parâmetros de raciocínio projetual por meio da análise de projetos e métodos projetivos analógicos e digitais de arquitetos, designers e artistas. Contextualiza as manifestações de clara relação da Arquitetura com a compreensão do espaço, tempo e movimento e propõe-se como base de reflexão comparativa entre a modernidade e a contemporaneidade.
This research is characterized as a study of graphconceptual analysis concerning to the importance of processes of creative action related to the subject of the movement by means of representation forms and exploration of space and time in the Architecture. It introduces the representation in the architectural language, understood as the relationship between time and space. It investigates how the movement - being a possible synthesis of this equation - can be noticed, represented and interpreted in the generation of an architectural project. The dissertation contemplates the change of paradigms which characterize the transition of the representational methods, from analogical to digital movement expressions in the architectural language, as well as new parameters of projetual reasoning by means of the analysis of projects of architects, designers and artists. It contextualizes the manifestations of clear relationships in Architecture within the understanding of space, time and movement as a basis of comparative reflection between the modernity and the contemporaneity.
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Bednarski, Andrzej. "Integrated Optimal Code Generation for Digital Signal Processors." Doctoral thesis, Linköping : Department of Computer and Information Science, Linköpings universitet, 2006. http://www.bibl.liu.se/liupubl/disp/disp2006/tek1021s.pdf.

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Books on the topic "Digital processor architectures"

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1965-, Lapsley Phil, ed. DSP processor fundamentals: Architectures and features. New York: IEEE Press, 1997.

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Woon-Seng, Gan, ed. Digital signal processors: Architectures, implementations, and applications. Upper Saddle River, N.J: Pearson/Prentice Hall, 2005.

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A digital optical cellular image processor: Theory, architecture, and implementation. Singapore: World Scientific, 1990.

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Material strategies in digital fabrication. New York: Routledge, 2012.

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Hoffmann, Andreas. Architecture exploration for embedded processors with LISA. Boston: Kluwer Academic Publishers, 2002.

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Poppelbaum, W. J. The UNIFIELD processor: A matrix computer using strings of "ones" to represent decimals. Urbana, Ill. (1304 W. Springfield Ave., Urbana 61801): Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1986.

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International Conference on Application Specific Systems, Architectures and Processors (12th 2000 Boston, Massachusetts). IEEE International Conference on Application-Specific Systems, Architectures and Processors: Proceedings, July 10-12, 2000, Boston, Massachusetts. Los Alamitos, Calif: IEEE Computer Society Press, 2000.

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1967-, Schulte Michael Joseph, and IEEE Computer Society. Technical Committee on VLSI., eds. IEEE International Conference on Application-Specific Systems, Architectures and Processors: Proceedings : 17-19 July, 2002 ; San Jose, California. Los Alamitos, California: IEEE Computer Society, 2002.

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IEEE International Conference on Application-Specific Systems, Architectures, and Processors (16th 2005 Samos, Greece). 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors: ASAP 2005 : 23-25 July 2005, Samos, Greece. Los Alamitos, Calif: IEEE Computer Society, 2005.

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1944-, Deprettere Ed F., and IEEE Computer Society, eds. IEEE International Conference on Application-Specific Systems, Architectures and Processors: Proceedings : ASAP 2003 : 24-26 June, 2003, The Hague, The Netherlands. Los Alamitos, Calif: IEEE Computer Society, 2003.

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Book chapters on the topic "Digital processor architectures"

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Crovato, César, Delfim Torok, Regina Heidrich, Bernardo de Cerqueira, and Eduardo Velho. "A Preprocessing Algorithm to Increase OCR Performance on Application Processor-Centric FPGA Architectures." In Inclusive Smart Cities and Digital Health, 27–34. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-39601-9_3.

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Brennecke, R. "Image Processors for Digital Angiography Algorithms and Architectures." In Digital Radiography, 13–33. Boston, MA: Springer US, 1986. http://dx.doi.org/10.1007/978-1-4684-5068-2_2.

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Bonwetsch, Tobias. "Robotic Assembly Processes as a Driver in Architectural Design." In Digital Fabrication, 483–94. Basel: Springer Basel, 2012. http://dx.doi.org/10.1007/978-3-0348-0582-7_7.

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Breitfuss, D., G. Šibenik, and M. Srećković. "Digital traceability for planning processes." In ECPPM 2021 – eWork and eBusiness in Architecture, Engineering and Construction, 132–38. London: CRC Press, 2021. http://dx.doi.org/10.1201/9781003191476-18.

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Carlini, Alessandra. "Museum Education Between Digital Technologies and Unplugged Processes. Two Case Studies." In Makers at School, Educational Robotics and Innovative Learning Environments, 155–63. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-77040-2_21.

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AbstractThis document presents the results of architectural design and prototyping of educational kits within the museum context, two case studies featuring a combination of digital technologies and unplugged processes. The field of application is cultural heritage and the topics are part of school curricula. The first case study is a museum display of digital video installations and educational kits that reproduce mechanisms of symmetry from patterned flooring (“www.formulas.it” laboratory, Department of Architecture, Roma Tre University and Liceo Scientifico Cavour” high school). The second case concerns the setting up of a school fab lab in which 3D-printed prototype educational kits are made for schools and museums in Rome, in partnership with the Municipality of Rome and the Ministry of Cultural Heritage and Activities (General Directorate for Education and Research). The cases involve professional, research and didactic experiences which led to funding-supported projects. The experiences showcase good practices in informal and cooperative learning, and highlight the relationship between education and popularization that draws on our architectural heritage.
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Chiarella, Mauro, Andrés Martín-Pastor, and Nicolás Saez. "Graphic Thinking and Digital Processes: Three Built Case Studies of Digital Materiality (COCOON/Colombia, BANCAPAR/Chile, SSFS/Argentina)." In Architectural Draughtsmanship, 1033–44. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-58856-8_81.

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Jullien, G. A. "Architectures and Building Blocks for Data Stream DSP Processors." In VLSI Design Methodologies for Digital Signal Processing Architectures, 319–63. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2762-6_9.

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Tous, Rubén, Roberto García, Eva Rodríguez, and Jaime Delgado. "Architecture of a Semantic XPath Processor. Application to Digital Rights Management." In E-Commerce and Web Technologies, 1–10. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11545163_1.

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Reyserhove, Hans, and Wim Dehaene. "Near-Threshold Operation: Technology, Building Blocks and Architecture." In Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors, 17–51. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-12485-4_2.

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Stavrić, Milena, Predrag Šiđanin, and Bojan Tepavčević. "Manufacturing Scale Models & Scale Model Components: Methods And Processes." In Architectural Scale Models in the Digital Age, 123–60. Vienna: Springer Vienna, 2013. http://dx.doi.org/10.1007/978-3-7091-1448-3_5.

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Conference papers on the topic "Digital processor architectures"

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Petrov, P., and A. Orailoglu. "Customizable embedded processor architectures." In Proceedings. Euromicro Symposium on Digital System Design. IEEE, 2003. http://dx.doi.org/10.1109/dsd.2003.1231986.

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Schaffer, R., R. Merker, and F. Catthoor. "Causality constraints for processor architectures with sub-word parallelism." In Proceedings. Euromicro Symposium on Digital System Design. IEEE, 2003. http://dx.doi.org/10.1109/dsd.2003.1231904.

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Wolinski, Christophe, Krzysztof Kuchcinski, Jürgen Teich, and Frank Hannig. "Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures." In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. IEEE, 2008. http://dx.doi.org/10.1109/dsd.2008.1.

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Tulabandhula, Theja, Amit Patra, and Nirmal B. Chakrabarti. "Design of a Two Dimensional PRSI Image Processor." In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. IEEE, 2008. http://dx.doi.org/10.1109/dsd.2008.80.

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Danese, G., M. Giachero, F. Leporati, and N. Nazzicari. "A Multicore Embedded Processor for Fingerprint Recognition." In 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD). IEEE, 2010. http://dx.doi.org/10.1109/dsd.2010.101.

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Jeitler, Marcus, and Jakob Lechner. "Low Latency Recovery from Transient Faults for Pipelined Processor Architectures." In 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD). IEEE, 2010. http://dx.doi.org/10.1109/dsd.2010.87.

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Funaki, Toshimasa, and Toshinori Sato. "Formulating MITF for a Multicore Processor with SEU Tolerance." In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. IEEE, 2008. http://dx.doi.org/10.1109/dsd.2008.48.

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Kundeti, Vamsi, Yunsi Fei, and Sanguthevar Rajasekaran. "An efficient digital circuit for implementing Sequence Alignment algorithm in an extended processor." In 2008 International Conference on Application-Specific Systems, Architectures and Processors (ASAP). IEEE, 2008. http://dx.doi.org/10.1109/asap.2008.4580171.

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Antichi, Gianni, Andrea Di Pietro, Domenico Ficara, Stefano Giordano, Gregorio Procissi, and Fabio Vitucci. "Design of a High Performance Traffic Generator on Network Processor." In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. IEEE, 2008. http://dx.doi.org/10.1109/dsd.2008.36.

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Hempel, Gerald, and Christian Hochberger. "A resource optimized Processor Core for FPGA based SoCs." In 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). IEEE, 2007. http://dx.doi.org/10.1109/dsd.2007.4341449.

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Reports on the topic "Digital processor architectures"

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Bequillard, A. L., D. O. Carhoun, and W. L. Eastman. Advanced Architectures for Digital Signal Processors. Fort Belvoir, VA: Defense Technical Information Center, October 1985. http://dx.doi.org/10.21236/ada166921.

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Andrews, Michael, and David James. SBNR (Signed Binary Number Representations) Digital Signal Processor Architecture. Fort Belvoir, VA: Defense Technical Information Center, May 1987. http://dx.doi.org/10.21236/ada184603.

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Parhi, Keshab K. Design Tools and Architectures for Dedicated Digital Signal Processing (DSP) Processors. Fort Belvoir, VA: Defense Technical Information Center, July 1996. http://dx.doi.org/10.21236/ada397589.

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Urquidi, Manuel, Gloria Ortega, Víctor Arza, and Julia Ortega. New Employment Technologies: The Benefits of Implementing Services within an Enterprise Architecture Framework: Executive Summary. Inter-American Development Bank, July 2021. http://dx.doi.org/10.18235/0003403.

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Public employment services (PES) offer tools through different channels to both employers and job seekers. The multiplicity of services and channels, paired with processes that are sometimes inadequately mapped, creates challenges when implementing digital systems. This document discusses how using enterprise architecture can provide a framework for defining and representing a high-level view of the organizations processes and its information technology (IT) systems, as well as their relationship with different parts of the organization and external entities. Having a strategic vision and a high-level design allows implementing systems in phases and modules to organize services to improve their efficiency and effectiveness. This document aims to support policy makers, managers and officials working with employment policies in understanding the benefits of implementing a comprehensive digital transformation in institutions within the framework of a strategic tool such as enterprise architecture.
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INNOVATION AND PRACTICE IN BUILDING STRUCTURE DESIGN. The Hong Kong Institute of Steel Construction, August 2022. http://dx.doi.org/10.18057/icass2020.p.158.

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The innovation of building structure design should satisfy the aspects of architectural form, function using and interior space design. The process of structural innovation is the fusion of structure and architecture. Firstly, structural system should relate to the architectural design of the building. Secondly, the structural layout should correspond to the building space using. Finally, digital design is a critical technology during the innovation of structural design. Therefore, this essay is going to express how the structural innovation can be achieved during the design of structure from eight cases in details. Keywords: Large-span stadiums, Architectural form, Structural system, Structural layout, Digital Design
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