Dissertations / Theses: 'Digital power systems'

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Grimes, Todd S. "Adaptive Power Analog-to-Digital Interface for Digital Systems." Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1483366560887816.

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Choi, Kyu-Won. "Hierarchical power optimization for ultra low-power digital systems." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04082004-180111/unrestricted/choi%5Fkyu-won%5F200312%5Fphd.pdf.

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Luo, F. L. "Digital control of power semiconductor converters." Thesis, University of Cambridge, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383314.

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Schmitt, Andreas Joachim. "Digital Implementation of Power System Metering and Protection." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/51194.

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An entirely digital system is presented which has several benefits as compared to the systems that are deployed currently. Utilizing digital capabilities to a much greater extent than is currently used within the power system allows for various improvements upon the current system. One such improvement is the ease of configuring and using the system. Each device can easily alter its functionality through a user interface, and the addition of devices is as easy as plugging it in. Additionally, the burden on the transformer due to the increase in the number of devices is nullified. The information remains accurate and unchanged, even when new devices are added to the system. The entire system conforms to the IEC 61850 standard, such that it adheres to the requirements of the actual power system.
Master of Science

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Gubba, Ravikumar Krishnanjan. "Distributed simulation of power systems using real time digital simulator." Master's thesis, Mississippi State : Mississippi State University, 2009. http://library.msstate.edu/etd/show.asp?etd=etd-06152009-222641.

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Llanos, Roger Vicente Caputo. "Voltage scaling interfaces for multi-voltage digital systems." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/159617.

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Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação.
Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.

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Li, Yan Ph D. Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science. "Digital assistance design for analog systems : digital baseband for outphasing power amplifiers." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/82353.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 145-150).
Digital assistance is among many aspects that can be leveraged to help analog/mixed-signal designers keep up with the technology scaling. It usually takes the form of predistorter or compensator in an analog/mixed-signal system and helps compensate the nonidealities in the system. Digital assistance takes advantage of the process scaling with faster speed and a higher level of integration. When a digital system is co-optimized with system modeling techniques, digital assistance usually becomes a key enabling block for the high performance of the overall system. This thesis presents the design of digital assistances through the digital baseband design for outphasing power amplifiers. In the digital baseband design, this thesis conveys two major points: the importance of the use of the reduced-complexity system modeling techniques, and the communications between hardware design and system modeling. These points greatly help the success in the design of the energy-efficient baseband. The first part of the baseband design is to realize the nonlinear signal processing unit required by the modulation scheme. Conventional approaches of implementing this functionality do not scale well to meet the throughput, area and energy-efficiency targets. We propose a novel fixed-point piece-wise linear approximation technique for the nonlinear function computations involved in the signal processing unit. The new technique allows us to achieve an energy and area-efficient design with a throughput of 3.4Gsamples/s. Compared to the projected previous designs, our design shows 2x improvement in energy-efficiency and 25x in area-efficiency. The second part of the baseband design devotes to the nonlinear compensator design, aiming to improve the linearity performance of the outphasing power amplifier. We first explore the feasibility of a working compensator by use of an off-line iterative solving scheme. With the confirmation that a compensator does exist, we analyze the structure of the nonlinear baseband-equivalent PA system and create a dynamical real-time compensator model. The resulting compensator provides the overall PA system with around 10dB improvement in ACPR and up to 2.5% in EVM.
by Yan Li.
Ph.D.

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Celanovic, Ivan. "A Distributed Digital Control Architecture for Power Electronics Systems." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/34998.

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This thesis proposes a novel approach to power electronics system design that is based on the open-architecture distributed digital controller and modular power electronics building blocks (PEBBs). The proposed distributed digital controller partitions the controller in three levels of control authority. The power stage controller, designated as hardware manager, is responsible for low-level hardware oriented tasks; the high level controller, designated as applications manager, performs higher-level application-oriented tasks; and the system level controller handles system control and monitoring functions. Communications between the hardware-oriented controller and the higher-level controller are implemented with the previously proposed 125 Mbits/sec daisy-chained fiber optic communication protocol. Real-time control and status data are communicated by means of communication protocol. The distributed controller on the power converter level makes the system open, flexible and simple to use. Furthermore, this work gives an overview and comparison of current state-of-the-art communication protocols for real-time control applications with emphasis on industrial automation and motion control. All of the studied protocols have been considered as local area networks (LAN) for system-level control in power converter systems. The most promising solution has been chosen for the system level communication protocol. This thesis also provides the details of design and implementation of the distributed controller. The design of both the hardware and software components are explained. A 100 kVA three-phase voltage source inverter (VSI) prototype was built and tested using the distributed controller approach to demonstrate the feasibility of the proposed concept.
Master of Science

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Al-doori, Q. "Design of a smart power manager for digital communication systems." Thesis, University of Salford, 2017. http://usir.salford.ac.uk/43361/.

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Portable devices, like mobile phones, are in an increasing need for power due to the growing complexity of applications and services provided by them. At the same time, mobile devices need to adapt their communication techniques so as to be able to work with different communication standards. The need for a multistandard communication circuit arises to overcome such a problem. Unfortunately, these circuits need to consume a considerable amount of power to achieve their designed goal. The researchers use the Dynamic Voltage/Frequency Scheduling technique to reduce power consumption in digital systems. This method employs the task time to schedule the system supply voltage along the task time to reduce the overall consumed power. Since the task time in digital communication systems is not defined, the application of the dynamic voltage/frequency technique on such systems is not possible. In this research, a closer look at the digital circuit power dissipation is given. Then, a new power model is introduced which can predict the digital circuit instantaneous power dissipation accurately. This model is used to build a power control strategy that makes use of the frequency as a control parameter. A setup is carried out using MATLAB to simulate the power of a NOT gate, a multiplexer circuit, a full adder and a two-bit full adder. The results are compared with OrCAD Cadence simulation for the same circuits. The results show that the new model can simulate the power dissipation accurately under different voltages, frequencies, and different technology sizes. In the second part of this research, a smart power manager is designed based on a fuzzy logic controller. The smart power manager makes use of the measured power and the input frequency to produce the required voltage to the digital system. The smart power manager is tested on a multiplexer circuit, two-bit full adder circuit, and cyclic redundancy check circuits. The results of the simulations show that the manager can reduce up to 60% of the consumed power by these circuits in low frequencies and up to 5% of the consumed power in high frequencies. The smart power manager can fulfil the purpose of the dynamic voltage/frequency scheduling technique without the need for the task time. In the final part of this research, the Long Term Evolution (LTE) system is taken as a case study. A unique cyclic redundancy check circuit is designed. This circuit is directed to work with LTE systems, so it has three generators integrated into it. The circuit can select the needed cyclic redundancy generator and produce the required remainder for the LTE system. The smart power manager is modified to supply both the voltage and frequency to the new cyclic redundancy check circuit so that it can control its consumed power. The selection of frequency depends on the used cyclic redundancy generator and the used modulation technique. The selected frequency ensures that the data rate between the LTE stages is constant. The results of the setup show that the smart power manager is capable of reducing the power of the circuit by more than 40% if it was operating at a constant frequency. The smart power manager can lower the power of the cyclic redundancy check circuit by more than 20% if the circuit is running under variable clock frequency. The conclusion driven from the results above proves that the SPM can reduce the consumed power in multi standard systems and Software Defined Radio (SDR) circuits.

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Henry, Michael Brewer. "Power Reduction of Digital Signal Processing Systems using Subthreshold Operation." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/33691.

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Over the past couple decades, the capabilities of battery-powered electronics has expanded dramatically. What started out as large bulky 2-way radios, wristwatches, and simple pacemakers, has evolved into pocket sized smart-phones, digital cameras, person digital assistants, and implantable biomedical chips that can restore hearing and prevent heart attacks. With this increase in complexity comes an increase in the amount of processing, which runs on a limited energy source such as a battery or scavenged energy. It is therefore desirable to make the hardware as energy efficient as possible. Many battery-powered systems require digital signal processing, which often makes up a large portion of the total energy consumption. The digital signal processing of a battery-powered system is therefore a good target for power reduction techniques. One method of reducing the power consumption of digital signal processing is to operate the circuit in the subthreshold region, where the supply voltage is lower than the threshold voltage of the transistors. Subthreshold operation greatly reduces the power and energy consumption, but also decreases the maximum operating frequency. Many digital signal processing applications have real-time throughput requirements, so various architectural level techniques, such as pipelining and parallelism, must be used in order to achieve the required performance.

This thesis investigates the use of parallelization and subthreshold operation to lower the power consumption of digital signal processing applications, while still meeting throughput requirements. Using an off the shelf fast fourier transform architecture, it will be shown that through parallelization and subthreshold operation, a 70 \% reduction in power consumption can be achieved, all while matching the performance of a nominal voltage single core architecture. Even better results can be obtained when an architecture is specifically designed for subthreshold operation. A novel Discrete Wavelet Transform architecture is presented that is designed to eliminate the need for memory banks, and a power reduction of 26x is achieved compared to a reference nominal voltage architecture that uses memory banks. Issues such as serial to parallel data distribution, dynamic throughput scaling, and memory usage are also explored in this thesis. Finally, voltage scaling greatly increases the design space, so power and timing analysis can be very slow due long SPICE simulation times. A simulation framework is presented that can characterize subthreshold circuits accurately using only fast gate level design automation tools.

Master of Science

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Jin, Jie. "Low power design for high performance wireless digital baseband building blocks /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20JIN.

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Garrett, Bretton Wayne. "Digital simulation of power system protection under transient conditions." Thesis, University of British Columbia, 1987. http://hdl.handle.net/2429/27303.

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This work demonstrates the use of digital simulation for analyzing protection system performance. For studies of complex, multi-relay protection systems, digital simulation provides utility engineers with an attractive alternative to relay testing techniques. The cost of digital simulation facilities can be lower than the cost of comparable testing facilities; relay hardware does not have to be made available for the test laboratory. Digital simulation would ordinarily be impractical for security and dependability studies, due to the thousands of individual simulations involved. The number of simulations needed can be greatly reduced by using a technique called "numerical logic replacement" for implementing the protection scheme logic. This unconventional technique makes near-misoperation visible from individual simulations. The likelihood of overlooking potential misoperation is thus much lower than with the usual direct (Boolean) implementations.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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Venkatraman, Chandrasekar. "Hill climbing digital control algorithm for maximum power point tracking of photovoltaic arrays." Laramie, Wyo. : University of Wyoming, 2006. http://proquest.umi.com/pqdweb?did=1320938081&sid=2&Fmt=2&clientId=18949&RQT=309&VName=PQD.

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Han, Yu. "Optimization of Modulation Constrained Digital Transmission Systems." Thesis, Université d'Ottawa / University of Ottawa, 2018. http://hdl.handle.net/10393/37097.

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The regular waterfilling(WF) policy maximizes the mutual information of parallel channels, when the inputs are Gaussian. However, Gaussian input is ideal, which does not exist in reality. Discrete constellations are usually used instead, such as $ M $-PAM and $ M $-QAM. As a result, the mercury/waterfilling (MWF) policy is introduced, which is a generalization of the regular WF. The MWF applies to inputs with arbitrary distributions, while the regular WF only applies to Gaussian inputs. The MWF-based optimal power allocation (OPA) is presented, for which an algorithm called the internal/external bisection method is introduced. The constellation-constrained capacity is discussed in the thesis, where explicit expressions are presented. The expression contains an integral, which does not have a closed-form solution. However, it can be evaluated via the Monte Carlo method. An approximation of the constellation-constrained capacity based on the sphere packing method is introduced, whose OPA is a convex optimization problem. The CVX was used initially, but it did not generate satisfactory results. Therefore, the bisection method is used instead. Capacities of the MWF and its sphere packing approximation are evaluated for various cases, and compared with each other. It turns out the sphere packing approximation has similar performances to the MWF, which validates the approximation. Unlike the MWF, the sphere packing approximation does not suffer from the loss of precision due to the structure of MMSE functions, which demonstrates its robustness.

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Ding, Lei. "Digital predistortion of power amplifiers for wireless applications." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-04022004-020955/unrestricted/ding%5Flei%5F200405%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004.
J. Stevenson Kenney, Committee Member ; G. Tong Zhou, Committee Chair ; W. Marshall Leach, Committee Member ; Ye (Geoffrey) Li, Committee Member ; Jianmin Qu, Committee Member. Includes bibliographical references (leaves 100-103).

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Doneddu, Daniele. "The use of novel digital power supply to drive laser systems." Thesis, Swansea University, 2010. https://cronfa.swan.ac.uk/Record/cronfa42441.

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Light-based therapies are becoming increasingly important and widely applied within the clinical practice. Their advantages over more traditional therapies have created an expanding market which is driving the development of more efficient and sophisticated devices. These devices allow a more precise control of the characteristics of the optical output to maximise benefits of the treatment. Although many studies have been conducted on light, and more specifically lasers, both from a therapeutic and a technological perspective, there is still much research to be undertaken. Laser systems have been used for more than two decades for the treatment of vascular lesions. Indeed the application of selective photothermolysis utilising the monochromaticity of the laser system has become the treatment of choice. However the treatment of larger blood vessels remains problematic. Many workers have, for theoretical and clinical reasons, elected to choose the YAG laser for the treatment of larger thread veins and vascular lesions containing larger vessels. The therapeutic output has been mixed and the need for further work identified. This thesis describes the design of a novel approach to the control of the temporal profile of the YAG laser. The design aspect of the work includes a computer modelling study which shows that careful control of the temporal parameters can in principle improve the therapeutic output. A novel approach to the digital control of the flashlamps pumping the YAG crystal is also described. The digital control of the flashlamp translates to sensitive control of the temporal profile of the laser output in a way that has not been described to date. The thesis therefore concludes that control of the temporal output of the YAG laser, if possible, should give improved therapeutic output and that the necessary level of control can be achieved by advanced digital techniques. Future clinical work should prove improved therapeutic results.

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Jooste, Charl Roelof. "Development of a generic digital controller for power electronic applications." Thesis, Cape Peninsula University of Technology, 2011. http://hdl.handle.net/20.500.11838/2210.

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Thesis (MTech (Electrical Engineering)))--Cape Peninsula University of Technology, 2011.
This thesis presents an investigation into the generic tools, hardware and firmware, involved in power electronic converter control and feedback. The aim was to determine the optimal controller architecture through research of existing controllers. As soon as the architecture was established, design of the controller commenced. Explanations for the various components selected were provided. The design considerations when designing a printed circuit board (PCB) with mixed signals was also presented. The theory behind the control of a multicell converter as well the practical implementation of the control scheme in firmware was presented.

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Franco, Marcelo Jorge Herczfeld Peter R. "Wideband digital predistortion linearization of radio frequency power amplifiers with memory /." Philadelphia, Pa. : Drexel University, 2005. http://dspace.library.drexel.edu/handle/1860/485.

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Chung, Jae Hak. "Applications of digital signal processing to electric power quality and wireless communications /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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Al-Atrash, Hussam. "INTEGRATED TOPOLOGIES AND DIGITAL CONTROL FOR SATELLITE POWER MANAGEMENT AND DISTRIBUTION SYSTEMS." Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3287.

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This work is focused on exploring advanced solutions for space power management and distribution (PMAD) systems. As spacecraft power requirements continue to increase, paralleled by the pressures for reducing cost and overall system weight, power electronics engineers will continue to face major redesigns of the space power systems in order to meet such challenges. Front-end PMAD systems, used to interface the solar sources and battery backup to the distribution bus, need to be designed with increased efficiency, reliability, and power density. A new family of integrated single-stage power converter structures is introduced here. This family allows the interface and control of multiple power sources and storage devices in order to optimize utilization of available resources. Employing single-stage power topologies, these converters control power flow efficiently and cost-effectively. This is achieved by modifying the operation and control strategies of isolated soft-switched half-bridge and full-bridge converters--two of the most popular two-port converter topologies. These topologies are reconfigured and utilized to realize three power processing paths. These paths simultaneously utilize the power devices, allowing increased functionality while promising reduced losses and enhanced power densities. Each of the proposed topologies is capable of performing simultaneous control of two of its three ports. Control objectives include battery or ultra-capacitor charge regulation, solar array maximum power point tracking (MPPT), and/or bus voltage regulation. Another advantage of the proposed power structure is that current engineering design concepts can be used to optimize the new topologies in a fashion similar to the mother topologies. This includes component selection and magnetic design procedures, as well as achieving soft-switching for increased efficiency at higher switching frequencies. Galvanic isolation of the load port through high-frequency transformers provides design flexibility for high step-up/step-down conversion ratios. It further allows the converters to be used as power electronics building blocks (PEBB) with outputs connected in different series/parallel combinations to meet different load requirements. Utilizing such converters promises significant savings in size, weight, and costs of the power management system as well as the devices it manages. Chapter 1 of this dissertation provides an introduction to the requirements, challenges, and trends of space PMAD. A review of existing multi-port converter technologies and digital control techniques is given in Chapter 2. Chapter 3 discusses different PMAD system architectures. It outlines the basic concepts used for PMAD integration and discusses the potential for improvement. Chapters 4 and 5 present and discuss the operation and characteristics of three different integrated multi-port converters. Chapter 6 presents improved methods for practical digital control of switching converters, which are especially useful in complex multi-objective controllers used for PMAD. This is followed by conclusions and suggested future work.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD

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Popescu, George. "Digital Signal Processing Methods for Safety Systems Employed in Nuclear Power Industry." University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1479815935917872.

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Shridevi, Rajesh Jayashankara. "Emerging Security Threats in Modern Digital Computing Systems: A Power Management Perspective." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7483.

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Design of computing systems — from pocket-sized smart phones to massive cloud based data-centers — have one common daunting challenge : minimizing the power consumption. In this effort, power management sector is undergoing a rapid and profound transformation to promote clean and energy proportional computing. At the hardware end of system design, there is proliferation of specialized, feature rich and complex power management hardware components. Similarly, in the software design layer complex power management suites are growing rapidly. Concurrent to this development, there has been an upsurge in the integration of third-party components to counter the pressures of shorter time-to-market. These trends collectively raise serious concerns about trust and security of power management solutions. In recent times, problems such as overheating, performance degradation and poor battery life, have dogged the mobile devices market, including the infamous recall of Samsung Note 7. Power outage in the data-center of a major airline left innumerable passengers stranded, with thousands of canceled flights costing over 100 million dollars. This research examines whether such events of unintentional reliability failure, can be replicated using targeted attacks by exploiting the security loopholes in the complex power management infrastructure of a computing system. At its core, this research answers an imminent research question: How can system designers ensure secure and reliable operation of third-party power management units? Specifically, this work investigates possible attack vectors, and novel non-invasive detection and defense mechanisms to safeguard system against malicious power attacks. By a joint exploration of the threat model and techniques to seamlessly detect and protect against power attacks, this project can have a lasting impact, by enabling the design of secure and cost-effective next generation hardware platforms.

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Pan, Fei. "Multifrequency Averaging in Power Electronic Systems." UKnowledge, 2014. http://uknowledge.uky.edu/ece_etds/62.

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Power electronic systems have been widely used in the electrical power processing for applications with power levels ranging from less than one watt in battery-operated portable devices to more than megawatts in the converters, inverters and rectifiers of the utility power systems. These systems typically involve the passive elements such as inductors, capacitors, and resistors, the switching electronic components such as IGBTs, MOSFETS, and diodes, and other electronic circuits. Multifrequency averaging is one of the widely used modeling and simulation techniques today for the analysis and design of power electronic systems. This technique is capable of providing the average behavior as well as the ripple behavior of power electronic systems. This work begins with the extension of multifrequency averaging to represent uniformly sampled PWM converters. A new multifrequency averaging method of solving an observed issue with model stability is proposed and validated. Multifrequency averaging can also be applied to study the instability phenomenon in power electronic systems. In particular, a reduced-order multifrequency averaging method, along with a genetic algorithm based procedure, is proposed in this work to estimate the regions of attraction of power electronic converters. The performance of this method is shown by comparing the accuracy and efficiency with the existing methods. Finally, a new continuous-time multifrequency averaging method of representing discrete-time systems is proposed. The proposed method is applied to model digitally controlled PWM converters. Simulation and hardware results show that the proposed method is capable of predicting the average behavior as well as the ripple behavior of the closed-loop systems. Future research in the area of multifrequency averaging is proposed.

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Newman, Michael John 1976. "Design and control of a Universal Custom Power Conditioner (UCPC)." Monash University, Dept. of Electrical and Computer Systems Engineering, 2003. http://arrow.monash.edu.au/hdl/1959.1/5651.

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Martelli, Chiara. "Multi-standard low-power base-band digital receiver, enhanced for HSDPA /." Konstanz : Hartung-Gorre, 2006. http://www.loc.gov/catdir/toc/fy0707/2007366221.html.

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Originally presented as the author's thesis (Swiss Federal Institute of Technology), Diss. ETH No. 16683.
Summary in Italian and English; text in English. Includes bibliographical references (p. 171-177).

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Van, Papendorp J. F. "Digital control of line-interactive UPS." Thesis, Stellenbosch : University of Stellenbosch, 2011. http://hdl.handle.net/10019.1/6537.

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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2011.
ENGLISH ABSTRACT: The digital control of UPS systems has been difficult in the past due to a lack of DSP technology. It was for this reason not possible to establishing the necessary control to regulate the voltages and currents of the UPS systems. Recent advances in DSP technology have however provided the means of establishing central control of the UPS system as well as incorporating more complex closed-loop control algorithms by utilising a single floating-point DSP. Closed-loop control strategies are investigated and the central control of a line-interactive UPS is established in this study. Both the status of the physical system as well as various system parameters are controlled. The system both regulates and charges the storage batteries when the main utility supply is maintained. In the event that the utility fails, the converter instantaneously changes power flow towards the load with the aim of maintaining an uninterrupted voltage supply. Several closed-loop deadbeat based control strategies are investigated for the regulation of the inductor current. A solution for the regulation of the DC-link is also developed and implemented. Furthermore, an intensive study is done on the regulation of the voltage supplied to the load in the event that the utility supply fails. The investigation is initially approached by considering classical control theory. Although these control strategies provided sufficient results, a predictive strategy that is based on the physical conditions of the switching converter is finally investigated to establish closed loop control of the output voltage. This resulted in a high-bandwidth voltage controller capable of maintaining control under a wide-array of load conditions.
AFRIKAANSE OPSOMMING: Die digitale beheer van UPS stelsels was moeilik in the verlede as gevolg van 'n gebrek aan DSP tegnologie. Dit was vir hierdie rede nie moontlik om beheer te kon bewerkstelling ten einde die spannings and strome in the UPS stelsels te kon reguleer nie. Onlangse vordering in DSP tegnologie het egter dit moontlik gemaak om sentrale beheer van die UPS stelsel te bewerkstellig sowel as om meer komplekse geslote lus beheer algoritmes te inkorporeer met behulp van 'n enkele DSP. Geslote lus beheer strategiëe word ondersoek en die sentrale beheer van die line-interaktiewe UPS word bewerkstellig in hierdie studie. Beide die huidige toestand van die fisiese stelsel sowel as die verskeie parameters word beheer. Die stelsel beide laai en reguleer die batterye terwyl die hooftoevoer onderhou word. In die geval dat die hooftoevoer faal, word die omsetter se rigting van drywingsvloei verander om die las te voorsien van 'n ononderbroke spannings toevoer. Verskeie geslote-lus “deadbeat” beheer strategiëe word ondersoek vir die regulasie van die induktor stroom. 'n Oplossing vir die regulasie van die GS-koppervlak word ook ontwikkel en geïmplementeer. Verder word 'n intensiewe studie gedoen op regulasie van die spanning wat aan die las gevoer word in die geval dat die hooftoevoer faal. Hierdie ondersoek word aanvanklik benader deur klassieke beheer teorie te bestudeer. Alhoewel hierdie beheer strategiëe voldoene resultate gebied het, was 'n voorspel beheerstrategie gebaseer op die fisiese toestand van die omsetter finaal ondersoek. Die resultaat is 'n hoë-bandwydte spannings beheerder wat daartoe instaat is om beheer te handhaaf onder 'n verskeidenheid van lastoestande.

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Ganesan, Sharan Kumaar. "Design and Implementation of Digital Spiking Neurons for Ultra-low-Power In-cluster processors." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-198115.

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Neuromorphic computing is a recent and growing field of research. Its conceptual attractiveness is due to the potential it has in deep learning applications such as sensor networks, low-power computer vision, robotics and other fields. Inspired by the functioning of brain, different neural network models have been devised, each with their own special focus on certain applications. Using such computing models are already helping us in different cases such as image, character and voice recognition, data analysis, stock market prediction, etc. Among the multitude of artificial neural models available, spiking neurons are more deeply inspired by biological neural networks. Leaky, Integrate and Fire (LIF) neuron model is one such model that can reproduce a good number of functions, be simple and also extensible in structure. Current deep learning applications are tied to servers and datacenters for their power and resource hungry existence. This work aims at building a low power neuron core taking advantage of LIF neuron, that could possible result in independent battery powered devices. A hardware design of LIF neuron based scalable neural core is explored, constructed and analysis for power consumption is made.

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Woo, Wangmyong. "Hybrid Digital/RF Envelope Predistortion Linearization for High Power Amplifiers in Wireless Communication Systems." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6924.

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Hybrid Digital/RF Envelope Predistortion Linearization for High Power Amplifiers in Wireless Communication Systems Wangmyong Woo 151 Pages Directed by Dr. J. Stevenson Kenney The objective of this research is to implement a hybrid digital/RF envelope predistortion linearization system for high-power amplifiers used in wireless communication systems. It is well known that RF PAs have AM/AM (amplitude modulation) and AM/PM (phase modulation) nonlinear characteristics. Moreover, the distortion components generated by a PA are not constant, but vary as a function of many input conditions such as amplitude, signal bandwidth, self-heating, aging, etc. Memory effects in response to past inputs cause a hysteresis in the nonlinear transfer characteristics of a PA. This hysteresis, in turn, creates uncertainty in predictive linearization techniques. To cope with these nonlinear characteristics, distortion variability, and uncertainty in linearization, an adaptive digital predistortion technique, a hybrid digital/RF envelope predistortion technique, an analog-based RF envelope predistortion technique, and a combinational digital/analog predistortion technique have been developed. A digital adaptation technique based on the error vector minimization of received PA output waveforms was developed. Also, an adaptive baseband-to-baseband test system for the characterization of RF PAs and for the validation of linearization algorithms was implemented in conjunction with the adaptation technique. To overcome disadvantages such as limited correction bandwidth and the need for a baseband input signal in digital predistortion, an adaptive, wideband RF envelope predistortion system was developed that incorporates a memoryless predistortion algorithm. This system is digitally controlled by a look-up table (LUT). Compared with conventional baseband digital approaches, this predistortion architecture has a correction bandwidth that is from 20 percent to 33 percent wider at the same clock speeds for third to fifth order IMDs and does not need a digital baseband input signal. For more accurate predistortion linearization for PAs with memory effects, an RF envelope predistortion system has been developed that uses a combination of analog-based envelope predistortion (APD) working in conjunction with digital LUT-based adaptive envelope predistortion (DPD). The resulting combination considerably decreases the computational complexity of the digital system and significantly improves linearity and efficiency at high power levels.

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Chae, Kwanyeob. "Design methodologies for robust low-power digital systems under static and dynamic variations." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/52174.

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Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The safety margin makes it difficult to meet the target performance within a limited power budget. This research explores methodologies to minimize the safety margin, thereby improving the energy efficiency of a system. The safety margin can be reduced by either minimizing the variation or adapting to the variation. This research explores three different methods to compensate for variations efficiently. First, post-silicon tuning methods for minimizing variations in 3D ICs are presented. Design methodologies to apply adaptive voltage scaling and adaptive body biasing to 3D ICs and the associated circuit techniques are explored. Second, non-design-intrusive circuit techniques are proposed for adaptation to dynamic variations. This work includes adaptive clock modulation and bias-voltage generation techniques. Third, design-intrusive methods to eliminate the safety margin are proposed. The proposed methodologies can prevent timing-errors in advance with a minimized performance penalty. As a result, the methods presented in this thesis minimize static variations and adapt to dynamic variations, thereby, enabling robust low-power operation of digital systems.

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Betowski, David James. "Optimizing the performance of direct digital frequency synthesizers for low-power wireless communication systems." Online access for everyone, 2004. http://www.dissertations.wsu.edu/Thesis/Fall2004/d%5Fbetowski%5F111104.pdf.

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Ziegler, Silvio. "New current sensing solutions for low-cost high-power-density digitally controlled power converters." University of Western Australia. School of Electrical, Electronic and Computer Engineering, 2009. http://theses.library.uwa.edu.au/adt-WU2010.0077.

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[Truncated abstract] This thesis studies current sensing techniques that are designed to meet the requirements for the next generation of power converters. Power converters are often standardised, so that they can be replaced with a model from another manufacturer without an expensive system redesign. For this reason, the power converter market is highly competitive and relies on cutting-edge technology, which increases power conversion efficiency and power density. High power density and conversion efficiency reduce the system cost, and thus make the power converter more attractive to the customer. Current sensing is a vital task in power converters, where the current information is required for monitoring and control purposes. In order to achieve the above-mentioned goals, existing current sensing techniques have to be improved in terms of cost, power loss and size. Simultaneously, current information needs to be increasingly available in digital form to enable digital control, and to allow the digital transmission of the current information to a centralised monitoring and control unit. All this requires the output signal of a particular current sensing technique to be acquired by an analogue-to-digital converter, and thus the output voltage of the current sensor has to be sufficiently large. This thesis thoroughly reviews contemporary current sensing techniques and identifies suitable techniques that have the potential to meet the performance requirements of the next-generation of power converters. After the review chapter, three novel current sensing techniques are proposed and investigated: 1) The usefulness of the resistive voltage drop across a copper trace, which carries the current to be measured, to detect electrical current is evaluated. Simulations and experiments confirm that this inherently lossless technique can measure high currents at reasonable measurement bandwidth, good accuracy and low cost if the sense wires are connected properly. 2) Based on the mutual inductance theory found during the investigation of the copper trace current sense method, a modification of the well-known lossless inductor current sense method is proposed and analysed. This modification involves the use of a coupled sense winding that significantly improves the frequency response. Hence, it becomes possible to accurately monitor the output current of a power converter with the benefits of being lossless, exhibiting good sensitivity and having small size. 3) A transformer based DC current sense method is developed especially for digitally controlled power converters. This method provides high accuracy, large bandwidth, electrical isolation and very low thermal drift. Overall, it achieves better performance than many contemporary available Hall Effect sensors. At the same time, the cost of this current sensor is significantly lower than that of Hall Effect current sensors. A patent application has been submitted. .... The current sensing techniques have been studied by theory, hardware experiments and simulations. In addition, the suitability of the detection techniques for mass production has been considered in order to access the ability to provide systems at low-cost.

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Ku, Hyunchul. "Behavioral modeling of nonlinear RF power amplifiers for digital wireless communication systems with implications for predistortion linearization systems." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04052004-180035/unrestricted/ku%5Fhyunchul%5F200312%5Fphd.pdf.

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Marwali, Mohammad Nanda Rahmana. "Digital control of pulse width modulated inverters for high performance uninterruptible power supplies." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1100484647.

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Thesis (Ph. D.)--Ohio State University, 2004.
Title from first page of PDF file. Document formatted into pages; contains xviii, 224 p.; also includes graphics. Includes bibliographical references (p. 199-211).

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Mandrekar, Rohan Uday. "Modeling and Co-simulation of Signal Distribution and Power Delivery in Packaged Digital Systems." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10459.

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The pursuit for higher performance at a lower cost is driving rapid progress in the field of packaged digital systems. As the complexity of interconnects and packages increases, and the rise and fall time of the signal decreases, the electromagnetic effects in distributed passive structures become an important factor in determining the system performance. Hence there is a need to accurately simulate these parasitic electromagnetic effects that are observed in the signal distribution network (SDN) and the power delivery network (PDN) of an electronic system. The accurate simulation of high-speed systems requires information on the high frequency transient currents that are injected into the power distribution network causing simultaneous switching noise. Existing techniques for determining these transient currents are not sufficiently accurate. Furthermore existing transient simulation techniques suffer from two major drawbacks: 1) they are not scalable and hence cannot be applied to large sized systems, and 2) the time domain simulations violate causality. This dissertation addresses the above-mentioned problems in the domain of high-speed packaging. It proposes a new technique to accurately extract the transient switching noise currents in high-speed digital systems. The extracted switching noise currents can be used in both the frequency domain and the time domain to accurately simulate simultaneous switching noise. The dissertation also proposes a methodology for the transient co-simulation of the SDN and the PDN in high-speed digital systems. The methodology enforces causality on the transient simulation and can be scaled to perform large sized simulations. The validity of the proposed techniques has been demonstrated by their application on a variety of real-world test cases.

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Muppalla, Ashwin K. "Ultra low power multi-gigabit digital CMOS modem technology for millimeter wave wireless systems." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41084.

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The objective of this research is to present a low power modem technology for a high speed millimeter wave wireless system. The first part of the research focuses on a robust ASIC design methodology. There are several aspects of the ASIC flow that require special attention such as logical synthesis, timing driven physical placement, Clock Tree Synthesis, Static Timing Analysis, estimation and reduction of power consumption and LVS and DRC closure. The latter part is dedicated to high speed baseband circuits such as Coherent and Non coherent demodulator which are critical components of a multi-gigabit wireless communication system. The demodulator operates at input data rates of multiple gigabits per second, which presents the challenge of designing the building blocks to operate at speeds of multiple GHz. The high speed complex multiplier is a major component of the non coherent demodulator. As part of the coherent demodulator the complex multiplier derotates the input sequence by multiplying with cosine and sine functions, Costas error calculator computes the phase error in the derotated input signal. The NCO (Numerically controlled Oscillator) is a look up table based system used to generate the cosine and sine functions, used by the derotator.The CIC filter is used to decimate the costas error signal as the loop bandwidth is significantly smaller compared to the sampling frequency. All these modules put together form the coherent demodulator which is an integral part of the wireless communication system. An implementation of Serdes is also presented which acts as an interface between the baseband modules and the RF front end.

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Nsumbu, Cassandra Daviane. "Development of a soft-core based power electronic conversion controller." Thesis, Cape Peninsula University of Technology, 2014. http://hdl.handle.net/20.500.11838/2379.

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Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2014.
The application of digital control techniques has become dominant in power electronics owing to several advantages they present, when compared to analogue solutions. Their development is based on the use of microprocessors and microcontrollers, such as Application Specific Integrated Circuit (ASIC), Digital signal processors (DSP), Field Programmable Gate Arrays (FPGA), or a combination of these devices. This thesis presents an investigation of a soft-core based FPGA control system as a solution for power electronic applications. The aim was the development and implementation of a conversion controller, which purpose is to supply control inputs in the form of digital Pulse Width Modulation (PWM) signals, to a number of power electronic applications, such as single half and full bridge DC-DC converters, three phase and multicell inverters. The PWM control technique is achieved via their power semiconductor switching devices. These PWM control signals are necessary for the high frequency conversion of an analog input voltage (AC, DC or unregulated) to an analog output voltage of another level (AC or DC). This was intended to be achieved by exploiting and combining the advantages that FPGA and embedded processors provide such as high reconfigurability and multipurpose ability. This controller’s digital outputs, namely PWM switching signals, can be directly delivered to an analog signal amplification circuit to create an adequate voltage level before being processed by the converters’ switches.

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Liang, Feng. "Performance enhancement of digital relays for transmission line distance protection /." Internet access available to MUN users only, 2003. http://collections.mun.ca/u?/theses,153681.

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Zhang, Fan. "Power-aware scheduling in computing and communications with QoS requirements /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?COMP%202005%20ZHANGF.

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Rachinger, Christoph [Verfasser]. "Power Efficient Digital Transmission for MIMO Systems using Spherical Codes : Leistungseffiziente digitale Übertragung für Mehrantennensysteme mittels sphärischer Codes / Christoph Rachinger." Aachen : Shaker, 2018. http://d-nb.info/1162794305/34.

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Francis, Gerald. "A Synchronous Distributed Digital Control Architecture for High Power Converters." Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/31942.

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Power electronics applications in high power are normally large, expensive, spatially distributed systems. These systems are typically complex and have multiple functions. Due to these properties, the control algorithm and its implementation are challenging, and a different approach is needed to avoid customized solutions to every application while still having reliable sensor measurements and converter communication and control.

This thesis proposes a synchronous digital control architecture that allows for the communication and control of devices via a fiber optic communication ring using digital technology. The proposed control architecture is a multidisciplinary approach consisting of concepts from several areas of electrical engineering. A review of the state of the art is presented in Chapter 2 in the areas of power electronics, fieldbus control networks, and digital design. A universal controller is proposed as a solution to the hardware independent control of these converters. Chapter 3 discusses how the controller was specified, designed, implemented, and tested. The power level specific hardware is implemented in modules referred to as hardware managers. A design for a hardware manager was previously implemented and tested. Based on these results and experiences, an improved hardware manager is specified in Chapter 4. A fault tolerant communication protocol is specified in Chapter 5. This protocol is an improvement on a previous version of the protocol, adding benefits of improved synchronization, multimaster support, fault tolerant structure with support for hot-swapping, live insertion and removals, a variable ring structure, and a new network based clock concept for greater flexibility and control. Chapter 6 provides a system demonstration, verifying the components work in configurations involving combinations of controllers and hardware managers to form applications. Chapter 7 is the conclusion. VHDL code is included for the controller, the hardware manager, and the protocol. Schematics and manufacturing specifications are included for the controller.
Master of Science

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41

al-Sarʻāwī, Said Fares. "Design techniques for low power mixed analog-digital circuits with application to smart wireless systems /." Title page, contents and abstract only, 2003. http://web4.library.adelaide.edu.au/theses/09PH/09pha461.pdf.

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Tauqeer, Tauseef. "Low Power, High Speed InP-Based Digital Intergrated Circuits for Ultra Wide Band Communicatiopn Systems." Thesis, University of Manchester, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.508526.

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Alharbi, Faisal Shaji. "Digital signal processing techniques for peak-to-average power ratio mitigation in MIMO-OFDM systems." Thesis, Loughborough University, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.510322.

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Sun, Xin. "Protection performance study for secondary systems with IEC61850 process bus architecture." Thesis, University of Bath, 2012. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.563989.

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Following the introduction of the microprocessor into the power system protection field, modern microprocessor based numeric relays have developed very rapidly in the last 20 years, and modern power system protection schemes are virtually all based on microcomputers technology. The International Electro-technical Commission (IEC) recently launched the standard IEC61850, “Communication Networks and System in Substation”, which is having a major impact on the structure of new protection systems and schemes. In itself it describes the concepts for sub-station communications covering protection, control and metering functions. However, although it is going to have a major impact on the power systems communications, it will also influence the design of future protection systems. There will also be a host of other opportunities and advantages that can be realised. These include easier upgrading, refurbishment and replacement of sub-station protection. They also provide for greater use of general purpose Intelligent Electronics Devices (IEDs), self-healing systems, and plug and play type facilities. The Ethernet based communication network for data transfer between process level switchyard equipment and bay level IEDs, the process bus, is defined in IEC61850 Section 9-2. This process bus facilitates the communication of two types of real-time, peer-to-peer communication messages. Generic object-oriented substation event messages, the GOOSE messages and the data sample values, SVs which include the measured currents and voltages. Although this standard describes the message structures and the timing requirements, it does not describe the process bus topology. This work describes different LAN topologies that can be used in the design of process bus for protection systems. It considers the implications of the different structures on the operation of the protection scheme and how these relate to the operational strategy of different operators. It provides an assessment of the data handling capabilities of the system and how the demands of the protection system can be met. Several potential problem areas are identified and analyzed. The probabilistic nature of these systems is discussed and the implications explained. It also provides an insight into the implementation of the alternative topologies and their performance when applied to a transmission line feeder protection and transformer protection. The digital substation and the implementation of IEC61850 are fundamental to the future of protection ‘relays’. There are many pointers to the potential directions that these systems will develop and the skills required for the protection engineers of the future. This project is seeking to overcome some of the ownership challenges presented by modern protection and control (P&C) devices, which have an inherent short life due to their dependence on modern electronics and software.

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Fung, Cheuk-wai. "A diagrammatic algorithm for minimum sampling frequency and quantization resolution for digital control of power converters." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/hkuto/record/B39389960.

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Fung, Cheuk-wai, and 馮卓慧. "A diagrammatic algorithm for minimum sampling frequency and quantization resolution for digital control of power converters." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39389960.

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Sperlich, Roland. "Adaptive power amplifier linearization by digital pre-distortion with narrowband feedback using genetic algorithms." Diss., Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-06232005-152633/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2006.
Leach, William M., Committee Member ; Sills, James A., Committee Member ; Kenney, J. Stevenson, Committee Chair ; Zhou, G. Tong, Committee Co-Chair ; Fenney, Robert K., Committee Member.

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Leung, Matthew Chung-Hin. "CMOS RF SOC Transmitter Front-End, Power Management and Digital Analog Interface." Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24664.

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With the growing trend of wireless electronics, frequency spectrum is crowded with different applications. High data transfer rate solutions that operate in license-exempt frequency spectrum range are sought. The most promising candidate is the 60 GHz multi-giga bit transfer rate millimeter wave circuit. In order to provide a cost-effective solution, circuits designed in CMOS are implemented in a single SOC. In this work, a modeling technique created in Cadence shows an error of less than 3dB in magnitude and 5 degree in phase for a single transistor. Additionally, less than 3dB error of power performance for the PA is also verified. At the same time, layout strategies required for millimeter wave front-end circuits are investigated. All of these combined techniques help the design converge to one simulation platform for system level simulation. Another aspect enabling the design as a single SOC lies in integration. In order to integrate digital and analog circuits together, necessary peripheral circuits must be designed. An on-chip voltage regulator, which steps down the analog power supply voltage and is compatible with digital circuits, has been designed and has demonstrated an efficiency of 65 percent with the specific area constraint. The overall output voltage ripple generated is about 2 percent. With the necessary power supply voltage, gate voltage bias circuit designs have been illustrated. They provide feasible solutions in terms of area and power consumption. Temperature and power supply sensitivities are minimized in first two designs. Process variation is further compensated in the third design. The third design demonstrates a powerful solution that each aspect of variations is well within 10%. As the DC conditions are achieved on-chip for both the digital and analog circuits, digital and analog circuits must be connected together with a DAC. A high speed DAC is designed with special layout techniques. It is verified that the DAC can operate at a speed higher than 3 Gbps from the pulse-shaping FIR filter measurement result. With all of these integrated elements and modeling techniques, a high data transfer rate CMOS RF SOC operating at 60 GHz is possible.

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Pendyala, Shilpa. "Synthesis Techniques for Sub-threshold Leakage and NBTI Optimization in Digital VLSI Systems." Scholar Commons, 2015. http://scholarcommons.usf.edu/etd/6012.

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The rising power demands and cost motivates us to explore low power solutions in electronics. In nanometer Complementary Metal Oxide Semiconductor (CMOS) processes with low threshold voltages and thin gate oxides, subthreshold leakage power dominates total power of a circuit. As technology scales, Negative Bias Temperature Instability (NBTI) emerged as a major limiting reliability mechanism. It causes a threshold voltage shift which, over time, results in circuit performance degradation. Hence, leakage power and NBTI degradation are two key challenges in deep sub micron regime. In this dissertation, interval arithmetic based interval propagation technique is introduced as an effective leakage optimization technique in high level circuits with little overhead. The concept of self similarity from fractal theory is adopted for the first time in VLSI research to handle large design space. Though there are some leakage and NBTI co-optimization techniques in literature, our vector cycling approach combined with a back tracking algorithm have achieved better results for ISCAS85 benchmarks. We did not find any previous research works on NBTI optimization of finite state machines (FSMs). The optimization techniques of NBTI optimization in FSMs is introduced in this dissertation as well and substantial NBTI optimization is reported. Input vector control has been shown to be an effective technique to minimize subthreshold leakage. Applying appropriate minimum leakage vector (MLV) to each register transfer level (RTL) module instance results in a low leakage state with significant area overhead. For each module, via Monte Carlo simulation, we identify a set of MLV intervals such that maximum leakage is within (say) 10% of the lowest leakage points. As the module bit width increases, exhaustive simulation to find the low leakage vector is not feasible. Further, we need to search the entire input space uniformly to obtain as many low leakage intervals as possible. Based on empirical observations, we observed self similarity in the leakage distribution of adder/multiplier modules when input space is partitioned into smaller cells. This property enables uniform search of low leakage vectors in the entire input space. Also, the time taken for characterization increases linearly with the module size. Hence, this technique is scalable to higher bit width modules with acceptable characterization time. We can reduce area overhead (in some cases to 0) by choosing Primary Input (PI) MLVs such that resultant inputs to internal nodes are also MLVs. Otherwise, control points can be inserted. Based on interval arithmetic, given a DFG, we propose a heuristic with several variations for PI MLV identification with minimal control points. Experimental results for DSP filters simulated in 16nm technology demonstrated leakage savings of 93.8% with no area overhead, compared to existing work. Input vector control can also be adopted to reduce NBTI degradation as well as leakage in CMOS circuits. In the prior work, it is shown that minimum leakage vector of a circuit is not necessarily NBTI friendly. In order to achieve NBTI and leakage co-optimization, we propose an input vector cycling technique which applies different sub-optimal low leakage vectors to primary inputs at regular intervals. A co-optimal input vector for a given circuit is obtained by using simulated annealing (SA) technique. For a given input vector, a set of critical path PMOS transistors are under stress. A second input vector is obtained using a back tracking algorithm such that most of the critical path PMOS transistors are put in recovery mode. When a co-optimized input vector is assigned to primary input, critical path nodes under stress with high delay contribution are set to recovery. Logic 1 is back propagated from the nodes to the primary inputs to obtain the second input vector. These two vectors are alternated at regular time intervals. The total stress is evenly distributed among transistor sets of two vectors, as the intersection of the two sets is minimized. Hence, the overall stress on critical path transistors is alleviated, thereby reducing the NBTI delay degradation. For ISCAS85 benchmarks, an average of 5.3% improvement is achieved in performance degradation at 3.3% leakage overhead with NBTI-leakage co-optimization with a back tracking algorithm compared to solely using co-optimization. A 10.5% average NBTI improvement is obtained when compared to circuit with minimum leakage input vector for 18% average leakage overhead. Also, an average NBTI improvement of 2.13% is obtained with 6.77% leakage improvement when compared to circuit with minimum NBTI vector. Vector cycling is shown to be more eﬀective in mitigating NBTI over input vector control. Several works in the literature have proposed optimal state encoding techniques for delay, leakage, and dynamic power optimization. In this work, we propose, for the first time, NBTI optimization based on state code optimization. We propose a SA based state code assignment algorithm, resulting in minimization of NBTI degradation in the synthesized circuit. A PMOS transistor when switched ON for a long period of time, will lead to delay degradation due to NBTI. Therefore, in combinational circuits, an NBTI friendly input vector that stresses the least number of PMOS transistors on the critical path can be applied. For sequential circuits, the state code can significantly influence the ON/OFF mode of PMOS transistors in the controller implementation. Therefore, we propose to focus on state encoding. As the problem is computational intractable, we will focus on encoding states with high state probability. The following SA moves are employed: (a) code swap; and (b) code modification by flipping bits. Experiments with LGSYNTH93 benchmarks resulted in 18.6% improvement in NBTI degradation on average with area and power improvements of 5.5% and 4.6% respectively.

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Wan, Kai. "Advanced current-mode control techniques for DC-DC power electronic converters." Diss., Rolla, Mo. : Missouri University of Science and Technology, 2009. http://scholarsmine.mst.edu/thesis/pdf/Wan_09007dcc80642d38.pdf.

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Thesis (Ph. D.)--Missouri University of Science and Technology, 2009.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed May 4, 2009) Includes bibliographical references.

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Dissertations / Theses on the topic 'Digital power systems'

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