Journal articles: 'Digital logic circuits'

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Hasuo, S., and T. Imamura. "Digital logic circuits." Proceedings of the IEEE 77, no. 8 (1989): 1177–93. http://dx.doi.org/10.1109/5.34118.

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Duncan, Philip N., Siavash Ahrar, and Elliot E. Hui. "Scaling of pneumatic digital logic circuits." Lab on a Chip 15, no. 5 (2015): 1360–65. http://dx.doi.org/10.1039/c4lc01048e.

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We present strategies for scaling pneumatic logic circuits to smaller dimensions. Our process achieves order-of-magnitude increases in both circuit density and speed, enabling the construction of a 12-bit counter.

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Kamde, Shilpa, Jitesh Shinde, Sanjay Badjate, and Pratik Hajare. "Comparative Analysis Domino Logic Based Techniques For VLSI Circuit." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, no. 8 (March 21, 2014): 3803–8. http://dx.doi.org/10.24297/ijct.v12i8.2998.

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Domino logic is a CMOS-based evolution of the dynamic logicÂ techniques Â basedÂ onÂ eitherÂ PMOSÂ orÂ NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circuit simulation used BSIM(Berkeley Short Channel IGFET ) Model because it control leakage current.

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Hou, Yue Wei, Xin Xu, Wei Wang, Xiao Bo Tian, and Hai Jun Liu. "Titanium Oxide Memristor Based Digital Encoder Circuit." Applied Mechanics and Materials 644-650 (September 2014): 3430–33. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3430.

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Memristors have the ability to remember their last resistance and quickly switch between different states, such characteristics could make logic circuits simple in structure and fast in boolean computations. A kind of digital encoder circuit utilizing titanium oxide memristors is proposed. A logic NAND gate which acts as key part in the circuit is designed. The works in this letter also provide a practical approach for designing logic gate circuit with memristors.

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Raman, Karthik, and Andreas Wagner. "The evolvability of programmable hardware." Journal of The Royal Society Interface 8, no. 55 (June 9, 2010): 269–81. http://dx.doi.org/10.1098/rsif.2010.0212.

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In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 10 45 logic circuits (‘genotypes’) and 10 19 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry.

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Dokic, B. L. "A Review on Energy Efficient CMOS Digital Logic." Engineering, Technology & Applied Science Research 3, no. 6 (December 18, 2013): 552–61. http://dx.doi.org/10.48084/etasr.389.

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Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt) and power supply voltage (Vdd) on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed) depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL), complementary pass logic (CPL), push-pull pass logic (PPL) and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.

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Avdeev, N. A., and P. N. Bibilo. "Design of Digital Operational Units with Low Power Consumption." Programmnaya Ingeneria 12, no. 2 (March 16, 2021): 63–73. http://dx.doi.org/10.17587/prin.12.63-73.

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The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power consumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.

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Jóźwiak, Lech. "General Decomposition and Its Use in Digital Circuit Synthesis." VLSI Design 3, no. 3-4 (January 1, 1995): 225–48. http://dx.doi.org/10.1155/1995/16259.

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Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a wide diversity of logic building blocks. Although logic designers have been building circuits for many years, they have realized that advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In this paper, we present the fundamentals of a logic design methodology which meets the requirements of today's complex circuits and modem building blocks. The methodology is based on the theory of general full-decompositions which constitutes the theory of digital circuit structures at the highest abstraction level. The paper explains the theory and shows how it can be used for digital circuit synthesis. The decomposition methodology that is presented ensures “correctness by construction” and enables very effective and efficient post-factum validation. It makes possible extensive examination of the structural features of the required information processing in relation to a given set of objectives and constraints.

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Shukla, Vandana, O. P. Singh, G. R. Mishra, and R. K. Tiwari. "Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (November 1, 2015): 213. http://dx.doi.org/10.11591/ijres.v4.i3.pp213-218.

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Shifter circuits are the key component of arithmetic logic unit as well as storage unit of any digital computing device. Designing these shifter circuits using reversible logic approach leads to create low power loss digital systems. Reversible circuit design approach is nowadays widely applicable in various disciplines such as Nanotechnology, Low power CMOS design, Optical computing etc. This paper presents two design approaches for four bit binary combinational shifter circuit with the help of different types of reversible logic gates. The proposed optimized design is simulated using Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency.

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Žemva, Andrej, Andrej Trost, and Baldomir Zajc. "Educational Programmable System for Prototyping Digital Circuits." International Journal of Electrical Engineering & Education 35, no. 3 (July 1998): 236–44. http://dx.doi.org/10.1177/002072099803500306.

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In this paper, we present an educational programmable system for prototyping digital circuits. The system is composed of the PC and the prototyping board composed of 3 FPGAs. PC is used for designing a digital circuit, programming the FPGAs, automatic generation of the interface logic and hardware verification of the designed circuit.

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Saman, B., R. H. Gudlavalleti, R. Mays, J. Chandy, Evan Heller, and F. Jain. "3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs." International Journal of High Speed Electronics and Systems 29, no. 01n04 (March 2020): 2040014. http://dx.doi.org/10.1142/s0129156420400145.

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Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.

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Santhi, C., and Dr Moparthy Gurunadha Babu. "Symmetric stacked fast binary counters based on reversible logic." International Journal of Engineering & Technology 7, no. 4 (October 6, 2018): 2747. http://dx.doi.org/10.14419/ijet.v7i4.14141.

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A Symmetric Stacked Fast Binary counter design is proposed in this paper. In the circuit design, the first phase is occupied by 3-bit stacking circuits, which are further followed by combining circuits. The resultant novel circuit thus becomes a 6-bit stacker. A 6:3 counter has been chosen as an example to demonstrate the working of the proposed circuit. The proposed circuit is further implemented by using reversible logic gates. Heat dissipation is a major problem in the designing of a digital circuit. Rolf Landauer has proved that the information loss in a digital circuit is directly proportional to the energy dissipation. The proposed modified Symmetric Stacking counter is implemented using reversible logic gates thus reducing the power dissipation of the circuit.

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Galadima, B. Y., G. S. M. Galadanci, A. Tijjani, and M. Ibrahim. "A review on reversible logic gates." Bayero Journal of Pure and Applied Sciences 12, no. 1 (April 15, 2020): 242–50. http://dx.doi.org/10.4314/bajopas.v12i1.38s.

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In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit. Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic,

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Y. N., Sharath Kumar, and Dinesha P. "TFI-FTS: An efficient transient fault injection and fault-tolerant system for asynchronous circuits on FPGA platform." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 3 (June 1, 2021): 2704. http://dx.doi.org/10.11591/ijece.v11i3.pp2704-2710.

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Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the faults based on BMA based LFSR with faulty logic insertion and one hot encoded register. The BMA based LFSR reduces the hardware complexity with less power consumption on-chip than standard LFSR method. The FTS uses triple mode redundancy (TMR) based majority voter logic (MVL) to tolerant the faults for asynchronous circuits. The benchmarked 74X-series circuits are considered as an asynchronous circuit for TMR logic. The TFI-FTS module is modeled using Verilog-HDL on Xilinx-ISE and synthesized on hardware platform. The Performance parameters are tabulated for TFI-FTS based asynchronous circuits. The performance of TFI-FTS Module is analyzed with 100% fault coverage. The fault coverage is validated using functional simulation of each asynchronous circuit with fault injection in TFI-FTS Module.

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Al-Rabadi, Anas. "Three-dimensional lattice logic circuits, Part I: Fundamentals." Facta universitatis - series: Electronics and Energetics 18, no. 1 (2005): 1–13. http://dx.doi.org/10.2298/fuee0501001a.

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Fundamentals of regular three-dimensional (3D) lattice circuits are introduced. Lattice circuits represent an important class of regular circuits that allow for local interconnections, predictable timing, fault localization, and self-repair. In addition, three-dimensional lattice circuits can be potentially well suited for future 3D technologies, such as nanotechnologies, where the intrinsic physical delay of the irregular and lengthy interconnections limits the device performance. Although the current technology does not offer a menu for the immediate physical implementation of the proposed three-dimensional circuits, this paper deals with three-dimensional logic circuit design from a fundamental and foundational level for a rather new possible future directions in designing digital logic circuits.

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Lin, Shan, Tao Lin, and Zhan Wen Liu. "A Discussion of the Design Method of Full Adder Circuit." Applied Mechanics and Materials 135-136 (October 2011): 15–20. http://dx.doi.org/10.4028/www.scientific.net/amm.135-136.15.

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A bit full adder is a very important component in the digital system. Design of a full-adder circuit, as an example, by changing its output function expression in the form of expression, use the gates, decoder, multiplexer etc 74 series devices, the eight circuits realization form are given respectively, and briefly analyzed the advantages and disadvantages of the various circuit implementation. The example show that the design of combinational logic circuits has mobility and variety, it could give the instructiveness and the guiding for other design of combinational logic circuits.

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Hossain, M., M. P. Singh, and J. K. Rakshit. "Modelling of one-bit Arithmetic Logic Circuit using silicon micro-ring resonator." Journal of Physics: Conference Series 2335, no. 1 (September 1, 2022): 012003. http://dx.doi.org/10.1088/1742-6596/2335/1/012003.

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Abstract All-optical technology overcomes the problems that arise in traditional digital circuits such as speed limitation, energy consumption and size. In this manuscript, we have implemented a one-bit arithmetic logic circuit employing all-optical silicon micro-ring resonator that utilizes the advantages over other all-optical techniques. The Arithmetic logic circuit is the core component of ultra-fast combinational circuits. The proposed arithmetic logic circuit is validated through MATLAB at about 260 Gbps. Performance of our design has been investigated by numerical simulation. The critical parameters of MRR are optimized on the basis of performance metrics.

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Wang, Lu, Hongyu Zhu, Ze Zuo, and Dianzhong Wen. "Full-function logic circuit based on egg albumen resistive memory." Applied Physics Letters 121, no. 24 (December 12, 2022): 243505. http://dx.doi.org/10.1063/5.0124826.

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The logic gate is the basic unit of a digital circuit structure. The operation, memory, I/O, and other reading and writing functions of computer systems require logic circuits. Logic gates based on resistive memory can make existing integrated circuits denser, smaller, faster, and use fewer devices. In this paper, Al/polymethyl methacrylate (PMMA)/egg albumen (EA):Au nanoparticles/PMMA/Al multilayer biological resistive random access memory was prepared based on the natural biological material—egg albumen (EA). The device has bipolar switching behavior, a higher switching current ratio, a lower threshold voltage, and better stability. A circuit based on auxiliary logic is constructed using this device, and the logic functions of AND, OR, NOT, NAND, and NOR are realized. This device provides an effective potential solution for implementing high-performance electronic devices and large-scale integrated circuits.

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Ferreira Pontes, Matheus, Clayton Farias, Rafael Schvittz, Paulo Butzen, and Leomar Da Rosa Jr. "Survey on Reliability Estimation in Digital Circuits." Journal of Integrated Circuits and Systems 16, no. 3 (December 31, 2021): 1–11. http://dx.doi.org/10.29292/jics.v16i3.568.

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The aggressive technology scaling has significantly affected the circuit reliability. The interaction of environmental radiation with the devices in the integrated circuits (ICs) may be the dominant reliability aspect of advanced ICs. Several techniques have been explored to mitigate the radiation effects and guarantee a satisfactory reliability levels. In this context, estimating circuit radiation reliability is crucial and a challenge that has not yet been overcome. For decades, several different methods have been proposed to provide circuit reliability. Recently, the radiation effects have been more faithfully incorporated in these strategies to provide the circuit susceptibility more accurately. This paper overviews the current trend for estimating the radiation reliability of digital circuits. The survey divides the approaches into two abstraction levels: (i) gate-level that incorporate the layout information and (ii) circuit-level that traditionally explore the logic circuit characteristic to provide the radiation susceptibility of combinational circuits. We also present an open-source tool that incorporates several previously explored methods. Finally, the actual research aspects are discussed, providing the newly emerging topic, such as selective hardening and critical vector identification.

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Li, Hongtao, Chunbiao Li, Zeshi Yuan, Wen Hu, and Xiaochen Zhen. "A New Class of Chaotic Circuit with Logic Elements." Journal of Circuits, Systems and Computers 24, no. 09 (August 27, 2015): 1550136. http://dx.doi.org/10.1142/s0218126615501364.

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When signum operation is applied in chaotic systems to realize piecewise-linearity, the original nonlinearity turns to be a kind of Boolean calculation, and correspondingly the chaotic circuit can be implemented by an analog structure embedded with some logic-gate circuits. In this paper, as examples based on the diffusionless Lorenz system we proposed a couple of chaotic flows with signum piecewise-linearity, which experimentally resorts to digital gate circuits. The experimental chaotic circuit with logic elements was built, and the oscillation in the physical circuit agrees well with the numerical simulation.

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Simonetta, Alessandro, and Maria Cristina Paoletti. "Designing Digital Circuits in Multi-Valued Logic." International Journal on Advanced Science, Engineering and Information Technology 8, no. 4 (July 31, 2018): 1166. http://dx.doi.org/10.18517/ijaseit.8.4.5966.

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Hauser, J. R. "Noise margin criteria for digital logic circuits." IEEE Transactions on Education 36, no. 4 (1993): 363–68. http://dx.doi.org/10.1109/13.241612.

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Shukla, Vandana, O. P. Singh, G. R. Mishra, and R. K. Tiwari. "A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate." International Journal of Business Data Communications and Networking 11, no. 1 (January 2015): 36–49. http://dx.doi.org/10.4018/ijbdcn.2015010104.

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In the recent scenario of microelectronic industry, the reversible logic is considered as the burgeonic technology for digital circuit designing. It deals with the aim to generate digital circuits with zero power loss characteristics. Optical computing, Nanotechnology, Low power CMOS design and Digital Signal Processing (DSP) processors are leading areas of development with the concept of reversible logic. Researchers have already proposed various subsystems of the computer for the creation of low power loss devices with the help of numerous available reversible logic gates. Here in this paper, the authors have proposed a new reversible gate named as CDSM gate with 4×4 size. This CDSM gate is used to design optimized 4-bit binary comparator. The optimization is improved as compared to the existing designs based on some significant performance parameters such as total number of gates, garbage outputs generated, constant inputs and quantum cost. Comparators are widely used in various computing applications such as counters, convertor, Central Processing Unit (CPU) and control circuits etc. The comparator circuits using reversible logic can be visualized as a low power loss subsystem for the development of improved digital systems.

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BROCK, DARREN K. "RSFQ TECHNOLOGY: CIRCUITS AND SYSTEMS." International Journal of High Speed Electronics and Systems 11, no. 01 (March 2001): 307–62. http://dx.doi.org/10.1142/s0129156401000861.

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Rapid Single-Flux-Quantum (RSFQ) logic is a superconductor IC technology that, with only a modest number of researchers worldwide, has produced some of the world's highest performance digital and mixed-signal circuits. This achievement is due, in part, to a constellation of characteristics that manifest themselves at the circuit level – namely, high-speed digital logic at low-power, ideal interconnects, quantum accuracy, scalability, and simplicity of fabrication. A necessary key to translating these advantages to the system-level involves understanding the I/O, synchronization, and packaging issues associated with a cryogenic technology. The objective of this paper is to review the status of current RSFQ circuit-level infrastructure components and their potential impact on system-level applications.

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Huang, Mingqiang, Xingli Wang, Guangchao Zhao, Philippe Coquet, and Bengkang Tay. "Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials." Applied Sciences 9, no. 20 (October 9, 2019): 4212. http://dx.doi.org/10.3390/app9204212.

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With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS2 and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrated circuits. Various ternary logic devices, including the standard ternary inverter (STI), negative ternary inverter (NTI), positive ternary inverter (PTI) and especially the ternary decrement cycling inverter (DCI), have been successfully implemented using the 2D materials. Then, by taking advantage of the optimized ternary adder algorithm and the novel ternary cycling inverter, we design a novel ternary ripple-carry adder with great circuitry simplicity. Our design shows about a 50% reduction in the required number of transistors compared to the existing ternary technology. This work paves a new way for the ternary integrated circuits design, and shows potential to fulfill higher logic data density and a smaller chip area in the future.

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Wang, Zicheng, Zijie Cai, Zhonghua Sun, Jian Ai, Yanfeng Wang, and Guangzhao Cui. "Research of Molecule Logic Circuit Based on DNA Strand Displacement Reaction." Journal of Computational and Theoretical Nanoscience 13, no. 10 (October 1, 2016): 7684–91. http://dx.doi.org/10.1166/jctn.2016.5194.

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Because of its outstanding advantages, DNA strand displacement (DSD) reaction has been widely used for signals processing and molecular logic circuit constructing. Two digital logic circuits are constructed in this paper. One is the encoder circuit with four inputs and two outputs, and the other is the decoder circuit with two inputs and four outputs. Of particular interest to us is the multicolor fluorescent gold nanoprobe detection part, where a gold nanoparticle is modified with multicolor fluorophores which exploits the ultrahigh quenching ability of gold nanoparticles (AuNPs). Finally, the circuits can be programmed and simulated with the software Visual DSD. The simulated results based on DSD show that the molecular circuits constructed in this paper is reliable and effective, which has wide prospects in logical circuits and nano-electronics study.

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Naveenkumar, Majety. "Novel Design of Reversible MUX and DEMUX using GDI Techinque." International Journal of Advances in Applied Sciences 4, no. 3 (September 1, 2015): 103. http://dx.doi.org/10.11591/ijaas.v4.i3.pp103-108.

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Now a day’s Reversible logic is playing a crucial role in designing of digital circuits and it is used in reducing power consumption in digital design. By regaining the bit loss it reduces the power consumption in digital circuits. Gate diffusion input (GDI) is a technique of low-power digital circuit design. This technique reduces the power consumption, delay, and transistor count by maintaining the complexity very low of logic design. In these paper a novel MUX and DEMUX has been presented, which can be extended up to 1:2n and 2n:1 respectively and these are developed by using only one type of Reversible gate i.e. Fredkin Gate (FRG) and Not Gate. The simulations are done in H-Spice using 90nm technology.

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Fadaei, Mohammadreza. "Designing ALU using GDI method." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 3 (November 1, 2019): 151. http://dx.doi.org/10.11591/ijres.v8.i3.pp151-161.

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<p>As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical need for integrated circuits today. In this study, we deal with GDI techniques for designing logic and arithmetic circuits. We show that this logic in addition to low power consumption has little complexity so that arithmetic and logic circuits can be implemented with fewer transistors. Various circuits such as adders, differentiation and multiplexers, etc. have been designed and implemented using these techniques, and published in various articles. In this study, we review and evaluate the advantages and disadvantages of these circuits.</p>

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Dilshad, Sk, Gannu Akhil, Simhadri RajaNandini, Javeria Unissa, and Pulapakori Yadav Chandu. "Design and Implementation of Seven Segment Display Using Reversible Logic Gates." International Journal for Research in Applied Science and Engineering Technology 10, no. 11 (November 30, 2022): 1500–1504. http://dx.doi.org/10.22214/ijraset.2022.47523.

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Abstract: An important issue in Seven segment display is heat, but the reversible logic gives less amount of heat dissipation. So, it’s an important role in nanotechnology, less energy complementary metal oxide semiconductor CMOS designs etc. Seven segment displays are most effective devices used in electronic meters, digital calculators, clock radios, digital clocks, odometers, displays in home appliances, etc.In this project, an efficient seven segment display is designed using reversible logic gates CNOT, FREDKIN and PERES gates. Retrievability is a feature which every electronic device wants to posses , In reversible logic gates the inputs and outputs can be retrievable from each other. Backward operation is used in this circuit which allows to retrieve the inputs from the outputs therefore consuming zero power. Reversible logic circuits are also known as lossless circuits, which has neither information loss nor energy loss. The reversible logic operations dissipate less heat and can't erase information.

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Kumaresan, Raja Sekar, Marshal Raj, and Lakshminarayanan Gopalakrishnan. "Design and implementation of a nano magnetic logic barrel shifter using beyond-CMOS technology." Journal of Electrical Engineering 73, no. 1 (February 1, 2022): 1–10. http://dx.doi.org/10.2478/jee-2022-0001.

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Abstract Bit manipulation plays a significant role in high-speed digital signal processing (DSP) and data computing systems, and shift and rotation operations are crucial functions in it. In general, barrel shifters are used to perform these operations effectively. Nano magnetic logic circuits are among the promising beyond-CMOS alternative technologies for the design of high-speed circuits. Most of the existing circuits that have been developed using nano magnets are combinational circuits. In this work, a barrel shifter is implemented and realised using in-plane nano magnetic logic. The proposed design is the first of its kind nano magnetic logic circuit. The nano magnetic logic circuit implementation, layout generation, simulation, and validation were performed using the ToPoliNano and ModelSim tools. The logical equivalent design was synthesised and evaluated using the Synopsys Design Compiler tool. The proposed barrel shifter was realised using majority logic has 1769037 nano magnets with a boxing area of 481 × 13104 µm2 and 3276 clock zones after optimisation with the Barycenter algorithm. The proposed barrel shifter realised using Boolean logic has 315276 nano magnets with a boxing area of 265 × 5028 µm2 and 1257 clock zones after optimisation with the Barycenter algorithm. The proposed design results demonstrate that complex systems can be developed using nano magnetic logic by combining combinational and sequential circuits.

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LIU, YUYU, JINGUO QUAN, HUAZHONG YANG, and HUI WANG. "MOS CURRENT MODE LOGIC CIRCUITS: DESIGN CONSIDERATION IN HIGH-SPEED LOW-POWER APPLICATIONS AND ITS FUTURE TREND, A TUTORIAL." International Journal of High Speed Electronics and Systems 15, no. 03 (September 2005): 599–614. http://dx.doi.org/10.1142/s0129156405003351.

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In this paper, a logic style that is becoming increasingly popular is presented, which is called MOS Current Mode Logic (MCML). MCML is a novel and useful logic style for high-speed, low-power and mixed-signal applications. Its high-speed switching, low supply voltage and reduced output voltage swing contribute to its high performance, low power dissipation, and low noise features. MCML circuits are compared to several other logic styles, such as conventional static CMOS, dynamic logic, and traditional emitter coupled logic (ECL) in terms of power, delay and common mode noise immunity. MCML circuits seem to be very promising in high-speed, low-power and mixed-signal digital circuit applications, such as portable electronic devices, gigahertz microprocessors, and optical transceivers.

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MOORE, PHILLIP W., and GANESH K. VENAYAGAMOORTHY. "EVOLVING DIGITAL CIRCUITS USING HYBRID PARTICLE SWARM OPTIMIZATION AND DIFFERENTIAL EVOLUTION." International Journal of Neural Systems 16, no. 03 (June 2006): 163–77. http://dx.doi.org/10.1142/s0129065706000585.

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This paper presents the evolution of combinational logic circuits by a new hybrid algorithm known as the Differential Evolution Particle Swarm Optimization (DEPSO), formulated from the concepts of a modified particle swarm and differential evolution. The particle swarm in the hybrid algorithm is represented by a discrete 3-integer approach. A hybrid multi-objective fitness function is coined to achieve two goals for the evolution of circuits. The first goal is to evolve combinational logic circuits with 100% functionality, called the feasible circuits. The second goal is to minimize the number of logic gates needed to realize the feasible circuits. In addition, the paper presents modifications to enhance performance and robustness of particle swarm and evolutionary techniques for discrete optimization problems. Comparison of the performance of the hybrid algorithm to the conventional Karnaugh map and evolvable hardware techniques such as genetic algorithm, modified particle swarm, and differential evolution are presented on a number of case studies. Results show that feasible circuits are always achieved by the DEPSO algorithm unlike with other algorithms and the percentage of best solutions (minimal logic gates) is higher.

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33

Tyurin, S. F., A. Yu Skornyakova, Y. A. Stepchenkov, and Y. G. Diachenko. "SELF-TIMED LOOK UP TABLE FOR ULAs AND FPGAs." Radio Electronics, Computer Science, Control 1, no. 1 (March 24, 2021): 36–45. http://dx.doi.org/10.15588/1607-3274-2021-1-4.

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Context. Self-Timed Circuits, proposed by D. Muller on the rise of the digital era, continues to excite researchers’ minds. These circuits started with the task of improving performance by taking into account real delays. Then Self-Timed Circuits have moved into the field of green computing. At last, they are currently positioned mainly in the field of fault tolerance. There is much redundancy in Self-Timed Circuits. It is believed that Self-Timed Circuits approaches will be in demand in the nano-circuitry when a synchronous approach becomes impossible. Strictly Self-Timed Circuits check transition process completion for each gate’s output. For this, they use so-called D. Muller elements (C-elements, hysteresis flip-flops, G-flip-flops). Usually, Self-Timed Circuits are designed on Uncommitted Logic Array. Now an extensive base of Uncommitted Logic Array Self-Timed gates exists. It is believed that SelfTimed Circuits are not compatible with FPGA technology. However, attempts to create self-timed FPGAs do not stop. The article proposes a Self-Timed Lookup Table for the Self-Timed Uncommitted Logic Array and the Self-Timed FPGA, carried out either by constants or utilizing additional memory cells. Authors proposed 1,2 – Self-Timed Lookup Table and described simulation results. Objective. The work’s goal is the analysis and design of the Strictly Self-Timed universal logic element based on Uncommitted Logic Array cells and pass-transistors circuits. Methods. Analysis and synthesis of the Strictly Self-Timed circuits with Boolean algebra. Simulation of the proposed element in the CAD “ARC”, TRANAL program, system NI Multisim by National Instruments Electronics Workbench Group, and layout design by Microwind. The reliability theory and reliability calculations in PTC Mathcad. Results. Authors designed, analyzed, and proved the Self-Timed Lookup Table’s workability for the Uncommitted Logic Arrays and FPGAs. Layouts of the novel logic gates are ready for manufacturing. Conclusions. The conducted studies allow us to use proposed circuits in perspective digital devices.

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Sharmila Devi, S., and V. Bhanumathi. "Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits." Computers, Materials & Continua 70, no. 2 (2022): 3609–24. http://dx.doi.org/10.32604/cmc.2022.020426.

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Ramsay, E. P., D. T. Clark, J. D. Cormack, A. E. Murphy, D. A. Smith, R. F. Thompson, R. A. R. Young, and S. Finney. "Digital and Analogue Integrated Circuits in Silicon Carbide for High Temperature Operation." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000373–77. http://dx.doi.org/10.4071/hitec-thp11.

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A need for high temperature integrated circuits is emerging in a number of application areas. As Silicon Carbide power discrete devices become more widely available, there is a growing need for control ICs capable of operating at the same temperatures and mounted on the same modules. Also, the use of high temperature sensors, in, for example, aero engines and in deep hydrocarbon and geothermal drilling applications results in a demand for high temperature sensor interface ICs. This paper presents new results on a range of simple logic and analogue circuits fabricated on a developing Silicon Carbide CMOS process which is intended for mixed signal integrated circuit applications such as those above. A small family of logic circuits, pin compatible with the 74xx series TTL logic parts, has been designed, fabricated and tested and includes, for example, a Quad Nand gate and a Dual D-type flip-flop. These have been found to be functional from room temperature up to 400°C. Analogue blocks have been investigated with a view to using switched capacitor or autozero techniques to compensate for temperature and time induced drifts, allowing very high temperature operation.

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Assaf, Mansour, Leslie-Ann Moore, Sunil Das, Satyendra Biswas, and Scott Morton. "Low-level logic fault testing ASIC simulation environment." World Journal of Engineering 11, no. 3 (June 1, 2014): 279–86. http://dx.doi.org/10.1260/1708-5284.11.3.279.

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A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.

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Bhoi, Bandan Kumar, Nirupma Pathak, Santosh Kumar, and Neeraj Kumar Misra. "Designing digital circuits using 3D nanomagnetic logic architectures." Journal of Computational Electronics 20, no. 3 (February 5, 2021): 1310–25. http://dx.doi.org/10.1007/s10825-020-01647-7.

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Milter, O., and A. Kolodny. "Crosstalk noise reduction in synthesized digital logic circuits." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11, no. 6 (December 2003): 1153–58. http://dx.doi.org/10.1109/tvlsi.2003.817551.

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Hajj, I. N., and I. N. D. Saab. "Switch-Level Logic Simulation of Digital Bipolar Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 2 (March 1987): 251–58. http://dx.doi.org/10.1109/tcad.1987.1270269.

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Goñi-Moreno, Angel. "On genetic logic circuits: forcing digital electronics standards?" Memetic Computing 6, no. 3 (June 21, 2014): 149–55. http://dx.doi.org/10.1007/s12293-014-0136-8.

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Falkowski, Bogdan J. "Spectral Testing of Digital Circuits." VLSI Design 14, no. 1 (January 1, 2002): 83–105. http://dx.doi.org/10.1080/10655140290009828.

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Fault detection techniques using data compression methods have evolved during the last few years. Considerable work using individual Walsh spectral coefficients has been reported. In this paper, the application of spectral methods in testing of digital circuits with the emphasis on their usage for both input and output test compaction of digital circuits is described. Two closely related testing methods are discussed: syndrome testing and spectral testing as well as an overview of syndrome-testing and syndrome-testable design is presented. The necessary background and notation on Walsh spectral coefficients as well as their meaning in classical logic terms is shown.

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Xu, Haoran, Jianghua Ding, and Jian Dang. "Design and Characteristics of CMOS Inverter based on Multisim and Cadence." Journal of Physics: Conference Series 2108, no. 1 (November 1, 2021): 012034. http://dx.doi.org/10.1088/1742-6596/2108/1/012034.

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Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for various types of communications. Based on multisim 14.0 and cadence, the characteristics and performance of CMOS inverter are studied by simulation.

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Chen, Ling, and Zhong Liang Pan. "Fault Detection of Bridging Faults in Digital Circuits by Shared Binary Decision Diagram." Key Engineering Materials 439-440 (June 2010): 1235–40. http://dx.doi.org/10.4028/www.scientific.net/kem.439-440.1235.

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A new test generation method for the bridging faults in digital circuits is proposed in this paper, the method is based on shared binary decision diagram. The shared binary decision diagram can represent many logic functions simultaneously by sharing isomorphic subgraphs, it is used to represent the digital circuits with multiple primary outputs. The binary decision diagram is constructed respectively for the normal circuit and faulty circuit having a bridging fault. The test vectors of the bridging fault can be produced by a XOR operation of the two binary decision diagrams. The experimental results on a lot of benchmark circuits demonstrate that the test method proposed in this paper can get the test vectors of the bridging faults if the faults are testable.

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Gavrilenkov, Sergey I., Elizaveta O. Petrenko, and Evgeny V. Arbuzov. "A Digital Device for Automatic Checking of Homework Assignments in the Digital Circuits Course." ITM Web of Conferences 35 (2020): 04009. http://dx.doi.org/10.1051/itmconf/20203504009.

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This paper considers a digital device for automatic checking of homework assignments in the digital circuits course. The assignment is to make a digital circuit corresponding to a given logical expression; the circuit is comprised of elementary logic gates. The process of manual testing the built circuit is very labor-intensive because checking a circuit with N inputs variables requires checking the correctness of the output variable for 2N cases. We propose automating this pro-cess with a special digital device. The device is comprised of a microcontroller connected to the circuit tested. The microcontroller is connected to a personal computer with an application written in C# for executing the main operations of the testing process. During testing, the student chooses from a database or enters the logical expression corresponding to the circuit tested. For the expression, the software generates truth tables where actual and required responses of the circuit are given. Actual circuit responses are acquired by probing the circuit via the microcontroller, and the expected values are calculated from the logical expression. The truth tables are then presented to the student with a message of whether the circuit works correctly or not. The device was integrated into the process of checking homework assignments in the digital electronics course, and it significantly sped up the process of checking homework assignment circuits, resulting in better education quality.

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Hudli, Anand V., and Raghu V. Hudli. "Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits." VLSI Design 2, no. 1 (January 1, 1994): 69–80. http://dx.doi.org/10.1155/1994/94514.

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Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.

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Kumagai, Masaaki, and Takashi Emura. "Development of a Universal Interface Board and its Application to Robot Controllers and Signal Processors." Journal of Robotics and Mechatronics 16, no. 2 (April 20, 2004): 200–207. http://dx.doi.org/10.20965/jrm.2004.p0200.

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Multipurpose digital interface boards for the PCI bus were designed for robot controllers. They used a programmable logic device reconfigured for internal circuits. The user plugs the board in, then downloads circuit data to obtain various interfaces. Optional modules such as analog front ends and support software also were developed. The board enables rapid prototyping and flexible use of high-speed digital circuits. Three applications of the board — robot interfaces of DC servomotors for a walking robot, high-speed digital signal processing for a motion capture system, and pipelined image processing units — showed the effectiveness of the board.

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Muñoz-Quijada, Maria, Samuel Sanchez-Barea, Daniel Vela-Calderon, and Hipolito Guzman-Miranda. "Fine-Grain Circuit Hardening Through VHDL Datatype Substitution." Electronics 8, no. 1 (December 25, 2018): 24. http://dx.doi.org/10.3390/electronics8010024.

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Radiation effects can induce, amongst other phenomena, logic errors in digital circuits and systems. These logic errors corrupt the states of the internal memory elements of the circuits and can propagate to the primary outputs, affecting other onboard systems. In order to avoid this, Triple Modular Redundancy is typically used when full robustness against these phenomena is needed. When full triplication of the complete design is not required, selective hardening can be applied to the elements in which a radiation-induced upset is more likely to propagate to the main outputs of the circuit. The present paper describes a new approach for selectively hardening digital electronic circuits by design, which can be applied to digital designs described in the VHDL Hardware Description Language. When the designer changes the datatype of a signal or port to a hardened type, the necessary redundancy is automatically inserted. The automatically hardening features have been compiled into a VHDL package, and have been validated both in simulation and by means of fault injection.

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Chandna, A., R. B. Brown, D. Putti, and C. D. Kibler. "Power rail logic: a low power logic style for digital GaAs circuits." IEEE Journal of Solid-State Circuits 30, no. 10 (1995): 1096–100. http://dx.doi.org/10.1109/4.466073.

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Zhongliang, Pan, Chen Ling, and Chen Yihui. "Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits." Open Electrical & Electronic Engineering Journal 8, no. 1 (September 16, 2014): 104–10. http://dx.doi.org/10.2174/1874129001408010104.

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The VLSI technology has led to the increased complexity in hardward design, therefore the verification for the correctness of circuit operations has become an exrtremely important task. The verification procedure can be reduced by means of the equivalent signal lines in the circuits. In this paper, a new method is presented for determining the equivalent signal lines, the method utilizes the weight value assignment of signal lines in circuits. First of all, the method makes use of the topological information of circuits to perform forward weight value assignments, assign weight values to the signal lines from the primary inputs to primary outputs. Afterwards, carry out the backward weight value assignment, assign weight values to the signal lines from the primary outputs to primary inputs. Secondly, carry out the random pattern simulation to further check the equivalence of signal lines. A lot of experimental results show that the verification of digital circuits can be carried out effectively by using the method proposed in this paper, the time being needed for the verification procedure can be cut down by utilizing the equivalent signal lines.

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Xu, Xingjian, Tian Ban, and Yuehua Li. "SPLM: A Flexible and Accurate Reliability Assessment Model for Logic Circuits." Journal of Circuits, Systems and Computers 28, no. 02 (November 12, 2018): 1950032. http://dx.doi.org/10.1142/s0218126619500324.

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Reliability evaluation by using probabilistic computational models has become an important research field in modern digital designs. Based on the profound understanding of different reliability evaluation methods, this paper proposes a universal model for signal probability and reliability analysis of logic circuits. The proposed Signal Probability Level Matrix (SPLM) provides us with the reliability and signal probability of the entire circuit as well as individual outputs. We can deal with SPLM very flexibly depending on different applications and design constraints. The accuracy and efficiency of the proposed model have been proved and verified by representative circuits in literatures. Furthermore, the proposed model is particularly useful in reliability assessment in cascade-structure circuits such as ripple carry adders.

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Journal articles on the topic 'Digital logic circuits'

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