Journal articles on the topic 'Digital IC hardware'
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Ananth, G. S., N. Shylashree, Satish Tunga, and Latha B. N. "A novel design for hardware interface board with reduced resource utilization." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 3 (December 1, 2021): 1414. http://dx.doi.org/10.11591/ijeecs.v24.i3.pp1414-1420.
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The final cost of an integrated circuit (IC) is proportional to its testing time. One of the main goals of test engineers when building an IC test solution is to reduce test time. Reduction of Test time is achieved by multi-site testing where multiple ICs are tested simultaneously using automated test equipment (ATE). During multi-site testing, if a certain test requires abundant resources, it is accomplished by testing one set of ICs at a time while the other ICs remain idle, thus lengthening the total test time. In digital-analog hybrid ICs, both analog and digital tests need to be performed, increasing the tester resource requirement and causing digital resource shortage. This paper describes a hardware interface board (HIB) design for a test case of a digital-analog IC on Teradyne’s ETS-364 ATE. The HIB's design allows the ATE to perform multi-site I<sup>2</sup>C based tests, which usually require lot of tester resources, utilizing only two digital resources and one measurement resource. This design achieves halving the I2C test time while lowering the number of resources necessary for multi-site testing compared to set-by-set testing. The proposed work has achieved up to 90.625% of resource reduction for multisite testing for a single test.
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Ni, Zhong Jin, Liang Fang, and Mao Jun Chen. "Realization of A Data Communication Card for A High Speed Digital Electronic Engraving Machine." Advanced Materials Research 476-478 (February 2012): 979–83. http://dx.doi.org/10.4028/www.scientific.net/amr.476-478.979.
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As the digital electronic engraving machine needs high speed and credible communication between a host computer and a slave computer, a data communication card for a high speed digital electronic engraving machine is designed and realized using PDIUSBD12 IC and S3C44B0X IC. PDIUSBD12 IC is USB interface device with parallel bus. In the paper, hardware circuit is described, USB driver program is depicted in detail based on the µC/OS-Ⅱ operation system, and the ways and means of debugging the data communication card are given. It has been experimentally validated that the data communication card is applied successfully and works steadily in high speed digital electronic engraving machines.
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Chien, Wei-Chen, Yu-Chian Chang, Yao-Tung Tsou, Sy-Yen Kuo, and Ching-Ray Chang. "STT-DPSA: Digital PUF-Based Secure Authentication Using STT-MRAM for the Internet of Things." Micromachines 11, no. 5 (May 15, 2020): 502. http://dx.doi.org/10.3390/mi11050502.
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Physical unclonable function (PUF), a hardware-efficient approach, has drawn a lot of attention in the security research community for exploiting the inevitable manufacturing variability of integrated circuits (IC) as the unique fingerprint of each IC. However, analog PUF is not robust and resistant to environmental conditions. In this paper, we propose a digital PUF-based secure authentication model using the emergent spin-transfer torque magnetic random-access memory (STT-MRAM) PUF (called STT-DPSA for short). STT-DPSA is an original secure identity authentication architecture for Internet of Things (IoT) devices to devise a computationally lightweight authentication architecture which is not susceptible to environmental conditions. Considering hardware security level or cell area, we alternatively build matrix multiplication or stochastic logic operation for our authentication model. To prove the feasibility of our model, the reliability of our PUF is validated via the working windows between temperature interval (−35 ∘ C, 110 ∘ C) and Vdd interval [0.95 V, 1.16 V] and STT-DPSA is implemented with parameters n = 32, i = o = 1024, k = 8, and l = 2 using FPGA design flow. Under this setting of parameters, an attacker needs to take time complexity O( 2 256 ) to compromise STT-DPSA. We also evaluate STT-DPSA using Synopsys design compiler with TSMC 0.18 um process.
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FIELDS, C. H., M. SOKOLICH, S. THOMAS, K. ELLIOT, and J. JENSEN. "Progress toward 100 GHz Logic in InP HBT IC Technology." International Journal of High Speed Electronics and Systems 11, no. 01 (March 2001): 217–43. http://dx.doi.org/10.1142/s0129156401000836.
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Future wideband communications, mm-wave digital synthesis, and digital beam-steering will benefit from digital operation at clock frequencies between 50 and 100 GHz at reasonable power levels. HRL has developed InP-based HBT technology that is capable of supporting these needs. We have demonstrated InP HBTs with cutoff frequencies, ft, over 200 GHz and with f max over 300 GHz as well as fully static dividers operating at 72.8 GHz.
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Wang, Jing Xia. "Design of Intelligent Management System for Open Labs Based on Wireless Transmission." Applied Mechanics and Materials 631-632 (September 2014): 889–93. http://dx.doi.org/10.4028/www.scientific.net/amm.631-632.889.
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This paper describes the design ideas of intelligent management system for open labs based on wireless transmission. The student legal identity authentication is completed using IC cards and the equipments power supply is controlled using wireless digital transceiver chip nRF401.The system hardware is simple, no complex wiring, easy to use. It can be used in any laboratory of electronic equipment, has the very good practicability and wide application prospects.
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OTSUJI, TAIICHI, KOICHI MURATA, KOICHI NARAHARA, KIMIKAZU SANO, EIICHI SANO, and KIMIYOSHI YAMASAKI. "20-40-Gbit/s-CLASS GaAs MESFET DIGITAL ICs FOR FUTURE OPTICAL FIBER COMMUNICATIONS SYSTEMS." International Journal of High Speed Electronics and Systems 09, no. 02 (June 1998): 399–435. http://dx.doi.org/10.1142/s0129156498000191.
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This paper describes recent advances in high-speed digital IC design technologies based on GaAs MESFETs for future high-speed optical communications systems. We devised new types of a data selector and flip-flops, which are key elements in performing high-speed digital functions (signal multiplexing, decision, demultiplexing, and frequency conversion) in front-end transmitter/receiver systems. Incorporating these circuit design technologies with state-of-the-art 0.12 μm gate-length GaAs MESFET process, we developed a DC-to-44-Gbit/s 2:1 data multiplexer IC, a DC-to 22-Gbit/s static decision IC, and a 20-to-40-Gbit/s dynamic decision IC. The fabricated ICs demonstrated record speed performances for GaAs MESFETs. Although further operating speed margin is still required, the GaAs MESFET is a potential candidate for 20- to 40-Gbit/s class applications.
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Chen, Qiang, Zhixin Tie, Liang Hong, Youtian Qu, and Dengwen Wang. "Improved Search Algorithm of Digital Speckle Pattern Based on PSO and IC-GN." Photonics 9, no. 3 (March 9, 2022): 167. http://dx.doi.org/10.3390/photonics9030167.
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Digital speckle correlation method has not only been widely used in a variety of photometric mechanical scenarios, but also integrated with multiple disciplines. In the future, it will even be inextricably linked to the Internet of Things, autonomous driving, deep learning and other fields. For a given hardware condition, it is of great significance to improve the efficiency of integer-pixel search and increase the accuracy and efficiency of the sub-pixel algorithm. In this paper, we propose an improved digital speckle correlation method, which consists of an integer-pixel search algorithm and a sub-pixel search algorithm. With respect to the integer-pixel search, aiming to address the two problems of uniqueness of maximum value and parameter setting of PSO-W algorithm, the algorithm PSO-1 is proposed, and the results of comparison experiments show that it has higher search efficiency. In terms of sub-pixels, based on IC-GN algorithm with the highest accuracy at present, the IV-ICGN algorithm is proposed, and the simulation experiment results show that the proposed algorithm has higher accuracy and higher efficiency than the comparison algorithm.
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Brück, Rainer. "Dingo-XT: A technology description language for analog and digital IC layout." Integration 17, no. 1 (August 1994): 53–81. http://dx.doi.org/10.1016/0167-9260(94)90020-5.
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LONG, STEPHEN I. "HIGH SPEED DIGITAL CIRCUIT TECHNOLOGY." International Journal of High Speed Electronics and Systems 06, no. 01 (March 1995): 163–210. http://dx.doi.org/10.1142/s0129156495000055.
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The performance of high speed digital integrated circuits, defined here as those requiring operation at high clock frequency, is generally more sensitive to material properties and process techniques than ICs used at lower frequencies. Obtaining high speed and low power concurrently is especially challenging. Circuit architectures must be selected for the device and application appropriately. This paper presents simple models for high speed digital IC performance and applies these to the FET and bipolar transistor. Heterojunction devices are compared with those using single or binary materials. Circuits for high speed SSI and low power VLSI applications are described, and their performance is surveyed.
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Kung, Ying-Shieh, Jin-Mu Lin, Yu-Jen Chen, and Hsin-Hung Chou. "ModelSim/Simulink Cosimulation and FPGA Realization of a Multiaxis Motion Controller." Mathematical Problems in Engineering 2015 (2015): 1–17. http://dx.doi.org/10.1155/2015/202474.
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This paper is to implement a multiaxis servo controller and a motion trajectory planning within one chip. At first, SoPC (system on a programmable chip) technology which is composed of an Altera FPGA (field programmable gate arrays) chip and an embedded soft-core Nios II processor is taken as the development of a multiaxis motion control IC. The multiaxis motion control IC has two modules. The first module is Nios II processor which realizes the motion trajectory planning by software. It includes the step, circular, window, star, and helical motion trajectory. The second module presents a function of the multiaxis position/speed/current controller IP (intellectual property) by hardware. And VHDL (VHSIC Hardware Description Language) is applied to describe the multiaxis servo controller behavior. Before the FPGA realization, a cosimulation work by ModelSim/Simulink is applied to test the VHDL code. Then, this IP combined by Nios II processor will be downloaded to FPGA. Therefore, a fully digital multiaxis motion controller can be realized by a single FPGA chip. Finally, to verify the effectiveness and correctness of the proposed multiaxis motion control IP, a three-axis motion platform (XYZtable) is constructed and some experimental results are presented.
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YAMANE, YASURO, and KOICHI MURATA. "The InP-HEMT IC Technology for 40-Gbit/s Optical Communications." International Journal of High Speed Electronics and Systems 13, no. 01 (March 2003): 141–73. http://dx.doi.org/10.1142/s0129156403001569.
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We present the outline of the InP HEMT IC technology. This technology realizes InP HEMT digital ICs for 40-Gbit/s optical fiber communication systems through the integration of 0.1-μm-gate-length HEMTs, vertical diodes, capacitors, and WSiN resistors with two level interconnections. This paper describes the high-speed digital IC circuit design and fabrication in InP HEMT technology for 40-Gbit/s/channel optical communication systems. Some results on InP HEMTs' reliability are also covered. Basic circuit design techniques utilizing SCFL topology and fundamental circuit elements of the selector and D-type flip-flop are discussed in detail. The basic digital ICs of MUX, D-FF, and DEMUX ICs fabricated with 0.1-μm-gate InP HEMTs successfully operated up to 50 Gbit/s in the packaged modules. These IC modules offer large speed margins for the 43-Gbit/s OTU-3 data rate. In order to develop cost-effective optical transmitters and receivers, we designed a PLL-based CDR with a full-rate architecture. The fully monolithic integrated CDR exhibited error-free operation for 231-1 PRBS data signal at the OTU-3 bit rate of 43.0184 Gbit/s. Four-bit MUX and DEMUX ICs are other key components, and could be implemented by using InP HEMT technology. Additionally, we describe InP-IC fabrication technology with two-level inter-connection. This is already fully matured for 40-Gbit/s SSI fabrication. The uniform FET characteristics and high-yield passive component fabrication technologies support this degree of maturity. InP HEMT lifetime is 107 hours at l00°C. These results prove the InP HEMT IC fabrication technology presented here, to be highly reliable. These investigation show that robust performance and yield when realizing SSI and MSI 40-Gbit/s functions.
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OTA, YUSUKE, ROBERT G. SWARTZ, JOHN S. SCHAFER, MIHAI M. BANU, ALFRED E. DUNLOP, WILHELM C. FISCHER, and THADDEUS J. GABARA. "LOW COST, LOW POWER DIGITAL OPTICAL RECEIVER MODULE FOR 50 Mb/s PASSIVE OPTICAL NETWORK." International Journal of High Speed Electronics and Systems 07, no. 04 (December 1996): 471–89. http://dx.doi.org/10.1142/s012915649600027x.
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A low cost digital optical receiver module for passive optical networks was developed. In order to reduce the cost of the receiver module, ICs are packaged in low cost plastic packages and the receiver module is fabricated using conventional surface mount technology. The receiver module is capable of receiving burst and packet digital optical signals, and recovered data and recovered clock in CMOS logic level are available. The receiver module contains a connectorized InGaAs PIN photodiode, a burst/packet mode-compatible preamplifier IC in a 32-lead TQFP plastic package, a comparator IC in an 8-lead SOIC plastic package, a clock recovery IC in a 32-lead TQFP plastic package and other active and passive components. These components are mounted on a four-layer printed wiring board. The intrinsic minimum receivable optical signal power is around -42 dBm/Ave and the dynamic range is over 26 dB for BER 1 × 10-8 at a bit rate of up to 60 Mb/s. The total power consumption of this module is less than 200 mW.
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Rao, K. Madhava, B. Karthik Reddy, C. Rameshkumar Reddy, K. Charan Kumar, and Jakka Yeshwanth Reddy. "Implementation of on-chip high precision oscillators with RC and LC using digital compensation technique." AIMS Electronics and Electrical Engineering 6, no. 2 (2022): 188–97. http://dx.doi.org/10.3934/electreng.2022012.
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<abstract> <p>High precision oscillators became a significant call for both designer and testing engineers. Modern vibrators are being utilized in a variety of circuits, and accessibility to a wide range of frequencies is of the utmost importance in all research establishments. To produce various frequencies, utilizing a single gadget is very challenging for the designers. This article aims to provide the low frequency (RC) oscillator and high frequency (LC) oscillators with various output frequencies on a single chip. The use of both oscillators is necessary due to the fact that there are currently no such devices on the market, which makes it necessary to avoid using bulky recurrence generator hardware in order to facilitate rapid exploration and plausibility research. Here, a RC oscillator with high current accuracy and a LC oscillator with low force have been used to design a voltage controlled oscillator (VCO) IC by utilizing the Cadence 45 nm technology. This particular VCO IC is able to obtain two different frequencies with reasonable precision. Further, execution is completed by utilizing exclusive requirement inconsistent message format designing<italic>.</italic> This proposed work can be used at both audio frequency and radio frequency ranges from megahertz (MHz) to gigahertz (GHz).</p> </abstract>
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Ali, Liakot, and Farshad. "Analog hardware trojan design and detection in OFDM based wireless cryptographic ICs." PLOS ONE 16, no. 7 (July 29, 2021): e0254903. http://dx.doi.org/10.1371/journal.pone.0254903.
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Due to Hardware Trojan (HT), trustworthiness of Integrated Circuit (IC) supply chain is a burning issue in Semiconductor Industry nowadays. Over the last decade, extensive research has been carried on HT detection methods for digital circuits. However, the HT issue remains largely unexplored in the domain of Analog Mixed Signal (AMS)/ RF circuit where it is now an appealing target for the attackers. The increasing popularity of Orthogonal Frequency Division Multiplexing (OFDM) based wireless cryptographic ICs in modern communication systems makes it a lucrative target for HT-based attacks which could have a devastating impact on data security. This paper presents a trigger-based Hardware Trojan Threat model that exploits the extended cyclic prefix (ECP) property of the OFDM communication scheme to leak the secret encryption key over low noise Additive White Gaussian Channel (AWGN) and developed a Cyclic Prefix (CP) checker based detection mechanism named “SENTRY” to detect such trojans once it is triggered.
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WANG, KEH-CHUNG, RANDALL B. NUBLING, KEN PEDROTTI, NENG-HAUNG SHENG, PETER M. ASBECK, KEN POULTON, JOHN CORCORAN, KNUD KNUDSEN, HAN-TZONG YUAN, and CHRISTOPHER CHANG. "AlGaAs/GaAs HBTs FOR ANALOG AND DIGITAL APPLICATIONS." International Journal of High Speed Electronics and Systems 05, no. 03 (September 1994): 213–52. http://dx.doi.org/10.1142/s0129156494000127.
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AlGaAs/GaAs Heterojunction Bipolar Transistor (HBT) technology has emerged as an important IC technology for high performance electronic systems. Many outstanding circuits have been demonstrated as a result of the AlGaAs/GaAs HBTs high speed, high accuracy and its semi-insulating substrate. Several GaAs HBT manufacturing lines have been established; some of which are shipping products. In this paper, we describe AlGaAs/GaAs HBT technology, summarize some key and representative circuits in analog, A/D conversion and digital applications, and provide prospects of GaAs HBT research.
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Rizk, Mostafa, Amer Baghdadi, and Michel Jézéquel. "Computational Complexity Reduction of MMSE-IC MIMO Turbo Detection." Journal of Circuits, Systems and Computers 28, no. 13 (March 1, 2019): 1950228. http://dx.doi.org/10.1142/s0218126619502281.
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High data rates and error-rate performance approaching close to theoretical limits are key trends for evolving digital wireless communication applications. To address the first requirement, multiple-input multiple-output (MIMO) techniques are adopted in emergent wireless communication standards and applications. On the other hand, turbo concept is used to alleviate the destructive effects of the channel and ensure error-rate performance close to theoretical limits. At the receiver side, the incorporation of MIMO techniques and turbo processing leads to increased complexity that has a severe impact on computation speed, power consumption and implementation area. Because of its increased complexity, the detector is considered critical among all receiver components. Low-complexity algorithms are developed at the cost of decreased performance. Minimum mean-squared error (MMSE) solution with iterative detection and decoding shows an acceptable tradeoff. In this paper, the complexity of the MMSE algorithm in turbo detection context is investigated thoroughly. Algorithmic computations are surveyed to extract the characteristics of all involved parameters. Consequently, several decompositions are applied leading to enhanced performance and to a significant reduction of utilized computations. The complexity of the algorithm is evaluated in terms of real-valued operations. The proposed decompositions save an average of [Formula: see text] and [Formula: see text] of required operations for 2 [Formula: see text] 2 and 4 [Formula: see text] 4 MIMO systems, respectively. In addition, the hardware implementation designed applying the devised simplifications and decompositions outperforms available state-of-the-art implementations in terms of maximum operating frequency, execution time, and performance.
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Ren, Nan, Zaiming Fu, Shengcun Lei, Hanglin Liu, and Shulin Tian. "Methodology for Digital Synthesis of Deterministic and Random Jitter Generation on Rising or Falling Edges of Data Pattern." Electronics 8, no. 12 (December 9, 2019): 1510. http://dx.doi.org/10.3390/electronics8121510.
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Jitter is becoming an important factor in high-speed serial link and integrated circuits (ICs). Generating controllable jitter plays a crucial role in simulating the test environment of high-data links, evaluating the performance of IC, preventing jitter in high-speed serial link, and even testing the synchronous trigger circuit. In this paper, a digital synthesis for jitter generation and a logical combination method for selecting jitter on the rising edge or falling edge of a data pattern are presented. Precisely controllable jitter is generated by digital synthesis, including sinusoidal period jitter, rectangular period jitter, duty cycle distortion (DCD) jitter, and adjustable random jitter. Additionally, the validity and accuracy of the proposed method were demonstrated by hardware experiments, where the jitter frequency had an accuracy of ±30 ppm and the jitter amplitude had a step of 2 ps.
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CARTA, CORRADO, MUNKYO SEO, and MARK RODWELL. "A MIXED-SIGNAL ROW/COLUMN ARCHITECTURE FOR VERY LARGE MONOLITHIC mm-WAVE PHASED ARRAYS." International Journal of High Speed Electronics and Systems 17, no. 01 (March 2007): 111–14. http://dx.doi.org/10.1142/s012915640700431x.
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The range of mm-wave radio communications is severely constrained by high losses arising from the short wavelength and from atmospheric attenuation. Large phased arrays can overcome these limitations, but it is very difficult to realize them using present monolithic beamsteering IC architectures. We propose an alternative architecture for large monolithic phased arrays. The beam is steered in altitude and in azimuth by separately imposing vertical and horizontal phase gradients. This choice reduces IC complexity, making large arrays feasible. Since extensive digital processing provides robust amplitude control and reduces die area, the LOs are processed as digital signals. Being very sensitive to compression, the IF signals are processed as analog signals and distributed by means of synthetic transmission-line buses. With careful frequency planning, this mixed-signal approach can allow large phased arrays to operate at frequencies much higher than those achievable with pure analog design.
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MASUDA, T., N. SHIRAMIZU, E. OHUE, K. ODA, R. HAYAMI, M. KONDO, T. ONAI, et al. "A SiGe HBT IC CHIPSET for40-Gb/s OPTICAL TRANSMISSION SYSTEMS." International Journal of High Speed Electronics and Systems 13, no. 01 (March 2003): 239–63. http://dx.doi.org/10.1142/s0129156403001594.
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Using a 0.2-μm self-aligned epitaxial-growth silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology, we have developed a chipset for 40-Gb/s time-division multiplexing optical transmission systems. In this paper, we describe seven analog and digital ICs: a 45-GHz bandwidth transimpedance amplifier, a 48.7-GHz bandwidth automatic-gain-controllable amplifier, a 40-Gb/s decision circuit, a 40-Gb/s full-wave rectifier, a 40-Gb/s limiting amplifier with a 32-dB gain, a 45-Gb/s 1:4 demultiplexer, and a 45-Gb/s 4:1 multiplexer. To increase bandwidth of the transimpedance amplifier, a common-base input stage is introduced. In order to have high gain and wide bandwidth simultaneously, active load circuits composed of a differential transimpedance amplifier are used for the AGC amplifier, the limiting amplifier, and the decision circuit. Full-rate clocking is employed to reduce the influence caused by clock-duty variation in digital circuits such as the decision circuit, the demultiplexer, and the multiplexer. All ICs were characterized by using on-wafer probes, and some of them were built in brass-packages for bit-error rate measurement.
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Taha Ahmed, Ismail, Baraa Tareq Hammad, and Norziana Jamil. "A comparative analysis of image copy-move forgery detection algorithms based on hand and machine-crafted features." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 2 (May 1, 2021): 1177. http://dx.doi.org/10.11591/ijeecs.v22.i2.pp1177-1190.
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<span>Digital image forgery (DIF) is the act of deliberate alteration of an image to change the details transmitted by it. The manipulation may either add, delete or alter any of the image features or contents, without leaving any hint of the change induced. In general, copy-move forgery, also referred to as replication, is the most common of the various kinds of passive image forgery techniques. In the copy-move forgery, the basic process is copy/paste from one area to another in the same image. Over the past few decades various image copy-move forgery detection (IC-MFDs) surveys have been existed. However, these surveys are not covered for both IC-MFD algorithms based hand-crafted features and IC-MFDs algorithms based machine-crafted features. Therefore, The paper presented a comparative analysis of IC-MFDs by collect various types of IC-MFDs and group them rely on their features used. Two groups, i.e. IC-MFDs based hand-crafted features and IC-MFDs based machine-crafted features. IC-MFD algorithms based hand-crafted features are the algorithms that detect the faked image depending on manual feature extraction while IC-MFD algorithms based machine-crafted features are the algorithms that detect the faked image automatically from image. Our hope that this presented analysis will to keep up-to-date the researchers in the field of IC-MFD.</span>
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YEO, KIAT-SENG, ZHI-HUI KONG, NUKALA NISHANT, HAITAO FU, and WEI ZENG. "INTEGRATED CIRCUIT DESIGN RESEARCH RANKING FOR WORLDWIDE UNIVERSITIES." Journal of Circuits, Systems and Computers 17, no. 01 (February 2008): 141–67. http://dx.doi.org/10.1142/s0218126608004204.
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The proliferation of integrated circuits (ICs) in the present technological era has brought forth revolutionary digital modernization that has ultimately transformed the history and lifestyle of humankind. ICs have become the heart of practically all state-of-the-art electronic devices such as computers, cell phones, video game consoles, and cameras. This ever-flourishing IC design industry is knowledge-intensive, which in turn translates into a huge appetite for technically precocious talents. Hence, in an effort to fuel and further foster the industry with more highly skilled manpower and at the same time to vie for a share of the burgeoning industry, higher educational institutions and universities from all around the globe are placing greater than ever emphasis on IC design research. Most importantly, strenuous efforts in a holistic manner are being made by each university in order to elicit outstanding and top-notch research in IC design. The authors have conducted a detailed and extensive survey to rank the various universities of the world in the field of IC design based on their research performance. In fact, assessments in the form of ranking have gained prominence over the recent years captivating the attention of a large number of students and universities. It helps the students in knowing how each university is progressing in a particular field and in turn helps the universities in analyzing their positions globally to remain competitive. Three ranking indicators, namely the Number of Publications, Citation Counts, and Cites per Paper have been chosen. The methodology used in ranking is also reported. The universities occupying the top echelons in IC design research are identified and a proven three-pronged approach for eliciting outstanding research performance is discussed.
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SAPONARA, SERGIO, TOMMASO BALDETTI, LUCA FANUCCI, EMILIO VOLPI, and FRANCESCO D'ASCOLI. "DESIGN OF AN INTEGRATED SCANNING MICROMIRROR DRIVER IN BCD TECHNOLOGY." Journal of Circuits, Systems and Computers 20, no. 04 (June 2011): 781–99. http://dx.doi.org/10.1142/s0218126611007608.
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The paper presents the design and characterization of a smart IC driver for MEMS scanning micromirrors. The driver integrates in 0.18 μm BCD technology the cascade of the following circuits: resistor-string DAC circuitry for direct interface to a host digital processing unit, a voltage buffer between the DAC and the High-Voltage (HV) stage, and a fully-differential HV amplifier with programmable output common mode. A couple of the designed DACs permits to generate, starting from digital samples, low-voltage analog stimuli. This signal amplified up to 25 V by the HV stage provides the electrostatical actuation of the micromirror. When compared to state-of-the-art the driver offers an integrated solution with good dynamic performances.
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SANO, EIICHI, KAZUO HAGIMOTO, and YASUNOBU ISHII. "PRESENT STATUS AND FUTURE PROSPECTS OF HIGH-SPEED LIGHTWAVE ICS BASED ON INP." International Journal of High Speed Electronics and Systems 09, no. 02 (June 1998): 567–93. http://dx.doi.org/10.1142/s0129156498000245.
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High-speed integrated circuits (ICs) are essential for expanding the capacity of light-wave communications. InP-based heterostructure field effect transistors (HFETs) and heterojunction bipolar transistors (HBTs) are very promising for producing high-speed digital and analog ICs. This paper reviews the current status of InP-based lightwave communication ICs in terms of device, circuit, and packaging technologies. A successful 40-Gbit/s, 300-km optical fiber transmission using InP HFET ICs demonstrates the feasibility of the ICs. Furthermore, we estimate future IC performance based on the relationship between electron device figures-of-merit and IC speed. To keep up with the performance trend, technological problems, like inter- and intra-chip interconnections, have to be solved.
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Kitchen, Jennifer, Soroush Moallemi, and Sumit Bhardwaj. "Multi-chip module integration of Hybrid Silicon CMOS and GaN Technologies for RF Transceivers." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000339–82. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_tp1_010.
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Digital transceiver architectures offer the potential for achieving wireless hardware flexibility to frequency and modulation scheme for future-generation communications systems. Additionally, digital transmitters lend themselves to the use of switch-mode power amplifiers, which can have significantly higher efficiency than their linear counterparts. Two proposed architectures for realizing digital transmitters will be described in this work, both of which employ a hybrid combination of silicon integrated circuits (IC) and a power technology (e.g. GaN). This hybrid architecture takes advantage of the silicon to implement the high-complexity signal processing required for wireless communications, and uses power devices with high power density and low parasitic capacitance to sufficiently amplify the RF signals for transmission. Unfortunately, interfacing the low-power RF switching signals with off-chip high-power devices poses numerous design challenges, including: generation of integrated silicon power drivers with sufficient voltage swing for controlling power devices such as GaN, mitigation of on-chip current transients, wideband assembly interface from the silicon IC to the power device, and full system design verification using multiple process technologies. This work presents two CMOS driver architectures that can be used to interface low-power CMOS processing circuits with off-chip high-power devices. This work also details the performance limitations when assembling and interfacing multiple process technologies that are not co-located on the same IC. The main function of the driver circuitry within the digital transceiver system is to interface the low-power digital modulator to a large, high capacitance, off-chip power device. The driver must provide adequate transient current to charge/discharge the off-chip power devices' input capacitance through parasitic routing. Furthermore, the driver is designed to exhibit rise/fall times of less than 5% of the switching period and low jitter to meet RF signal quality requirements. Since silicon process technologies typically have much lower voltage breakdowns than those required to drive a power devie (e.g. GaN device), special driver architectures must be implemented to ensure the CMOS devices never exceed their breakdown voltages. Two architectures were implemented within this work to simultaneously achieve RF switching speeds and 5V signal swing from a 0.9V silicon CMOS process technology. The two architectures are: 1) a House-of-Cards configuration, and 2) a Cascode topology. These architectures will be detailed and compared with respect to performance in this presentation. Two of the most common techniques to assemble and connect a silicon IC, which includes the driver circuitry, and a (GaN) power device are: 1) direct wire bonding or flip-chip connection from the IC to the GaN, and 2) connection through a board or package interface circuit. Since most high-performance RF power devices such as GaN have negative threshold voltage, the driver (CMOS) IC must either: 1) have a supply and ground that are shifted to negative voltage values, or 2) decouple the IC's output from the GaN device's input in order to properly control the GaN. Off-chip decoupling is more easily implemented, but may limit maximum operating frequencies due to the added interface network and board/module parasitics. This work shall detail the interface models and compare the assembly procedures and potential performance limits when using both of these most common assembly techniques.
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Feldman, Alexander, Ion Matei, Emil Totev, and Johan De Kleer. "Analog Accelerator for Simulation and Diagnostics." Proceedings of the AAAI Conference on Artificial Intelligence 34, no. 08 (April 3, 2020): 13261–66. http://dx.doi.org/10.1609/aaai.v34i08.7034.
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We propose a new method for solving Initial Value Problems (IVPs). Our method is based on analog computing and has the potential to almost eliminate traditional switching time in digital computing. The approach can be used to simulate large systems longer, faster, and with higher accuracy. Many algorithms for Model-Based Diagnosis use numerical integration to simulate physical systems. The numerical integration process is often either computationally expensive or imprecise. We propose a new method, based on Field-Programmable Analog Arrays (FPAAs) that has the potential to overcome many practical problems. We envision a software/hardware framework for solving systems of simultaneous Ordinary Differential Equations (ODEs) in fraction of the time of traditional numerical algorithms. In this paper we describe the solving of an IVP with the help of an Analog Computing Unit (ACU). To do this we build a special calculus based on operational amplifiers (op-amps) with local feedback. We discuss the implementation of the ACU on an Integrated Circuit (IC). We analyze the working if the IC and simulate the dynamic Lotka-Volterra system with the de-facto standard tool for electrical simulation: Spice.
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Kajtez, Nemanja, Yue Zhang, and Basel Halak. "Lockit: A Logic Locking Automation Software." Electronics 10, no. 22 (November 17, 2021): 2817. http://dx.doi.org/10.3390/electronics10222817.
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The significant rise in the cost of manufacturing nanoscale integrated circuits (ICs) has led the majority of IC design companies to outsource the fabrication of their products to other companies, often located in different countries. The multinational nature of the hardware supply chain has led to a host of security threats, including IP piracy, IC overproduction, and Trojan insertion. To combat these, researchers have proposed logic locking techniques to protect the intellectual properties of the design and increase the difficulty of malicious modification of its functionality. However, the adoption of logic locking approaches has been rather slow due to the lack of integration with the IC production process and the lack of efficacy of existing algorithms. This work automates the logic locking process by developing software using Python that performs the locking on a gate-level netlist, which can be integrated with the existing digital synthesis tools. Analysis of the latest logic locking algorithms has demonstrated that the SFLL-HD algorithm is one of the most secure and versatile when trading-off levels of protection against different types of attacks and was thus selected for implementation. The presented tool can also be expanded to incorporate the latest locking mechanisms to keep up with the fast-paced development in this field. The paper also presents a case study to demonstrate the functionality of the tool and how it could be used to explore the design space and compare different locking solutions.
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Kung, Ying-Shieh, Seng-Chi Chen, Jin-Mu Lin, and Tsung-Chun Tseng. "FPGA-realization of a speed control IC for induction motor drive." Engineering Computations 33, no. 6 (August 1, 2016): 1835–52. http://dx.doi.org/10.1108/ec-08-2015-0260.
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Purpose – The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the slip speed estimator, the space vector pulse width modulation scheme, the quadrature encoder pulse, and analog to digital converter interface circuit, etc. into one field programmable gate array (FPGA). Design/methodology/approach – First, the mathematical modeling of an IM drive, the field-oriented control algorithm, and PI controller are derived. Second, the very high speed IC hardware description language (VHDL) is adopted to describe the behavior of the algorithms above. Third, based on electronic design automation simulator link, a co-simulation work constructed by ModelSim and Simulink is applied to verify the proposed VHDL code for the speed controller intellectual properties (IP). Finally, the developed VHDL code will be downloaded to the FPGA for further control the IM drive. Findings – In realization aspect, it only needs 5,590 LEs, 196,608 RAM bits, and 14 embedded 9-bit multipliers in FPGA to build up a speed control IP. In computational power aspect, the operation time to complete the computation of the PI controller, the slip speed estimator, the current vector controller are only 0.28 μs, 0.72 μs, and 0.96 μs, respectively. Practical implications – Fast computation in FPGA can speed up the speed response of IM drive system to increase the running performance. Originality/value – This is the first time to realize all the function of a speed controller for IM drive within one FPGA.
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Ahmed, Iftekhar Uddin, Abdul Kadar Muhammad Masum, and S. M. A. Motakabber. "The proposed model of pulse code modulation encoder for voice frequencies." International Journal of Scientific World 3, no. 1 (April 26, 2015): 152. http://dx.doi.org/10.14419/ijsw.v3i1.4495.
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<p>In this paper, we have developed a hardware-based model of pulse code modulation (PCM) system for voice frequencies. Firstly, we have constructed sample and hold circuit using triggered semiconductor switch (e.g., MOSFET), which is capable of sampling voice signals at 8 kHz according to Nyquist theory. Then an Analogue to Digital Converter (ADC) Integrated Circuit (IC) is introduced to quantize and to digitize of the output of the sample and hold as pulse amplitude modulation (PAM). The converted outputs are 8-bit digital parallel value per sample at a frequency of 8 kHz. Finally, a parallel to serial converter logic is constructed which remains the voice frequency at the accurate time without any delay. The principle feature of this PCM system is that during a final interval of time, it makes a waveform into 8 bit serial code word. An 8-bit shift register with decade counter and flip-flop based logic are providing to this wave-from one after another without any interruptions of the sequences.</p>
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Omisakin, Adedayo, Rob Mestrom, Georgi Radulov, and Mark Bentum. "Sub-Milliwatt Transceiver IC for Transcutaneous Communication of an Intracortical Visual Prosthesis." Electronics 11, no. 1 (December 22, 2021): 24. http://dx.doi.org/10.3390/electronics11010024.
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An intracortical visual prosthesis plays a vital role in partially restoring the faculty of sight in visually impaired people. Reliable high date rate wireless links are needed for transcutaneous communication. Such wireless communication should receive stimulation data (downlink) and send out neural recorded data (uplink). Hence, there is a need for an implanted transceiver that is low-power and delivers sufficient data rate for both uplink and downlink. In this paper, we propose an integrated circuit (IC) solution based on impulse radio ultrawideband using on-off keying modulation (OOK IR-UWB) for the uplink transmitter, and binary phase-shift keying (BPSK) with sampling and digital detection for the downlink receiver. To make the solution low-power, predominantly digital components are used in the presented transceiver test-chip. Current-controlled oscillators and an impulse generator provide tunability and complete the on-chip integration. The transceiver test-IC is fabricated in 180 nm CMOS technology and occupies only 0.0272 mm2. At 1.3 V power supply, only 0.2 mW is consumed for the BPSK receiver and 0.3 mW for the IR-UWB transmitter in the transceiver IC, while delivering 1 Mbps and 50 Mbps, respectively. Our link budget analysis shows that this test chip is suitable for intracortical integration considering the future off-chip antennas/coils transcutaneous 3–7 mm communication with the outer side. Hence, our work will enable realistic wireless links for the intracortical visual prosthesis.
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Kolbl, Florian, Yannick Bornat, Jonathan Castelli, Louis Regnacq, Gilles N’Kaoua, Sylvie Renaud, and Noëlle Lewis. "IC-Based Neuro-Stimulation Environment for Arbitrary Waveform Generation." Electronics 10, no. 15 (August 3, 2021): 1867. http://dx.doi.org/10.3390/electronics10151867.
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Electrical stimulation of the nervous system is commonly based on biphasic stimulation waveforms, which limits its relevance for some applications, such as selective stimulation. We propose in this paper a stimulator capable of delivering arbitrary waveforms to electrodes, and suitable for non-conventional stimulation strategies. Such a system enables in vivo stimulation protocols with optimized efficacy or energy efficiency. The designed system comprises a High Voltage CMOS ASIC generating a configurable stimulating current, driven by a digital circuitry implemented on a FPGA. After fabrication, the ASIC and system were characterized and tested; they successfully generated programmable waveforms with a frequential content up to 1.2 MHz and a voltage compliance between [−17.9; +18.3] V. The system is not optimum when compared to single application stimulators, but no embedded stimulator in the literature offers an equivalent bandwidth which allows the wide range of stimulation paradigms, including high-frequency blocking stimulation. We consider that this stimulator will help test unconventional stimulation waveforms and can be used to generate proof-of-concept data before designing implantable and application-dedicated implantable stimulators.
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BROCK, DARREN K. "RSFQ TECHNOLOGY: CIRCUITS AND SYSTEMS." International Journal of High Speed Electronics and Systems 11, no. 01 (March 2001): 307–62. http://dx.doi.org/10.1142/s0129156401000861.
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Rapid Single-Flux-Quantum (RSFQ) logic is a superconductor IC technology that, with only a modest number of researchers worldwide, has produced some of the world's highest performance digital and mixed-signal circuits. This achievement is due, in part, to a constellation of characteristics that manifest themselves at the circuit level – namely, high-speed digital logic at low-power, ideal interconnects, quantum accuracy, scalability, and simplicity of fabrication. A necessary key to translating these advantages to the system-level involves understanding the I/O, synchronization, and packaging issues associated with a cryogenic technology. The objective of this paper is to review the status of current RSFQ circuit-level infrastructure components and their potential impact on system-level applications.
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Wang, Chua-Chin, Lean Karlo S. Tolentino, Pin-Chuan Chen, John Richard E. Hizon, Chung-Kun Yen, Cheng-Tang Pan, and Ya-Hsin Hsueh. "A 40-nm CMOS Piezoelectric Energy Harvesting IC for Wearable Biomedical Applications." Electronics 10, no. 6 (March 11, 2021): 649. http://dx.doi.org/10.3390/electronics10060649.
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This investigation presents an energy harvesting IC (integrated circuit) for piezoelectric materials as a substitute for battery of a wearable biomedical device. It employs a voltage multiplier as first stage which uses water bucket fountain approach to boost the very low voltage generated by the piezoelectric. The boosted voltage was further improved by the boost DC/DC converter which follows a predefined timing control directed by the digital logic for the said converter to be operated efficiently. TSMC 40-nm CMOS process was used for implementation and fabrication of the energy harvesting IC. The chip’s core has an area of 0.013 mm2. With an output of 1 V which is enough to supply the wearable biomedical devices, it exhibited the highest pump gain and accommodated the lowest piezoelectric generated voltage among recent related works.
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OTSUJI, TAIICHI. "PRESENT AND FUTURE OF HIGH-SPEED COMPOUND SEMICONDUCTOR IC's." International Journal of High Speed Electronics and Systems 13, no. 01 (March 2003): 1–25. http://dx.doi.org/10.1142/s0129156403001508.
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This paper describes state-of-the-art of high-speed electronic device and IC technologies for very high-speed lightwave communications systems. The technology of interest is for over 40-Gbit/s transmitter and receiver operations. Device technology including Si-Ge, GaAs-based, and InP-based heterostructure transistors as well as circuit design technology including analog/digital/mixed-signal and optoelectronic IC's are reviewed. The speed limiting factors are discussed to address the future trends toward 100 Gbit/s and beyond.
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MEYERSON, B. S., D. L. HARAME, J. STORK, E. CRABBE, J. COMFORT, and G. PATTON. "SILICON:GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTORS: FROM EXPERIMENT TO TECHNOLOGY." International Journal of High Speed Electronics and Systems 05, no. 03 (September 1994): 473–91. http://dx.doi.org/10.1142/s012915649400019x.
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Recent advances in thin film growth techniques, notably the maturation of low temperature silicon epitaxy, have enabled the routine fabrication of highly controlled dopant and silicon:germanium alloy profiles. These capabilities, combined with refinements in heterojunction bipolar transistor designs, have led to the first integrated circuits in the silicon:germanium materials system. Utilizing a commercial (Leybold-AG) UHVCVD tool for SiGe epitaxy on a standard 8" CMOS line, medium scale integration has been achieved, with the first IC components being SiGe HBT based 1 Ghz, 12 bit, digital to analog converters.
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Yeh, Chung-Huang, Jwu-E. Chen, Chia-Jui Chang, and Tse-Chia Huang. "Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield." Electronics 11, no. 7 (March 31, 2022): 1115. http://dx.doi.org/10.3390/electronics11071115.
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In this work, we use statistical concepts to evaluate the joint probability distribution of manufacturing and test parameters and estimate the future trend of wafer test yield. Owing to the difference between the development speeds of testing technology and manufacturing technology, the testing capability of wafers is far behind the manufacturing capability of the semiconductor. Therefore, with the advancement in technology, the test yield loss caused by the tester inaccuracy has become an important problem. In this article, we propose an enhanced integrated circuit (IC) test scheme (ITS) that uses multiplex testing to improve test quality and test pass rate by retesting, and we rely on the cost evaluation mechanism to obtain the best test and the best profit. Furthermore, the International Roadmap for Devices and Systems (IRDS) 2017 data are used to estimate future test yield trends, and the results prove that the enhanced test scheme (ETS) can effectively estimate the best retest time to obtain the best test yield and the best profit.
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Szplet, Ryszard, and Arkadiusz Czuba. "Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device." Electronics 10, no. 18 (September 7, 2021): 2190. http://dx.doi.org/10.3390/electronics10182190.
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This article presents an idea, design and test results of a new time-to-digital converter (TDC) implemented in an FPGA device. The high resolution of 13 ps and measurement range of 3.4 ns are achieved based on a two-stage time interpolation (TI). In the first and second stages of the TI we have used the Vernier delay line and a single tapped delay line, respectively. This solution provides respectable metrological parameters without the need to use a clock signal, and significantly saves the logical resources of an integrated circuit (IC). The proposed method, generally based on two different variants of the discrete delay line, is easy to design and implement in digital ICs. For experimental verification, the TDC was implemented in a single programmable device from family Virtex-7 (Xilinx).
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Piróg, S., R. Stala, and Ł. Stawiarski. "Power electronic converter for photovoltaic systems with the use of FPGA-based real-time modeling of single phase grid-connected systems." Bulletin of the Polish Academy of Sciences: Technical Sciences 57, no. 4 (December 1, 2009): 345–54. http://dx.doi.org/10.2478/v10175-010-0137-9.
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Power electronic converter for photovoltaic systems with the use of FPGA-based real-time modeling of single phase grid-connected systemsThe paper presents a method of investigation of grid connected systems with a renewable energy source. The method enables fast prototyping of control systems and power converters components by real-time simulation of the system. Components of the system such as energy source (PV array), converters, filters, sensors and control algorithms are modeled in FPGA IC. Testing the systems before its practical application reduces cost and time-to-market. FPGA devices are commonly used for digital control. The resources of the FPGAs used for preliminary testing can be sufficient for the complete system modelling. Debugging tools for FPGA enable observation of many signals of the analyzed power system (as a result of the control), with very advanced triggering tools. The presented method of simulation with the use of hardware model of the power system in comparison to classical simulation tools gives better possibilities for verification of control algorithms such as MPPT or anti-islanding.
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Hänggi, Daniel, Michael Reinert, and Hans-Jakob Steiger. "C-Port Flex-A–assisted automated anastomosis for high-flow extracranial-intracranial bypass surgery in patients with symptomatic carotid artery occlusion: a feasibility study." Journal of Neurosurgery 111, no. 1 (July 2009): 181–87. http://dx.doi.org/10.3171/2009.2.jns081388.
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Object Preliminary experience with the C-Port Flex-A Anastomosis System (Cardica, Inc.) to enable rapid automated anastomosis has been reported in coronary artery bypass surgery. The goal of the current study was to define the feasibility and safety of this method for high-flow extracranial-intracranial (EC-IC) bypass surgery in a clinical series. Methods In a prospective study design, patients with symptomatic carotid artery (CA) occlusion were selected for C-Port–assisted high-flow EC-IC bypass surgery if they met the following criteria: 1) transient or moderate permanent symptoms of focal ischemia; 2) CA occlusion; 3) hemodynamic instability; and 4) had provided informed consent. Bypasses were done using a radial artery graft that was proximally anastomosed to the superficial temporal artery trunk, the cervical external, or common CA. All distal cerebral anastomoses were performed on M2 branches using the C-Port Flex-A system. Results Within 6 months, 10 patients were enrolled in the study. The distal automated anastomosis could be accomplished in all patients; the median temporary occlusion time was 16.6 ± 3.4 minutes. Intraoperative digital subtraction angiography (DSA) confirmed good bypass function in 9 patients, and in 1 the anastomosis was classified as fair. There was 1 major perioperative complication that consisted of the creation of a pseudoaneurysm due to a hardware problem. In all but 1 case the bypass was shown to be patent on DSA after 7 days; furthermore, in 1 patient a late occlusion developed due to vasospasm after a sylvian hemorrhage. One-week follow-up DSA revealed transient asymptomatic extracranial spasm of the donor artery and the radial artery graft in 1 case. Two patients developed a limited zone of infarction on CT scanning during the follow-up course. Conclusions In patients with symptomatic CA occlusion, C-Port Flex-A–assisted high-flow EC-IC bypass surgery is a technically feasible procedure. The system needs further modification to achieve a faster and safer anastomosis to enable a conclusive comparison with standard and laser-assisted methods for high-flow bypass surgery.
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Biswas, Tathagato. "Spy Robot." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (June 30, 2022): 4265–69. http://dx.doi.org/10.22214/ijraset.2022.44887.
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Abstract: Nowadays, the technological and digital world is developing very fast. Everything is getting smart, so we are talking about the technological world the devices like home appliances and other things are getting control by mobile applications, and this only happens by the device Arduino Uno / raspberry pi3 and many others. Still, in our research we have used Arduino Uno to create a Wi-Fi controlled car with camera-top on it to monitor everything in its surrounding, we have seen many similar projects which using Arduino to makes things easy to use and its saving time and energy too. Automation is used for operating an electronic device such as the remote control car, home lighting system, and other useful things or reduced human invention. This report proposes a design and implementation of a remote. controlled camera car by Wi-Fi technology mobile devices. In this analysis work, radio code and hardware technologies area unit used, like the wireless module of ESP8266 for (transmitter and receiver), Arduino Uno as microcontroller, associate H-bridge L293D IC for motor controller and 2 electrical DC motors are used to move the car, & a Camera attached on the top of the vehicle.
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Li, Li Hua, C. Y. Chan, and W. B. Lee. "Design of a Novel Compound Eye System." Applied Mechanics and Materials 870 (September 2017): 303–8. http://dx.doi.org/10.4028/www.scientific.net/amm.870.303.
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Much progress has been made in the field of digital imaging technology with the widespread use of CMOS and CCD devices and the high computing power of IC chips. However, there still are many technological problems to overcome to achieve lightweight and affordable high density 3D lossless imaging for both industrial and scientific applications. This paper will focus on the latest development of freeform optical technology and powerful image analysis techniques to develop a compound eye camera system so as to extract the 3D relative position coordinates of the sub-object in the field of view, and to compensate the shadow effect in the images caused by the non-uniform illumination to obtain high quality lossless images. Such a novel compound eye system will find applications in delivering 3D image of digital camera, increasing capability of scientific profiling measuring instrument, and lowering cost and enhancing resolution of wide-field, video-rate, gigapixel cameras such as the AWARE designed by Duke University.The main objective of this paper is to design a novel compound eye system from high definition 3D lossless digital imaging technology to achieve the realistic three-dimensional positional information of the object in both near and far fields. In the imaging process, the ultimate imaging quality is affected and limited by the resolution of the detector, the field of view, wavefront aberration, resolution of the optical imaging system and the ambient light.The novel compound eye imaging system includes two modules: one is the optical imaging module with compound eye optical elements with other secondary optical lenses, while the other one is the image analysis module. By combining the above optical hardware with the image analysis software, the relative position information of the sub-objects in the picture and the lighting condition of the environment can be deduced accurately.
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Wang, Nan-Lei, and Douglas Adam. "Low Power Design for Wireless RF Transceiver–An Industrial View." Journal of Circuits, Systems and Computers 07, no. 01 (February 1997): 1–16. http://dx.doi.org/10.1142/s0218126697000024.
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In recent years, wireless communication in the radio frequency has a rapid growth, most noticeably the cellular phone. Analog FM systems, such as AMPS and TACS, have won a great success. In the 90s, digital systems appear, such as GSM in Europe, IS54/136 and IS95 in US, and PDC in Japan. Most recently, PCS draws the attention; there are many standards proposed around the world and they all use digital modulation schemes. With the ISM bands at 900 MHz and 2.4 MHz, many other innovative application will become possible. Unlike the computer such RF wireless gadgets contain one peculiar subsystem: the RF transceiver. The RF transceiver translates the baseband voice and data to and from a radio frequency signal which is emitted and received by antennae. Each system specifies the operation frequency, the transmit power, the receiver sensitivity, and the signal quality. The RF transceiver must satisfy all these requirements. As technology progresses, portable product becomes the dominant one which relies on the rechargeable battery. To maintain a decent talk time standby time, the completed product must be designed with low power consumption in mind. In the portable cellular phone the RF transceiver faces the greatest challenge in the low power design since it is the most power hungry portion: the transmitter consumes 90% power during transmission in the FM cellular phone nowadays. To achieve low power consumption of the RF transceiver, the designer has to work to: (1) transceiver architecture to reduce parts count and therefore power comsumption. (2) selection/design the lowest power comsumption IC/module for a given function block. (3) maintain competitive pricing and small size. In this article, FM system will be used as the baseline example to illustrate the importance of the RF transceiver in low power application. The RF transceiver architecture is described first, followed by the introduction to each function block. State-of-the-art products for each function block will be referred to. Theorectical limit of power consumption for each block will be discussed. Impact from digital modulation on RF circuit design will be reviewed as well.
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Liu, Yuntao, Michael Zuzak, Yang Xie, Abhishek Chakraborty, and Ankur Srivastava. "Robust and Attack Resilient Logic Locking with a High Application-Level Impact." ACM Journal on Emerging Technologies in Computing Systems 17, no. 3 (May 11, 2021): 1–22. http://dx.doi.org/10.1145/3446215.
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Logic locking is a hardware security technique aimed at protecting intellectual property against security threats in the IC supply chain, especially those posed by untrusted fabrication facilities. Such techniques incorporate additional locking circuitry within an integrated circuit (IC) that induces incorrect digital functionality when an incorrect verification key is provided by a user. The amount of error induced by an incorrect key is known as the effectiveness of the locking technique. A family of attacks known as “SAT attacks” provide a strong mathematical formulation to find the correct key of locked circuits. To achieve high SAT resilience (i.e., complexity of SAT attacks), many conventional logic locking schemes fail to inject sufficient error into the circuit when the key is incorrect. For example, in the case of SARLock and Anti-SAT, there are usually very few (or only one) input minterms that cause any error at the circuit output. The state-of-the-art s tripped functionality logic locking (SFLL) technique provides a wide spectrum of configurations that introduced a tradeoff between SAT resilience and effectiveness. In this work, we prove that such a tradeoff is universal among all logic locking techniques. To attain high effectiveness of locking without compromising SAT resilience, we propose a novel logic locking scheme, called Strong Anti-SAT (SAS). In addition to SAT attacks, removal-based attacks are another popular kind of attack formulation against logic locking where the attacker tries to identify and remove the locking structure. Based on SAS, we also propose Robust SAS (RSAS) that is resilient to removal attacks and maintains the same SAT resilience and effectiveness as SAS. SAS and RSAS have the following significant improvements over existing techniques. (1) We prove that the SAT resilience of SAS and RSAS against SAT attack is not compromised by increase in effectiveness . (2) In contrast to prior work that focused solely on the circuit-level locking impact, we integrate SAS-locked modules into an 80386 processor and show that SAS has a high application-level impact. (3) Our experiments show that SAS and RSAS exhibit better SAT resilience than SFLL and their effectiveness is similar to SFLL.
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YUE, C. PATRICK, JAEJIN PARK, RUIFENG SUN, L. RICK CARLEY, and FRANK O'MAHONY. "LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 459–76. http://dx.doi.org/10.1142/s0129156405003260.
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This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.
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Srinath, B., Rajesh Verma, Abdulwasa Bakr Barnawi, Ramkumar Raja, Mohammed Abdul Muqeet, Neeraj Kumar Shukla, A. Ananthi Christy, C. Bharatiraja, and Josiah Lange Munda. "An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts." Electronics 10, no. 22 (November 15, 2021): 2795. http://dx.doi.org/10.3390/electronics10222795.
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Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.
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Paul, Shubhra Deb, and Swarup Bhunia. "SILVerIn: Systematic Integrity Verification of Printed Circuit Board Using JTAG Infrastructure." ACM Journal on Emerging Technologies in Computing Systems 17, no. 3 (June 25, 2021): 1–28. http://dx.doi.org/10.1145/3460232.
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A printed circuit board (PCB) provides necessary mechanical support to an electronic system and acts as a platform for connecting electronic components. Counterfeiting and in-field tampering of PCBs have become significant security concerns in the semiconductor industry as a result of increasing untrusted entities in the supply chain. These counterfeit components may result in performance degradation, profit reduction, and reputation risk for the manufacturers. While Integrated Circuit (IC) level authentication using physical unclonable functions (PUFs) has been widely investigated, countermeasures at the PCB level are scarce. These approaches either suffer from significant overhead issues, or opportunistic counterfeiters can breach them like clockwork. Besides, they cannot be extended to system-level (both chip and PCB together), and their applications are also limited to a specific purpose (i.e., either counterfeiting or tampering). In this article, we introduce SILVerIn , a novel systematic approach to verify the authenticity of all chips used in a PCB as well as the board for combating attacks such as counterfeiting, cloning, and in-field malicious modifications. We develop this approach by utilizing the existing boundary scan architecture (BSA) of modern ICs and PCBs. As a result, its implementation comes at a negligible (∼0.5%) hardware overhead. SILVerIn is integrated into a PCB design during the manufacturing phase. We implement our technique on a custom hardware platform consisting of an FPGA and a microcontroller. We incorporate the industry-standard JTAG (Joint Test Action Group) interface to transmit test data into the BSA and perform hands-on measurement of supply current at both chip and PCB levels on 20 boards. We reconstruct these current values to digital signatures that exhibit high uniqueness, robustness, and randomness features. Our approach manifests strong reproducibility of signatures at different supply voltage levels, even with a low-resolution measurement setup. SILVerIn also demonstrates a high resilience against machine learning-based modeling attacks, with an average prediction accuracy of ∼51%. Finally, we conduct intentional alteration experiments by replacing the on-board FPGA to replicate the scenario of PCB tampering, and the results indicate successful detection of in-field modifications in a PCB.
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Chen, Qiwei, Sanja Kastratovic, Mohamad Eid, and Sohmyung Ha. "A Non-Contact Compact Portable ECG Monitoring System." Electronics 10, no. 18 (September 17, 2021): 2279. http://dx.doi.org/10.3390/electronics10182279.
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Cardiovascular diseases (CVDs) have been listed among the most deadly diseases worldwide. Many CVDs are likely to manifest their symptoms some time prior to the onset of any adverse or catastrophic events, and early detection of cardiac abnormalities is incredibly important. However, traditional electrocardiography (ECG) monitoring systems face challenges with respect to their scalability and affordability as they require direct body contact and cumbersome equipment. As a step forward from the large-scale direct-contact ECG monitoring devices, which are inconvenient for the user in terms of wearability and portability, in this research, we present a small-sized, non-contact, real-time recording system for mobile long-term monitoring of ECG signals. The device mainly comprises three non-contact electrodes to sense the bio-potential signal, an AD8233 AFE IC to extract the ECG signal, and a CC2650 MCU to read, filter, and transmit them. The device is powered by a 2000 mAh lithium-ion battery with isolation between digital and analog powers on the board using two low-dropout regulators (LDOs). The board’s dimension is 8.56 cm × 5.4 cm, the size of a credit card, making it optimal to be worn in a shirt chest pocket. In spite of its small form factor, the device still manages to achieve a continuous measurement battery life of over 16 h, total harmonic distortion below −30 dB across the interested frequency range, an input-referred noise as low as 1.46 µV for contacted cases and 5.15 µV for non-contact cases through cotton, and clear ECG recording for both contact and non-contact sensing, all at a cost around USD 50.
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Bagde, Vandana, and Dethe C. G. "Performance improvement of space diversity technique using space time block coding for time varying channels in wireless environment." International Journal of Intelligent Unmanned Systems 10, no. 2/3 (June 8, 2020): 278–86. http://dx.doi.org/10.1108/ijius-04-2019-0026.
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PurposeA recent innovative technology used in wireless communication is recognized as multiple input multiple output (MIMO) communication system and became popular for quicker data transmission speed. This technology is being examined and implemented for the latest broadband wireless connectivity networks. Though high-capacity wireless channel is identified, there is still requirement of better techniques to get increased data transmission speed with acceptable reliability. There are two types of systems comprising of multi-antennas placed at transmitting and receiving sides, of which first is diversity technique and another is spatial multiplexing method. By making use of these diversity techniques, the reliability of transmitting signal can be improved. The fundamental method of the diversity is to transform wireless channel such as Rayleigh fading into steady additive white Gaussian noise (AWGN) channel which is devoid of any disastrous fading of the signal. The maximum transmission speed that can be achieved by spatial multiplexing methods is nearly equal to channel capacity of MIMO. Conversely, for diversity methods, the maximum speed of broadcasting is much lower than channel capacity of MIMO. With the advent of space–time block coding (STBC) antenna diversity technique, higher-speed data transmission is achievable for spatially multiplexed multiple input multiple output (SM-MIMO) system. At the receiving end, detection of the signal is a complex task for system which exhibits SM-MIMO. Additionally, a link modification method is implemented to decide appropriate coding and modulation scheme such as space diversity technique STBC to use two-way radio resources efficiently. The proposed work attempts to improve detection of signal at receiving end by employing STBC diversity technique for linear detection methods such as zero forcing (ZF), minimum mean square error (MMSE), ordered successive interference cancellation (OSIC) and maximum likelihood detection (MLD). The performance of MLD has been found to be better than other detection techniques.Design/methodology/approachAlamouti's STBC uses two transmit antennas regardless of the number of receiver antennas. The encoding and decoding operation of STBC is shown in the earlier cited diagram. In the following matrix, the rows of each coding scheme represent a different time instant, while the columns represent the transmitted symbols through each different antenna. In this case, the first and second rows represent the transmission at the first and second time instant, respectively. At a time t, the symbol s1 and symbol s2 are transmitted from antenna 1 and antenna 2, respectively. Assuming that each symbol has duration T, then at time t + T, the symbols –s2* and s1*, where (.)* denotes the complex conjugate, are transmitted from antenna 1 and antenna 2, respectively. Case of one receiver antenna: The reception and decoding of the signal depend on the number of receiver antennas available. For the case of one receiver antenna, the received signals are received at antenna 1 , hij is the channel transfer function from the jth transmit antenna and the ith receiver antenna, n1 is a complex random variable representing noise at antenna 1 and x (k) denotes x at time instant k ( at time t + (k – 1)T.FindingsThe results obtained for maximal ratio combining (MRC) with 1 × 4 scheme show that the BER curve drops to 10–4 for signal-to-noise (SNR) ratio of 10 dB, whereas for MRC 1 × 2 scheme, the BER drops down to 10–5 for SNR of 20 dB. Results obtained in Table 1 show that when STBC is employed for MRC with 1 × 2 scheme (one antenna at transmitter node and two antennas at receiver node), BER curve comes down to 0.0076 for Eb/N0 of 12. Similarly, when MRC with 1 × 4 antenna scheme is implemented, BER drops down to 0 for Eb/N0 of 12. Thus, it can be concluded from the obtained graph that the performance of MRC with STBC gives improved results. When STBC technique is used with 3 × 4 scheme, at SNR of 10 dB, BER comes nearer to 10–6 (figure 7.3). It can be concluded from the analytics observed between AWGN and Rayleigh fading channel that for AWGN channel, BER is found to be equal to 0 for SNR value of 13.5 dB, whereas for Rayleigh fading channel, BER is observed nearer to 10–3 for Eb/N0 = 15. Simulation results (in figure 7.2) from the analytics show BER drops to 0 for SNR value of 12 dB.Research limitations/implicationsOptimal design and successful deployment of high-performance wireless networks present a number of technical challenges. These include regulatory limits on useable radio-frequency spectrum and a complex time-varying propagation environment affected by fading and multipath. The effect of multipath fading in wireless systems can be reduced by using antenna diversity. Previous studies show the performance of transmit diversity with narrowband signals using linear equalization, decision feedback equalization, maximum likelihood sequence estimation (MLSE) and spread spectrum signals using a RAKE receiver. The available IC techniques compatible with STBC schemes at transmission require multiple antennas at the receiver. However, if this not a strong constraint at the base station level, it remains a challenge at the handset level due to cost and size limitation. For this reason, SAIC technique, alternative to complex ML multiuser demodulation technique, is still of interest for 4G wireless networks using the MIMO technology and STBC in particular. In a system with characteristics similar to the North American Digital mobile radio standard IS-54 (24.3 K symbols per sec. with an 81 Hz fading rate), adaptive retransmission with time deviation is not practical.Practical implicationsThe evaluation of performance in terms of bit error rate and convergence time which estimates that MLD technique outperforms in terms of received SNR and low decoding complexity. MLD technique performs well but when higher number of antennas are used, it requires more computational time and thereby resulting in increased hardware complexity. When MRC scheme is implemented for singe input single output (SISO) system, BER drops down to 10–2 for SNR of 20 dB. Therefore, when MIMO systems are employed for MRC scheme, improved results based on BER versus SNR are obtained and are used for detecting the signal; comparative study based on different techniques is done. Initially ZF detection method is utilized which was then modified to ZF with successive interference cancellation (ZFSIC). When successive interference cancellation scheme is employed for ZFSIC, better performance is observed as compared to the estimation of ML and MMSE. For 2 × 2 scheme with QPSK modulation method, ZFSIC requires more computational time as compared to ZF, MMSE and ML technique. From the obtained results, the conclusion is that ZFSIC gives the improved results as compared to ZF in terms of BER ratio. ZF-based decision statistics can be produced by the detection algorithm for a desired sub-stream from the received vector whichs consist of an interference which occurred from previous transmitted sub-streams. Consequently, a decision on the secondary stream is made and contribution of the noise is regenerated and subtracted from the vector received. With no involvement of interference cancellation, system performance gets reduced but computational cost is saved. While using cancellation, as H is deflated, coefficients of MMSE are recalculated at each iteration. When cancellation is not involved, the computation of MMSE coefficients is done only once, because of H remaining unchanged. For MMSE 4 × 4 BPSK scheme, bit error rate of 10–2 at 30 dB is observed. In general, the most thorough procedure of the detection algorithm is the computation of the MMSE coefficients. Complexity arises in the calculation of the MMSE coefficients, when the antennas at the transmitting side are increased. However, while implementing adaptive MMSE receivers on slow channel fading, it is probable to recover the signal with the complications being linear in the antennas of transmitter node. The performance of MMSE and successive interference cancellation of MMSE are observed for 2 × 2 and 4 × 4 BPSK and QPSK modulation schemes. The drawback of MMSE SIC scheme is that the first detected signal observes the noise interference from (NT-1) signals, while signals processed from every antenna later observe less noisy interference as the process of cancellation progresses. This difficulty could be overcome by using OSIC detection method which uses successive ordering of the processed layers in the decreasing power of the signal or by power allocation to the signal transmitted depending on the order of the processing. By using successive scheme, a computation of NT delay stages is desired to bring out the abandoned process. The work also includes comparison of BER with various modulation schemes and number of antennas involved while evaluating the performance. MLD determines the Euclidean distance among the vector signal received and result of all probable transmitted vector signals with the specified channel H and finds the one with the minimum distance. Estimated results show that higher order of the diversity is observed by employing more antennas at both the receiving and transmitting ends. MLD with 8 × 8 binary phase shift keying (BPSK) scheme offers bit error rate near to 10–4 for SNR (16 dB). By using Altamonti space ti.Social implicationsIt should come as no surprise that companies everywhere are pushing to get products to market faster. Missing a market window or a design cycle can be a major setback in a competitive environment. It should be equally clear that this pressure is coming at the same time that companies are pushing towards “leaner” organizations that can do more with less. The trends mentioned earlier are not well supported by current test and measurement equipment, given this increasingly high-pressure design environment: in order to measure signals across multiple domains, multiple pieces of measurement equipment are needed, increasing capital or rental expenses. The methods available for making cross-domain, time-correlated measurements are inefficient, reducing engineering efficiency. When only used on occasion, the learning curve to understand how to use equipment for logic analysis, time domain and RF spectrum measurements often requires an operator to re-learn each piece of separate equipment. The equipment needed to measure wide bandwidth, time-varying spectral signals is expensive, again increasing capital or rental expenses. What is needed is a measurement instrument with a common user interface that integrates multiple measurement capabilities into a single cost-effective tool that can efficiently measure signals in the current wide-bandwidth, time-correlated, cross-domain environments. The market of wireless communication using STBCs has large scope of expansion in India. Therefore, the proposed work has techno-commercial potential and the product can be patented. This project shall in turn be helpful for remote areas of the nearby region particularly in Gadchiroli district and Melghat Tiger reserve project of Amravati district, Nagjira and so on where electricity is not available and there is an all the time problem of coverage in getting the network. In some regions where electricity is available, the shortage is such that they cannot use it for peak hours. In such cases, stand-alone space diversity technique, STBC shall help them to meet their requirements in making connection during coverage problem, thereby giving higher data transmission rates with better QOS (quality of service) with least dropped connections. This trend towards wireless everywhere is causing a profound change in the responsibilities of embedded designers as they struggle to incorporate unfamiliar RF technology into their designs. Embedded designers frequently find themselves needing to solve problems without the proper equipment needed to perform the tasks.Originality/valueWork is original.
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Pearce, Hammond, Ramesh Karri, and Benjamin Tan. "High-Level Approaches to Hardware Security: A Tutorial." ACM Transactions on Embedded Computing Systems, January 17, 2023. http://dx.doi.org/10.1145/3577200.
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Designers use third-party intellectual property (IP) cores and outsource various steps in the integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabilities have been rising. This is forcing IC designers and end users to re-evaluate their trust in ICs. If attackers get hold of an unprotected IC, they can reverse engineer the IC and pirate the IP. Similarly, if attackers get hold of a design, they can insert malicious circuits or take advantage of “backdoors” in a design. Unintended design bugs can also result in security weaknesses. This tutorial paper provides an introduction to the domain of hardware security through two pedagogical examples of hardware security problems. The first is a walk-through of the scan chain-based side channel attack. The second is a walk-through of logic locking of digital designs. The tutorial material is accompanied by open access digital resources that are linked in this article.
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"GaAs high-speed digital IC technology: an overview." Microprocessors and Microsystems 11, no. 2 (March 1987): 111. http://dx.doi.org/10.1016/0141-9331(87)90222-5.
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"Physical IC Design Layout of Memory-Based Real Fast Fourier Transform Architecture using 90nm Technology." International Journal of Recent Technology and Engineering 8, no. 5 (January 30, 2020): 3681–85. http://dx.doi.org/10.35940/ijrte.e6592.018520.
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In this paper we present a low complexity physical IC layout for memory based Real Fast Fourier Transform (RFFT) architecture using 90nm technology. FFT architectures are the most important algorithms in the modern communication systems like and very high bit rate digital subscriber line (VDSL) asymmetric digital subscriber line (ADSL). In this FFT algorithm is based on radix-2 decimation-in-frequency. In order to meet the real time requirements of very large scale integration (VLSI), we designed a low complexity and high speed FFT architecture. The RFFT architecture was realised using Verilog hardware description language (HDL). This architecture is simulated using Native code launch of cadence and synthesized using RTL code complier of cadence tool. Each step of application specific integrated circuit (ASIC) physical IC design flow was synthesized using cadence Innovus 90nm technology and we optimize the design to reduce the area, power and timing requirements