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Relevant bibliographies by topics / Digital IC hardware

Academic literature on the topic 'Digital IC hardware'

Author: Grafiati

Published: 10 December 2022

Last updated: 28 January 2023

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Dissertations / Theses
Book chapters
Conference papers

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Journal articles on the topic "Digital IC hardware"

1

Ananth, G. S., N. Shylashree, Satish Tunga, and Latha B. N. "A novel design for hardware interface board with reduced resource utilization." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 3 (December 1, 2021): 1414. http://dx.doi.org/10.11591/ijeecs.v24.i3.pp1414-1420.

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The final cost of an integrated circuit (IC) is proportional to its testing time. One of the main goals of test engineers when building an IC test solution is to reduce test time. Reduction of Test time is achieved by multi-site testing where multiple ICs are tested simultaneously using automated test equipment (ATE). During multi-site testing, if a certain test requires abundant resources, it is accomplished by testing one set of ICs at a time while the other ICs remain idle, thus lengthening the total test time. In digital-analog hybrid ICs, both analog and digital tests need to be performed, increasing the tester resource requirement and causing digital resource shortage. This paper describes a hardware interface board (HIB) design for a test case of a digital-analog IC on Teradyne’s ETS-364 ATE. The HIB's design allows the ATE to perform multi-site I<sup>2</sup>C based tests, which usually require lot of tester resources, utilizing only two digital resources and one measurement resource. This design achieves halving the I2C test time while lowering the number of resources necessary for multi-site testing compared to set-by-set testing. The proposed work has achieved up to 90.625% of resource reduction for multisite testing for a single test.

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Ni, Zhong Jin, Liang Fang, and Mao Jun Chen. "Realization of A Data Communication Card for A High Speed Digital Electronic Engraving Machine." Advanced Materials Research 476-478 (February 2012): 979–83. http://dx.doi.org/10.4028/www.scientific.net/amr.476-478.979.

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As the digital electronic engraving machine needs high speed and credible communication between a host computer and a slave computer, a data communication card for a high speed digital electronic engraving machine is designed and realized using PDIUSBD12 IC and S3C44B0X IC. PDIUSBD12 IC is USB interface device with parallel bus. In the paper, hardware circuit is described, USB driver program is depicted in detail based on the µC/OS-Ⅱ operation system, and the ways and means of debugging the data communication card are given. It has been experimentally validated that the data communication card is applied successfully and works steadily in high speed digital electronic engraving machines.

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Chien, Wei-Chen, Yu-Chian Chang, Yao-Tung Tsou, Sy-Yen Kuo, and Ching-Ray Chang. "STT-DPSA: Digital PUF-Based Secure Authentication Using STT-MRAM for the Internet of Things." Micromachines 11, no. 5 (May 15, 2020): 502. http://dx.doi.org/10.3390/mi11050502.

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Physical unclonable function (PUF), a hardware-efficient approach, has drawn a lot of attention in the security research community for exploiting the inevitable manufacturing variability of integrated circuits (IC) as the unique fingerprint of each IC. However, analog PUF is not robust and resistant to environmental conditions. In this paper, we propose a digital PUF-based secure authentication model using the emergent spin-transfer torque magnetic random-access memory (STT-MRAM) PUF (called STT-DPSA for short). STT-DPSA is an original secure identity authentication architecture for Internet of Things (IoT) devices to devise a computationally lightweight authentication architecture which is not susceptible to environmental conditions. Considering hardware security level or cell area, we alternatively build matrix multiplication or stochastic logic operation for our authentication model. To prove the feasibility of our model, the reliability of our PUF is validated via the working windows between temperature interval (−35 ∘ C, 110 ∘ C) and Vdd interval [0.95 V, 1.16 V] and STT-DPSA is implemented with parameters n = 32, i = o = 1024, k = 8, and l = 2 using FPGA design flow. Under this setting of parameters, an attacker needs to take time complexity O( 2 256 ) to compromise STT-DPSA. We also evaluate STT-DPSA using Synopsys design compiler with TSMC 0.18 um process.

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FIELDS, C. H., M. SOKOLICH, S. THOMAS, K. ELLIOT, and J. JENSEN. "Progress toward 100 GHz Logic in InP HBT IC Technology." International Journal of High Speed Electronics and Systems 11, no. 01 (March 2001): 217–43. http://dx.doi.org/10.1142/s0129156401000836.

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Future wideband communications, mm-wave digital synthesis, and digital beam-steering will benefit from digital operation at clock frequencies between 50 and 100 GHz at reasonable power levels. HRL has developed InP-based HBT technology that is capable of supporting these needs. We have demonstrated InP HBTs with cutoff frequencies, ft, over 200 GHz and with f max over 300 GHz as well as fully static dividers operating at 72.8 GHz.

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Wang, Jing Xia. "Design of Intelligent Management System for Open Labs Based on Wireless Transmission." Applied Mechanics and Materials 631-632 (September 2014): 889–93. http://dx.doi.org/10.4028/www.scientific.net/amm.631-632.889.

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This paper describes the design ideas of intelligent management system for open labs based on wireless transmission. The student legal identity authentication is completed using IC cards and the equipments power supply is controlled using wireless digital transceiver chip nRF401.The system hardware is simple, no complex wiring, easy to use. It can be used in any laboratory of electronic equipment, has the very good practicability and wide application prospects.

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OTSUJI, TAIICHI, KOICHI MURATA, KOICHI NARAHARA, KIMIKAZU SANO, EIICHI SANO, and KIMIYOSHI YAMASAKI. "20-40-Gbit/s-CLASS GaAs MESFET DIGITAL ICs FOR FUTURE OPTICAL FIBER COMMUNICATIONS SYSTEMS." International Journal of High Speed Electronics and Systems 09, no. 02 (June 1998): 399–435. http://dx.doi.org/10.1142/s0129156498000191.

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This paper describes recent advances in high-speed digital IC design technologies based on GaAs MESFETs for future high-speed optical communications systems. We devised new types of a data selector and flip-flops, which are key elements in performing high-speed digital functions (signal multiplexing, decision, demultiplexing, and frequency conversion) in front-end transmitter/receiver systems. Incorporating these circuit design technologies with state-of-the-art 0.12 μm gate-length GaAs MESFET process, we developed a DC-to-44-Gbit/s 2:1 data multiplexer IC, a DC-to 22-Gbit/s static decision IC, and a 20-to-40-Gbit/s dynamic decision IC. The fabricated ICs demonstrated record speed performances for GaAs MESFETs. Although further operating speed margin is still required, the GaAs MESFET is a potential candidate for 20- to 40-Gbit/s class applications.

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Chen, Qiang, Zhixin Tie, Liang Hong, Youtian Qu, and Dengwen Wang. "Improved Search Algorithm of Digital Speckle Pattern Based on PSO and IC-GN." Photonics 9, no. 3 (March 9, 2022): 167. http://dx.doi.org/10.3390/photonics9030167.

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Digital speckle correlation method has not only been widely used in a variety of photometric mechanical scenarios, but also integrated with multiple disciplines. In the future, it will even be inextricably linked to the Internet of Things, autonomous driving, deep learning and other fields. For a given hardware condition, it is of great significance to improve the efficiency of integer-pixel search and increase the accuracy and efficiency of the sub-pixel algorithm. In this paper, we propose an improved digital speckle correlation method, which consists of an integer-pixel search algorithm and a sub-pixel search algorithm. With respect to the integer-pixel search, aiming to address the two problems of uniqueness of maximum value and parameter setting of PSO-W algorithm, the algorithm PSO-1 is proposed, and the results of comparison experiments show that it has higher search efficiency. In terms of sub-pixels, based on IC-GN algorithm with the highest accuracy at present, the IV-ICGN algorithm is proposed, and the simulation experiment results show that the proposed algorithm has higher accuracy and higher efficiency than the comparison algorithm.

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8

Brück, Rainer. "Dingo-XT: A technology description language for analog and digital IC layout." Integration 17, no. 1 (August 1994): 53–81. http://dx.doi.org/10.1016/0167-9260(94)90020-5.

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LONG, STEPHEN I. "HIGH SPEED DIGITAL CIRCUIT TECHNOLOGY." International Journal of High Speed Electronics and Systems 06, no. 01 (March 1995): 163–210. http://dx.doi.org/10.1142/s0129156495000055.

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The performance of high speed digital integrated circuits, defined here as those requiring operation at high clock frequency, is generally more sensitive to material properties and process techniques than ICs used at lower frequencies. Obtaining high speed and low power concurrently is especially challenging. Circuit architectures must be selected for the device and application appropriately. This paper presents simple models for high speed digital IC performance and applies these to the FET and bipolar transistor. Heterojunction devices are compared with those using single or binary materials. Circuits for high speed SSI and low power VLSI applications are described, and their performance is surveyed.

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Kung, Ying-Shieh, Jin-Mu Lin, Yu-Jen Chen, and Hsin-Hung Chou. "ModelSim/Simulink Cosimulation and FPGA Realization of a Multiaxis Motion Controller." Mathematical Problems in Engineering 2015 (2015): 1–17. http://dx.doi.org/10.1155/2015/202474.

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This paper is to implement a multiaxis servo controller and a motion trajectory planning within one chip. At first, SoPC (system on a programmable chip) technology which is composed of an Altera FPGA (field programmable gate arrays) chip and an embedded soft-core Nios II processor is taken as the development of a multiaxis motion control IC. The multiaxis motion control IC has two modules. The first module is Nios II processor which realizes the motion trajectory planning by software. It includes the step, circular, window, star, and helical motion trajectory. The second module presents a function of the multiaxis position/speed/current controller IP (intellectual property) by hardware. And VHDL (VHSIC Hardware Description Language) is applied to describe the multiaxis servo controller behavior. Before the FPGA realization, a cosimulation work by ModelSim/Simulink is applied to test the VHDL code. Then, this IP combined by Nios II processor will be downloaded to FPGA. Therefore, a fully digital multiaxis motion controller can be realized by a single FPGA chip. Finally, to verify the effectiveness and correctness of the proposed multiaxis motion control IP, a three-axis motion platform (XYZtable) is constructed and some experimental results are presented.

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Dissertations / Theses on the topic "Digital IC hardware"

1

Patel, Mayank Raman. "HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275246.

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Shi, Jiajun. "Architecting NP-Dynamic Skybridge." 2015. https://scholarworks.umass.edu/masters_theses_2/171.

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With the scaling of technology nodes, modern CMOS integrated circuits face severe fundamental challenges that stem from device scaling limitations, interconnection bottlenecks and increasing manufacturing complexities. These challenges drive researchers to look for revolutionary technologies beyond the end of CMOS roadmap. Towards this end, a new nanoscale 3-D computing fabric for future integrated circuits, Skybridge, has been proposed [1]. In this new fabric, core aspects from device to circuit style, connectivity, thermal management and manufacturing pathway are co-architected in a 3-D fabric-centric manner. However, the Skybridge fabric uses only n-type transistors in a dynamic circuit style for logic and memory implementations. Therefore, it requires complicated clocking schemes to overcome signal monotonicity associated with cascading dynamic logic gates. For Skybridge’s large-scale circuits, the dynamic circuit style requires cascaded stages to be micro-pipelined, which results in large number of buffers used for storing minterms causing significant overhead in terms of area and power. Moreover, implementation of logic is limited to NAND or AND-of-NAND based logic expressions, which does not always result in compact circuits. In this work, we propose an extension of original Skybridge fabric, called NP-Dynamic-Skybridge, to solve these challenges by using both n-and p-type transistors in an innovative circuit style. Here, every stage in a given circuit is implemented by either n-type or p-type dynamic logic. Cascading n- and p-type dynamic logic effectively avoids signal monotonicity problem, and allows combinational-like circuit implementation. This helps to simplify the clocking scheme for cascaded logics requiring only one set of global precharge and evaluate clock signals. And also it expands the degree of expressing logic enabling expressions such as NOR, OR-of-NORs, in addition to those previously mentioned. Furthermore, the number of pipeline stages is significantly reduced for a given logic function, and buffer requirements are less compared with Skybridge 3D fabric thus improving on area and power metrics. Initial evaluation for NP-Dynamic-Skybridge’s 4-bit carry look-ahead adder shows up to 2x density benefits over Skybridge 3-D fabric and at least 17% power/throughput benefit.

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Book chapters on the topic "Digital IC hardware"

1

"Electrical Design for 5G Hardware-Digital Focus." In 3D IC and RF SiPs, 199–237. Singapore: John Wiley & Sons Singapore Pte. Ltd, 2018. http://dx.doi.org/10.1002/9781119289654.ch5.

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Conference papers on the topic "Digital IC hardware"

1

Miller, J. F., and P. Thomson. "Discovering novel digital circuits using evolutionary techniques." In IEE Colloquium Evolvable Hardware Systems. IEE, 1998. http://dx.doi.org/10.1049/ic:19980207.

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Miller, J. F. "An evolvable hardware approach to digital filter design." In IEE Half-day Colloquium on Evolutionary Hardware Systems. IEE, 1999. http://dx.doi.org/10.1049/ic:19990182.

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3

Noras, J. M. "Hardware-efficient turbo coding." In IEE Colloquium. Turbo Codes in Digital Broadcasting - Could it Double Capacity? IEE, 1999. http://dx.doi.org/10.1049/ic:19990798.

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Tempesti, G. "Embryonics: multi-cellular and multi-molecular digital systems." In IEE Half-day Colloquium on Evolutionary Hardware Systems. IEE, 1999. http://dx.doi.org/10.1049/ic:19990178.

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Vassilev, V. K. "Digital circuit evolution: the ruggedness and neutrality of two-bit multiplier landscapes." In IEE Half-day Colloquium on Evolutionary Hardware Systems. IEE, 1999. http://dx.doi.org/10.1049/ic:19990183.

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Acock, S. J. B. "Hardware implementations of algorithms on networks of FPGA processors." In IEE Colloquium on Digital System Design Using Synthesis Techniques. IEE, 1996. http://dx.doi.org/10.1049/ic:19960164.

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Il Song Han. "Hardware implementation of neuro-fuzzy system with the analogue-digital hybrid neural chip." In IEE Colloquium on Neural and Fuzzy Systems: Design, Hardware and Applications. IEE, 1997. http://dx.doi.org/10.1049/ic:19970733.

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Salous, S. "Computer based and dedicated hardware projects for the teaching of digital signal processing." In IEE Colloquium on The Teaching of Digital Signal Processing (DSP) in Universities. IEE, 1995. http://dx.doi.org/10.1049/ic:19950207.

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Taehong, Kim, Hong Jung-Hyun, and Chung Ki-Seok. "An efficient hardware and software co-verification method for HEVC decoders." In 2014 4th IEEE International Conference on Network Infrastructure and Digital Content (IC-NIDC). IEEE, 2014. http://dx.doi.org/10.1109/icnidc.2014.7000299.

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Kim, Yongmin, Jae Seong Lee, and Dong Kyue Kim. "Countermeasure techniques for SEED hardware modules against differential power analysis." In 2010 2nd IEEE International Conference on Network Infrastructure and Digital Content (IC-NIDC 2010). IEEE, 2010. http://dx.doi.org/10.1109/icnidc.2010.5657883.

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