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Ciacciulli, A. "FRUIT FLESH IN PEACH:CHARACTERIZATION OF THE 'SLOW SOFTENING' TEXTURE." Doctoral thesis, Università degli Studi di Milano, 2018. http://hdl.handle.net/2434/540666.
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The aim of this research was to deepen the knowledge about the slow softening texture in peach.
The texture is a synthesis of several parameters detected by senses, derived from the food structure. The paramount sense in the texture perception is the tactile one, principally perceived by hand and mouth. The tactile perception is a combination of four classes of mechanoreceptors, each one specialized to perceive mechanic deformation with different speed. This combined perception influences the consumer evaluation of food quality, giving the texture importance among food characteristics. The texture could also affect the taste perception through mechanical actions on food structure. The mechanical property linked to the texture is associated with the cellular organization and the cell wall strength. The main cell wall component affecting texture in fresh fruit is pectin, a polymer of galacturonic acid. The disassembly of pectin involves several enzymatic and non-enzymatic activities acting directly in pectin cleavage or indirectly disrupting non-covalent interactions. The gold standard of texture analyses is the sensorial one, however several issues make sensorial analyses inapplicable to breeding programs to select plant with improved fruit texture. Several efforts were made to achieve instrumental analyses capable of substitute humans in texture analyses. To mimic the tactile sense, a discipline studying the material response to an applied force, the rheology, is applied. The easiest instrumental measure of rheology parameters is the penetrometer test, diffused to measure the firmness, but exploitable to collect the Young’s modulus and the slope of yield stress represented respectively elasticity and fracturability.
In peach, so far at least four textures were described, melting (M), stony hard (SH), non-melting (NM) and slow softening (SS). Prior to this work, no reliable objective nor fast tool were available to phenotype and select the SS trait in peach germplasm. The only reliable approach was a sensorial assessment done by a texture-trained panel, requiring repeated and time-consuming assessment. An objective, instrumental method, was set up by processing the data of a digital penetrometer test. The penetrometer itself, as reported in paragraph 2, does not support the ability to discriminate among the different texture types, as already reported in other works. In addition, this method appears to be affected by the fruit ripening season, since the early-ripening accessions tend to show faster loss of firmness, while the late-ripening exhibit a slower firmness loss.
Using the data collected in our experiment, the texture dynamic (TD) model was developed from the observation of differences in the rheogram shape due to the elasticity and fracturability parameters. The TD model, that excludes the firmness effect on the fracturability and elasticity parameters, was thus developed, after testing it on 20 accessions in three years, allowing for reliable discrimination between SS and M phenotype. Differences in the TD were also found when comparing M vs SH and M vs NM textures. In particular, when comparing M and SS, TD value is explained for the 96% from the texture.
The developed method was then applied (together with sensorial evaluation) to genetically dissect the SS trait. Association and QTL mapping approaches were combined by analyzing a germplasm panel and a biparental progeny, and a single locus at the end of chromosome 8 was identified. RNA-seq analysis of 2 SS and 2 M accessions suggested some common features with the SH type described in literature. In both texture types a lower auxin response was found when compared to the M type. This agrees with the already known activity of auxin in the modulation of cell wall rearrangement and expansion. Therefore, slower softening could be associated to slower cell wall rearrangement. In future, comparison of auxin content in slow softening and melting type peaches might provide further insight into the validity of this hypothesis. In detail, by RNA-seq comparing M and SS a total of 64 differentially expressed genes were found in the genomic region harboring the SS locus. Out of these 64 genes, 16 are uncharacterized, while among the characterized ones, 4 are putatively involved in auxin response based on peach genome annotation. Analysis of polymorphisms in these 4 DEGs based on resequencing data of the ‘Max10’ and ‘Rebus 028’ parents of biparental population did not uncover any variants in agreement with the observed segregation. Analyzing 2kb gene models flanking regions, 16 genes were associated with polymorphisms outside the coding sequence: the possible regulatory effects of such variants require further evaluation by expression analyses.
In summary, the major results are the setup of a reliable tool to score objectively the SS texture and the detection of a major locus and his dominant mendelian inheritance. However, NGS and RNA-seq approaches are presented as a speculative data only, because they are not supported by hormones content in fruit, and the large locus detected did not allow indication of a putative variant.
These results will: a) give impetus in exploring SS genetic and physiology; b) support the design of future crosses and experiments; c) increase marker density in the locus; d) point out the possible central role of auxin (to validate the hypothesis of a similarity between SS and SH physiology); e) allow texture assessment of improved cultivars; and f) allow phenotyping of segregating progenies to develop molecular markers associated with the SS trait.
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Majidi, Rabeeh. "DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-dissertations/275.
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With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington,MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100kSps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich,RI.
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Puig, Mailhol Vincent. "Le numérique et l'esprit. Prendre soin des technologies numériques de l'esprit à la lumière de Gilbert Simondon, Maurice Merleau-Ponty, Henri Bergson." Electronic Thesis or Diss., Poitiers, 2023. http://www.theses.fr/2023POIT5001.
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Cette adresse aux designers procède d'une démarche de décentrement anthropologique pour tenter de penser et prendre soin du digital comme spiritual au sens où Derrida interprétait ainsi le processus de questionnement mais aussi la technique chez Heidegger. Cet itinéraire passe par une critique de la notion d'information chez Simondon pour repenser « l'âme des objets ». Il se poursuit par une analyse de la question de la chair à partir de Merleau-Ponty pour proposer le passage d'une « chair souffrante du numérique » à une organologie et une pharmacologie du geste digital. Il aborde enfin ce que Bernard Stiegler nommait les technologies de l'esprit, par le prisme de l'intuition bergsonienne et de la transduction simondonienne pour réintroduire la pensée analogique dans le design numérique d'une bienveillance dispositive, condition techno-esthétique, éthique, cosmotechnique et politique du développement du bien commun et des savoirsThis address to designers stems from an approach of anthropological decentering to think and take care of the digital as spiritual in the sense that Derrida designated the process of questioning but also the of technique in Heidegger. This route goes through a critique of the notion of information in Simondon to try to rethink "the soul of objects". It continues with an analysis of the question of the Flesh from Merleau-Ponty to propose the passage from a "digital suffering flesh" to an organology and a pharmacology of the digital gesture. Finally, it approaches what Bernard Stiegler called the technologies of the through the prism of Bergsonian intuition and Simondonian transduction to reintroduce analogical thought into the digital design of a dispositive benevolence, techno-estheú, cosmotechnic, ethical and political condiú)n for the development of the common good and of knowledge
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Seto, Jim Carleton University Dissertation Engineering Electrical. "An 8 bit BiCMOS subranging flash analog to digital converter." Ottawa, 1991.
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Hassan, Raza Naqvi Syed. "1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8382.
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The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.
Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.
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Sivakumar, Balasubramanian. "A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control." The Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=osu1229631191.
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Säll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator Technology." Licentiate thesis, Linköping University, Linköping University, Electronics System, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5260.
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High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.
To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.
The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.
The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.
A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.
Report code: LiU-Tek-Lic-2005:68.
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Cicalo, James. "An embedded calibration technique for high-resolution flash time-to-digital converters." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/31637.
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As CMOS technology continues to advance, device dimensions will continue to decrease, thus enabling the creation of circuits which operate at increasingly greater frequencies. However, this Increase In operating frequency has resulted in a reduced tolerance for circuit timing uncertainties. Therefore, techniques capable of measuring the timing characteristics of multi-GHz signals are needed to help address the growing number of timing problems found in modem CMOS circuits. For cost and accuracy reasons, embedded time interval measurement techniques which offer picosecond measurement accuracies and millisecond test-times are required to overcome these challenges. The "sampling offset" based flash time-to-digital converter (SOTDC) is an embedded time interval measurement technique that has recently garnered much attention due to its attractive properties. These properties include sub-millisecond test times of multi-GHz signals, in addition to the potential for measurement accuracies in the order of picoseconds. However, the accuracy of an SOTDC is strongly dependent upon the capabilities of its calibration technique, and present SOTDC calibration techniques suffer from some very serious limitations. In fact, these limitations are so severe that present calibration techniques are impractical under realistic production test conditions. This thesis presents the design and analysis of a novel embedded SOTDC calibration technique. The proposed calibration technique offers the potential for both sub-picosecond calibration accuracies and sub-100 millisecond calibration times. However, the main contribution of this work concerns the suitability of the proposed technique with a realistic production test environment. The capabilities of the proposed calibration technique have been proven using both mathematical analysis and behavioural modelling simulations.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Säll, Erik. "Implementation of flash analog-to-digital converters in silicon-on-insulator technology /." Linköping : Linköpings universitet, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5260.
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Guerrero, Maximiliano. "“3-1, shut your flash” : How shooter games convey agency." Thesis, Karlstads universitet, Institutionen för geografi, medier och kommunikation (from 2013), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-80328.
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This study aims to understand how games teach the player how to enact agency within them. Agency refers to the ability of the player to actively interact with the world around them, and understand the circumstances and results of those actions. Three games of the shooter sub-genre were selected: Call of Duty: Modern Warfare (2019), Cuphead, and Red Dead Redemption 2. These were chosen as they are modern representations of three of the most popular genres within the shooter mantle: First-Person Shooter, Run and Gun, and Third-Person Shooter, respectively. Each game’s first level was analyzed to see how they introduce the selected definition of agency. Each element that was found to convey agency was categorized according to it being diegetic (existing within the story) or non-diegetic (existing outside the story), explicit or implicit, and by the level of agency play it represented, these being Agency Relationship (the relationship between the user agency and system agency), Agency Scope (the impact the player’s actions will have on the narrative), Agency Dynamics (changes in agency through time, or more accurately, in different circumstances) and User Input Direction (what controls can be pressed to perform certain direct actions). These elements and their respective categories have been represented in a cell document, followed by which categories they belong to. Furthermore, for each game, the categories and which elements represent them are displayed as well, for a more identifiable examination of each category’s representation in each game, and to allow for comparison between them. Each level was described in accordance with the elements that conveyed agency, in their order of appearance. The elements or instances were described, and what categories they belong to were noted as well. In addition, explanations for why they belong to those specific categories were expressed if necessary. Conclusively, the games were shown to contain certain similarities among them, such as agency relationship being conveyed through the positioning of certain elements in connection to their environment and the player. However, the differences between the games were more prominent than their similarities. With each game having a particularly noticeable way in which they presented a great deal of the elements. In Modern Warfare, the game tried to use as few non-diegetic and as many diegetic elements as possible. In Cuphead, the game presented agency exclusively through enemy and object placement in relation to the level to teach the player about how certain mechanics functioned. And in Red Dead Redemption 2, the game tries to teach the player about game mechanics by juxtaposing the narrative, non-diegetic explanations, and diegetic instances, to accustom players to a fusion of elements trying to communicate the same message.
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Sheikhaei, Samad. "A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/2746.
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The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed and power specifications of high speed low to medium resolution analog to digital converters (ADCs). While multi channel ADCs can achieve high speeds, they often require extensive and costly post fabrication calibration.
A single channel 4 bit flash ADC, suitable for abovementioned or similar applications, implemented entirely using current mode logic (CML) blocks, is presented. CML implementation allows for high sampling rates, while typically providing low power consumption at high speeds. To improve the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the ADC are fully pipelined. Furthermore, the logic functions in the encoder are reformulated to reduce wire crossings and delay and to equalize the wires lengths in the layout. To keep the design simple, inductors are avoided. As a result, a compact design with small wire parasitics is achieved. Moreover, some geometric layout techniques, including a common centroid layout for the resistor ladder, are introduced to reduce the effect of mismatches to eliminate the use of digital calibration.
The ADC is designed and fabricated in 0.18um CMOS and operates at 4GS/s. It achieves an effective number of bits (ENOB) of 3.71 (3.14, 2.75) for a 10MHz (0.501GHz, 1.491GHz) signal sampled at 4GS/s (3GS/s, 3GS/s). Differential/integral nonlinearity (DNL/INL) errors are between +/-0.35LSB and +/-0.26LSB, respectively. The ADC consumes 43mW from a 1.8V supply and occupies 0.06mm2 active area.
Due to the use of CML circuits, the ADC achieves the highest speed reported for a single channel 4 bit ADC in a 0.18um CMOS technology. It also reports the best power performance among the 4-bit ADCs with similar or higher speeds. The active area is also among the smallest reported.
In addition, in this thesis, the signal to noise ratio (SNR) of an ADC is formulated in terms of its INL performance. The related formulas in the literature are not accurate for low resolution ADCs, and yet they do not take the input waveform into account. Two standard waveforms, ramp and sinusoid, are considered here. The SNR formulas are derived and confirmed by simulation results.
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Säll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator CMOS Technology." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8712.
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A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluation through implementation of three flash analog-to-digital converters (ADCs). Our study indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be replaced by a fully depleted technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved. A strong motivator for using the SOI CMOS technology instead of bulk CMOS seems to be the smaller gate leakage power consumption. The targeted applications in mind for the ADCs are read channel and ultra wideband radio applications. These applications requires a resolution of at least four to six bits and a sampling frequency of above 1 GHz. Hence the flash ADC topology is chosen for the implementations. In this work we do also propose enhancements to the flash ADC converter. Further, this work also investigates introduction of dynamic element matching (DEM) into a flash ADC. A method to introduce DEM into the reference net of a flash ADC is proposed and evaluated. To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a top-down design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level using MATLAB and SpectreHDL. The modeling results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase. The first flash ADC implementation has a conventional topology. It has a resistor net connected to a number of latched comparators and employs a ones-counter thermometer-to-binary decoder. This ADC serves as a reference for evaluating the other topologies. The measurements indicate a maximum sampling frequency of 470 MHz, an SNDR of 26.3 dB, and an SFDR of about 29 to 35 dB. The second ADC has a similar topology as the reference ADC, but its thermometer-to-binary decoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact decoder with a regular structure and a short critical path. The measurements show that it is more efficient in terms of power consumption than the ones-counter decoder and it has 40 % smaller chip area. Further, the SNDR and SFDR are similar as for the reference ADC, but its maximum sampling frequency is about 660 MHz. The third ADC demonstrates the introduction of DEM into the reference net of a flash ADC. Our proposed technique requires fewer switches in the reference net than other proposals. Our technique should thereby be able to operate at higher sampling and input frequencies than compared with the other proposals. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB in average when introducing DEM. The transistor level simulations in Cadence and measurements of the ADC with DEM indicates that the SFDR improves by 6 dB and 1.5 dB, respectively, when applying DEM. The smaller improvement indicated by the measurements is believed to be due to a design flaw discovered during the measurements. A mask layer for the resistors of the reference net is missing, which affects their accuracy and degrades the ADC performance. The same reference net is used in the other ADCs, and therefore degrades their performance as well. Hence the measured performance is significantly lower than indicated by the transistor level simulations. Further, it is observed that the improved SFDR is traded for an increased chip area and a reduction of the maximum sampling frequency. The DEM circuitry impose a 30 % larger chip area.
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Säll, Erik. "Implementation of flash analog-to-digital converters in silicon-on-insulator CMOS technology /." Linköping : Department of Electrical Engineering, Linköping University, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8712.
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Carter, Nathan R. "A 12-b 50Msample/s Pipeline Analog to Digital Converter." Digital WPI, 2000. https://digitalcommons.wpi.edu/etd-theses/749.
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This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage structure. Correction of the pipeline is accomplished by measuring the offset and gain of each of the first six stages using subsequent stages. The measured values are used to calculate digtal values the compensate for the inaccuracies of the analog pipeline. Corrected digital values for each stage are stored in the pipeline and used to create corrected output codes. Errors caused by measuring the first six stages using uncalibrated stages are minimized by using extra switching circuitry during calibration.
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Figueiredo, Michael. "Reference-free high-speed cmos pipeline analog-to-digital converters." Doctoral thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8776.
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Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering of the Faculdade de Ciências e Tecnologia of Universidade Nova de LisboaMore and more signal processing is being transferred to the digital domain to profit from the technological enhancement of digital circuits. Where technology scaling enhances the capabilities of digital circuits, it degrades the performance of analog circuits. However, it is important to note that the impact that technology scaling has on digital circuits is becoming smaller and smaller, which means that, in nanotechnologies, to enhance energy and area efficiency, we can not simply depend on the benefits of this scaling. Although, a share of the efficiency can be obtained from the technology, new circuit architectures and techniques have to be developed to really push the limits of efficiency. In data converters, more specifically analog-to-digital converters (ADCs), a decision can be made: research energy and area efficient analog circuit techniques and architectures that cope with technological scaling issues, or design algorithms that use digital circuitry to assist the poor analog technological performance. The former option is the premise for the work developed in this thesis. The work reported in this thesis explores various design techniques with the purpose of enhancing the power and area efficiency of building blocks mainly to be used in multiplying digital-to-analog converter based ADCs. Therefore, novel analog techniques are developed for the three main blocks of an MDAC-based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. These techniques include self-biasing and inverter-based design for the flash quantizer and amplifier. Regarding the MDAC, it combines three techniques: unity feedback factor, insensitivity to capacitor mismatch, and current-mode reference shifting. In the second part of this work, the designed amplifier is implemented and experimentally characterized demonstrating its practical feasibility and performance. The final part of this work explores the design and implementation of a medium-low resolution high speed pipeline ADC incorporating all the developed circuits. Experimental results validate the feasibility of the techniques and demonstrate the attractiveness in terms of power dissipation and reduced area.
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Brady, Philomena C. "Offset correction in flash ADCs using floating-gate circuits." Thesis, Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/14832.
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Lindh, Lina, and Atena Ahmadi. "Digital presentation av Sunnerbogymnasiet : - En studie över hur VR kan användas för att locka nya elever." Thesis, University of Kalmar, School of Communication and Design, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:hik:diva-2105.
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Syftet med detta arbete är att skapa en applikation som ska hjälpa och gynna Sunnerbogymnasiet när det gäller att locka till sig elever som går på högstadiet. För att göra detta har gruppen använt sig av bland annat VR (Virtual Reality) och Panorama som metoder till att göra applikationen attraktiv för målgruppen. För att få fram vad som kan locka elever till att använda applikationen utfördes enkätundersökningar på målgruppen som är elever i årskurs 8-9. Genom undersökningarna fick gruppen fram vad för information applikationen bör innehålla för att locka till sig elever. Med hjälp utav intervjuerna som utfördes på elever som går på Sunnerbogymnasiet, framkom det vilka platser som eleverna ansåg vara populärast på skolan. På dessa platser togs det bilder som sedan gjordes om till panorama filmer. Det finns en introduktionsdel där gruppen har visualiserat Sunnerbogymnasiets entré. Tanken bakom det är att elever ska känna igen sig när de besöker skolan. Resultatet blev en kompletterande applikation med en introduktionsfilm i 3D som föreställer skolans entré. För att visa upp populära platser på skolan finns det panorama filmer på dessa platser.
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EL, RACHINI ALI. "Redundant analog to digital conversion architectures in CMOS technology." Doctoral thesis, Università degli Studi di Cagliari, 2015. http://hdl.handle.net/11584/266860.
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The operation of modern electronic devices in different fields as communications, signal processing, and sensor interface is critically affected with robust, high performance and scalable Analog-to-Digital Converter (ADCs), that can be considered as one of the main blocks in many systems, since they are mandatory to make the link between the analog outside world and the evermore-ubiquitous digital computer world. The design of these ADCs come distinct tradeoffs between speed, power, resolution, and die area embodied within many data conversion architectural variations.
The flash ADC structure are often the base structure for high-speed operation and simple architecture analog-to-digital converters (ADCs). As the input signal is applied to (2
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Ritter, Philipp. "Design and optimization of high speed flash analog-to-digital converters in SiGe BiCMOS technologies." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0052.
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Le Convertisseur Analogique Numérique (CAN) est une brique essentielle de la ré- ception et du traitement des données à très haut débit. L’architecture de type "flash" effectue la quantification en comparant simultanément le signal analogique d’entrée à l’ensemble des références du codeur, ce qui en fait, par construction, l’architecture la plus rapide de CAN. Par le passé, cette architecture a démontré des capacités de codage supérieures à 20GS/s dans les conditions de Nyquist. Cependant, cette capac- ité à travailler à très haute vitesse a donné le jour à des réalisations très consommantes (plusieurs Watts) donc peu efficaces énergétiquement. Cette thèse explore différentes approches d’optimisation de l’efficacité énergétique des CAN "flash". Afin de min- imiser la consommation du CAN, il n’y a pas d’Echantillonneur-Bloqueur (EB) en tête du circuit. Les étages d’entrée du codeur sont ainsi exposés à la pleine bande passante du signal, à savoir DC-10GHz. Ceci impose des contraintes très strictes sur la précision temporelle de la détection et de la quantification du signal. L’essentiel de cette thèse est donc concentré sur l’analyse des effets hautes frèquences impactant la conception des éléments frontaux du CAN. La validité et l’efficacité des méthodes présentées sont démontrées par des mesures autour d’un CAN 6 bit 20 GS/s. En em- pruntant les techniques de conception des circuits ultra-rapides et en exploitant le po- tentiel haute-fréquence de la technologie à l’état de l’art SiGe BiCMOS, un circuit complètement analogique a ainsi pu être réalisé. Ce CAN est mono-voie et n’a besoin d’aucune calibration ou correction, ni d’assistance digitale. Avec à peine 1W, ce cir- cuit atteint un record d’efficacité énergétique dans l’état de l’art des CAN rapides non entrelacésHigh speed Analog-to-Digital Converters (ADC) are essential building blocks for the reception and processing in high data rate reception circuits. The flash ADC archi- tecture performs the digitization by comparing the analog input signal to all refer- ence levels of the quantization range simultaneously and is thus the fastest architecture available. In the past the flash architecture has been employed successfully to digitize signals at Nyquist rates beyond 20 GS/s. However the inherent high speed operation has led to power consumptions of several watts and hence to poor energy efficien- cies. This thesis explores approaches to optimize the energy efficiency of flash ADCs. In particular, no dedicated track-and-hold stage is used at the high speed data input. This imposes very stringent requirements on the timing accuracy and level accuracy in the high speed signal distribution to the comparators. The comparators need to ex- hibit a very high speed capability to correctly perform the quantization of the signal against the reference levels. The main focus of this thesis is hence the investigation of design relevant high frequency effects in the analog ADC frontend, such as the bandwidth requirement of overdriven comparators, the data signal distribution over a passive transmission line tree and the dynamic linearity of emitter followers. The correctness and efficacy of the presented methods is demonstrated by measurement results of a 6 bit 20 GS/s Nyquist rate flash ADC fabricated within the context of this work. The demonstrator ADC operates without time interleaving, no calibration or correction whatsoever is needed. By employing design techniques borrowed from high speed analog circuits engineering and by exhausting the high speed potential of a state-of-the-art SiGe BiCMOS production technology, a flash ADC with a record energy efficiency could be realized
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Savory, Fuller Rebecca. "Embodying 'new India' through remixed global performance : flash mobs redefined in contemporary urban India, 2003-15." Thesis, University of Exeter, 2018. http://hdl.handle.net/10871/33146.
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This thesis conducts a history of flash mob performance in India, asking how the form has evolved over a 12-year period from its first emergence in 2003. Due to its rhizomatic appearance worldwide and its close association with internet technologies and digital culture, the flash mob has typically been treated as a ‘global’ phenomenon, and theories of flash mob performance derived from Euro-American contexts are frequently glossed as generic. However, this thesis asks what a close history of the genre in India can reveal, both in terms of the performance practice itself, and as a reflection of the specific cultural moment in which it emerged. It offers an examination of the processes of adaptation and remix underway as a ‘global’ performance practice has been re-interpreted and re-enacted from this specific, local and historical perspective, and it argues that these processes demonstrate one of the ways in which performance, particularly in a digital sphere, can operate to effect a ‘politics of forgetting’ in globalising India. To do so, the thesis employs an interdisciplinary approach combining ethnographic and archival research, and draws on literature and theory from both performance studies and social sciences. The flash mob form is shown to have emerged in two distinct waves, marked by aesthetic and formal shifts which I relate to the evolving mediascape of the internet during this period. In its second wave, the genre has become spectacularised for an online video context and ‘Bollywoodised’ within an Indian context, reflecting broader practices of hybridity as well as cultural tensions surrounding national identity in globalising India. The thesis positions flash mob performance in this context as a social media practice engaged in symbolic, representational discourses which perform place and identity within a global sphere.
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Wang, Mingzhen. "High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.
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Rossoni, Mattos Diego. "Design and characterization of an 8gsps flash analog-to-digital converter for radio astronomy and cosmology applications." Thesis, Bordeaux 1, 2012. http://www.theses.fr/2012BOR14653/document.
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Un Convertisseur Analogique-Numérique (CAN) pour les applications spatiales en astrophysique et cosmologie a été développé au cours de cette thèse. Cette catégorie de circuits demande des bandes passantes très larges, de très hautes fréquences d'échantillonnage et une faible résolution. L’architecture flash a été retenue pour sa rapidité et sa bande passante. La fréquence d’échantillonnage est de 8GHz. La technologie utilisée est la CMOS 65 nm de chez STMicroeletronics. La conception a été faite en deux phases. Une première qui a amené à un prototype d'un échantillonneur-bloqueur et une deuxième qui a amené au CAN. Les deux prototypes ont été caractérisés et à partir de ces résultats des perspectives d'amélioration pour les nouvelles implémentations ont été retrouvées.Pour atteindre l'objectif final du CAN multi-bits (6-bit sont visés) il a été décidé de dessiner une première version du CAN avec la moitié de la résolution initialement prévue (on passe de 6-bit à 3-bit). L'objectif est de nous permettre d’analyser le comportement des blocs fonctionnels intégrés et ensuite passer à une deuxième voire troisième version pour remplir le cahier des charges initialAn Analog-to-Digital Converter (ADC) has been developed for astrophysical and cosmological applications. This class of circuits demands, especially in the millimeter wavelength domain, ultra wide bandwidths, ultra high sampling frequencies and a low resolution. The “flash” architecture has been chosen for its speed and bandwidth. This ADC samples at 8Gsps and it has been fabricated in 65nm CMOS technology from STMicroelectornics.The design has been done in two steps. The first was the prototype of a track-and-hold circuit. The second was the ADC. Both circuits have been characterized and from these results some perspectives for further improvements have been proposed.In order to achieve the final goal of the multi-bit ADC (6-bit resolution) we have decided to design a first prototype with half the final resolution, namely a 3-bit resolution ADC. Our idea was, with this first prototype, to conduct a first analysis of the behavior of the integrated functional blocks and, consequently, find the correct improvements required for the ADC final version
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Hennen, John Andrew. "Registration Algorithms for Flash Inverse Synthetic Aperture LiDAR." University of Dayton / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1576142937639181.
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Antonopoulou, Aikaterini. "From digital creations of space to analogous experiences of places : living in second life and acting in Flash Mob." Thesis, University of Newcastle upon Tyne, 2013. http://hdl.handle.net/10443/2316.
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This dissertation aims to raise the question of how individuals and groups become placed – or take up place – in the contemporary environment and to consider what forms the need for situatedness takes today, by examining the phenomena of the Flash Mob and Second Life. In a Flash Mob, an email activates a virtual community and converts it into a physical performance in the city, challenging a new cognition of place, where place is constituted by the event. On the other hand, Second Life takes the form of a digitally constructed world, which opens the possibility of a “virtual place” that enables users to establish connections not only with each other, but also with the [virtual] environment itself. The two case studies together question place in its materiality and its symbolism, and it is argued that they act as media to re-code “groundedness”. Thus we reach a paradoxical conclusion: although the contemporary world suggests a dynamic and more flexible existence on the earth, the need for “situatedness” and the demand for “well-grounded claims” remain stronger than ever. The structure of this research reflects a double set of conditions that, although not new, have intensified due to the emergence of new technologies: first, the expansion of the human body beyond its corporeal limits and second, the augmentation of the perceived world beyond the mere materiality of any kind of environment. Therefore the thesis studies how, on the one hand, bodies, communities and crowds transform within digitisation, and, on the other, how the world develops as a consequence of the digital reconstruction of grounds. It examines the way in which individuals detach from their “real-world groundedness” by forming bonds-connections to these digitised grounds, which display – as generators of endless possibilities – a kind of utopian openendedness. Finally, it explores the phenomenon of “virtualisation” to raise the question of whether the contemporary world is infused by information and thus augmented in terms of meanings, connections, and attachments, or is instead made of a series of projections, transforming reality into an idealised version of itself.
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Kakizaki, Valter Eiji 1988. "Aspectos gerais e técnicos do violino/viola sob a perspectiva de Carl Flesch e Ivan Galamian : suas influências na era digital." [s.n.], 2014. http://repositorio.unicamp.br/jspui/handle/REPOSIP/285225.
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Orientador: Emerson Luiz De BiaggiDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Artes
Made available in DSpace on 2018-08-26T08:41:14Z (GMT). No. of bitstreams: 1 Kakizaki_ValterEiji_M.pdf: 7721830 bytes, checksum: 6364af8be28879188712d29b477bdcc2 (MD5) Previous issue date: 2014
Resumo: Este trabalho tem por finalidade a compreensão e comparação dos pensamentos de dois dos mais importantes pedagogos do ensino de violino no século XX, Carl Flesch e Ivan Galamian, e averiguar suas influências nos dias de hoje em vídeos disponibilizados na internet. Inicialmente levantamos nos livros The Art of Violin Playing (Carl Flesch, 1923) e Principles of Violin Playing and Teaching (Ivan Galamian, 1962) as principais ideias desses autores sobre aspectos gerais, técnicos e interpretativos, fazendo uma comparação entre suas propostas pedagógicas. Em seguida analisamos os materiais pedagógicos postados na internet por professores de reconhecida competência, Todd Ehle e Kurt Sassmannshaus, observando os mesmos aspectos e parâmetros observados nos livros, verificando como as informações transmitidas por esses últimos se relacionam com as técnicas sugeridas por Carl Flesch e Ivan Galamian
Abstract: The purpose of this study is to understand and compare the thoughts of two of the most important violin pedagogues of the 20th Century, Carl Flesch and Ivan Galamian, and investigate their influences nowadays in videos available on the internet. Therefore, we summarized the main ideas presented by the two authors regarding general, technical and interpretative aspects in the books "The Art of Violin playing " (Carl Flesch, 1923) and "The Art of Violin Playing and Teaching" (Ivan Galamian, 1962), making a comparison between their pedagogical proposals. Then, we examined the pedagogical materials posted on the internet by professors of recognized competence, Todd Ehle e Kurt Sassmannshaus, observing the same aspects and parameters discussed in the two books, verifying how this more recent material relates to the techniques suggested by Carl Flesch and Ivan Galamian
Mestrado
Praticas Interpretativas
Mestre em Música
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Hiremath, Vinayashree. "DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.
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Stefanou, Nikolaos. "A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18(mu)m CMOS." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2469.
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Hard disk drive applications require a high Spurious Free Dynamic Range (SFDR),
6-bit Analog-to-Digital Converter (ADC) at conversion rates of 1GHz and beyond.
This work proposes a robust, fault-tolerant scheme to achieve high SFDR in an av-
eraging flash A/D converter using comparator chopping. Chopping of comparators
in a flash A/D converter was never previously implemented due to lack of feasibility
in implementing multiple, uncorrelated, high speed random number generators. This
work proposes a novel array of uncorrelated truly binary random number generators
working at 1GHz to chop all comparators.
Chopping randomizes the residual offset left after averaging, further pushing
the dynamic range of the converter. This enables higher accuracy and lower bit-error
rate for high speed disk-drive read channels. Power consumption and area are reduced
because of the relaxed design requirements for the same linearity.
The technique has been verified in Matlab simulations for a 6-bit 1Gsamples/s
flash ADC under case of process gradients with non-zero mean offsets as high as 60mV
and potentially serious spot offset errors as high as 1V for a 2V peak to peak input
signal. The proposed technique exhibits an improvement of over 15dB compared to
pure averaging flash converters for all cases.
The circuit-level simulation results, for a 1V peak to peak input signal, demon-
strate superior performance. The reported ADC was fabricated in TSMC 0.18 ??mCMOS process. It occupies 8.79mm2 and consumes about 400mW from 1.8V power
supply at 1GHz. The targeted SFDR performance for the fabricated chip is at least
45dB for a 256MHz input sine wave, sampled at 1GHz, about 10dB improvement on
the 6-bit flash ADCs in the literature.
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Grillo, Kelly J. "An investigation of the effects of using digital flash cards to increase biology vocabulary knowledge in high school students with learning disabilities." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4907.
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The field of science education, specifically biology, is becoming more challenging due to richer and more rigorous content demands. Along with new demands is the emergence of National Common Core Standards and End of Course Exams. Despite these changes, one factor remains consistent: As content knowledge increases, language demands also increase. For students with learning disabilities (LD), specifically those with language-based disabilities, the increasing vocabulary demand can lead to failure due not to a lack of understanding biology but the vocabulary associated with the content. In an attempt to impact high school students with learning disabilities'success in biology, a vocabulary intervention was investigated. Research suggests as more and more content is compressed into science courses, teachers are looking toward technology to assist with vocabulary mastery. The current research study examined the effects of a digital flash card intervention, Study Stack, versus a paper flash card intervention in biology for students with LD by measuring students'word knowledge and overall biology course achievement. Findings from repeated measures ANOVA showed a statistically significant increase on both the vocabulary assessment as well as the course grades in biology over time. However, the test of between effects considering card type yielded no differential change on vocabulary assessment and course grades in biology. Based on qualitative data, students interviewed liked the tool and found it to be helpful in learning biology terminology.ID: 030423499; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 212-221).
Ph.D.
Doctorate
Education
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Vaiho, :. Sara. "Konsten att döda en digital teknologi och tillvaron därefter : En kvalitativ studie om aktiviteter vid avvecklingen av ettinformationssystem." Thesis, Mittuniversitetet, Institutionen för data- och systemvetenskap, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-41258.
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To end the use of a digital technology one must go througha process that research entitle information systems (IS)discontinuance. Prior research has developed phases andactivities that can be implemented in the IS discontinuanceprocess, but this knowledge is limited and has not beencompiled. This study purpose is therefore to create a modelof the IS discontinuance process and in it identify furtheractivities. To accomplish this, a real IS discontinuance hasbeen studied, who has had different circumstances andstakeholders than of previous studies. The discontinuanceprocess has occurred at a large organisation whomanufacture vehicles and the study has been conducted incollaboration with this organisation. The studied IS inquestion is an eLearning authoring tool. Information aboutthis discontinuance process has been collected throughsemi-structured personal interviews with five participantswho are employees at the organisation. The collected datahas been analysed and interpreted in comparison to atheoretical model of the IS discontinuance process, whichcontains phases and activities. The result of the analysis andinterpretation is an iterative model of the IS discontinuanceprocess with phases and activities, of which 34 are newfound activities. A big part of these activities can be relatedto the new circumstance and stakeholders within thestudied discontinuance processAtt sluta använda digitala teknologier sker genom en processsom forskningen benämner sominformationssystemsavveckling (IS-avveckling). Tidigareforskning har tagit fram faser och aktiviteter som kangenomföras i IS-avvecklingsprocessen, men denna kunskapär begränsad och har inte sammanställts. Denna studie syftarsåledes att skapa en modell av IS-avvecklingsprocessen och iden identifiera ytterligare aktiviteter. För att realisera dettahar en verklig IS-avvecklingsprocess studerats som haft ettannat förhållande och intressenter än i tidigare studier.Avvecklingen har skett hos en stor organisation somtillverkar fordon och studien har genomförts tillsammansmed dem. Avvecklingen harutförts på organisationens eLearning författarverktyg.Information om avvecklingen har samlats in genomsemistrukturerade personliga intervjuer med fem styckenrespondenter som är anställda hos organisationen. Deninsamlade datan har analyserats och tolkats i jämförelse meden framtagen teoretisk modell för IS-avvecklingsprocessensom innehåller faser och aktiviteter. Resultatet av analysenoch tolkningen blev en iterativ modellen för ISavvecklingsprocessen med faser och aktiviteter, varav 35stycken nya aktiviteter hittats. Stor del av dessa nyaaktiviteter kan kopplas till det nya förhållandet ochintressenterna i avvecklingen.
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Josyula, Sai Prashanth. "On the Applicability of a Cache Side-Channel Attack on ECDSA Signatures : The Flush+Reload attack on the point multiplication in ECDSA signature generation process." Thesis, Blekinge Tekniska Högskola, Institutionen för datalogi och datorsystemteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10820.
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Context. Digital counterparts of handwritten signatures are known as Digital Signatures. The Elliptic Curve Digital Signature Algorithm (ECDSA) is an Elliptic Curve Cryptography (ECC) primitive, which is used for generating and verifying digital signatures. The attacks that target an implementation of a cryptosystem are known as side-channel attacks. The Flush+Reload attack is a cache side-channel attack that relies on cache hits/misses to recover secret information from the target program execution. In elliptic curve cryptosystems, side-channel attacks are particularly targeted towards the point multiplication step. The Gallant-Lambert-Vanstone (GLV) method for point multiplication is a special method that speeds up the computation for elliptic curves with certain properties. Objectives. In this study, we investigate the applicability of the Flush+Reload attack on ECDSA signatures that employ the GLV method to protect point multiplication. Methods. We demonstrate the attack through an experiment using the curve secp256k1. We perform a pair of experiments to estimate both the applicability and the detection rate of the attack in capturing side-channel information. Results. Through our attack, we capture side-channel information about the decomposed GLV scalars. Conclusions. Based on an analysis of the results, we conclude that for certain implementation choices, the Flush+Reload attack is applicable on ECDSA signature generation process that employs the GLV method. The practitioner should be aware of the implementation choices which introduce vulnerabilities, and avoid the usage of such ECDSA implementations.
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Kučerka, Daniel. "Návrh animace digitálního spojovacího pole." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217315.
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This thesis describes types and parameters of memories used in communication engineering. The memory is a device which is able to record and to save information for the certain period of time. The memory is used in computers, measuring devices, consumer electronics etc. Main parameters of the memory are capacity, data stream speed, price of bit and time of memory cycle. The first part of this thesis deals with two types of memory – external and internal. External memories are removable media such as discs and magnetic tapes used for information saving and data backup for longtime period. Inner memories – in the form of semiconductive components – are mostly attached to the main panel. There are two types of inner memories – RAM (random access memory) and ROM (read only memory). The memories could be further divided according to their dependence on feeding used for memory saving. Types of memories used in switching exchanges are also mentioned in this part. The next part discusses the scheme of T switch for the first level of European PDH E1. The space switch and the time switch T belongs to switches used in digital switching exchange. In this part, the T switch, in particular the switch TR with controlled reading and the switch TW with controlled writing are described into details such as its parameters and methods of control. Furthermore, the calculation of call memory and control memory extant in E1 and E2 hierarchy are presented as well as the memory reading time and writing time of T switch in E1 and E2 hierarchy. The result of this thesis is a design of digital switching field animation that consists of four T switches. All operations, which are used in building linking of digital switching field, are shown in this animation.
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Queiroz, Alan Rômulo Silva. "Utilização de relés digitais para mitigação dos riscos envolvendo arco elétrico." Universidade de São Paulo, 2011. http://www.teses.usp.br/teses/disponiveis/3/3143/tde-30052012-124531/.
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O trabalho tem como objetivo avaliar e propor a utilização de soluções tecnológicas que permitam a redução dos riscos causados por arcos elétricos nas instalações de uma unidade industrial com sistema isolado de geração elétrica. Por ser extremamente danosa à segurança das pessoas que interagem com uma instalação elétrica e por causar danos significativos aos equipamentos e instalações, a energia incidente, proveniente de um arco elétrico, deve ser mensurada em conformidade com as normas existentes e os riscos devem ser controlados e mitigados, de maneira a não comprometer a integridade física das pessoas e das instalações. Dessa forma, o presente trabalho propõe alterações no sistema de proteção e a inserção de dispositivos dedicados à identificação de arcos elétricos no interior de painéis da unidade em questão, contribuindo significativamente para a redução da energia incidente liberada na ocorrência de um arco elétrico. Essa redução da energia incidente é conseguida devido à redução do tempo para eliminação da falta, necessitando, dessa forma, de dispositivos e relés de proteção voltados exclusivamente para a proteção contra arco elétrico.This dissertation aims to evaluate and propose the use of technological solutions that enable the reduction of risks caused by arc flash on the premises of an industrial unit with insulated system of electricity generation. It may be extremely damaging to the safety of people who interact with electrical installations and could cause significant damage to the equipment and facilities, the incident energy from an arc flash should be measured in accordance with existing standards, their risks must be controlled and attenuated, in order not to compromise the physical integrity of people and facilities. That way, this paper proposes changes into the system of protection and the insertion of devices dedicated to the identification of arc flashes inside panels of the unit concerned, contributing significantly to the reduction of incident energy released in the event of an arc flash. This reduction is obtained by lowering the time for the elimination of absence, requiring, therefore, devices and protective relays devoted exclusively to protect against electric arc.
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Preston, Douglas. "Last Two Surface Range Detector for Direct Detection Multisurface Flash Lidar in 90nm CMOS Technology." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright150392243439439.
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Bojan, Vujičić. "Detekcija nule A/D konvertorom niske rezolucije." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2017. https://www.cris.uns.ac.rs/record.jsf?recordId=104132&source=NDLTD&language=en.
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U tezi je rešavan centralni problem – detekcija nule dvobitnomstohastičkom digitalnom mernom metodom (SDMM). Formulisane sudve metode detekcije nule primenom dvobitne SDMM. Po prvoj metodidinamička rezerva je oko 100 dB a po drugoj ne manje od 160 dB. Obemetode su proverene teorijski, simulaciono i eksperimentalno. Poredrešenja centralnog problema, dato je i nekoliko rešenja problemakoji su sa njim vezani. Hipoteza ove teze – „dvobitna SDMM je u opsegu0 % - 10% FS bolja od standardne sempling metode (SSM)“ – je potpunopotvrđena u svim razmatranim slučajevima.The main goal of this thesis was null-detection using a two-bit stochasticdigital measurement method (SDMM). Two methods of null-detection, usingtwo-bit SDMM, were formulated. Using the first method around 100 dB ofdynamic reserve was achieved and using the second one no less than160 dB. Both methods were theoretically, using simulation and experimentallyconfirmed. In addition to the solution of the main problem, several otherrelated problems were also solved. The hypothesis of this thesis – “two-bitSDMM in range from 0 % - 10 % FS is better than the standard samplingmethod (SSM)” has been fully confirmed in all considered cases.
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Marjan, Urekar. "Prilog optimizaciji performansi digitalnih merenja." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2018. https://www.cris.uns.ac.rs/record.jsf?recordId=107133&source=NDLTD&language=en.
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U tezi se razmatra kriterijum optimalnosti stohastičkog fleš A/D konvertora (SFADC) koji predstavlja osnovu stohastičke digitalne metode merenja (SDMM). Razvijen je matematički i simulacioni model višebitnog SFADC i određen optimum broja bita rezolucije. Napravljen je hardverski prototip 4-bitnog stohastičkog mernog instrumenta (SMI), koji je ispitan brojnim eksperimentima i upoređen sa teorijski određenim vrednostima performansi merenja. Hipoteza ove teze – da postoji optimalni broj bita rezolucije SMI pri kome se ostvaruje maksimalna dobit u preciznosti merenja po ceni dupliranja potrebnog hardvera – potpuno je potvrđena.The thesis considers the criterion of optimality of the stochastic flash A/D converter (SFADC), which is the basis of the stochastic digital measurement method (SDMM). The mathematical and simulation model of the multibit SFADC was developed and the optimal number of bits of resolution was determined. A hardware prototype of a 4-bit stochastic measuring instrument (SMI) was made, tested in numerous experiments and compared with theoretically determined measurement performance values. The hypothesis of this thesis - that there is an optimal number of SMI resolution bits in which the maximum benefit of the measurement precision is achieved at the price of duplication of the required hardware - is fully confirmed
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Sibanda, Phathisile. "Connection management applications for high-speed audio networking." Thesis, Rhodes University, 2008. http://hdl.handle.net/10962/d1006532.
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Traditionally, connection management applications (referred to as patchbays) for high-speed audio networking, are predominantly developed using third-generation languages such as C, C# and C++. Due to the rapid increase in distributed audio/video network usage in the world today, connection management applications that control signal routing over these networks have also evolved in complexity to accommodate more functionality. As the result, high-speed audio networking application developers require a tool that will enable them to develop complex connection management applications easily and within the shortest possible time. In addition, this tool should provide them with the reliability and flexibility required to develop applications controlling signal routing in networks carrying real-time data. High-speed audio networks are used for various purposes that include audio/video production and broadcasting. This investigation evaluates the possibility of using Adobe Flash Professional 8, using ActionScript 2.0, for developing connection management applications. Three patchbays, namely the Broadcast patchbay, the Project studio patchbay, and the Hospitality/Convention Centre patchbay were developed and tested for connection management in three sound installation networks, namely the Broadcast network, the Project studio network, and the Hospitality/Convention Centre network. Findings indicate that complex connection management applications can effectively be implemented using the Adobe Flash IDE and ActionScript 2.0.
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Kobal, Damjan. "The use of technology to motivate, to present and to deepen the comprehension of math." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-80412.
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The aim of the workshop is to present and discuss several ideas which relate to technology as well as to creative teaching. Educational experience, common sense and educational research have all proven how important for comprehensive understanding different cognitive
representations are. We will present and discuss several elementary mathematical ideas of which mechanical realisations mean ingenius technological inventions (for example: ‘car differential’ and ‘digital sound technology’). Technological insights can provide deep intuitive understanding of otherwise abstract mathematical concepts and therefore yield also better comprehension of mathematics. Besides that we will use and present the technology in the form of dynamic geometry programs to show, provoke and motivate rethinking and
deeper understanding of several elementary mathematical concepts.
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Hedayati, Raheleh. "High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology." Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.
Full textAbstract:
Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (SOI). Owing to its superior material properties such as wide bandgap, three times larger than Silicon, and low intrinsic carrier concentration, SiC is an excellent candidate for high-temperature applications. In this thesis, analog and mixed-signal circuits have been implemented using SiC bipolar technology, including bandgap references, amplifiers, a master-slave comparator, an 8-bit R-2R ladder-based digital-to-analog converter (DAC), a 4-bit flash analog-to-digital converter (ADC), and a 10-bit successive-approximation-register (SAR) ADC. Spice models were developed at binned temperature points from room temperature to 500 °C, to simulate and predict the circuits’ behavior with temperature variation. The high-temperature performance of the fabricated chips has been investigated and verified over a wide temperature range from 25 °C to 500 °C. A stable gain of 39 dB was measured in the temperature range from 25 °C up to 500 °C for the inverting operational amplifier with ideal closed-loop gain of 40 dB. Although the circuit design in an immature SiC bipolar technology is challenging due to the low current gain of the transistors and lack of complete AC models, various circuit techniques have been applied to mitigate these problems. This thesis details the challenges faced and methods employed for device modeling, integrated circuit design, layout implementation and finally performance verification using on-wafer characterization of the fabricated SiC ICs over a wide temperature range.QC 20170905
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Hancock, Amber N. "A Radical Approach to Syntheses and Mechanisms." Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/77139.
Full textAbstract:
The critically important nature of radical and radical ion mechanisms in biology and chemistry continues to be recognized as our understanding of these unique transient species grows. The work presented herein demonstrates the versatility of kinetic studies for understanding the elementary chemical reactions of radicals and radical ions.
Chapter 2 discusses the use of direct ultrafast kinetics techniques for investigation of crucially important enzymatic systems; while Chapter 3 demonstrates the value of indirect competition kinetics techniques for development of synthetic methodologies for commercially valuable classes of compounds. The mechanism of decay for aminyl radical cations has received considerable attention because of their suspected role as intermediates in the oxidation of tertiary amines by monoamine oxygenases and the cytochrome P450 family of enzymes. Radical cations are believed to undergo deprotonation as a key step in catalysis. KIE studies performed by previous researchers indicate N,N-dimethylaniline radical cations deprotonate in the presence of the bases acetate and pyridine. By studying the electrochemical kinetics of the reaction of para substituted N,N-dimethylaniline radical cations with acetate anion, we have produced compelling evidence to the contrary. Rather than deprotonation, acetate reacts with N,N-dimethylaniline radical cation by electron transfer, generating the neutral amine and acetoxyl radical.
Transport properties of reactants and solvent polarity changes were investigated and confirmed not to influence the electrochemical behavior forming the basis for our mechanistic hypothesis. To reconcile our conclusion with earlier results, KIEs were reinvestigated electrochemically and by nanosecond laser flash photolysis. Rather than a primary isotope effect (associated with C-H bond cleavage), we believe the observed KIEs are secondary, and can be rationalized on the basis of a quantum effect due to hyperconjugative stabilization in aromatic radical cations during an electron transfer reaction. Product studies performed by constant potential coulometry indicate N,N-dimethylaniline radical cations are catalytic in carboxylate oxidations. Collectively, our results suggest that aminyl radical cation deprotonations may not be as facile as was previously thought, and that in some cases, may not occur at all.
Interest in design and synthesis of selenium containing heterocycles stems from their ability to function as antioxidants, anti-virals, anti-inflammatories, and immunomodulators. To establish synthetic feasibility of intramolecular homolytic substitution at selenium for preparation of selenocycles, we set out to determine what factors influence cyclization kinetics.
A series of photochemically labile Barton and Kim esters have been syntheisized and employed as radical precursors. The effect of leaving radical stability on kinetics has been investigated through determination of rate constants and activation parameters for intramolecular homolytic substitution of the corresponding radicals via competition experiments. Notable leaving group effects on measured kinetic parameters show more facile reactions for radical precursors with more stable leaving radicals. Moreover, cyclizations to form six-membered (as opposed to five- membered) ring systems exhibited order of magnitude decreases in rate constants for a given leaving radical. Our results are congruent with expectations for radical cyclizations trends for the varied experimental parameters and suggest homolytic substitution affords a convenient means for synthesis of selenocycles.Ph. D.
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Huang, Chun-Cheng, and 黃鈞正. "Digitally-Calibrated Comparator and Its Application in Flash Analog-to-Digital Converters." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/60362296932435912652.
Full textAbstract:
博士國立交通大學
電子研究所
98
This thesis presents a digital background calibration technique to trim the input-referred offsets of a comparator circuit. The calibration does not interrupt the normal operation of the comparator, hence is suitable for high speed and power efficient applications such as flash analog-to-digital converters(ADC). For a random-chopping comparator, the polarity of its offset is detected by observing the code density of its comparison results. A calibration loop is then used to adjust the comparator offset so that the offset is minimized. All procedures in the calibration loop are performed in digital domain. This arrangement ensures excellent reliability and high yields. The calibration performance is characterized by the converging speed of the calibration loop and the fluctuation noise imposed to the input signal. These two performance indexes of a background-calibrated comparator (BCC) are determined by three parameters: the probabilistic distribution of input signal, the quantized step size of offset adjustment, and the threshold of an internal bilateral peak detector. In flash ADCs, the offset fluctuation of a BCC can be drastically reduced by input windowing mechanism, which is accomplished by incorporating the thermometer-code edge detector(TCED) into the calibration loop. When introducing the TCED, uncorrelated random chopping for neighboring BCCs is used to avoid upward locking phenomenon which may lock calibration. A 2Gsample/s 6-bit ADC with the developed calibration technique is fabricated using 65 nm CMOS technology. A circuit architecture with no DC bias and small transistor sizes is selected for comparators used in the ADC. The comparator includes modifications for variable offset mechanism and high common-mode rejection capability. The parameters for the calibration loop are 1/4 LSB for the quantized offset adjustment step, and 16 for the bilateral peak detector threshold. The active area of the fabricated ADC is 0.21×0.66mm2. Drawing from 1.5V supply voltage, the ADC consumes 54mW. Before activating the calibration, the DNL is -1.0/+4.9 LSB and the INL is -4.3/+5.4 LSB. After activating the offset calibration, the DNL becomes -0.5/+0.6 LSB and the INL is reduced to -0.4/+0.7 LSB. The calibration improves the SNDR from 20.4dB to 31.0dB with an input frequency of 32MHz. When operating at 2GS/s, the effective resolution of bandwidth extends over the Nyquist frequency. The figure-of-merit of the ADC is 0.93pJ/conversion-step.
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Maleki, Mohammad. "Current-mode flash analog-to-digital converter." Thesis, 1992. http://hdl.handle.net/1957/37347.
Full textAbstract:
This thesis describes the development of a flash analog-to-digital converter based on
current-mode technique. The advantages of current -mode technique are higher speed,
smaller chip area, and simple division of reference current based on current mirror. A
current-mode comparator is designed consisting of a cascode current mirror and a
current sense amplifier used as a latch. The new method allows effective and simple
high-speed A/D conversion where the input is a current signal and the output of the
latch is a digital voltage signal. A four-bit flash analog-to-digital converter, using
current sense amplifier comparator is designed and simulated in 1-micron CMOS
technology. Simulation results show that for ADC with resolution below six-bit, this
technique offers a comparable accuracy with the existing voltage-mode methods at
much higher speed.Graduation date: 1993
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Lin, Kaih-Ping, and 林凱評. "High Speed Flash Analog to Digital Converter." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/12280330170131356783.
Full textAbstract:
碩士國立臺北科技大學
機電整合研究所
91
Applications of analog-to-digital converters (ADC) have become widespread as photoelectric devices, magnetic storages, and various sensors, such as light, color, temperature, and signal detectors. Furthermore, specifications of analog-to-digital converters are more stringent as a result of the growing needs for wireless network and communications, as well as photoelectric convergence and conversion knowledge. In this thesis, a flash ADC architecture is proposed to have 400 MHz samples rate with 6-bit resolution. We design the high speed architecture analog-to-digital converter by using two groups interleaved auto-zeroing technology for shortening the time period in charging to zero for each comparator. The auto-zeroing process of a comparator would keep normally its comparing operation. Also, we revise the circuit of the series resistors used for generating voltage references by adding a post amplifier to avoid effectively the distortion in voltage floating. Moreover, we instigate the democracy circuit to over on traditional bubble errors. Thus, we have not only lower the number of MOS units, but also increase the ration of bubble errors correction. We implemental the ADC in TSMC 0.25 µm 1P5M technology. The chip occupied 0.80*1.10 mm2 with both powers of 3.3V and 2.5V. Experimentally, the chip can work up to 400 MHz as the input sample of 100 MHz sin-wave and has the differential nonlinearity is DNL<0.4 LSB, the integral nonlinearity is INL<1.0 LSB ,and the efficient number of 5.03 bits in practical applications. Moreover, we use two groups interleaved auto-zeroing technology for reducing the comparators capacitor value, so we can minimize the chip size and power consumption(152mA).
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Sie, Ming-Jhou, and 謝明周. "4-Bit flash analog-to-digital converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60460902388790029068.
Full textAbstract:
碩士建國科技大學
電子工程系暨研究所
99
We use TSMC0.35μm2P 4M technology to design a positive feedback 3-bit 20MHz flash analog-to-digital converter and a 4-bit 1GHz flash analog-to-digital converter with hysteresis comparator. Reference potential was generated by resistor array, then compared with the input potential, and the resulting thermometer code pass through the pre-encoding circuit (1-out-of-N) and post-encoding circuit (Binary Code) after output. The 4-bit flash analog-to-digital-converter features working voltage range from 0.9 to 2.2 V, sampling rate of 1GHz, the power consumption is 5.158 mW and the chip layout area is 1.445×1.393mm . For 3-bit flash analog-to-digital converter, the working voltage ranges from 0 to 3.3 V, sampling rate of 20MHz, the power consumption is 2.2228mW and the chip layout area is 1.181 × 1.326 mm .
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Lin, Kai-Chie, and 林凱琪. "High Speed Flash Analog to Digital Converter." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/56085018306124426889.
Full textAbstract:
碩士國立臺北科技大學
電腦通訊與控制研究所
90
Applications of analog-to-digital converters (ADC) have become widespread as photoelectric devices, magnetic storages, and various sensors, such as light, colour, temperature, and signal detectors. Furthermore, specifications of analog-to-digital converters are more stringent as a result of the growing needs for wireless network and communications, as well as photoelectric convergence and conversion knowledge. The designs of analog to digital converter are innovative and versatile to have higher speed, more accuracy and stability, along with low operating potential and low power consumption. Various types of circuits such as flash、folding、feedback、parallel and pipe-line, are constructed according to match their specific characteristics. In this thesis, a flash ADC architecture is proposed to have 400 Mega-sample per second with 6-bit sample length. We design the architecture by using group interleaved auto-zeroing technology for shortening the time period in charging to zero for each comparator. The auto-zeroing process of a comparator would keep normally affect its comparing operation. Also, we revise the circuit of the series resistors used for generating voltage references by adding a post amplifier to avoid effectively the distortion in voltage floating. Moreover, we instigate the democracy circuit to over on traditional bubble errors. Thus, we have not only lower the number of MOS units, but also increase the ration of bubble errors correction. We implemental the ADC in TSMC 0.25 µm 1P5M technology. The chip occupied 0.60*0.66 mm2 with both powers of 3V and 2.5V, 8461 MOS units, 449 resistors, and 147 capacitors. Experimentally, the chip can work up to 400 MHz as the input sample of 10 MHz sin-wave and has the efficient number of 5.76 bits in practical applications.
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Chang, Hsuan-Yu, and 張軒瑜. "Design of Low-Power Flash Analog-to-Digital Converters Using Digital Calibration." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/47809309624999322555.
Full textAbstract:
博士國立中興大學
電機工程學系所
104
Flash-type ADCs have the inherent advantage on high-speed sampling rates. Although the flash ADC is superiority in sampling rate but its large power consumption makes itself bottleneck in many applications. Speed, power and accuracy are tradeoff in high-speed CMOS ADC design. Process technology scaling trends toward smaller transistor dimensions and low supply voltage, and thereby it leads to greatly reduce power consumption in flash ADCs. The never-ending story of CMOS technology trending toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Transistor size scaling results in significant offset voltage and supply voltage scaling makes it more difficult in higher accuracy design. In order to improving above design issues, many techniques have been proposed, such as resistor-averaging networks and digital calibrated techniques. Especially, the digital calibrated techniques are main solutions recently. In this thesis, the new idea of digital calibrated technique is proposed to realize high-speed ADCs. First chip, using tree-type metal layout and digital calibration, a 6-bit 2-GS/s flash ADC without track-and-hold is presented. Since large offset voltages caused by using small device sizes in front-end of high-speed ADCs usually result in nonlinearity in output, a digitally calibrated method is applied to improve the performance of the proposed ADC. In addition, no track-and-hold circuit used will cause dynamic error but tree-type metal layout will avoid it. Measurement results show the ADC achieves a SNDR of 35.6 dB for a low frequency input at 2 GS/s sampling frequency, and 32.7 dB for an ERBW input frequency. The power consumption is 28 mW at 2 GS/s from a 1.2-V supply. The core area is 0.56mm × 0.62mm and the figure of merit is 0.54pJ/conv. Second chip, a 6-bit flash ADC using reference-voltage- interpolated calibration to improve linearity and reduce power dissipation is presented. In the ADC, the digital calibration logic employs successive approximation algorithm and minimized residue algorithm to determine precise calibration levels. Implemented by 90-nm CMOS process, the proposed ADC can achieve a signal-to-noise-and-distortion ratio of 36 dB for a low input frequency and 33.5 dB for a Nyquist-rate input frequency at 2-GS/s sampling rate. The peaks of integral and differential nonlinearities after calibration are 0.36 LSB and 0.42 LSB, respectively. The power consumption is 25 mW at 2-GS/s from a 1.2-V supply. The core area is 0.32 mm × 0.62 mm, and the figure of merit is 0.34 pJ/conversion step. Finally, we compare the two chips design considerations and improvements. The first chip is suitable only in single ADC system application due to no track-and-hold circuit. The second chip is suitable in multi-sub ADCs system application, such as time-interleaved ultra-high speed ADCs. The second chip consumes less power comparing to the first chip due to wider calibration range. Transistor size of the comparator in flash ADC can be designed smaller due to wide calibration range, and it consumes less dynamic power. Performance summary and comparison table will be shown finally.
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Hsu, Ying-Yu, and 徐瑛佑. "Ultra High-Speed Flash Analog-to-Digital Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/9wam6k.
Full textAbstract:
碩士國立交通大學
電機與控制工程系所
93
Due to the advance process technologies, the operating frequency and circuit complexity of integrated circuit increase. The interfaces between the analog and the digital parts are required to operate at ultra high speed (over giga samples per second). The high-bit-rate applications include DVD read channel, multi level receiver, channel equalizer, jitter measurement system, and Ethernet need Analog-to-Digital Converters. There are two major topics in this thesis. First, we focus on the high speed ADC circuit design. Thus, we propose a 4-bit flash ADC typically operates at 3.125GSps and maximally at 4GSps. This 4-bit ADC achieves better than 3.1 effective bits for input frequencies up to 1.55GHz at 3.125GSps, and 2.3 effective bits for 2GHz input at 4GSps. The peak DNL and INL are less than 0.45 LSB and 0.6 LSB, respectively. This ADC consumes 180mW from 1.8V power supply at 4GSps. The chip occupies 0.36- active area, implemented in TSMC 0.18-um 1P6M CMOS. Second, based on the circuits presented in the 4-bit flash ADC, and we propose two methods to improve the 4-bit accuracy to 5-bit accuracy. The methods are active averaging and active interpolation techniques. Using averaging technique can improve accuracy white using interpolation technique can reduce power consumption. The 5-bit flash ADC with averaging technique achieves better than 3.8 effective bits for input frequencies up to 1.55GHz at 3.125GSps, and 3 effective bits for 2GHz input at 4GSps. The peak DNL and INL are less than 0.35 LSB and 0.8 LSB, respectively. This ADC consumes 270mW from 1.8V power supply at 4GSps. The 5-bit flash ADC with interpolation technique achieves better than 3.6 effective bits for input frequencies up to 1.55GHz at 3.125GSps, and 2.9 effective bits for 2GHz input at 4GSps. The peak DNL and INL are less than 0.5 LSB and 0.9 LSB, respectively. This ADC consumes 243mW from 1.8V power supply at 4GSps.
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白薇詩. "Pipelined Encoding for a Flash Analog-to-Digital Converter." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/40064734984142616238.
Full textAbstract:
碩士國立彰化師範大學
電機工程學系
96
In this research, fundamentals of power line signal sampling, quantization, and design of a pipelined encoder for flash analog to digital converter (Flash ADC) are presented. The current mode logic (CML) is applied because of lower voltage supply and faster processing time are considered. The second stage of this research is the analytical individual case of the electric power quality signal .The power quality has become an increasingly important topic due to rapid development of high-technology and precision instrument industries. Therefore, the quality of stable power supply is one of the main issues. The front-end device of power quality monitoring is an analog-to-digital converter, since the later processing of the power line signal is a key factor to the monitor or controller module.
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Lien, Yu-Chang, and 連昱彰. "Low-Power High-Speed Flash Analog-to-Digital Converters." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/01613899949492304196.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
96
The performance and power consumption of analog-to-digital converters (ADCs) affect the efficiency of the ultra wideband (UWB) systems. In this thesis, we focus on the design techniques development of high speed ADCs, and propose a 6-bit high speed ADC design for the applications of UWB systems. In this design, a design methodology for pre-amplifier is used to achieve the maximum bandwidth while consuming the fixed power. Also, the non-ideality of comparators can be suppressed by improving the comparator’s timing. This proposed design adopts the offset cancellation, capacitive interpolation and distributed sample-and-hold techniques to solve the problems in designing flash ADCs. This proposed ADC is designed in TSMC 0.13�慆 process, and the experimental results show that the effective number of bit (ENOB) is 5.3 in the sampling frequency of 700MHz. The power consumption is 112mW, and the resolution bandwidth (ERBW) is 500MHz. Due to the high input bandwidth and low power consumption, this ADC is very suitable to UWB systems.
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WANG, GUO-LONG, and 王國隆. "A new current-mode flash analog-to-digital converter." Thesis, 1991. http://ndltd.ncl.edu.tw/handle/27257510409184859270.
Full text
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Sajjadian, Farnad. "A 10MHz flash analog-to-digital converter system for digital oscilloscope and signal processing applications." 1985. http://hdl.handle.net/2097/27577.
Full text