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Journal articles on the topic 'Digital filter synthesis'

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Published: 30 May 2022

Last updated: 31 May 2022

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1

Petrosian, Ruslan, Vladyslav Chukhov, and Arsen Petrosian. "Development of a method for synthesis the FIR filters with a cascade structure based on genetic algorithm." Technology audit and production reserves 4, no. 2(60) (July 31, 2021): 6–11. http://dx.doi.org/10.15587/2706-5448.2021.237271.

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The object of research is the process of digital signal processing. The subject of research is methods of synthesis of digital filters with a finite impulse response based on a genetic algorithm. Digital filtering is one of the tasks of digital signal processing. FIR filters are always stable and provide a constant group delay. There are various methods for synthesizing digital filters, but they are all aimed at synthesizing filters with a direct structure. One of the most problematic areas of a digital filter with a direct structure in digital processing is the high sensitivity of the filter characteristics to inaccuracies in setting the filter coefficients. Genetic algorithm-based filter synthesis methods use an ideal filter as the approximated filter. This approach has a number of disadvantages: it complicates the search for an optimal solution; computation time increases. The study used random search method, which is the basis of genetic algorithm (used for solving optimization problems); theory of digital filtering in filter analysis; numerical methods for modeling in a Python program. Prepared synthesis method FIR filter with the cascade structure, which is less sensitive to the effect of finite bit width. Computation time was reduced. This is due to the fact that the proposed method searches for the most suitable filter coefficients based on a genetic algorithm and has a number of features, in particular, it is proposed to use a piecewise-linear function as an approximated amplitude-frequency response. This makes it possible to reduce the number of populations of the genetic algorithm when searching for a solution. The synthesis of an FIR filter with a cascade structure based on a genetic algorithm showed that for a 24-order filter it took about 30–40 generations to get the filter parameters close to the optimal values. In comparison with classical methods of filter synthesis, the following advantages are provided: calculations of the coefficients of a filter with a cascade structure directly, the possibility of optimizing coefficients with limited bit depth.

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2

Chen, Liang‐Gee, and Chun‐Tang Chao. "Intelligent digital filter synthesis system." Journal of the Chinese Institute of Engineers 16, no. 1 (January 1993): 117–33. http://dx.doi.org/10.1080/02533839.1993.9677483.

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3

Solovev, Denis B. "Selection of Digital Filter for Microprocessor Protection Relays." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 3 (June 1, 2018): 1498. http://dx.doi.org/10.11591/ijece.v8i3.pp1498-1512.

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The article considers some issues related to replacement of electromechanical relays used for protection of power facilities with microprocessor relays. One of the urgent problems connected with implementation of microprocessor overcurrent protections is how to use current transducers other than usual current transformers and in particular Rogowski coils that become more and more widespread. In the article are compared twelve methods of synthesis of a digital filter basing on the analog prototype – second-order integrating filter. The bilinear filter and Boxer-Thaler filters are analyzed in respect to their use in microprocessor relays. Basing on the research results a technique for selection of parameters of digital integrating filters for microprocessor relays is proposed. Simulation results show that Boxer-Thaler and bilinear filters have better accuracy during transient current measurements than the analog filter. The study allows concluding that in many cases the digital second-order bilinear filter is the best choice for use in microprocessor relays.

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4

Xiangyang, Wen, and Wei Yixiang. "Constrained digital matched filter method for optimum filter synthesis." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 560, no. 2 (May 2006): 346–51. http://dx.doi.org/10.1016/j.nima.2005.12.199.

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5

Stamenkovic, Negovan. "Digital FIR filter architecture based on the residue number system." Facta universitatis - series: Electronics and Energetics 22, no. 1 (2009): 125–40. http://dx.doi.org/10.2298/fuee0901125s.

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In this paper, architecture of residue number system used in FIR filters, is presented. For many years residue number coding has been recognized as a system which provides capability for implementation of a high speed addition and multiplication. These advantages of residue number system coding for the high speed FIR filters design results from the fact that an digital FIR filter requires only addition and multiplication. The proposed FIR filter architecture is performed as series of modulo multiplication and accumulation across each modulo. A numerical example illustrates the principles of FIR filtering of an 32 order low pass filter. This architecture is compared with FIR filters direct synthesis. .

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6

Zhu, Wei Hua, Ying Shen, and Guo Bing Huang. "Digital Frequency Synthesis Using DDS-Based Approach." Advanced Materials Research 630 (December 2012): 226–30. http://dx.doi.org/10.4028/www.scientific.net/amr.630.226.

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This paper deals with some issues during the synthesis of DF signals such as change of phase and sine amplitude, smooth output and wave filter which features dynamics and variability. Utilizing AD9833 chip, this paper design the circuit that is used for synthesizing DF signals, including external circuit, wave filter circuit and amplify circuit. Given the characteristics of this chip, this paper provides the procedure design methodology that includes AD9833 initiative, write control and synthesis frequency. The testing experiments indicate the accurateness and reliability of this design.

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7

Chu, Rui Hong, and Graham Town. "Birefringent filter synthesis by use of a digital filter design algorithm." Applied Optics 41, no. 17 (June 10, 2002): 3412. http://dx.doi.org/10.1364/ao.41.003412.

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8

Kadhim, Ola N., Kifah T. Khudhair, Fallah H. Najjar, and Hassan M. Al-Jawahry. "Digital filters windowing for data transmission enhancement in communication channel." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 3 (December 1, 2021): 1454. http://dx.doi.org/10.11591/ijeecs.v24.i3.pp1454-1468.

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In this search, an important methodology has been presented for communicated information rectification utilizing advanced channel windowing approach. The modern data communication technologies are ensured with numerous challenges because of their unpredictability and arrangement. Various digital transmission topologies in 4G can't fulfill the requirements in future arrangements, therefore, alternative multicarrier modulation (MCM) becoming the nominated approaches among all other data transmission techniques. Wherein prototype filter configuration is a fundamental system based on which the synthesis and analysis filters are derived. This paper presents a complete review on the ongoing advances of finite impulse response (FIR) filter plan procedures in MCM based correspondence frameworks. Initially, the essential issues are tried, taking into consideration the presentation of available data signal applicants and the FIR filter design concept. At that point the techniques for FIR filter configuration are summed up in subtleties and are center around the accompanying three group’s recurrence testing strategies, windowing based strategies and advancement-based techniques. At last, the exhibitions of different FIR structure strategies are assessed and measured by power spectral density (PSD) and bit error rate (BER), and variable MCM plots as well as their potential prototype filters are examined.

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9

Cherniakov, M., V. I. Sizov, and L. Donskoi. "Synthesis of a periodically time-varying digital filter." IEE Proceedings - Vision, Image, and Signal Processing 147, no. 5 (2000): 393. http://dx.doi.org/10.1049/ip-vis:20000425.

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10

Ciccarella, G., and P. Marietti. "Time domain approach to recursive digital filter synthesis." Signal Processing 12, no. 4 (June 1987): 385–93. http://dx.doi.org/10.1016/0165-1684(87)90141-1.

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11

Samad, S. A. "DIRECT SYNTHESIS OF LADDER WAVE DIGITAL FILTERS WITH TUNABLE PARAMETERS." ASEAN Journal on Science and Technology for Development 20, no. 1 (December 21, 2017): 1–18. http://dx.doi.org/10.29037/ajstd.364.

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This paper proposes a method for the synthesis of ladder wave digital filters (WDFs) directly from the digital domain. This method avoids the need for the synthesis of analog reference filters conventionally required in WDF design. This direct method allows for the determination of the WDF coefficients from the digital domain transfer function. This is similar to conventional infinite impulse response (IIR) filter coefficient determination but the WDF will give a more efficient realization. Due to the WDFs power complementary properties, a first-order ladder WDF can simultaneously realize both lowpass and highpass responses using the same structure, while a second-order WDF can realize both the bandpass and bandstop responses simultaneously. By appropriately choosing the WDF adaptor configuration and structure, tunable parameters can be determined from the digital domain transfer function that controls the 3dB cut-off frequency of the lowpass and highpass filters, and the centre frequency and 3-dB bandwidth of the bandpass and bandstop filters. This results in the WDFs requiring a minimum number of multipliers for realization.

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12

Siwczyński, M., A. Drwal, and S. Żaba. "The digital function filters – algorithms and applications." Bulletin of the Polish Academy of Sciences: Technical Sciences 61, no. 2 (June 1, 2013): 371–77. http://dx.doi.org/10.2478/bpasts-2013-0036.

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Abstract The simple digital filters are not sufficient for digital modeling of systems with distributed parameters. It is necessary to apply more complex digital filters. In this work, a set of filters, called the digital function filters, is proposed. It consists of digital filters, which are obtained from causal and stable filters through some function transformation. In this paper, for several basic functions: exponential, logarithm, square root and the real power of input filter, the recursive algorithms of the digital function filters have been determined The digital function filters of exponential type can be obtained from direct recursive formulas. Whereas, the other function filters, such as the logarithm, the square root and the real power, require using the implicit recursive formulas. Some applications of the digital function filters for the analysis and synthesis of systems with lumped and distributed parameters (a long line, phase shifters, infinite ladder circuits) are given as well.

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13

Memon, Tayab, Paul Beckett, and Amin Z. Sadik. "Sigma-Delta Modulation Based Digital Filter Design Techniques in FPGA." ISRN Electronics 2012 (November 14, 2012): 1–10. http://dx.doi.org/10.5402/2012/538597.

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In this paper efficient digital filter design techniques categorized as sigma-delta modulation based short word length (SWL) and multibit (or contemporary) techniques are reviewed in terms of hardware complexity, area, performance and power tradeoffs, synthesis issues, and algorithm versatility. More recent, general purpose DSP applications including classical LMS algorithms reported using sigma-delta modulation encoding are reviewed thoroughly. A small number of basic arithmetic circuits designed using sigma-delta modulation encoding and synthesized by using FPGAs are also described. Finally, recent FPGA based area-performance-power analysis of single-bit ternary FIR filtering is discussed and compared to its corresponding multi-bit system. This work shows that in most cases single-bit ternary FIR-like filters are able to outperform their equivalent multi-bit filters in terms of area, power, and performance.

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14

Cadzow, J. A., and T. C. Chen. "Algebraic approach to two-dimensional recursive digital filter synthesis." IEEE Transactions on Acoustics, Speech, and Signal Processing 37, no. 5 (May 1989): 655–64. http://dx.doi.org/10.1109/29.17558.

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15

Brantingham, George L., and Richard H. Wiggins. "System using digital filter for waveform or speech synthesis." Journal of the Acoustical Society of America 81, no. 6 (June 1987): 2005. http://dx.doi.org/10.1121/1.394698.

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16

Venkateswarlu, T. "Direct canonic synthesis of all-pass digital filter structures." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 46, no. 12 (1999): 1495–97. http://dx.doi.org/10.1109/81.809553.

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17

Uesaka, K., and M. Kawamata. "Evolutionary synthesis of digital filter structures using genetic programming." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 50, no. 12 (December 2003): 977–83. http://dx.doi.org/10.1109/tcsii.2003.820240.

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18

Vetterli, Martin. "Analysis, synthesis and computational complexity of digital filter banks." Signal Processing 11, no. 3 (October 1986): 312. http://dx.doi.org/10.1016/0165-1684(86)90012-5.

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19

Yagain, Deepa, and A. Vijaya Krishna. "Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool." VLSI Design 2014 (July 24, 2014): 1–18. http://dx.doi.org/10.1155/2014/280701.

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Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power.

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20

Satyanarayana, J. H., and B. Nowrouzian. "A New Technique for the High-Level Synthesis of Digit-Serial Digital Filters Based on Genetic Algorithms." Journal of Circuits, Systems and Computers 07, no. 06 (December 1997): 517–35. http://dx.doi.org/10.1142/s0218126697000395.

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This paper is concerned with the exploitation of genetic algorithms and their application to the development of a new optimization technique for the high-level synthesis of digit-serial digital filter data-paths. In the resulting optimization technique, the cost associated with the final digital filter data-path is minimized subject to user-specified constraints on the number of physical arithmetic functional units employed. The proposed technique is capable of obtaining global area-optimal, time-optimal, or combined area-cum-time-optimal data-paths, where the optimality takes into account not only the cost associated with the required arithmetic functional units but also that associated with the required support cells (multiplexors and registers). This optimization is made computationally effective by encoding the digital filter data flow-graph into chromosomes which preserve the data-dependency relationships in the original digital filter signal flow-graph under the operations of crossover and mutation by the underlying genetic algorithm. The usefulness of the proposed technique is demonstrated by applying to the constrained optimization of a benchmark elliptic wave digital filter for full bit-serial, full bit-parallel, as well as general digit-serial high-level synthesis. The results thus obtained are compared to those of the existing techniques (whenever appropriate) to confirm the validity of the technique.

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21

Lowenborg, P., H. Johansson, and L. Wanhammar. "Two-channel digital and hybrid analog/digital multirate filter banks with very low-complexity analysis or synthesis filters." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 50, no. 7 (July 2003): 355–67. http://dx.doi.org/10.1109/tcsii.2003.813589.

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22

Watanabe, Eiji, Kenji Minagawa, and Akinori Nishihara. "A synthesis of low-sensitivity digital filters using T-cascade connections. Extraction of wave digital lattice filter sections." Electronics and Communications in Japan (Part III: Fundamental Electronic Science) 73, no. 5 (1990): 87–95. http://dx.doi.org/10.1002/ecjc.4430730509.

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23

Soibam*, Daimond Singh, and Manoj Kumar. "Design and Implementation of Third Order Low Pass Digital FIR Filter using Pipelining Retiming Technique." International Journal of Engineering and Advanced Technology 10, no. 4 (April 30, 2021): 178–84. http://dx.doi.org/10.35940/ijeat.d2446.0410421.

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: This paper presents design and implementation of 3rd order low pass digital FIR filter using pipelining retiming technique. Aim of this paper is to apply pipelining retiming technique on low pass digital FIR filter and compare with the existing second order retimed FIR filter and third order broadcast, non-broadcast low pass FIR filter. MATLAB FDA tool is used to calculate digital FIR filter coefficients. Hamming and Kaiser window methods are used to find out the coefficients of the FIR filter. Broadcast and non broadcast third order low pass FIR filter architectures are used for pipelining retiming .Cutset and feed forward pipelining retiming techniques are used to retime the third order low pass digital FIR filter. We design our algorithm in VHDL and implemented on Xilinx Vivado xc7a35tcpg261-1. Area (LUT), speed and power are calculated using Xilinx Vivado 2015.2 tool. Synthesis and simulation results are discussed in this paper. Speed and area (LUT) of proposed third order low pass FIR filter is improved in comparison with existing designs.

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24

Sinha, Pankaj Kumar, and Preetha Sharan. "Multiplexer Based Multiplications for Signal Processing Applications." Indonesian Journal of Electrical Engineering and Computer Science 9, no. 3 (March 1, 2018): 583. http://dx.doi.org/10.11591/ijeecs.v9.i3.pp583-586.

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<p>In signal processing, Filter is a device that removes the unwanted signals. In any electronic circuits, Filters are widely used in the fundamental hands on tool. The basic function of the filter is to selectively allow the desired signal to pass through and /or control the undesired signal based on the frequency. A signal processing filter satisfies a set of requirements which are realization and improvement of the filter. A filter system consists of an analog to digital converter is used to sample the input signal, traced by a microprocessor and some components such as memory to store the data and filter coefficients. Filters can easily be designed to be “linear phase” and it is easy to implement. In this paper, the birecoder multiplier (BM) is designed in terms of VLSI design environment. The proposed multiplier is implemented by using VHDL language and Xilinx ISE for synthesis. The multiplier is mainly used for image processing applications as well as signal processing applications.</p>

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25

Pelletier, Marcus, and Marcos Underwood. "Multichannel Simultaneous Digital Tracking Filters for Swept-Sine Vibration Control." Journal of the IEST 37, no. 5 (September 1, 1994): 23–29. http://dx.doi.org/10.17764/jiet.2.37.5.a5l5530p41v62271.

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The digital control of swept sine-wave tests and the associated theory needed for swept sine-wave synthesis and analysis will be discussed. This type of testing requires that the digital vibration control system drive the actuator subsystem with an analog signal. This signal is a low-distortion sine wave with a smoothly varying frequency and amplitude. The testing also requires that the controller be able to measure the response of this type of excitation by way of a control transducer mounted at some chosen point on the device under test. This paper will concentrate on the details of output signal generation to enhance its accuracy and suitability for complex heterodyne generation. The complex heterodyne is used in conjunction with 0-Hz intermediate frequency detectors to implement a digital tracking filter. Digital low-pass filters are used to implement 0-Hz intermediate frequency detectors. The tracking filter is used for time-variable spectral analysis6 (i.e., determining the instantaneous complex amplitude of a sweeping sine wave as encounted in swept sine testing).

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26

Zhao, S. H., and S. C. Chan. "Design and Multiplierless Realization of Digital Synthesis Filters for Hybrid-Filter-Bank A/D Converters." IEEE Transactions on Circuits and Systems I: Regular Papers 56, no. 10 (October 2009): 2221–33. http://dx.doi.org/10.1109/tcsi.2008.2012213.

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27

Pilipović, Ratko, Vladimir Risojević, and Patricio Bulić. "On the Design of an Energy Efficient Digital IIR A-Weighting Filter Using Approximate Multiplication." Sensors 21, no. 3 (January 22, 2021): 732. http://dx.doi.org/10.3390/s21030732.

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This paper presents a new A-weighting filter’s design and explores the potential of using approximate multiplication for low-power digital A-weighting filter implementation. It presents a thorough analysis of the effects of approximate multiplication, coefficient quantization, the order of first-order sections in the filter’s cascade, and zero-pole pairings on the frequency response of the digital A-weighting filter. The proposed A-weighting filter was implemented as a sixth-order IIR filter using approximate odd radix-4 multipliers. The proposed filter was synthesized (Verilog to GDS) using the Nangate45 cell library, and MATLAB simulations were performed to verify the designed filter’s magnitude response and performance. Synthesis results indicate that the proposed design achieves nearly 70% reduction in energy (power-delay product) with a negligible deviation of the frequency response from the floating-point implementation. Experiments on acoustic noise suggest that the proposed digital A-weighting filter can be deployed in environmental noise measurement applications without any notable performance degradation.

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28

Jameil, Ahmed K., Yassir A. Ahmed, and Saad Albawi. "Efficient FIR Filter Architecture using FPGA." Recent Advances in Computer Science and Communications 13, no. 1 (March 13, 2020): 91–98. http://dx.doi.org/10.2174/2213275912666190603115506.

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Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

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29

Bank, B., and V. Valimaki. "Robust loss filter design for digital waveguide synthesis of string tones." IEEE Signal Processing Letters 10, no. 1 (January 2003): 18–20. http://dx.doi.org/10.1109/lsp.2002.806707.

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30

Getmanov, Victor, Vladislav Chinkin, Roman Sidorov, Alexei Gvishiani, Mikhail Dobrovolsky, Anatoly Soloviev, Anna Dmitrieva, Anna Kovylyaeva, Nataliya Osetrova, and Igor Yashin. "Low-Pass Filtering Method for Poisson Data Time Series." Applied Sciences 11, no. 10 (May 15, 2021): 4524. http://dx.doi.org/10.3390/app11104524.

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Problems of digital processing of Poisson-distributed data time series from various counters of radiation particles, photons, slow neutrons etc. are relevant for experimental physics and measuring technology. A low-pass filtering method for normalized Poisson-distributed data time series is proposed. A digital quasi-Gaussian filter is designed, with a finite impulse response and non-negative weights. The quasi-Gaussian filter synthesis is implemented using the technology of stochastic global minimization and modification of the annealing simulation algorithm. The results of testing the filtering method and the quasi-Gaussian filter on model and experimental normalized Poisson data from the URAGAN muon hodoscope, that have confirmed their effectiveness, are presented.

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31

Hadi Mohammad, Alaa, Azura Che Soh, Noor Faezah Ismail, Ribhan Zafira Abdul Rahman, and Mohd Amran Mohd Radzi. "Improvement of LMS adaptive noise canceller using uniform Poly-phase digital filter bank." Indonesian Journal of Electrical Engineering and Computer Science 17, no. 3 (March 1, 2020): 1258. http://dx.doi.org/10.11591/ijeecs.v17.i3.pp1258-1265.

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<span>This paper presents the Least Mean Square (LMS) noise canceller using uniform poly-phase digital filter bank to improve the noise can-cellation process. Analysis filter bank is used to decompose the full-band distorted input signal into sub-band signals. Decomposition the full-band input distorted signal into sub-band signals based on the fact that the signal to noise ratio (S/N) is inversely proportional to the signal bandwidth. Each sub-band signal is fed to individual LMS algorithm to produce the optimal sub-band output. Synthesis filter bank is used to compose the optimal sub-band outputs to produce the final optimal full-band output. In this paper, m-band uniform Discrete Fourier Transform (DFT) digital filter bank has been used because its computational complexity is much smaller than the direct implementation of digital filter bank. The simulation results show that the proposed method provides the efficient performance with less and smooth error signal as compared to conventional LMS noise canceller.</span>

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Yeromina, Nataliia, Serhii Petrov, Maksym Volk, Olena Daki, Volodymyr Cherednyk, Iryna Zinchenko, Ihor Chernykh, Oleksiy Alekseienko, Serhii Mykus, and Volodymyr Furdyk. "Synthesis of an optimal digital filter of a compensation radiometer for radiometric correlation-extreme navigation systems of unmanned aerial vehicles." Eastern-European Journal of Enterprise Technologies 2, no. 9 (110) (April 30, 2021): 79–86. http://dx.doi.org/10.15587/1729-4061.2021.230176.

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The expediency of using a compensation radiometer (CR) with periodic absolute calibration as a sensor for preprocessing the information of correlation-extreme navigation systems (CENS) of unmanned aerial vehicles (UAV) was shown. This is determined by the possibility of obtaining and using the estimates of gain fluctuations obtained in previous frames which will provide an increase in the radiometer sensitivity. In addition, due to the accumulation of information, an increase in accuracy of measurement of the elements of the current image formed by the CENS will be provided. The algorithm of processing the obtained calibration estimates during linear processing corresponds to a certain digital filter (DF). By defining a set of the DF weight coefficients, it is possible to improve the CR fluctuation sensitivity by reducing the gain fluctuations. Up to 1.8-time gain in sensitivity can be reached for typical frequency and time parameters of the compensation radiometer of UAV CENS. The problem of synthesis of a digital filter was set. A solution to the problem of synthesizing an optimal digital filter was proposed. Its use in a CR will improve the fluctuation sensitivity. In its turn, this will make it possible to improve the quality of a current image generated by the system when siting by means of sighting surfaces with low-contrast objects taking into account fluctuations in radio-brightness temperature. It was found that the gain in sensitivity when using the optimal digital filter increases with an increase in the operating period of the radiometer and an increase in the digital filter order. Improvement of fluctuation sensitivity of the CENS data preprocessing system is important for UAV location in low-contrast areas

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33

Sanko, N. S., and M. I. Vashkevich. "Research of application of DFT-modulated filter bank in systems with significant spectral component amplification." Doklady BGUIR 19, no. 6 (October 1, 2021): 14–22. http://dx.doi.org/10.35596/1729-7648-2021-19-6-14-22.

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The purpose of this article is to investigate the application of DFT-modulated filter bank in systems with significant spectral component amplification like hearing aid. There is a description of analysis / synthesis method based on short-time Fourier transform (STFT), which is used in most systems of speech information processing. It is shown that DFT-modulated filter bank is a generalization of STFT-method. In analysis / synthesis system based on DFT-modulated filter bank, the input signal is divided into subbands, passing through the analysis filter bank then each subband is amplified and the last step is to reconstruct the signal with synthesis filter bank. However, in digital systems with significant spectral component amplification, the resulting signal is distorted after reconstruction because of amplification factor difference in each subband. The article provides expressions for the distortion and the aliasing functions, allowing to estimate the distortion value, which appears in analysis / synthesis system of DFT-modulated filter bank. Efficient algorithms for calculating the distortion and the aliasing functions are also offered. In future it is planning to develop a procedure for optimizing the DFT-modulated filter bank based on the proposed efficient algorithms for calculating distortion and spectral aliasing in the filter bank.

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34

Gatti, E., A. Geraci, S. Riboldi, and G. Ripamonti. "Digital Penalized LMS method for filter synthesis with arbitrary constraints and noise." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 523, no. 1-2 (May 2004): 167–85. http://dx.doi.org/10.1016/j.nima.2003.12.032.

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35

Chen, Xiaofei, Fredric J. Harris, Elettra Venosa, and Bhaskar D. Rao. "Non-Maximally Decimated Analysis/Synthesis Filter Banks: Applications in Wideband Digital Filtering." IEEE Transactions on Signal Processing 62, no. 4 (February 2014): 852–67. http://dx.doi.org/10.1109/tsp.2013.2295549.

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36

SARAMÄKI, TAPIO, JUHA YLI-KAAKINEN, and HÅKAN JOHANSSON. "OPTIMIZATION OF FREQUENCY-RESPONSE MASKING BASED FIR FILTERS." Journal of Circuits, Systems and Computers 12, no. 05 (October 2003): 563–91. http://dx.doi.org/10.1142/s0218126603001070.

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A very efficient technique to drastically reduce the number of multipliers and adders in implementing linear-phase finite-impulse response (FIR) digital filters in applications demanding a narrow transition band is to use the frequency-response masking (FRM) approach originally introduced by Lim. The arithmetic complexity can be even further reduced using a common filter part for constructing the masking filters originally proposed by Lim and Lian. A drawback in the above-mentioned original FRM synthesis techniques is that the subfilters in the overall implementations are separately designed. In order to further reduce the arithmetic complexity in these two FRM approaches, the following two-step optimization technique is proposed for simultaneously optimizing the subfilters. At the first step, a good suboptimal solution is found by using a simple iterative algorithm. At the second step, this solution is then used as a start-up solution for further optimization being carried out by using an efficient unconstrained nonlinear optimization algorithm. An example taken from the literature illustrates that both the number of multipliers and the number of adders for the resulting optimized filter are less than 80% compared with those of the FRM filter obtained using the original FRM design schemes in the case where the masking filters are separately implemented. If a common filter part is used for realizing the masking filters, then an additional reduction of more than 10% is achieved compared with the optimized design with separately implemented masking filters.

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Li, Nan, Yi Nan Wang, Hong Shan Nie, Hong Qi Yu, and Hui Xu. "Biomaterial Impedance Analyzer Based on Digital Auto Balancing Bridge." Advanced Materials Research 291-294 (July 2011): 1259–62. http://dx.doi.org/10.4028/www.scientific.net/amr.291-294.1259.

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This paper presents the design method of a novel biomaterial impedance analyzer based on digital auto balancing bridge method. The system hardware mainly consists of FPGA, ADC, DACs and operational amplifiers. Many DSP algorithms such as direct digital frequency synthesis (DDS), digital phase sensitive demodulation (DPSD), digital modulation and digital filter are implemented in FPGA to realize the auto balancing function of the bridge circuit. Simulation results show that the system has good performance from low frequency to 10MHz. It is suitable for EIS application in biomaterial analysis.

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Keller, M., A. Buhmann, M. Kuderer, and Y. Manoli. "On the synthesis and optimization of cascaded continuous-time Sigma-Delta modulators." Advances in Radio Science 4 (September 6, 2006): 293–97. http://dx.doi.org/10.5194/ars-4-293-2006.

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Abstract. Up to now, there exist two completely different approaches for the synthesis of cascaded CT Sigma-Delta modulators. While the first method is based on a DT prototype and thus on the application of a DT-to-CT transformation, the second one is entirely performed in the CT domain. In this contribution, the method of lifting will be applied to overcome the disadvantages afflicted with the first method (e.g. less ideal anti-aliasing filter performance, increased circuit complexity) and to establish a time efficient DT simulation model for the second method. Thereby, optimal modulator coefficients as well as optimal digital cancellation filters for an arbitrary cascaded CT modulator can be simulated in an efficient and rapid manner. For illustrative purposes, the complete synthesis procedure is demonstrated by the example of a 2-1-1 cascaded CT modulator.

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Petrosian, R. V., and K. R. Kolos. "SYNTHESIS OF A DIGITAL FILTER OF SYMMETRIC COMPONENTS BASED ON A GENETIC ALGORITHM." Scientific notes of Taurida National V.I. Vernadsky University. Series: Technical Sciences, no. 4 (2021): 135–41. http://dx.doi.org/10.32838/2663-5941/2021.4/21.

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Li, Nan, Jing Guo, Hong Shan Nie, Wei Yi, Hai Jun Liu, and Hui Xu. "Design of Embedded Bio-Impedance Analyzer Based on Digital Auto Balancing Bridge Method." Applied Mechanics and Materials 135-136 (October 2011): 396–401. http://dx.doi.org/10.4028/www.scientific.net/amm.135-136.396.

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This paper presented the design of a novel embedded bio-impedance analyzer based on digital auto-balancing bridge method. The hardware architecture of the system mainly consists of FPGA, ADC, DACs, USB controller and so on. Many DSP algorithms such as direct digital synthesis, digital phase sensitive demodulation, digital modulation and digital filter were implemented in FPGA to realize the auto balancing function of the bridge circuit. Simulation results show that the system has good performance from low frequency up to 10 MHz. For the advantages of cost-efficient and high stability, it is suitable for BIA application.

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41

Dinesh, R., and Ramalatha Marimuthu. "An analysis of ADPLL applications in various fields." Indonesian Journal of Electrical Engineering and Computer Science 18, no. 2 (May 1, 2020): 856. http://dx.doi.org/10.11591/ijeecs.v18.i2.pp856-866.

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<span>ADPLL is now an essential component in applications like wireless sensor networks, Internet of things, health care applications, agricultural applications, etc, and also due the requirement of digital implementation by the industries. ADPLL consists of a phase detector, loop filter and digital controlled oscillator. The conventional PLL and digital PLL used for frequency synthesis, clock recovery circuit and synchronization give imprecise performance with respect to reliability, speed, power consumption, noise, locking speed, cost, etc. ADPLL overcomes the drawbacks of conventional PLL and digital PLL. In this paper, different approaches followed in All Digital Phase Locked Loop (ADPLL) for various applications are reviewed and their performance is compared based on components, modulation functions, frequency range, power utilization etc. In addition, an ADPLL with wide tuning range and frequency resolution is designed and implemented using automatic placement and routing, time to digital converter, digital loop filter and ring based oscillator. The ADPLL outputs and the results are analyzed with micro wind tool. The design gives a frequency range from 1.0-5.5GHz with low power consumption and it can also be used for Clock generation applications. </span>

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Yu, Y. J., K. L. Teo, Y. C. Lim, and G. H. Zhao. "Extrapolated impulse response filter and its application in the synthesis of digital filters using the frequency-response masking technique." Signal Processing 85, no. 3 (March 2005): 581–90. http://dx.doi.org/10.1016/j.sigpro.2004.11.003.

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Jia, Liang, Wei Sun, Xing Ma, Jun Sun, Feng Wang, and Wen Qi Zhao. "The Design of Signal Generator with DDS Based on FPGA." Applied Mechanics and Materials 644-650 (September 2014): 4427–30. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.4427.

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Direct Digital Synthesizer （DDS） is a new theory starting from the conceptual phase required for the direct synthesis of waveforms, This system in the FPGA chip and D/A conversion circuit, filter circuit, amplitude amplification circuit and power amplifier circuit's support to achieve a meet scheduled targets multiple waveform output.

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In-Cheol Park and Hyeong-Ju Kang. "Digital filter synthesis based on an algorithm to generate all minimal signed digit representations." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21, no. 12 (December 2002): 1525–29. http://dx.doi.org/10.1109/tcad.2002.804374.

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Temenos, Nikos, Anastasis Vlachos, and Paul P. Sotiriadis. "Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals." Technologies 10, no. 1 (January 20, 2022): 14. http://dx.doi.org/10.3390/technologies10010014.

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This work presents a soft-filtering digital signal processing architecture based on sigma-delta modulators and stochastic computing. A sigma-delta modulator converts the input high-resolution signal to a single-bit stream enabling filtering structures to be realized using stochastic computing’s negligible-area multipliers. Simulation in the spectral domain demonstrates the filter’s proper operation and its roll-off behavior, as well as the signal-to-noise ratio improvement using the sigma-delta modulator, compared to typical stochastic computing filter realizations. The proposed architecture’s hardware advantages are showcased with synthesis results for two FIR filters using FPGA and synopsys tools, while comparisons with standard stochastic computing-based hardware realizations, as well as with conventional binary ones, demonstrate its efficacy.

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Verheyen, K., G. Torfs, and J. Bauwelinck. "Digital PLL‐based frequency synthesis: effect of loop filter shape on required DCO frequency resolution." Electronics Letters 50, no. 20 (September 2014): 1425–27. http://dx.doi.org/10.1049/el.2014.1804.

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Wu-Sheng Lu and A. Antoniou. "Synthesis of 2-D state-space fixed-point digital-filter structures with minimum roundoff noise." IEEE Transactions on Circuits and Systems 33, no. 10 (October 1986): 965–73. http://dx.doi.org/10.1109/tcs.1986.1085853.

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Pinzon, P. J., C. Vazquez, I. Perez, and J. M. Sanchez Pena. "Synthesis of Asymmetric Flat-Top Birefringent Interleaver Based on Digital Filter Design and Genetic Algorithm." IEEE Photonics Journal 5, no. 1 (February 2013): 7100113. http://dx.doi.org/10.1109/jphot.2012.2235419.

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Ko, Hsien-Ju, and Jeffrey J. P. Tsai. "Robust and Computationally Efficient Digital IIR Filter Synthesis and Stability Analysis Under Finite Precision Implementations." IEEE Transactions on Signal Processing 68 (2020): 1807–22. http://dx.doi.org/10.1109/tsp.2020.2977848.

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Chinkin, V. E., V. G. Getmanov, and I. I. Yashin. "SYNTHESIS OF A DIGITAL LOW-PASS QUASI-GAUSSIAN FILTER FOR NOISE REDUCTION IN POISSON OBSERVATIONS." Автометрия 57, no. 4 (2021): 118–25. http://dx.doi.org/10.15372/aut20210414.

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