Dissertations / Theses on the topic 'Digital electronics'

Transmission of digital signals is today more frequently used than transmission of analog signals. One reason for this is that a digital signal is less sensitive to noise than an analog, another reason is that almost all signals today are handled in a digital format. This thesis describes the development of a system that receives digital video signals through FireWire. The standard for FireWire, which is a high performance serial bus, is under development. Today the standard of the bus supports transmission of data with a speed of up to 400 Mbit/s. In the future FireWire is supposed to transmit data with a speed of up to 3,2 Gbit/s. The thesis gives an introduction to the technique for FireWire and how it is implemented. It also includes a short description of digital video signals in DVCAM format.

In this thesis, digit-serial implementation of recursive digital filters is considered. The theories presented can be applied to any recursive digital filter, and in this thesis we study the lossless discrete integrator (LDI) allpass filter. A brief introduction regarding suppression of limit cycles at finite wordlength conditions is given, and an extended stability region, where the second-order LDI allpass filter is free from quantization limit cycles, is presented.

The realization of digit-serial processing elements, i.e., digit-serial adders and multipliers, is studied. A new digit-serial hybrid adder (DSHA) is presented. The adder can be pipelined to the bit level with a short arithmetic critical path, which makes it well suited when implementing high-throughput recursive digital filters.

Two digit-serial multipliers which can be pipelined to the bit level are considered. It is concluded that a digit-serial/parallelmultiplier based on shift-accumulation(DSAAM) is a good candidate when implementing recursive digital systems, mainly due to low latency. Furthermore, our study shows that low latency will lead to higher throughput and lower power consumption.

Scheduling of recursive digit-serial algorithms is studied. It is concluded that implementation issues such as latency and arithmetic critical path are usually required before scheduling considerations can be made. Cyclic scheduling using digit-serial arithmetics is also considered. It is shown that digit-serial cyclic scheduling is very attractive for high-throughput implementations.

The thesis demonstrates a low-cost, low-bandwidth and low-resolution Analog-to- Digital Converter(ADC) in 0.35 um CMOS Process. A second-order Sigma-Delta modulator is used as the basis of the A/D Converter. A Semi-Uniform quantizer is used with the modulator to take advantage of input distributions that are dominated by smaller-amplitude signals e.g. Audio, Voice and Image-sensor signals. A Single-bit feedback topology is used with a multi-bit quantizer in the modulator. This topology avoids the use of a multi-bit DAC in the feedback loop – hence the system does not need to use digital correction techniques to compensate for a multi-bit DAC nonlinearity.

High-Level Simulations of the second-order Sigma-Delta modulator single-bit feedback topology along with a Semi-Uniform quantizer are performed in Cadence. Results indicate that a 5-bit Semi-Uniform quantizer with a Over-Sampling Ratio of 32, can achieve a resolution of 10 bits, in addition, a semi-uniform quantizer exhibits a 5-6 dB gain in SNR over its uniform counterpart for input amplitudes smaller than –10 dB. Finally, this system is designed in 0.35um CMOS process.

In thesis a Digital Down Converter (DDC) for Long Term Evolution (LTE) signals is designed. The DDC shall be implemented in hardware in a Field Programmable Gate Array (FPGA). For an FPGA the desired operating speed is high. The purpose of this thesis is therefore to determine if it is possible to design such a system.

 The proposed DDC design consists of an efficient quadrature demodulator and a data rate decimation system. The decimation system consists of a Cascaded Integrator Comb (CIC) filter and a compensating Finite Impulse Response (FIR) filer. It is shown how the CIC and FIR filter can be made parallel in order to increase the data rate while still maintaining the clock speed.

This thesis shows that it is possible to design an FPGA based DDC for LTE signals with a decimation factor of 13, running at 399.36 MHz. The estimated performance increase of FPGA based design compared to the software based design is 319 times. Since floating-point numbers is inefficient to implement in hardware, thesis uses integer filter coefficients. This introduced gain in the system. This shows that fixed-point filter coefficients is to prefer.

I den här uppsatsen utvecklas en digital nerkonverterare (DDC) för signaler inom Long Term Evolution (LTE). DDC:n skall implementeras i hårdvara i en Field Programmable Gate Array (FPGA). Den önskade datahastigheten är hög för en FPGA. Därför är syftet med denna uppsatts att undersöka om det är möjligt att implementera ett sådant system i en FPGA.

Den framtagna designen av en DDC består av en effektiv I/Q-demodulator och ett datahastighetsdecimeringssystem. Systemet för att minska datahastigheten består av ett Cascaded Integrator Comb-filter (CIC) och ett kompenserande Finite Impulse Response-filter (FIR). Det visas hur CIC- och FIR-filter kan parallelliseras för att öka datahastigheten medan klockhastigheten bibehålls.

Det visas att det är möjligt att designa en FPGA-baserad DDC för LTE-signeler, med en decimeringsfactor på 13, som kör med en hastighet på 399.36 MHz. Den uppskattade prestandaökningen för denna FPGA-baserade lösning i jämförelse med mjukvarubaserad design är 319 gånger. I den här uppsatsen användes heltalsfilterkoefficienter eftersom flyttal inte kan implementeras effektivt i hårdvara. Detta skapade dock en oönskad förstärkning i det totala systemet. Därför är så kallade fixpunktsdecimaltal att föredra.

Master thesis work at ITN (Department of Science and Technology) in the areas of A/D-construction and RF-circuit design. Major goal of project were to research suitable possibilities for implementations of direct conversion in transceivers operating in the 160MHz band, theoretic study followed by development of components in the construction environment Cadence. Suitable A/D- converter and other important parts were selected at the end of the theoretic study. Subsampling technique was applied to make A/D sample requirements more realistic to achieve. Besides lowering requirements on A/D-converter it allows a more simple construction, which saves more components than subsampling adds. Subsampling add extra noise, because of that an A/D-converter based on the RSD algorithm was chosen to improve error rate. To achieve high bit-processing rate compared to the used number of transistors, pipeline structure were selected as conversion method. The receiver was that part which gained largest attention because it’s the part which is most interesting to optimise. A/D-conversion is more difficult to construct than D/A conversion, besides there’s more to gain from eliminating mixers in the receiver than in the transmitter.

In this thesis measurement systems for the purpose of characterization of radio frequency power amplifiers are studied. Methods to increase the speed, accuracy, bandwidth, as well as to reduce the sampling requirements and testing cost are presented. A method intended for signal shaping with respect to peak to-average ratio reduction and its effects-improvements on the radio frequency front-end performance is investigated.

A time domain measurement system intended for fast and accurate measurements and characterization of radio frequency power amplifiers is discussed. An automated, fast and accurate technique for power and frequency sweep measurements is presented. Multidimensional representation of measured figure of merits is evaluated for its importance on the production-testing phase of power amplifiers.

A technique to extend the digital bandwidth of a measurement system is discussed. It is based on the Zhu-Frank generalized sampling theorem which decreases the requirements on the sampling rate of the measurement system. Its application for power amplifiers behavioral modeling is discussed and evaluated experimentally.

A general method for designing multitone for the purpose of out-of-band characterization of nonlinear radio frequency modules using harmonic sampling is presented. It has an application with the validation of power amplifiers behavioral models in their out-of-band frequency spectral support when extracted from undersampled data.

A method for unfolding the frequency spectrum of undersampled wideband signals is presented. It is of high relevance to state-of-the-art radio frequency measurement systems which capture repetitive waveform based on a sampling rate that violates the Nyquist constraint. The method is presented in a compact form, it eliminates ambiguities caused by folded frequency spectra standing outside the Nyquist band, and is relevant for calibration matters.

A convex optimization reduction-based method of peaks-to-average ratio of orthogonal frequency division multiplexing signals is presented and experimentally validated for a wireless local area network system. Improvements on the radio frequency power amplifier level are investigated with respect to power added efficiency, output power, in-band and out-of-band errors. The influence of the power distribution in the excitation signal on power amplifier performance was evaluated.