Dissertations / Theses on the topic 'Digital electronics – Testing'
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Wenzel, Robert Joseph. "Multigigahertz digital test system electronics and high frequency data path modeling." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/13334.
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Yogi, Nitin Agrawal Vishwani D. "Spectral methods for testing of digital circuits." Auburn, Ala, 2009. http://hdl.handle.net/10415/1750.
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Chen, Yaw-Huei 1959. "A NEW TEST GENERATION ALGORITHM IMPLEMENTATION." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276527.
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This thesis describes a new test generating algorithm, depth-first algorithm. This algorithm detects the reconvergent fanout. The controllability and observability measures are included in this algorithm to guide the forward and consistency drives. The major objective of this research is to develop a test vector generatiang algorithm, which is modified from D-algorithm, and to link this algorithm with SCIRTSS programs. This depth-first algorithm is more accurate and more efficient than D-algorithm. Serveral circuits are tested under DF3 and SCR3 and the results are listed in this paper.
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Cervantes, Jonathan A. "Health prognosis of electronics via power profiling." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2009. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.
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Elbadri, Mohammed. "A reconfigurable processing unit for digital circuit testing using built-in self-test techniques." Thesis, University of Ottawa (Canada), 2007. http://hdl.handle.net/10393/27514.
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Digital circuit testing is presented in this thesis. This thesis introduces an architecture that accelerates benchmarked circuit testing. Traditionally, benchmark circuits are tested on software, because of the complexity in developing a generic hardware architecture capable of testing sequentially or concurrently. The testing is based on Built-in Self-Test (BIST) techniques. The circuit testing is accomplished by two hardware implementations, aimed at increasing execution time with respect to its counterpart, software. The implementation realized and executed in hardware, illustrates the advantages of utilizing hardware platforms for digital circuit testing and it gives a path to developing more complex benchmarked circuits; which would have higher fault coverage.
The novel architecture is targeted for digital circuit testing and adaptive embedded system applications. These applications vary in their constraints (i.e. hard and soft real-time constraints) and environmental conditions (i.e. unknown and unpredictable).
The novel architecture consists of a fixed hardware unit and a Reconfigurable Processor Unit (RPU). The RPU employs hardware functional blocks. These Hardware Blocks (HB) encompass logic that targets their respective applications. We realize and implement HBs that target digital circuit testing applications, by means of BIST techniques.
Experimental results are presented in this thesis. In simple terms, the speedup factors are as high as 1 x 104 for sequential testing.
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Lee, Chang-Hwa 1957. "Analysis of approaches to synchronous faults simulation by surrogate propagation." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276771.
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This thesis describes a new simulation technique, Synchronous Faults Simulation by Surrogate with Exception, first proposed by Dr. F. J. Hill and has been initiated under the direction of Xiolin Wang. This paper reports early results of that project. The Sequential Circuit Test Sequence System, SCIRTSS, is an automatic test generation system which is developed in University of Arizona which will be used as a target to compare against the results of the new simulator. The major objective of this research is to analyze the results obtained by using the new simulator SFSSE against the results obtained by using the parallel simulator SCIRTSS. The results are listed in this paper to verify superiority of the new simulation technique.
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Kowalczyk, Nina K. "The impact of voluntariness, gender, and age on subjective norm and intention to use digital imaging technology in a healthcare environment testing a theoretical model /." Columbus, Ohio : Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1226605857.
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Yang, Dayu Dai Foster. "Frequency syntheses with delta-sigma modulations and their applications for mixed signal testing." Auburn, Ala., 2006. http://hdl.handle.net/10415/1294.
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Marette, Alexandre J. "The Design, Building, and Testing of a Constant on Discreet Jammer for the Ieee 802.15.4/ZIGBEE Wireless Communication Protocol." DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1873.
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As wireless protocols become easier to implement, more products come with wireless connectivity. This latest push for wireless connectivity has left a gap in the development of the security and the reliability of some protocols. These wireless protocols can be used in the growing field of IoT where wireless sensors are used to share information throughout a network. IoT is being implemented in homes, agriculture, manufactory, and in the medical field. Disrupting a wireless device from proper communication could potentially result in production loss, security issues, and bodily harm. The 802.15.4/ZigBee protocol is used in low power, low data rate, and low cost wireless applications such as medical devices and home automation devices. This protocol uses CSMA-CA (Carrier Sense Multiple Access w/ Collision Avoidance) which allows for multiple ZigBee devices to transmit simultaneousness and allows for wireless coexistence with the existing protocols at the same frequency band. The CSMA-CA MAC layer seems to introduce an unintentional gap in the reliability of the protocol. By creating a 16-tone signal with center frequencies located in the center of the multiple access channels, all channels will appear to be in use and the ZigBee device will be unable to transmit data. The jamming device will be created using the following hardware implementation. An FPGA connected to a high-speed Digital to Analog Converter will be used to create a digital signal synthesizer device that will create the 16-tone signal. The 16-tone signal will then be mixed up to the 2.4 GHz band, amplified, and radiated using a 2.4 GHz up-converter device. The transmitted jamming signal will cause the ZigBee MAC layer to wait indefinitely for the channel to clear. Since the channel will not clear, the MAC layer will not allow any transmission and the ZigBee devices will not communicate.
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Chapel, Brian Ernie. "Digital disk recorder for geophysics." Thesis, University of British Columbia, 1985. http://hdl.handle.net/2429/24592.
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This thesis describes the design and testing of a floppy disk drive based digital recorder. The device was originally built for a geomagnetic research project, but is also suitable for other phenomena with time scales from fractions of a second to approximately one day. The system is designed specifically to improve the reliability for long-term observing programs and to enhance the efficency of the subsequent data analysis procedures. Using an STD-Z80 BUS microcomputer, under the control of a Forth language program, the recorder stores digital data on removable 8-inch floppy disks. This thesis explicitly addresses the issue of cost and provides the necessary detail for reproduction of the device. A procedure is described for preparing the acquired data for analysis using computing facilities equiped with an appropriate disk reader. Also presented is a quantitative and qualitative evaluation of the recorder's performance when applied to both synthetic and natural signals. The latter include geomagnetically induced currents in power transmission lines.Science, Faculty of
Earth, Ocean and Atmospheric Sciences, Department of
Graduate
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Pant, Pankaj. "Automated diagnosis of path delay faults in digital integrated circuits." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13556.
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Newman, Kimberly Eileen. "A parallel digital interconnect test methodology for multi-chip module substrate networks." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13847.
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Cosgrove, S. J. "Expert system technology applied to the testing of complex digital electronic architectures : TEXAS; a synergistic test strategy planning and functional test pattern generation methodology applicable to the design, development and testing of complex digit." Thesis, Brunel University, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234077.
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Berner, Heiko. "The selection and single event upset testing of a DSP processor for a LEO satellite." Thesis, Stellenbosch : Stellenbosch University, 2002. http://hdl.handle.net/10019.1/53171.
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Thesis (MScEng)--University of Stellenbosch, 2002.ENGLISH ABSTRACT: After successful use of a DSP processor onboard the SUNSAT satellite, the need arose for a faster floating-point processor. A list of possible processors was generated from various selection criteria. Two suitable DSP processors were chosen, and because no radiation information was available for one of them, the decision was made to perform radiation tests on it. The procedures used to test the processor are described in detail so the same methods can be used for future radiation tests. An error detection and correction circuit was implemented to check and correct upsets in the on-chip memory of the DSP processor. This ensures that the processor code and data stays intact.
AFRIKAANSE OPSOMMING: Na suksesvolle gebruik van 'n DSP verwerker aanboord die SUNSAT satelliet het die behoefte ontstaan vir 'n vinniger wissel-punt verwerker. 'n Lys van moontlike verwerkers is opgestel met die hulp van verskeie seleksie kriteria. Twee geskikte DSP verwerkers is gekies, en omdat geen radiasie informasie vir die een beskikbaar was nie, is besluit om radiasie toetse op hom te doen. Die prosedures gebruik om die verwerker te toets word deeglik beskryf sodat dieselfde metodes in die toekom gebruik kan word. 'n Fout deteksie en korreksie baan is geimplementeer om foute in die aanboord geheue van die DSP verwerker op te spoor en te korrigeer. Dit verseker dat die verwerker se kode en data intak bly.
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Bordovský, Tomáš. "Elektronická zátěž s digitálním řízením." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-220250.
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This diploma thesis deals with analysis and exploration of design options, how to design and produce an electronic load. The paper discussed the possibilities of digital control. It also describes the principles of structural components and there was chosen one type variant which is designed to circuits and printed circuit boards. Moreover, the thesis also include technical drawings of mechanical parts. At the end of this paper, final soulution with measurements and parameters are presented.
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Vos, Jacu. "Feasibility of the PowerPc 603ETM for a LEO satellite on-board computer." Thesis, Stellenbosch : Stellenbosch University, 2002. http://hdl.handle.net/10019.1/52844.
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Thesis (MScEng)--University of Stellenbosch, 2002.ENGLISH ABSTRACT: For space designs, just as for terrestrial applications, the appetite for more computing power is virtually insatiable. Further, like portable applications, space use implies severe power constraints. Among currently available commercial processors, the PowerPC family ranks high in Million Instructions Per Second (MIPS) per watt, but its suitability for space applications outside low-earth orbits (LEOs) may be limited by the radiation environment, particularly single ev nt effects (SEE). This thesis covers the feasibility of using the PowerPC 603e™ processor for LEO satellite applications. The PowerPC architecture is well established with an excellent roadmap, which makes for a baseline microprocessor with long-term availability and excellent software support. The evaluation board design leverages Commercial Off-The-Shelf (COTS) technologies, allowing early integration and test. It provides a clear path to upgrades and provides a high performance platform to suit multiple missions.
AFRIKAANSE OPSOMMING: Die soeke na rekenaars met hoer werkverrigting sal nooit ophou rue. Dit geld vir beide rekenaars op aarde as satelliet aanboord rekenaars. Rekenaars vir ruimte gebruik word ook streng drywingsbeperkings opgele. Die PowerPC familie vergelyk baie goed met ander verwerkers, maar hul bruikbaarheid vir ruimte toepassings kan dalk beperk word tot lae wentelbane waar die ruimte radiasie omgewing meer toeganklik is. Die skrywe behandel die bruikbaarheid van die PowerPC 603e verwerker vir lae wentelbaan satelliet gebruik. Die welgestelde argitektuur, bekombaarheid en uitstekende sagte- _ ware ondersteuning verseker 'n standvastige fondasie. Kornmersiele komponente het voorkeur geniet in die hardeware ontwerp wat spoedige ontwikkeling sowel as aanpasbaarheid verseker. Die ontwerp bied 'n hoe werkverrigting en maklik opgradeerbare oplossing vir 'n groot verskeidenheid gebruike.
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Lee, Chris Y. "Full Custom VLSI Design of On-Line Stability Checkers." DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/607.
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A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.
A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge.
The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports.
Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays.
Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values.
The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.
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Hawes, Michael Kerrigan. "A low-cost, flexible, automatic-testing-system for digital circuits." Thesis, 2015. http://hdl.handle.net/10539/16744.
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Wu, Chang-Ping, and 武昌平. "CPLD/FPGA Design for Testing Board of Digital Electronics Technician Authentication." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/26t8fn.
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碩士國立高雄應用科技大學
電子工程系碩士班
102
Nowadays, in order to investigate the effectiveness of the circuit design, EDA enables fast verification and design for electronic circuits. The technician certification receives much attention in recent years. Thus, the certification of the Level B Technician for Digital Electronics is an important certification of electronic engineer. To acquire this certification, the skill of practical electronics design must be inspected by examination. including the design ability of practical functional circuits. After finishing the designs based on the assigned 3 examination questions, the designs are verified by 3 instruments. The verified instruments with large volume are expensive. If the examinee wants to exercise before test, they need to find the place with the 3 specific instruments to verify their designs. So it is not convenient to the examinee. This research aims at the tester designs for the verification of the 3 skill examination questions of the Level B Technician for Digital Electronics. Three testers are finished for the verification of examinee’s designed circuits, i.e, 4-digit display, keyboard scanner and digital electronic clock. The designed testers have the advantages of low cost, small volume and complete function verification. We use complex programmable logic device (CPLD) to develop our testers, so the realization period becomes shorter. The used CPLD from Altera Corporation belongs to the low-cost EPM series chips. It can be used to design complex circuits instead of using traditional TTL/CMOS gates. The Quartus II software is used to describe the intended function, and then it has been downloaded to burn into the CPLD IC via PC Print Port. Then the CPLD can operate independently. After the measurement, it is found that the designed testers have identical functions as the mentioned 3 specific instruments. Thus the designs are verified.
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Amin, Bilal Surveying & Spatial Information Systems Faculty of Engineering UNSW. "Software radio global navigation satellite system (GNSS) receiver front-end design: sampling and jitter considerations." 2007. http://handle.unsw.edu.au/1959.4/40881.
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This thesis examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software Radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. In this thesis, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter is calculated and the required jitter standard deviation allowable for wach GNSS band of interest is evaluated and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. Analysis shows that psec-level jitter specifications are required in order to keep jitter noise well below the thermal noise for software radio satellite navigation receivers. However, analysis of a BPSK system shows that large errors occur if the jittered sample crosses a data bit boundary. However, the signal processing techniques required to process the BOC modulation are much more challenging than those for traditional BPSK. BOC and AltBOC have more transitions per chip of spreading code and hence jitter creates greater SNR degradation. This work derives expressions for noise due to jitter taking into account the transition probability in QPSK, BOC, AltBOC systems. Both simulations and analysis are used to give a better understanding of jitter effects on Software Radio GNSS receivers.
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Mauser, Kevin Alton. "A digitally invertible universal amplifier for recording and processing of bioelectric signals." Thesis, 2014. http://hdl.handle.net/1805/3812.
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Indiana University-Purdue University Indianapolis (IUPUI)The recording and processing of bioelectric signals over the decades has led to the development of many different types of analog filtering and amplification techniques. Meanwhile, there have also been many advancements in the realm of digital signal processing that allow for more powerful analysis of these collected signals. The issues with present acquisition schemes are that (1) they introduce irreversible distortion to the signals and may ultimately hinder analyses that rely on the unique morphological differences between bioelectric signal events and (2) they do not allow the collection of frequencies in the signal from direct-current (DC) to high-frequencies. The project put forth aims to overcome these two issues and present a new scheme for bioelectric signal acquisition and processing. In this thesis, a system has been developed, verified, and validated with experimental data to demonstrate the ability to build an invertible universal amplifier and digital restoration scheme. The thesis is primarily divided into four sections which focus on (1) the introduction and background information, (2) theory and development, (3) verification implementation and testing, and (4) validation implementation and testing. The introduction and background provides pertinent information regarding bioelectric signals and recording practices for bioelectric signals. It also begins to address some of the issues with the classical and present methods for data acquisition and make the case for why an invertible universal amplifier would be better. The universal amplifier transfer function and architecture are discussed and presented along with the development and optimization of the characterization and the inversion, or restoration, filter process. The developed universal amplifier, referred to as the invertible universal amplifier (IUA), while the universal amplifier and the digital restoration scheme together are referred to as the IUA system. The IUA system is then verified on the bench using typical square, sine, and triangle waveforms with varying offsets and the results are presented and discussed. The validation is done with in-vivo experiments showing that the IUA system may be used to acquire and process bioelectric signals with percent error less than to 6% when post-processed using estimated characteristics of and when compared to a standard flat bandwidth high-pass cutoff amplifier.
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Sinha, Alok Kumar. "Some Novel Ideas For Static And Dynamic Testing Of High-Speed High Resolution ADCs." Thesis, 2005. http://etd.iisc.ernet.in/handle/2005/1561.
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Abell, Stephen W. "Parallel acceleration of deadlock detection and avoidance algorithms on GPUs." Thesis, 2013. http://hdl.handle.net/1805/3653.
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Indiana University-Purdue University Indianapolis (IUPUI)Current mainstream computing systems have become increasingly complex. Most of which have Central Processing Units (CPUs) that invoke multiple threads for their computing tasks. The growing issue with these systems is resource contention and with resource contention comes the risk of encountering a deadlock status in the system. Various software and hardware approaches exist that implement deadlock detection/avoidance techniques; however, they lack either the speed or problem size capability needed for real-time systems. The research conducted for this thesis aims to resolve issues present in past approaches by converging the two platforms (software and hardware) by means of the Graphics Processing Unit (GPU). Presented in this thesis are two GPU-based deadlock detection algorithms and one GPU-based deadlock avoidance algorithm. These GPU-based algorithms are: (i) GPU-OSDDA: A GPU-based Single Unit Resource Deadlock Detection Algorithm, (ii) GPU-LMDDA: A GPU-based Multi-Unit Resource Deadlock Detection Algorithm, and (iii) GPU-PBA: A GPU-based Deadlock Avoidance Algorithm. Both GPU-OSDDA and GPU-LMDDA utilize the Resource Allocation Graph (RAG) to represent resource allocation status in the system. However, the RAG is represented using integer-length bit-vectors. The advantages brought forth by this approach are plenty: (i) less memory required for algorithm matrices, (ii) 32 computations performed per instruction (in most cases), and (iii) allows our algorithms to handle large numbers of processes and resources. The deadlock detection algorithms also require minimal interaction with the CPU by implementing matrix storage and algorithm computations on the GPU, thus providing an interactive service type of behavior. As a result of this approach, both algorithms were able to achieve speedups over two orders of magnitude higher than their serial CPU implementations (3.17-317.42x for GPU-OSDDA and 37.17-812.50x for GPU-LMDDA). Lastly, GPU-PBA is the first parallel deadlock avoidance algorithm implemented on the GPU. While it does not achieve two orders of magnitude speedup over its CPU implementation, it does provide a platform for future deadlock avoidance research for the GPU.