Relevant bibliographies by topics / Digital electronics – Testing

Academic literature on the topic 'Digital electronics – Testing'

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Published: 4 June 2021
Last updated: 4 February 2022

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Journal articles on the topic "Digital electronics – Testing"

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Newton, C. Mike, Paul I. Deffenbaugh, Kenneth H. Church, Nathan B. Crane, and Clayton Neff. "Digital Manufacturing and Performance Testing for Military Grade Application Specific Electronic Packaging (ASEP)." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000250–66. http://dx.doi.org/10.4071/isom-2016-wp13.

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I. Abstract This paper will discuss the development of additive manufacturing as a process integration methodology for printed electronics and 3D printed structures. This integration enables the ability to move from printed circuit boards (PCBs) to printed circuit structures (PCS). Historically packaging has been identified as a hierarchical (or levels) approach to interconnect electronic products or systems. Level one packaging addresses the interconnection between bare die and the module while level four moves up in the packaging chain to connections between subassemblies. With the advent of digital manufacturing and emergence of more robust materials, the enabling technology provides a manufacturing tool for building electronic packages with integrated passives (some printed) and actives. This further enables the capability to adjust the form factor to the mission or product requirements - also known as personalization. This ability to become form factor agnostic has produced the ability for printing or digitally manufacturing application specific electronic packages, ASEPs. With this emerging capability it begs the question of reliability and in particular to qualification for harsh environment applications. This paper will discuss the application of current standards, Mil-Std-883 or JESD93 for example and how these might be applied to ASEPs and to also explore the development of new or hybridization of current standards.
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Shalumov, Alexander Slavovich, Natalya Alexandrovna Shalumova, and Maxim Alexandrovich Shalumov. "ALGORITHM FOR MODELING MECHANICAL PROCESSES IN AVIATION ELECTRONICS, TAKING INTO ACCOUNT THE NONLINEARITY OF THE DAMPING PROPERTIES OF MATERIALS." Globus: technical sciences 7, no. 3(39) (August 19, 2021): 29–36. http://dx.doi.org/10.52013/2713-3079-39-3-4.

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The object of research is aviation electronics. The purpose of the work is to develop algorithms for modeling mechanical processes in aviation electronics for the subsequent implementation of a prototype of a software and methodological complex for creating digital twins of aviation electronics. The work was carried out under contract № 91GS1CTS10-D5/61789 dated September 23, 2020 on the provision of a grant for conducting research and development work on the topic «Development of a prototype of a software and methodological complex for creating digital twins of aviation electronics and its testing» with the Federal State budgetary institution «Fund for Assistance to the Development of Small Enterprises in the Scientific and Technical Sphere».
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Fang, Kun, Rui Zhang, Tami Isaacs-Smith, R. Wayne Johnson, Emad Andarawis, and Alexey Vert. "Thin Film Multichip Packaging for High Temperature Digital Electronics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000039–45. http://dx.doi.org/10.4071/hiten-paper1-rwjohnson.

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Digital silicon carbide integrated circuits provide enhanced functionality for electronics in geothermal, aircraft and other high temperature applications. A multilayer thin film substrate technology has been developed to interconnect multiple SiC devices along with passive components. The conductor is vacuum deposited Ti/Ti:W/Au followed by an electroplated Au. A PECVD silicon nitride is used for the interlayer dielectric. Adhesion testing of the conductor and the dielectric was performed as deposited and after aging at 320°C. The electrical characteristics of the dielectric as a function of temperature were measured. Thermocompression flip chip bonding of Au stud bumped SiC die was used for electrical connection of the digital die to the thin film substrate metallization. Since polymer underfills are not compatible with 300°C operation, AlN was used as the base ceramic substrate to minimize the coefficient of thermal expansion mismatch between the SiC die and the substrate. Initial die shear results are presented.
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Syryamkin, V. I. "Digital X-ray 3D-microtomograph for testing materials and components used in electronics." Russian Journal of Nondestructive Testing 52, no. 9 (September 2016): 504–11. http://dx.doi.org/10.1134/s1061830916090060.

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Rea, Richard. "Configurable Digital Logic for Extreme Environments." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2018, HiTEC (May 1, 2018): 000098–102. http://dx.doi.org/10.4071/2380-4491-2018-hiten-000098.

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Abstract This paper presents a multiple-configuration IC that implements a number of sequential or combinatorial logic functions for extreme environment electronics. Operating temperature is −55°C to +300°C. Combinatorial functions include AND, OR, XOR, muxes, bi-directional transceiver, priority-encoder, magnitude comparator, etc. Sequential functions include 8-bit DFF, counter, latch, programmable clock-divider, etc. The majority of 7400 logic parts are covered by this part. Special test circuitry is included for in-situ monitoring of the part during production. Endurance testing and monitoring of part lifetime at elevated stress temperature (+350°C) is also built-in.
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Gavrilenkov, Sergey I., Elizaveta O. Petrenko, and Evgeny V. Arbuzov. "A Digital Device for Automatic Checking of Homework Assignments in the Digital Circuits Course." ITM Web of Conferences 35 (2020): 04009. http://dx.doi.org/10.1051/itmconf/20203504009.

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This paper considers a digital device for automatic checking of homework assignments in the digital circuits course. The assignment is to make a digital circuit corresponding to a given logical expression; the circuit is comprised of elementary logic gates. The process of manual testing the built circuit is very labor-intensive because checking a circuit with N inputs variables requires checking the correctness of the output variable for 2N cases. We propose automating this pro-cess with a special digital device. The device is comprised of a microcontroller connected to the circuit tested. The microcontroller is connected to a personal computer with an application written in C# for executing the main operations of the testing process. During testing, the student chooses from a database or enters the logical expression corresponding to the circuit tested. For the expression, the software generates truth tables where actual and required responses of the circuit are given. Actual circuit responses are acquired by probing the circuit via the microcontroller, and the expected values are calculated from the logical expression. The truth tables are then presented to the student with a message of whether the circuit works correctly or not. The device was integrated into the process of checking homework assignments in the digital electronics course, and it significantly sped up the process of checking homework assignment circuits, resulting in better education quality.
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Liu, Wei, Zhuo Lin Miao, Huan Xin Cheng, and Li Cheng. "The Hardware Design of Ultrasonic Flaw Detector Based on Single-Chip Microcomputer AT89C52." Applied Mechanics and Materials 423-426 (September 2013): 2427–30. http://dx.doi.org/10.4028/www.scientific.net/amm.423-426.2427.

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Ultrasonic nondestructive testing is an important detection method in nondestructive testing field. It is widely used in steel manufacturing, machinery manufacturing, electronics manufacturing, aerospace and defense and other fields and departments to ensure production quality and safety. In this paper, the main research work and research results are as follows: analyze the principle of electromagnetic ultrasonic nondestructive testing and characteristic and the hardware design of ultrasonic flaw detector system based on single-chip microcomputer AT89C52. This paper laid a good foundation for more in-depth studies in the research of ultrasonic digital signal processing in future.
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Leng, Feng, Chengxiong Mao, Dan Wang, Ranran An, Yuan Zhang, Yanjun Zhao, Linglong Cai, and Jie Tian. "Applications of Digital-Physical Hybrid Real-Time Simulation Platform in Power Systems." Energies 11, no. 10 (October 9, 2018): 2682. http://dx.doi.org/10.3390/en11102682.

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Digital-physical hybrid real-time simulation (hybrid simulation) platform integrates the advantages of both digital simulation and physical simulation by combining the physical simulation laboratory and the real-time digital simulator. Based on a 400 V/50 kVA hybrid simulation platform with 500 kVA short-circuit capacity, the hybrid simulation methodology and a Hausdorff distance based accuracy evaluation method are proposed. The case validation of power system fault recurrence is performed through this platform, and the stability and accuracy are further validated by comparing the hybrid simulation waveform and field-recorded waveform and by evaluating the accuracy with the proposed error index. Two typical application scenarios in power systems are studied subsequently. The static var generator testing shows the hybrid simulation platform can provide system-level testing conditions for power electronics equipment conveniently. The low-voltage ride through standard testing of a photovoltaic inverter indicates that the hybrid simulation platform can be also used for voltage standard testing for various power system apparatus with low cost. With this hybrid simulation platform, the power system simulation and equipment testing can be implemented with many advantages, such as short period of modelling, flexible modification of parameter and network, low cost, and low risk. Based on this powerful tool platform, there will be more application scenarios in future power systems.
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Wileman, Andrew, Suresh Perinpanayagam, and Sohaib Aslam. "Physics of Failure (PoF) Based Lifetime Prediction of Power Electronics at the Printed Circuit Board Level." Applied Sciences 11, no. 6 (March 17, 2021): 2679. http://dx.doi.org/10.3390/app11062679.

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This paper presents the use of physics of failure (PoF) methodology to infer fast and accurate lifetime predictions for power electronics at the printed circuit board (PCB) level in early design stages. It is shown that the ability to accurately model silicon–metal layers, semiconductor packaging, printed circuit boards (PCBs), and assemblies allows, for instance, the prediction of solder fatigue failure due to thermal, mechanical, and manufacturing conditions. The technique allows a life-cycle prognosis of the PCB, taking into account the environmental stresses it will encounter during the period of operation. Primarily, it involves converting an electronic computer aided design (eCAD) circuit layout into computational fluid dynamic (CFD) and finite element analysis (FEA) models with accurate geometries. From this, stressors, such as thermal cycling, mechanical shock, natural frequency, and harmonic and random vibrations, are applied to understand PCB degradation, and semiconductor and capacitor wear, and accordingly provide a method for high-fidelity power PCB modelling, which can be subsequently used to facilitate virtual testing and digital twinning for aircraft systems and sub-systems.
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Tao, Quang Bang, Lahouari Benabou, Thien An Nguyen Van, and Ngoc Anh Nguyen Thi. "Using Digital Image Correlation Method to Evaluate Fracture Parameters of Lead-Free Solder." Applied Mechanics and Materials 902 (September 2020): 86–90. http://dx.doi.org/10.4028/www.scientific.net/amm.902.86.

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Newly developed lead-free solder alloys, which contain doping some elements such as Ni, Bi, Sb, Al,..., have improved properties with respect to the conventional solder alloys, particularly in terms of resistance to creep. Their high performances are specifically desired in applications of power electronics where they are used for the electrical interconnections between the components. Studies on their resistance to rupture remain relatively limited. Yet the comprehension of fracture behavior is essential for the correct design of the electronic packages which must be robust against fatigue and vibrations loads. In this study, rupture of notched specimens fabricated from the InnoLot lead-free solder alloy is investigated. The tests are performed with the help of a micro-tensile testing machine equipped with an optical system for full-field measurements with Digital Image Correlation. The images are taken at successive steps of deformation and the displacement field is measured in a region of interest which is the singularity dominated zone surrounding the plastic zone at the crack tip. The procedure consists then in comparing the measured field with the theoretical field given by the Williams’ solution. The stress intensity factor is calculated by fitting the analytical fields to the experimental data. The effects of the size and shape of the zone of data collection, as well as that of the number of terms considered in the Williams’s expansion series, are examined in the study. A method is also proposed for the automatic crack tip detection.
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Dissertations / Theses on the topic "Digital electronics – Testing"

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Wenzel, Robert Joseph. "Multigigahertz digital test system electronics and high frequency data path modeling." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/13334.

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Yogi, Nitin Agrawal Vishwani D. "Spectral methods for testing of digital circuits." Auburn, Ala, 2009. http://hdl.handle.net/10415/1750.

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Chen, Yaw-Huei 1959. "A NEW TEST GENERATION ALGORITHM IMPLEMENTATION." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276527.

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This thesis describes a new test generating algorithm, depth-first algorithm. This algorithm detects the reconvergent fanout. The controllability and observability measures are included in this algorithm to guide the forward and consistency drives. The major objective of this research is to develop a test vector generatiang algorithm, which is modified from D-algorithm, and to link this algorithm with SCIRTSS programs. This depth-first algorithm is more accurate and more efficient than D-algorithm. Serveral circuits are tested under DF3 and SCR3 and the results are listed in this paper.
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Cervantes, Jonathan A. "Health prognosis of electronics via power profiling." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2009. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.

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Elbadri, Mohammed. "A reconfigurable processing unit for digital circuit testing using built-in self-test techniques." Thesis, University of Ottawa (Canada), 2007. http://hdl.handle.net/10393/27514.

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Digital circuit testing is presented in this thesis. This thesis introduces an architecture that accelerates benchmarked circuit testing. Traditionally, benchmark circuits are tested on software, because of the complexity in developing a generic hardware architecture capable of testing sequentially or concurrently. The testing is based on Built-in Self-Test (BIST) techniques. The circuit testing is accomplished by two hardware implementations, aimed at increasing execution time with respect to its counterpart, software. The implementation realized and executed in hardware, illustrates the advantages of utilizing hardware platforms for digital circuit testing and it gives a path to developing more complex benchmarked circuits; which would have higher fault coverage. The novel architecture is targeted for digital circuit testing and adaptive embedded system applications. These applications vary in their constraints (i.e. hard and soft real-time constraints) and environmental conditions (i.e. unknown and unpredictable). The novel architecture consists of a fixed hardware unit and a Reconfigurable Processor Unit (RPU). The RPU employs hardware functional blocks. These Hardware Blocks (HB) encompass logic that targets their respective applications. We realize and implement HBs that target digital circuit testing applications, by means of BIST techniques. Experimental results are presented in this thesis. In simple terms, the speedup factors are as high as 1 x 104 for sequential testing.
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Lee, Chang-Hwa 1957. "Analysis of approaches to synchronous faults simulation by surrogate propagation." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276771.

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This thesis describes a new simulation technique, Synchronous Faults Simulation by Surrogate with Exception, first proposed by Dr. F. J. Hill and has been initiated under the direction of Xiolin Wang. This paper reports early results of that project. The Sequential Circuit Test Sequence System, SCIRTSS, is an automatic test generation system which is developed in University of Arizona which will be used as a target to compare against the results of the new simulator. The major objective of this research is to analyze the results obtained by using the new simulator SFSSE against the results obtained by using the parallel simulator SCIRTSS. The results are listed in this paper to verify superiority of the new simulation technique.
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Kowalczyk, Nina K. "The impact of voluntariness, gender, and age on subjective norm and intention to use digital imaging technology in a healthcare environment testing a theoretical model /." Columbus, Ohio : Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1226605857.

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Yang, Dayu Dai Foster. "Frequency syntheses with delta-sigma modulations and their applications for mixed signal testing." Auburn, Ala., 2006. http://hdl.handle.net/10415/1294.

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Marette, Alexandre J. "The Design, Building, and Testing of a Constant on Discreet Jammer for the Ieee 802.15.4/ZIGBEE Wireless Communication Protocol." DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1873.

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As wireless protocols become easier to implement, more products come with wireless connectivity. This latest push for wireless connectivity has left a gap in the development of the security and the reliability of some protocols. These wireless protocols can be used in the growing field of IoT where wireless sensors are used to share information throughout a network. IoT is being implemented in homes, agriculture, manufactory, and in the medical field. Disrupting a wireless device from proper communication could potentially result in production loss, security issues, and bodily harm. The 802.15.4/ZigBee protocol is used in low power, low data rate, and low cost wireless applications such as medical devices and home automation devices. This protocol uses CSMA-CA (Carrier Sense Multiple Access w/ Collision Avoidance) which allows for multiple ZigBee devices to transmit simultaneousness and allows for wireless coexistence with the existing protocols at the same frequency band. The CSMA-CA MAC layer seems to introduce an unintentional gap in the reliability of the protocol. By creating a 16-tone signal with center frequencies located in the center of the multiple access channels, all channels will appear to be in use and the ZigBee device will be unable to transmit data. The jamming device will be created using the following hardware implementation. An FPGA connected to a high-speed Digital to Analog Converter will be used to create a digital signal synthesizer device that will create the 16-tone signal. The 16-tone signal will then be mixed up to the 2.4 GHz band, amplified, and radiated using a 2.4 GHz up-converter device. The transmitted jamming signal will cause the ZigBee MAC layer to wait indefinitely for the channel to clear. Since the channel will not clear, the MAC layer will not allow any transmission and the ZigBee devices will not communicate.
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Chapel, Brian Ernie. "Digital disk recorder for geophysics." Thesis, University of British Columbia, 1985. http://hdl.handle.net/2429/24592.

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This thesis describes the design and testing of a floppy disk drive based digital recorder. The device was originally built for a geomagnetic research project, but is also suitable for other phenomena with time scales from fractions of a second to approximately one day. The system is designed specifically to improve the reliability for long-term observing programs and to enhance the efficency of the subsequent data analysis procedures. Using an STD-Z80 BUS microcomputer, under the control of a Forth language program, the recorder stores digital data on removable 8-inch floppy disks. This thesis explicitly addresses the issue of cost and provides the necessary detail for reproduction of the device. A procedure is described for preparing the acquired data for analysis using computing facilities equiped with an appropriate disk reader. Also presented is a quantitative and qualitative evaluation of the recorder's performance when applied to both synthetic and natural signals. The latter include geomagnetically induced currents in power transmission lines.
Science, Faculty of
Earth, Ocean and Atmospheric Sciences, Department of
Graduate
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Books on the topic "Digital electronics – Testing"

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Miczo, Alexander. Digital logic testing and simulation. New York: John Wiley & Sons, 1986.

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Digital logic testing and simulation. New York: Wiley, 1987.

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Miczo, Alexander. Digital logic testing and simulation. 2nd ed. Hoboken, NJ: Wiley-Interscience, 2002.

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Testing digital circuits: An introduction. Wokingham: Van Nostrand Reinhold (UK), 1986.

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Digital logic testing and simulation. 2nd ed. Hoboken, NJ: Wiley-Interscience, 2003.

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Digital logic testing and simulation. New York: Harper & Row, 1986.

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Cortner, J. Max. Digital test engineering. New York: Wiley, 1987.

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Yang, Zhao. Design and Testing of Digital Microfluidic Biochips. New York, NY: Springer New York, 2013.

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Litikov, I. P. Kolʹt͡s︡evoe testirovanie t͡s︡ifrovykh ustroĭstv. Moskva: Ėnergoatomizdat, 1990.

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Using MultiSIM: Digital electronics. Albany, N.Y: Delmar, 2002.

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Book chapters on the topic "Digital electronics – Testing"

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Ivask, Eero, Sergei Devadze, and Raimund Ubar. "Collaborative Distributed Computing in the Field of Digital Electronics Testing." In Balanced Automation Systems for Future Manufacturing Networks, 145–52. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-14341-0_17.

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"TESTING AND VERIFICATION OF DESIGNS." In MOS Digital Electronics, 183–93. WORLD SCIENTIFIC, 1987. http://dx.doi.org/10.1142/9789814415705_0011.

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Sterne, Jonathan. "The Software Passes the Test When the User Fails It." In Testing Hearing, 159–86. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780197511121.003.0007.

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Many music technologists have sought to reproduce the sonic signature of analog audio devices—amplifiers, compressors, signal processors, instruments—in the software domain. Assessing the effectiveness of the analog model involves a confusing mix of math, sound, electronics, appearances, and feelings, all of which are negotiated differently by users and designers. Drawing on ethnographic research at major software companies, along with close analysis of the technologies themselves, this chapter argues that “analog modeling” in the digital domain is one of the latest chapters in the long history of hearing tests, for it is in the moment of the listening test that engineers and users attempt to resolve competing epistemologies of sound. The listening test thus offers a privileged point of entry into both the classification and the experience of digital sound technologies.
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Grout, Ian. "Testing the Electronic System." In Digital Systems Design with FPGAs and CPLDs, 615–46. Elsevier, 2008. http://dx.doi.org/10.1016/b978-0-7506-8397-5.00009-x.

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Sanguinetti, John. "Digital Simulation." In Electronic Design Automation for IC System Design, Verification, and Testing, 401–16. CRC Press, 2017. http://dx.doi.org/10.1201/b19569-16.

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LEONHARDT, FRANK. "AUDITING, PENETRATION TESTING AND ETHICAL HACKING." In Handbook of Electronic Security and Digital Forensics, 93–101. WORLD SCIENTIFIC, 2010. http://dx.doi.org/10.1142/9789812837042_0005.

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Mitchem, Katherine, Gail Fitzgerald, and Kevin Koury. "Electronic Performance Support System (EPSS) Tools to Support Teachers and Students." In Transforming K-12 Classrooms with Digital Technology, 98–118. IGI Global, 2014. http://dx.doi.org/10.4018/978-1-4666-4538-7.ch006.

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This chapter describes the use of a family of Electronic Performance Support Systems (EPSS) to support teachers and students with mild disabilities, especially those with special learning and behavioral needs. This approach uses technology to support students in educational environments. In this chapter, the authors provide a brief overview of the family of tools and describe the need, rationale, and technical development process of the latest tools in the family, PictureTools™ and PictureTools-Mobile™. These tools are designed to support positive behaviors of young children, incorporate both images and video, and in the case of PT-Mobile, the capacity to run on iPod and iPad. In addition, they report the results from two federally funded projects related to development, usability, and feasibility testing of these tools. Future research directions are discussed.
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Kumar, Rajiv. "Design of ICT Framework to Manage the Records Electronically in the Government Offices of Botswana." In Advances in Electronic Government, Digital Divide, and Regional Development, 177–88. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-2527-2.ch009.

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The proposed framework is set up to guarantee that record keeping is considered when planning and actualizing ICT systems. The joining of record keeping usefulness in ICT frameworks is best practiced with regards to system planning, design, testing, implementation, and review. Integration of functionality of electronic records management functionality in ICT framework addresses to which extent existing ICT frameworks have been coordinated with records. The framework is pointed expressly at looking over 'master' application systems (for instance, HR, budgetary organization, or case the board structures). Regardless, it may similarly be used for assessing the arrangement and errand of employments, for instance, attempted substance organization structures that are proposed to supervise unstructured electronic records (messages, word-arranged reports, spreadsheets, etc.) consistent with the administrator's standards.
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Benna, Umar, and Indo Benna. "Revisiting Urban Theories." In Advances in Electronic Government, Digital Divide, and Regional Development, 1–22. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-2659-9.ch001.

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Urban theory has been dominated by the accumulation of social theories and has significant impact on global urbanization. The urban is becoming more complex and more global due to the contesting technological, political, social, economic and environmental forces. These disciplinary forces may be added to the global shifts in population and political power from rural to urban and from the developed to the developing nations, creating new global challenges. To cope with these challenges, the prevailing urban theories need a shift. By critically revisiting urban theories and testing them against emerging challenges, this chapter is advocating for and pointing to a new direction. The chapter revisits urban sociological theories, those global theories advocating planetary urbanization, the models responding to glocal forces as well as those promoting world systems. This is followed by an outline of the proposal for Activity Theoretical Framework. Possible future research direction for the inclusive and universal urbanization is identified.
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Paruthi, Mandakini, Priyam Mendiratta, and Gaurav Gupta. "Young Citizen's Political Engagement in India." In Advances in Electronic Government, Digital Divide, and Regional Development, 115–32. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1791-8.ch005.

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Social media has emerged as a dominant digital medium platform in contemporary society. The quick development of social media has instigated changes concerning the way publics to interact with a group of people with similar ideologies, the quality of information they share, or the opportunity to acquire and share ideas. Social media use has a major influence on public relations, marketing, and political communication. Therefore, politicians are formulating their strategies to reach increasingly networked individuals. The chapter defines political engagement concept, focuses on excessive use of social media to understand how the emergence of digital citizenship is changing political engagement. In addition to this, the chapter also examines whether the use of social media exercise any effect on 2014 and 2019. General elections outcome or not and discuss the proposed conceptual framework for future empirical testing. The chapter highlights the various concerns needed to be taken care of while using social media as a marketing tool for promoting political participation and engagement.
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Conference papers on the topic "Digital electronics – Testing"

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Freeman. "Testing Large Analog/Digital Signal Processing Chips." In IEEE International Conference on Consumer Electronics. IEEE, 1990. http://dx.doi.org/10.1109/icce.1990.665887.

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Hamed, S. M., A. H. Khalil, M. B. Abdelhalim, H. H. Amer, and A. H. Madian. "N-stage pipelined Digital to Analog converter testing." In 2012 13th Biennial Baltic Electronics Conference (BEC2012). IEEE, 2012. http://dx.doi.org/10.1109/bec.2012.6376827.

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Abbas, Mohammed, Sayyid Anas Vaqar, and Luai M. Alhems. "Digital energy meter testing under adverse field conditions." In 2016 IEEE 25th International Symposium on Industrial Electronics (ISIE). IEEE, 2016. http://dx.doi.org/10.1109/isie.2016.7744985.

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O'Donnell. "Digital Synthesis of Playback Signals for Automated Testing of Vcr's." In IEEE International Conference on Consumer Electronics. IEEE, 1990. http://dx.doi.org/10.1109/icce.1990.665889.

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Pereira, Renata I. S., and Sandro C. S. Juca. "Didactic tool for practical testing of digital voltage grading applications." In 2015 IEEE 13th Brazilian Power Electronics Conference (COBEP) and 1st Southern Power Electronics Conference (SPEC). IEEE, 2015. http://dx.doi.org/10.1109/cobep.2015.7420275.

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Pancik, Juraj, and Marek Kukucka. "Internet protocol based digital counters for legacy fatigue testing machines." In 2016 International Conference on Applied Electronics (AE). IEEE, 2016. http://dx.doi.org/10.1109/ae.2016.7577272.

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Junior, Manoel Jose S., Orlewilson B. Maia, Eddie B. L. Filho, Romulo Fabricio, and Aguinaldo Silva. "An Automated Testing Methodology For Digital TV Middleware Implementations." In 2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin). IEEE, 2019. http://dx.doi.org/10.1109/icce-berlin47944.2019.8966216.

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Arshak, Khalil, Essa Jafer, and Christian Ibala. "Testing FPGA based digital system using XILINX ChipScope logic analyzer." In 2006 29th International Spring Seminar on Electronics Technology. IEEE, 2006. http://dx.doi.org/10.1109/isse.2006.365129.

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Vanat, Toma, Jan Pospiil, Filip Kriek, Jozef Ferencei, and Hana Kubatova. "A System for Radiation Testing and Physical Fault Injection into the FPGAs and Other Electronics." In 2015 Euromicro Conference on Digital System Design (DSD). IEEE, 2015. http://dx.doi.org/10.1109/dsd.2015.98.

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Xinguo, Zhu, and Zhang Kai. "Antenna pattern testing method and verification for digital array radar." In 2015 IEEE 10th Conference on Industrial Electronics and Applications (ICIEA). IEEE, 2015. http://dx.doi.org/10.1109/iciea.2015.7334350.

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