Dissertations / Theses on the topic 'Digital electronic devices'
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Mackle, John. "Integrated digital filters." Thesis, Queen's University Belfast, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.334588.
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Bee, Sarah Caroline. "Radiation effects in analogue to digital converters." Thesis, University College London (University of London), 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.298887.
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Murad, Thamir Faraj. "Digital control of chopper-fed DC motor drive." Thesis, Loughborough University, 1985. https://dspace.lboro.ac.uk/2134/10836.
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Mirkazemi-Moud, Mehran. "Digital pulse width modulators for induction motor control." Thesis, Heriot-Watt University, 1993. http://hdl.handle.net/10399/1431.
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Stevens, M. J. "Digital control of high frequency pulse-width modulated inverters." Thesis, University of Bristol, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.373297.
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Leung, Chiu Hon. "The output frequency spectrum of a thyristor phase-controlled cycloconverter using digital control techniques." Thesis, University of Plymouth, 1985. http://hdl.handle.net/10026.1/2261.
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The principle of operation dictates that the output of a cycloconverter contains some harmonics. For drive applications, the harmonics at best increase losses in the motor and may well cause instability. Various methods of analysing the output waveform have been considered. A Fortran 77 program employing a modified Fourier series, making use of the fact that the input waveforms are sinusoidal, was used to compute the individual harmonic amplitudes. A six pulse three phase to single phase cycloconverter was built and a Z-80 microprocessor was used for the control of firing angles. Phase locked loops were used for timing, and their effect upon the output with changing input frequency and voltage were established. The experimental waveforms are analysed by a FFT spectrum analyser. The flexibility of the control circuit enables the following investigations not easily carry out using traditional analog control circuit. The phase relationship between the cosine timing and reference wave in the cosinusoidal control method was shown to affect the output waveform and hence the harmonic content. There is no clear optimum value of phase and the T.H.D. up to 500Hz remains virtually constant. However, the changes of individual harmonic amplitudes is quite significant. In practice it may not be possible to keep the value of phase constant but it should be considered when comparing control strategies. Another investigation involves the changing of the last firing angle in a half cycle. It shows that the value of firing angles produced by the cosinusoidal control method is desirable. Operation at theoretical maximum output frequency was also demonstrated.
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Sustar, Helena. "Older people as equal partners in the creative design of digital devices." Thesis, City University London, 2011. http://openaccess.city.ac.uk/1305/.
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This thesis describes research which explores the importance and feasibility of involving older people as equal partners in the creative design of digital devices for an ageing population. In exploring this topic, I have carried out two preliminary studies, a pilot study and a major empirical study. Firstly, I invited three groups of people, including very old people, active older people and postgraduate students, to evaluate a mock-‐up model of an interactive device intended for older people that was designed using a standard design process. The results of this study suggested that products without an adequate contribution from older people would not always meet their needs. Secondly, I carried out observations of very old people, active older people, and young designers to identify factors that influence the way in which both older people and young designers can be involved in the creative design process. These factors included experiences with technology, processes and approaches currently applied with older people and designers, factors that stimulate or inhibit creativity, and practical constraints such as health issues. The results of these observations fed into the design of a pilot study, where I tested the content of a creative design process and a procedure for analysing data for the main empirical study. The main study involved three creative workshops where the same creative methods were employed with different sets of people: young designers, mixed groups (with older people and designers) and older people only. The results show that older people are able to participate in a creative design process; however, certain practical constraints have to be taken into account. Also, older people perform better when they work together with designers. Finally, the mixed groups with older people, who have relevant life experiences, and designers, who are familiar with the newest technology, may be more suitable for designing appropriate products for the older population.
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Shaheed, Amjad. "A framework for the visualisation and control of ubiquitous devices, services and digital content." Thesis, Liverpool John Moores University, 2011. http://researchonline.ljmu.ac.uk/6018/.
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The General Organization for Technical Education and Vocational Training, Riyadh, Saudi Arabia, has developed a special feeding program for the students at its institutions. The effects of this program on the nutritional and health status of these students have not been evaluated yet, and since no published dietary research has been performed on Technical and Vocational young adult male students, the present work was undertaken to investigate the nutritional status of this community in Riyadh, Kingdom of Saudi Arabia. After a pilot survey, it was decided to use a selfcompleted questionnaire combined with personal interview to investigate the nutritional status of 690 students randomly selected from the study population. Dietary data was collected by two methods: usual weekly intakes "diet history" and actual daily intakes "diet diary". The nutrient intakes were calculated using the unilever Dietary Analysis Program (UNIDAP). The statistical Package for the social Science (SPSS/PC+) was employed to analyse the data; statistical significance of relationships between certain sets of data was determined by chi-square analysis. Some general factors affecting the nutritional status of these students were identified, their nutritional habits and attitudes were investigated, and the average daily intakes of energy, the macronutrients, and selected micronutrients were calculated. The main results of this study shows that the majority of the study population are adolescent, moderately active individuals, and have lower than the standard range of the Body Mass Index; anaemia is the most stated health problem; meal-skipping and eating between meals are common habits amongst the students. Regarding nutrient intake, there was an energy, polyunsaturated fat, and vitamin C deficiency; adequate intake of saturated fat, dietary fibre, retinol, and zinc; more than adequate intake of protein, total fat, cholesterol, thiamin, riboflavin, calcium, and iron. Recommendations are given which aim to improve the nutrition of technical and vocational students.
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Nguyen, Loc Bao. "Logic design using programmable logic devices." PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/4103.
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The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems.
This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the thesis also covers a seldomly used but very useful design style, Self-Synchronized Circuits.
The thesis introduces a new method to minimize Two-Level Boolean Functions using Graph Coloring Algorithms and the result is very encouraging. The raw speed of the coloring algorithms is as fast as the Espresso, the industry standard minimizer from Berkeley, and the solution is equally good.
The thesis also introduces a rule-based state assignment method which gives equal or better solutions than STASH (an Intel Automatic CAD tool) by as much as twenty percent.
One of the problems with Self-Synchronized circuits is that it takes many extra components to implement the circuit. The thesis shows how it can be designed using PLD devices and also suggests the idea of a Clock Chip to reduce the chip count to make the design style more attractive.
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Porras, Deivid Efrain Tellez. "Desenvolvimento de transmissores de pressão com sensor piezoresistivo e protocolo de comunicação HART." Universidade de São Paulo, 2014. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-19032015-171810/.
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O presente trabalho é uma pesquisa tecnológica (P&D) de inovação tecnológica de produto para o mercado brasileiro, que visa desenvolver um transmissor de pressão inteligente de alta exatidão com protocolo HART e sensor piezoresistivo em parceria LSI-USP / MEMS Ltda. Fornecendo assim um protótipo de um produto competitivo no mercado brasileiro. Neste trabalho se apresenta uma arquitetura baseada nos transmissores 4-20 mA de alta exatidão da MEMS Ltda. Essa arquitetura mantém as características de desemprenho da medição analógica e adiciona os componentes necessários para suportar as funções do padrão HART com camada física Bell 202. Além da arquitetura, neste documento é apresentado: o desenvolvimento das interfaces entre o algoritmo de compensação e os algoritmos responsáveis da comunicação digital, as modificações no circuito de controle da corrente de laço para permitir a modulação do sinal de 1200 Hz e 2200 Hz usado pela comunicação digital, e o projeto de alimentação do transmissor, que foi projetado visando a eficiência para respeitar os limites de consumo de corrente. Os resultados obtidos com essa nova arquitetura, apresentam que são mantidas as características dos transmissores 4-20 mA usados como base, e que a medição digital tem um nível de erro 0,05 %FS (porcentagem de fundo de escala) menor do que a saída analógica do mesmo transmissor, valor considerável comparado com o 0,2 %FS que é o nível de erro total do sistema. Os protótipos usados para as medições foram caracterizados num processo que levou 35 dias de operação continua, validando assim o projeto elétrico e software desenvolvido.This thesis consists of a technical research (P&D) on technological innovations of a highly accurate intelligent pressure transmitter using a HART protocol and piezoresistive sensors in collaboration with LSI-USP / MEMS Ltda. The outcome consists of a prototype of a competitive product in the Brazilian market. This project presents a product architecture based on highly accurate 4-20mA MEMS Ltda. transmitters. It maintains the features necessary for analogical measurements and adds components, which are compatible with the functions of HART with a Bell 202 physical layer. In addition to the architecture, this document presents the development of: interfaces between the compensation algorithm and digital communication algorithms, modifications of the current loop control circuit to allow signal modulation used by digital communications of 1200Hz and 2000Hz, a voltage source project, which envisioned efficiency and considered the limits of current consumption. Results of this architecture show that the 4-20mA transmitter´s characteristics, used as a starting point for the product, are maintained and that digital measurements present 0.05%FS (Full Scale) less error than analogical measurements taken by the same transmitter. This presents a significant error reduction when compared to the total error of the system, which is 0, 2 %FS. The prototypes used for measurements were tested during 35 continuous days, validating their electrical installation and software.
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Griffin, Brian Maxwell 1969. "Digital image processing in a high volume document environment." Monash University, Gippsland School of Engineering, 1997. http://arrow.monash.edu.au/hdl/1959.1/8680.
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Yoo, Heejong. "Low-Power Audio Input Enhancement for Portable Devices." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6821.
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With the development of VLSI and wireless communication
technology, portable devices such as personal digital assistants
(PDAs), pocket PCs, and mobile phones have gained a lot of
popularity. Many such devices incorporate a speech recognition
engine, enabling users to interact with the devices using
voice-driven commands and text-to-speech synthesis.
The power consumption of DSP microprocessors has been
consistently decreasing by half about every 18 months, following
Gene's law. The capacity of signal processing, however, is still
significantly constrained by the limited power budget of these
portable devices. In addition, analog-to-digital (A/D) converters
can also limit the signal processing of portable devices. Many
systems require very high-resolution and high-performance A/D
converters, which often consume a large fraction of the limited
power budget of portable devices.
The proposed research develops a low-power audio signal
enhancement system that combines programmable analog signal
processing and traditional digital signal processing. By
utilizing analog signal processing based on floating-gate
transistor technology, the power consumption of the overall
system as well as the complexity of the A/D converters can be
reduced significantly. The system can be used as a front end of
portable devices in which enhancement of audio signal quality
plays a critical role in automatic speech recognition systems on
portable devices. The proposed system performs background audio
noise suppression in a continuous-time domain using analog
computing elements and acoustic echo cancellation in a
discrete-time domain using an FPGA.
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Baker, Rebecca Dawn. "Comparing the Readability of Text Displays on Paper, E-Book Readers, and Small Screen Devices." Thesis, University of North Texas, 2010. https://digital.library.unt.edu/ark:/67531/metadc28390/.
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Science fiction has long promised the digitalization of books. Characters in films and television routinely check their palm-sized (or smaller) electronic displays for fast-scrolling information. However, this very technology, increasingly prevalent in today's world, has not been embraced universally. While the convenience of pocket-sized information pieces has the techno-savvy entranced, the general public still greets the advent of the e-book with a curious reluctance. This lack of enthusiasm seems strange in the face of the many advantages offered by the new medium - vastly superior storage capacity, searchability, portability, lower cost, and instantaneous access. This dissertation addresses the need for research examining the reading comprehension and the role emotional response plays in the perceived performance on e-document formats as compared to traditional paper format. This study compares the relative reading comprehension on three formats (Kindle, iTouch, and paper) and examines the relationship of subject's emotional response and relative technology exposure as factors that affect how the subject perceives they have performed on those formats. This study demonstrates that, for basic reading comprehension, the medium does not matter. Furthermore, it shows that, the more uncomfortable a person is with technology and expertise in the requested task (in this case, reading), the more they cling to the belief that they will do better on traditional (paper) media - regardless of how well they actually do.
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Forsby, Filip. "Digital Certificates for the Internet of Things." Thesis, KTH, Nätverk och systemteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-217120.
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This thesis will investigate the possibility of developing a lightweight digitalcertificate solution for resource constrained embedded systems in 6LoWPANnetworks. Such systems are battery powered or energy harvesting devices whereit is crucial that energy consumption and memory footprints are as minimalas possible. Current solutions for digital certificates are found to be moredemanding than what is desirable and therefore an issue that needs to besolved.The solution that is proposed in this thesis is a profile for the X.509 cer-tificate standard for use with constrained devices and the Internet of Things(IoT). Furthermore, a compression mechanism is designed and implementedfor certificates following this X.509 profile.Results show that compressing certificates is a highly viable solution, de-spite the added complexity it brings.This new lightweight digital certificate solution will allow resource con-strained systems to be able to run for longer without being interrupted orneeding maintenance.Denna avhandling undersöker möjligheten att utveckla lättviktslösning förinbyggda system med begränsade resurser i 6LoWPAN-nätverk. Eneheter isådanna system drivs på batteri och återvunnen energi från omgivningen därminimal energi- och minnesanvänding är avgörande. Nuvarande lösningar fördigitala certifikat anses vara mer krävande än önskvärt och det är därför ettproblem som behöver lösas.Lösningen som presenteras i denna avhandling är en profil för certifikatstan-darden X.509 för användning med begränsade enheter inom Internet of Things(IoT). Utöver det är en komprimeringsmekanism designad och implementeradför certifikat som följer denna X.509-profil.Resultat visar att det är högst genomförbart att komprimera certifikat,trots den ökade komoplexiteten det medför.Denna nya lösning för digitala certifikat tillåter resursbegränsade enheteratt köras längre utan att behöva avbrytas eller underhållas.
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Wistedt, Johan. "Digital secondary substations with auto-configuration of station monitoring through IEC 61850 and CIM." Thesis, Uppsala universitet, Elektricitetslära, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-360513.
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This thesis explore the possibility to automate a process for configuration of secondary substations monitoring and control. By using a network information system (NIS), information of secondary substations can be extracted, such as feeder naming, primary equipment type, rating and model. From this information an automated process of configuring the secondary substation is possible, which open up the possibility to cost-efficiently digitalise the distribution grid. In the project, the standard IEC 61850 for configuration of communications of intelligent electrical devices was used to automate and standardize the process. The process starts with a extracted IEC 61970 CIM file from the NIS. The IEC 61970 CIM file is converted into a IEC 61850 SCL file through an system engineering tool. The configuration is based of information from the NIS, where the models and types of the equipments decides what type of functionality that is needed for the secondary substation. With help of the created SCL file hardware and human-machine interface (HMI) was configured, creating a full functional system for the secondary substation monitoring and control equipment. The usage of 400V capable input module together with bus couplers, configured in IEC 61850, lowers the configuration needed for the hardware. The usage of SCL files also helps automate the creation of HMI for the secondary substation through IEC 61850 based tools in SCADA software. Creating views of both single-line diagrams as well as digital representation of the secondary substation outgoing feeders with measured values on display. The result of the project helps show NIS information is sufficient and standards mature enough to allow an almost fully automated system. Lowering the total time spent on each stations configuration to around two hours. Leading the way for future development of automating software for configurations of the secondary substations.
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Netto, Ulisses Chemin. "Determinação de um parâmetro para monitoramento do desempenho de mensagens GOOSE do padrão IEC 61850 utilizadas em subestações de energia elétrica." Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/18/18154/tde-16102012-083711/.
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O desenvolvimento e utilização do padrão IEC 61850 alterou a concepção e operação das subestações de energia elétrica. O desempenho e confiabilidade do sistema de proteção depende da rede de comunicação de dados. Esta pesquisa propõe um parâmetro de dimensionamento e comparação de desempenho para o tempo de transferência das mensagens Generic Object Oriented Substation Event (GOOSE) entre Intelligent Electronic Devices (IEDs). Esse parâmetro foi obtido através do levantamento experimental da curva do tempo de transferência das mensagens GOOSE versus a ocupação percentual da largura de banda dos IEDs. Para a realização dos experimentos foram utilizados três IEDs, um switch Ethernet gerenciável, três microcomputadores do tipo PC, um relógio sincronizador Global Positioning System (GPS), cordões de fibra óptica, cabos do tipo par trançado sem blindagem e aplicativos de software. Os resultados mostraram que a partir de um limiar característico, o qual é distinto para cada IED ensaiado, o tempo de transferência excede o limite máximo permitido pelo padrão IEC 61850. A partir da análise destes dados, foi desenvolvido um sistema preditivo de monitoramento de banda para supervisionar a interface de rede dos IEDs. O sistema preditivo apresentou para a medição de banda um erro relativo médio igual a 0,55% em relação ao aplicativo comercial utilizado na comparação, já a predição feita pela rede neural artificial apresentou um erro de estimativa menor do que 3% para 91,30% das amostras utilizadas, além de modelar adequadamente o comportamento da série temporal que representa a ocupação de banda do IED monitorado.The development and utilization of IEC 61850 standard changed the design and operation of electric power substations. The performance and reliability of the protection system depends on the data communication network. This research proposes a parameter for dimensioning and comparising the transfer time of Generic Object Oriented Substation Event (GOOSE) messages between different Intelligent Electronic Devices (IEDs). This parameter was obtained from experimental data related to the transfer time of GOOSE messages curve versus IEDs bandwidth percentage occupation. In this context, a laboratory structure was set up in order to carry out these experiments. This structure mainly consists of three IEDs, an Ethernet switch, three personal computers, a GPS Clock, fiber optic cables, unshielded twisted pair cables, as well as support software. The results show the existence of a characteristic threshold, different for each IED tested, after which the transfer time exceeded the total transmission time allowed for the IEC 61850 standard. Based on these results, a predictive bandwidth monitoring system was developed to supervise the IEDs bandwidth interface. The bandwidth measurement has a mean relative error of 0.55% regarding to the commercial software used for comparison. Finally, the forecasting made by the artificial neural network has a relative error of 3% for 91,30% of the samples used in test phase. In addition, that it was able to model the behaviour of the time series that represent the bandwidth occupation.
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Lum, Randall M. G. "Differential pulse code modulation data compression." Scholarly Commons, 1989. https://scholarlycommons.pacific.edu/uop_etds/2181.
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With the requirement to store and transmit information efficiently, an ever increasing number of uses of data compression techniques have been generated in diverse fields such as television, surveillance, remote sensing, medical processing, office automation, and robotics. Rapid increases in processing capabilities and the speed of complex integrated circuits make data compression techniques a prime candidate for application in the areas mentioned above. This report addresses, from a theoretical viewpoint, three major data compression techniques, Pixel Coding, Predictive Coding, and Transform Coding. It begins with a project description and continues with data compression techniques, focusing on Differential Pulse Code Modulation.
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Sehn, Thaís Cristina Martino. "As possíveis configurações do livro nos suportes digitais." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/97246.
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Esta pesquisa foi efetivada com a finalidade de mapear os artefatos que são atualmente denominados 'livros digitais', caracterizando-os a partir do cruzamento dos recursos próprios do meio digital com as principais especificidades dos livros impressos. A metodologia utilizada abrangeu revisão bibliográfica e observação do objeto de estudo. Para alcançar o objetivo proposto, realizou-se um resgate histórico, identificando as características associadas à noção de 'livro', levando em consideração as modificações ocorridas a partir de sua materialidade. Após esse estudo, foi possível compreender a remediação dos livros impressos nos e-books, principalmente naqueles que podem ser acessados através de e-readers e tablets. Outro recorte abordado por esta pesquisa focaliza a identificação e o registro dos recursos que vêm sendo explorados nas produções que estão sendo chamadas de livros digitais. Efetuada a revisão bibliográfica, foram estudadas as potencialidades do hipertexto, da multimídia e da interatividade dentro do livro eletrônico. Ademais, foram comentadas diferentes maneiras de o leitor se aproximar e interagir com o conteúdo da obra, através da utilização dos recursos citados. Antes de se realizar a análise dos artefatos em questão, foi necessário, ainda, aprender mais sobre a materialidade dos mesmos, percebendo como o hardware, o software e o conteúdo interagem entre si, restringindo, assim, as possibilidades que podem ser ofertadas ao leitor. Na tabela final de análise foram avaliadas as particularidades das seguintes macrocategorias: Identificação, Acesso, Funcionalidades, Potencialidades do meio digital, Aproximação da ideia de livro impresso (remediação) e Projeto gráfico. A partir do estudo teórico e empírico realizado, percebeu-se que o livro é um artefato com propriedades flexíveis, decidindo-se, por isto, propor uma série de princípios que, juntos, possam ser utilizados para caracterizar esse tipo de publicação, independente de ela ser digital ou impressa. Logo, chegou-se a conclusão de que o e-book é um conteúdo digital com as mesmas características de um livro e que pode explorar, além do texto e da imagem, recursos da mídia digital, tais como interatividade, som, vídeo e animação. Através das características predominantes dos artefatos analisados, foram identificados os seguintes tipos de livros digitais: customizável, PDF, digitalizado, multimídia e interativo.This research has as its purpose to map out the artifacts so-called ‘digital books’ nowadays. They were characterized from a crossing between printed books main specificities and those related to digital environment very own resources. The research methodology applied to it was of two kinds: literature review and an observational study of the object of study. A historical overview was unearthed in order to achieve the intended purpose, identifying the characteristics linked to the notion of ‘book’, taking into account changes that have taken place stemming from its materiality. Given this perception it was possible to understand the remediation of the print book proposed in e-books, the ones accessed through e-readers and tablets mainly. Identification and registration of the latest developments in digital books resources were another point covered in this work. From a literature review standpoint, interactivity, multimedia and hypertext potentialities were crossexamined. Moreover, there had been discussed some of the alternatives to offer readers proximity and different ways to interact with the work content through the use of cited resources. Still, before realizing the artifact analysis, a more in-depth study of e-book materiality was needed. That is, to perceive how hardware, content and software interact among themselves restricting the possibilities that might be made available to the reader. The singularities of the following macro categories: Identification, Access, Functionalities, Potentialities of the digital environment and the approach of the printed book concept (remediation) to graphic project were evaluated in the table analysis. After an empirical and theoretical study, it was realized that book is an artifact with flexible properties, thus, a definition was set forth based upon a series of principles that together characterize this type of publication, regardless of being in printed or digital form. Therefore, we came to the conclusion the e-book is a digital content with the same features of a printed book and the former can exploit digital media resources such as sound, video, animation and interactivity besides virtually text and image. We were also able to identify through the artifacts primary features that were under analysis the following types of digital books: customized, PDF, digitized, multimedia and interactive.
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Lee, Chris Y. "Full Custom VLSI Design of On-Line Stability Checkers." DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/607.
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A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.
A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge.
The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports.
Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays.
Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values.
The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.
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Zhang, Yi. "High performance DSP-based servo drive control for a limited-angle torque motor." Thesis, Loughborough University, 1997. https://dspace.lboro.ac.uk/2134/6768.
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This thesis describes the analysis, design and implementation of a high performance DSP-based servo drive for a limited-angle torque motor used in thermal imaging applications. A limited-angle torque motor is an electromagnetic actuator based on the Laws' relay principle, and in the present application the rotation required was from - 10° to + 10° in 16 ms, with a flyback period of 4 ms. To ensure good quality picture reproduction, an exceptionally high linearity of ±0.02 ° was necessary throughout the forward sweep. In addition, the drive voltage to the exciting winding of the motor should be less than the +35 V ceiling of the drive amplifier. A research survey shows that little literature was available, probably due to the commercial sensitivity of many of the applications for torque motors. A detailed mathematical model of the motor drive, including high-order linear dynamics and the significant nonlinear characteristics, was developed to provide an insight into the overall system behaviour. The proposed control scheme uses a multicompensator, multi-loop linear controller, to reshape substantially the motor response characteristic, with a non-linear adaptive gain-scheduled controller to compensate effectively for the nonlinear variations of the motor parameters. The scheme demonstrates that a demanding nonlinear control system may be conveniently analysed and synthesised using frequency-domain methods, and that the design techniques may be reliably applied to similar electro-mechanical systems required to track a repetitive waveform. A prototype drive system was designed, constructed and tested during the course of the research. The drive system comprises a DSP-based digital controller, a linear power amplifier and the feedback signal conditioning circuit necessary for the closed-loop control. A switch-mode amplifier was also built, evaluated and compared with the linear amplifier. It was shown that the overall performance of the linear amplifier was superior to that of the switch-mode amplifier for the present application. The control software was developed using the structured programming method, with the continuous controller converted to digital form using the bilinear transform. The 6- operator was used rather than the z-operator, since it is more advantageous for high speed sampling systems. The gain-scheduled control was implemented by developing a schedule table, which is controlled by the DSP program to update continuously the controller parameters in synchronism with the periodic scanning of the motor. The experimental results show excellent agreement with the simulated results, with linearity of ±0.05 ° achieved throughout the forward sweep. Although this did not quite meet the very demanding specifications due to the limitations of the experimental drive system, it clearly demonstrates the effectiveness of the proposed control scheme. The discrepancies between simulated and experimental results are analyzed and discussed, the control design method is reviewed, and detailed suggestions are presented for further work which may improve the drive performance.
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Marusiak, David. "MOS CURRENT MODE LOGIC (MCML) ANALYSIS FOR QUIET DIGITAL CIRCUITRY AND CREATION OF A STANDARD CELL LIBRARY FOR REDUCING THE DEVELOPMENT TIME OF MIXED-SIGNAL CHIPS." DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1363.
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Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells.
The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.
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Dawe, Roger Michael. "Digitally controlled soft-starting of cage induction motors." Thesis, University of Leeds, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.277301.
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Guardia, Filho Luiz Eduardo. "Sistema para controle de maquinas robotizadas utilizando dispositivos logicos programaveis." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259017.
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Orientador: Marconi Kolm MadridDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-04T17:12:57Z (GMT). No. of bitstreams: 1 GuardiaFilho_LuizEduardo_M.pdf: 2405031 bytes, checksum: b724836217b8586950a9ffabcd235f35 (MD5) Previous issue date: 2005
Resumo: Este trabalho de mestrado teve o propósito de projetar e construir um sistema de hard-ware capaz de realizar o controle de máquinas robotizadas em tempo real. Foi dada uma abordagem usando técnicas de processamento paralelo e eletrônica reconfigurável com o uso de dispositivos lógicos programáveis. Mostrou-se em função dos resultados das implementações que o sistema proposto é eficiente para ser utilizado no controle de robôs baseado em modelos matemáticos complexos como cinemático direto/inverso, dinâmico e de visão artificial. Esse mesmo sistema prevê sua utilização para os quatro níveis hierárquicos envolvidos em plantas que se utilizam de controle automático: supervisão, tarefas, trajetória e servomecanismos. O sistema possui interfaces de comunicação USE e RS-232, conversores A/D e D/A, sistema de processamento de imagens (entradas e saídas de sinais de vídeo analógico), portas E/S, chaves e leds para propósito geral. A eficiência foi comprovada através de experimentações práticas utilizando sistemas robóticos reais como: sistema de um pêndulo acionado, robô redundante de 4GDL denominado Cobra, e solução em hardware de funções importantes no sentido da resolução dos modelos matemáticos em tempo real como funções transcendentais
Abstract: This work had as purpose the project and build of a hardware system with abilities to accomplish the real time control of robotic machines. It was given an approach using tech-niques of parallel processing and programmable electronics configuration with programmable logic devices. According to the implementation results, it was shown that this proposed sys-tem is efficient to be used for controlling robots based on complex mathematical models, like direct/inverse kinematics, dynamics and artificial vision. This system foresees its use for the four hierarchical levels involved in industrial plants that use automatic control: supervision, tasks, trajectory /path and servomechanisms. The system has USE and RS-232 communica-tion interfaces, A/D and D/A converters, image processing capabilities (with input/output for analog video signals), I/O ports, and switches and leds for general purpose. Its efficiency is demonstrated through practical experimentations using real robotic systems as: a driven pendu-lum system, a redundant 4 DOF robot called "Cobra", and a hardware solution for important functions in the sense of real time mathematical models computing, like the transcendental functions
Mestrado
Automação
Mestre em Engenharia Elétrica
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Jackson, Jonathan Keith. "Enhancing the performance of residual current devices by the use of digital electronics." Thesis, Bangor University, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.440429.
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Zee, Kah Yep. "Design of the electronics and optics needed to support charge-coupled devices : a project report." Scholarly Commons, 1989. https://scholarlycommons.pacific.edu/uop_etds/2188.
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GILANI, HASSAN, and RAISUL BHUIYAN. "Development of ADQ214 user interface in labVIEW." Thesis, Blekinge Tekniska Högskola, Sektionen för ingenjörsvetenskap, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5451.
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This thesis was conducted in collaboration with Signal Processing (SP) Devices Sweden AB. SP Devices provides digital signal processing solutions for the enhancement of analogue to digital conversion (ADC). Their ADCs facilitate the development of products for Communications, Radio base stations, Radar, Signals intelligence and Test & Measurement. The ADQ series digitizers, from SP Devices, are portable high performance digitizers which incorporate one or more analog inputs, an on-board double data rate (DDR2) memory and USB or PXI Express interface. DDR2 refers to the ability of a computer bus to transfer data on both the rising and falling edges of a clock signal. The ADCaptureLab software is a graphical user interface used to control this digitizer. ADCaptureLab, designed in the C/C++ programming language, is an easy-to-use standalone program which allows for configuration and operation of all ADQ series digitizers from SP Devices. The use of the LabView program from National Instruments forms the backbone of this thesis. LabVIEW (short for Laboratory Virtual Instrumentation Engineering Workbench) is a platform and development environment for a visual programming language from National Instruments. The topic of this thesis was to reproduce the ADCaptureLab user interface using LabView instead of C/C++. The graphical user interface (GUI) developed in LabView should be able to communicate with and control the processing of the ADQ214 digitizer (the digitizer model provided to us) in the same way as the ADCaptureLab. This would involve not only the data capturing and visualization but also digitizer configurations, monitoring of the device and ADQ functions and the analyses of acquired signal and FFT. In order to implement the configuration settings we developed functions for trigger settings (conditions at which a trigger will occur), Analogue Front End settings (AC/DC coupling), clock settings (sets the clock source), data type settings (set sample format), gain and offset setting (sets amplitude gain and mean value), pre-trigger settings (size of pre-trigger buffer), trigger hold off settings ( number of samples to wait for acquiring data after trigger), data acquisition length settings (Length of the acquired signal), continuous and single batch data acquisition, FFT transformation, save, load , and “clear plots” control (resets graph indicators). The functioning of our device may be monitored through the “Status window” (displays connection status of the ADQ device), “Devices window” (displays product information about the ADQ device), “Device monitor window” (returns the status of ADQ-API functions used) and the “Device information window” (returns information related to the revision of the ADQ device). Analyzing the acquired data and its corresponding FFT is made simple with the “Signal Properties” window (displays analyzed data), “Mark Harmonics” control (marks harmonics in the FFT) and the “Mark Signal Props” control (marks the fundamental tone and highest distortion in the FFT). Our LabVIEW GUI efficiently incorporates the features described above. In addition to being able to communicate instructions to the ADQ214 device we are able to monitor its condition and analyze any output. This result serves to show that it is possible to develop a program such as ADCaptureLab in LabVIEW.HASSAN GILANI # : +46736742637 RAISUL BHUIYAN # :+46762596979
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Schultz, Alexander J. "Programmable Control of Non-Droplet Electrowetting Microfluidics: Enabling Materials, Devices, and Electronics." University of Cincinnati / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1427812427.
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Toker, Emre 1960. "A prototype charge-coupled device based image acquisition system for digital mammography." Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/277308.
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A Charge-Coupled Device (CCD) based electronic imaging system is proposed to overcome limitations of conventional film/screen mammography systems at no additional risk or discomfort to the patient. This thesis presents the design, implementation and evaluation of a number of prototype systems incorporating the latest advances in x-ray intensifying phosphor screen, fiber optic reducer, and CCD technologies. System design is based on an x-ray intensifying screen optically coupled to a high resolution, cooled, scientific CCD through a fiber optic reducer. The performance of the prototype system is compared to theoretical predictions, to the ideal x-ray detector, and to conventional film/screen detectors. Images of breast phantoms captured by the prototype CCD-based system and by conventional mammography systems are presented. Experimental results indicate that the CCD-based system can provide "film quality" images within seconds of x-ray exposure in needle localization, fine-needle aspiration biopsy, and magnification procedures in mammography.
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Nasis, Vasileios T. Kurzweg Timothy P. "A novel approach to programmable imaging using MOEMS /." Philadelphia, Pa. : Drexel University, 2008. http://hdl.handle.net/1860/2842.
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Penrod, Logan B. "An Exploratory Study of Pulse Width and Delta Sigma Modulators." DigitalCommons@CalPoly, 2020. https://digitalcommons.calpoly.edu/theses/2278.
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This paper explores the noise shaping and noise producing qualities of Delta-Sigma Modulators (DSM) and Pulse-Width Modulators (PWM). DSM has long been dominant in the Delta Sigma Analog-to-Digital Converter (DSADC) as a noise-shaped quantizer and time discretizer, while PWM, with a similar self oscillating structure, has seen use in Class D Power Amplifiers, performing a similar function. It has been shown that the PWM in Class D Amplifiers outperforms the DSM [1], but could this advantage be used in DSADC use-cases? LTSpice simulation and printed circuit board implementation and test are used to present data on four variations of these modulators: The DSM, PWM, the out-of-loop discretized PWM (OOLDP), and the cascaded modulator. A generic form of an Nth order loop filter is presented, where three orders of this generic topology are analyzed in simulation for each modulator, and two orders are used in physical testing.
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Hirtzlin, Tifenn. "Digital Implementation of Neuromorphic systems using Emerging Memory devices." Thesis, université Paris-Saclay, 2020. http://www.theses.fr/2020UPAST071.
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Depuis les années soixante-dix l'évolution des performances des circuits électroniques repose exclusivement sur l'amélioration des performances des transistors. Ce composant a des propriétés extraordinaires puisque lorsque ses dimensions sont réduites, toutes ses caractéristiques sont améliorées. Mais, dû à certaines limites physiques fondamentales, la diminution des dimensions des transistors n’est plus possible. Néanmoins, de nouveaux nano-composants mémoire innovants qui peuvent être intégré conjointement avec les transistors voient le jour tant au niveau académique qu'industriel, ce qui constitue une opportunité pour repenser complètement l'architecture des circuits électroniques actuels. L'une des voies de recherche possible est l’inspiration du fonctionnement du cerveau biologique. Ce dernier peut accomplir des tâches complexes et variées en consommant très peu d’énergie. Ces travaux de thèse explorent trois paradigmes neuro-inspirés pour l'utilisation de ces composants mémoire. Chacune de ces approches explore différentes problématiques du calcul en mémoireWhile electronics has prospered inexorably for several decades, its leading source of progress will stop in the next coming years, due to the fundamental technological limits of transistors. Nevertheless, microelectronics is currently offering a major breakthrough: in recent years, memory technologies have undergone incredible progress, opening the way for multiple research venues in embedded systems. Additionally, a major feature for future years will be the ability to integrate different technologies on the same chip. new emerging memory devices that can be embedded in the core of the CMOS, such as Resistive Random Access Memory (RRAM) or Spin Torque Magnetic Tunnel Junction (STMRAM) based on naturally intelligent inmemory-computing architecture. Three braininspired algorithms are carefully examined: Bayesian reasoning binarized neural networks, and an approach that further exploits the intrinsic behavior of components, population coding of neurons. Each of these approaches explores different aspects of in-memory computing
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Ghosh, Malinky Dai Foster. "A novel ROM compression technique and a high speed sigma-delta modulator design for direct digital synthesizer." Auburn, Ala., 2006. http://hdl.handle.net/10415/1312.
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Ostrander, Charles Nicholas. "Phase alignment of asynchronous external clock controllable devices to periodic master control signal using the Periodic Event Synchronization Unit." Thesis, Montana State University, 2009. http://etd.lib.montana.edu/etd/2009/ostrander/OstranderC0509.pdf.
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The Periodic Event Synchronization Unit aligns devices without the ability to be triggered by an external source. The primary function of the unit is to align the pattern trigger pulses of two pulse pattern generators which supply four inputs of a multiplexer. The pulse pattern generators lack the ability to start their code according to an external signal. When operating, the designed unit maintains a specific pattern alignment of two binary data streams of 5 gigabits per second as a multiplexer combines them into a data stream of four times the bit rate. In addition to alignment, the unit can introduce offsets of up to 50 nanoseconds to the pattern alignment which corresponds to 250 bits. The unit is designed to allow the alignment of other devices as well, requiring as input the two event signals of the same frequency which need to be aligned. In order to align the devices providing the event pulses, one of the devices must either accept an external clocking source or have the ability to frequency modulate the internal clock. In practice, the test system was able to achieve and maintain the desired signal characteristics from the output of the multiplexer. The unit's robust design is shown by providing alignment of patterns for the full operating range of the pulse pattern generators and allowing a generator pattern to be aligned to a generic event pulse. Use of multiple units allows alignment of additional devices. The development of the Periodic Event Synchronization Unit provided an inexpensive solution to creating very high bit rate signals using preexisting equipment, as no commercial products were found to accomplish the same function.
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Koche, Rahulkumar Sadanand. "Measurement and modeling of passive surface mount devices on FR4 substrates." PDXScholar, 2012. https://pdxscholar.library.pdx.edu/open_access_etds/754.
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Passive components like resistors, capacitors and inductors are used in every electronic system. These are the very basic components which affect the system performance at higher frequencies and it is necessary to understand and model the behavior of these components in a very accurate manner. This work focuses on utilizing Printed Circuit Board (PCB) test boards, or fixtures, made of FR4 for characterizing Surface Mount Device (SMD) components. Agilent's Advanced Design System (ADS) microwave circuit simulation software was used for designing the microstrip transmission lines as well as for generating the layout for manufacturing of the PCB. SMD resistors, capacitors and inductors were soldered into the fixture and then measured using the Vector Network Analyzer (VNA). The calibration kit was developed in ADS. The measured data were calibrated using the TRL (Thru-Reflect-Line) calibration algorithm. A calibration kit consisting of through, three transmission lines of various lengths, open and short was designed and manufactured. Calibration procedures were performed using Cascade Microtech's WinCal XE software. Based on our experience, TRL calibration did not perform to its full potential due to errors in the value of the characteristic impedance of microstrip transmission line. This impedance is ideally assumed to be 50 Ohm, but our lines had characteristic impedance of around 49 Ohm. Simple models for the resistors and capacitors were developed by our collaborators at the University of Zagreb and we developed the model for the inductors. We used ADS for simulations and comparison with the measured data. Extensive optimization of these models was done so as to fit the measured and modeled data. As the frequency goes above 4 GHz models and measurements don't match due to the limitations of the PCB material, the increasing effects of the parasitics and calibration artifacts. This work shows how and when we can use inexpensive FR4 PCB for the characterization of the passive SMD components in the low GHz frequency range. It also examines the range of operating frequency of SMD components, verifies the parameters extracted from the simple model and tests the TRL calibration algorithm.
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Grahn, Pontus. "Utilization of a tailormade condition monitoring device for third party motors." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-235281.
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Our society moves towards digitalization and the industry is not an exception. Siemenshas developed a wireless condition monitoring device called Simotics Connect in order tohelp them to move forward in the world of digitalization. The Simotics Connect has threeinbuilt sensors. One for temperature, one for vibrations and one for magnetic flux density,a product that is new in the market. This master thesis has investigated its usability forthird party motors, which has not been done.Four areas were investigated, the status in the current market, creating a motorgeometry estimation based on nameplate data, presenting a temperature model to calculatea motor’s cross section temperature and, finally, proposed a stator current model using themagnetic field measurement.Market research has shown that a space for the Simotics Connect to thrive in mostdefinitely exists.The motor geometry estimation, that is based on preliminary electromagnetic sizing,creates a digital twin for the motor that has sufficient accuracy as a tool when calculatinge.g. temperature calculations but lacks accuracy for more advanced and sensitivecalculations e.g for magnetic flux density measurement usability.The temperature model that is presented shows great accuracy when calculating thecross section temperature in the stator but the accuracy decreases for the cross sectiontemperature in the rotor.A stator current model is proposed using a proportional relationship between themagnetic flux density and stator current. The results indicates a linear relationship, thoughusing the digital twin to calculate the proportional constant were concluded to not beaccurate enough.Sammhället rör sig idag mot digitalisering och industrin är ej ett undantag. Siemens harutvecklat en trådlös underhållsmätare kallad Simotics Connect för att hjälpa dem strävamot en värld inom digitalisering. Simotics Connect hat tre inbyggda sensorer. En för temperatur,en för vibrationer och en för magnetisk flödestäthet, vilket är nytt på marknaden.Detta masterprojekt har undersökt användningen av Simotics Connect för tredjepartsmotorer,vilket ej har gjorts tidigare.Fyra områden undersöktes, statusen på den nuvarande marknaden, en motorgeometriuppskattningmodellbaserad på namnskylsdata, en temperaturmodell för att beräknamotorns tvärsnittstemperatur och, slutligen, en statorströmmodell som använder sig avmagnetiska flödestäthetsmätningen.Marknadsundersökningen har visat att det finns ett utrymme för Simotics Connectatt blomstra inom på den nuvarande marknaden.Motorns geometriska uppskattning, som är baserad i preliminär elektromagnetiskgeometribestämning, skapar en digital tvilling av motorn som är tillräckligt noggrann föratt aggera som ett verktyg vid t.ex. temperatursberäkningar men saknar noggrannhet förmer avancerade och känsliga beräkningar, t ex för användbarhet inom magnetisk flödestäthetsberäkningar.Temperaturmodellen som presenteras visar stor noggrannhet vid beräkning av statornstvärsnittstemperatur, men noggrannheten minskar för rotorns tvärsnittstemperatur.En statorströmmodell föreslås med ett proportionellt förhållande mellan magnetflödesdensitetenoch statorströmmen. Resultaten indikerar ett linjärt förhållande, men användandetav den digitala tvillingen för att beräkna proportionell konstant konstateras attinte vara tillräckligt noggrann metod.
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Meyer, Rüdiger Reinhard. "Quantitative Automated Object Wave Restoration in High-Resolution Electron Microscopy." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2002. http://nbn-resolving.de/urn:nbn:de:swb:14-1042118470265-98880.
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The main problem addressed by this dissertation is the accurate and automated determination of electron microscope imaging conditions. This enables the restoration of the object wave, which confers direct structural information about the specimen, from sets of differently aberrated images. An important member in the imaging chain is the image recording device, in many cases now a charge-coupled device (CCD) camera. Previous characterisations of these cameras often relied on the unjustified assumption that the Modulation Transfer Function (MTF) also correctly describes the spatial frequency dependent attenuation of the electron shot noise. A new theory is therefore presented that distinguishes between signal and noise transfer. This facilitates the evaluation of both properties using a detailed Monte-Carlo simulation model for the electron and photon scattering in the scintillator of the camera. Furthermore, methods for the accurate experimental determination of the signal and noise transfer functions are presented. In agreement with the Monte-Carlo simulations, experimental results for commercially available CCD cameras show that the signal transfer is significantly poorer than the noise transfer. The centrepiece of this dissertation is the development of new methods for determining the relative aberrations in a set of images and the absolute symmetric aberrations in the restored wave. Both are based on the analysis of the phase information in the Fourier domain and give each Fourier component a weight independent of its strength. This makes the method suitable even for largely crystalline samples with little amorphous contamination, where conventional methods, such as automated diffractogram fitting, usually fail. The method is then extended to also cover the antisymmetric aberrations, using combined beam tilt and focal series. The applicability of the new method is demonstrated with object wave restorations from tilt and focal series of complex inorganic block oxides and of carbon nanotubes filled with one-dimensional inorganic crystals. The latter specimens allowed for the first time a direct comparison between the phase shift in the restored object wave of a specimen with precisely known thickness and the value predicted by simulations.
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Silva, Humberto de Alencar Pizza da. "Protetor de redes inteligente e relé digital com tecnologia nacional integrando proteção, controle, telecomando e monitoramento viabilizando smart grid e geração distribuída a partir dos sistemas de distribuição subterrâneos nas grandes metrópoles." Universidade de São Paulo, 2011. http://www.teses.usp.br/teses/disponiveis/86/86131/tde-08062011-112922/.
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A importância das novas tecnologias de informação, automação, monitoramento e sistemas eletrônicos inteligentes têm aumentado significativamente nos últimos anos. Essas tecnologias desempenham um papel fundamental na sociedade moderna e contribuem de forma decisiva para a resolução de importantes desafios para uma sociedade que quer ser mais próspera, internacionalmente competitiva, saudável, segura e sustentável. Como eixo de \"inovação\", essas tecnologias são fatores importantes para todos os setores produtivos da economia. O motor destas tecnologias, entretanto, é a energia, particularmente a eletricidade. Assim, em uma sociedade cujo estilo de vida é fortemente dependente dela, desenvolver tecnologias que permitam não somente a geração, mas também a distribuição de energia de forma barata e limpa e que garantam seu fornecimento ao longo do tempo com a máxima eficiência é uma questão prioritária. Os sistemas baseados em redes inteligentes (do inglês: Smart Grid) vêm, justamente, atender a esses requisitos, representando o que há de mais moderno no setor elétrico, com aumento e diversificação de fontes de geração distribuída na forma de pequenos geradores, maior interação consumidor-distribuidor de energia, integração de diferentes fontes de geração renováveis (ex.: solar, eólica etc.). O cenário energético nacional está avançando de forma muito rápida. Nas distribuidoras, o foco claramente está na redução de perdas comerciais e de custos operacionais, principalmente por meio da modernização dos ativos e da crescente instalação de dispositivos eletrônicos inteligentes nos clientes de baixa tensão (ex.: medidores eletrônicos, dispositivos eletrônicos inteligentes para monitoramento e diagnóstico, relés digitais etc.). Esta tese de doutorado apresenta uma solução com tecnologia nacional que disponibiliza todos os benefícios do Smart Grid através dos equipamentos mais importantes e estratégicos presentes na topologia das Redes de Distribuição Subterrânea Secundária Trifásica: os Protetores de Redes. A partir do centro nevrálgico das Redes de Distribuição Subterrâneas (RDS), cuja topologia está presente nos centros de alta concentração de carga das principais metrópoles do Brasil, a solução desenvolvida pode viabilizar técnica e economicamente a modernização da automação da RDS, com tecnologia nacional de baixo custo, proporcionando igualmente a incorporação dos avanços do Smart Grid e da Geração Distribuída. Este salto tecnológico significaria para as distribuidoras de energia elétrica entre outros benefícios: Melhor controle do processo para uma melhor otimização da rede, desde integração das intermitentes fontes renováveis até uma interação mais dinâmica com os consumidores; Maior flexibilidade às concessionárias em relação ao uso da energia para atingir o grande objetivo social de redução do efeito estufa e otimização do consumo de energia reduzindo perdas e desperdícios; No curto prazo, os benefícios diretos da melhoria do gerenciamento da indisponibilidade, gerenciamento otimizado dos ativos e do capital, melhoria no planejamento, processos e serviços de fornecimento e usos finais de energia, aumento de eficiência de manutenção, redução de perdas técnicas e comerciais, otimização do investimento na compra de novos protetores com menores custos podendo superar a demanda reprimida pelos altos custos de alternativas importadas.The importance of new technologies in the field of, automation, monitoring, information technology and electronic systems have increased significantly in recent years. These technologies play a basic role in the modern society and contribute of decisive way for the resolution of important challenges for a society that is in search of a more prosperous life, internationally competitive, healthful, safe and sustainable. As a key of \"innovation\", these technologies are key factors for all the productive sectors of the economy in the society. The fuel for the engine of these technologies, however, is the energy, particularly the electricity. Thus, in a society whose life style is strongly dependent of electricity, to develop technologies that not only allow the generation, but also the distribution of energy in a cheap and clean way and which could guarantee its supply throughout the time with the maximum efficiency is a priority issue. The systems based on intelligent networks fully meet these requirements, representing what there is of most modern in the electric sector. The Brazilian energy scenario is quickly changing over the recent years toward modernization, with more distributed generation, in the form of smaller generators, more customer interaction, the integration of more variable resources such as wind and solar, and more renewables overall. For the Power Utilities, especially in the Distribution Sector, the focus is clearly in the reduction of commercial losses and operational costs, mainly by means of the modernization of the assets and an increase in the installation of intelligent electronic devices at consumers side (e.g.: electronic energy meters, intelligent electronic devices for condition monitoring, digital relays etc.). This work presents a solution developed based on Brazilian technology that incorporates all the benefits of smart grid to the most important equipment that is present in the topology of the Low-Voltage Secondary Network Distribution System: the Network Protector. From the neuralgic center of these Low-Voltage Secondary Network Systems, which topology is used in the most important cities in Brazil, which has a high load concentration, the solution presented here make it feasible technically and economically the use of smart grid topology profiting from its great benefits such as: Allow utilities to better optimize the grid to support a number of public policies, from intermittent renewable integration to more dynamic interfaces with customers; Offer utilities more flexibility relative to how they use energy toward the greater societal objectives of reducing greenhouse gases and energy consumption. In the short and mid term, a smarter grid offers utilities operational benefits (outage management, improved processes, maintenance and workforce efficiency, reduced losses, etc.) as well as benefits associated with improved asset management (system planning, better capital asset utilization, etc.), lower investment to acquire new Network Protectors.
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Leandro, Eduardo [UNESP]. "Um novo sistema de refrigeração com controle de temperatura, compressor aberto, máquina de indução trifásica com velocidade variável e correção ativa do fator de potência do estágio de entrada." Universidade Estadual Paulista (UNESP), 2006. http://hdl.handle.net/11449/87222.
Full textAbstract:
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Este trabalho apresenta uma nova proposta para sistema de refrigeração com controle dinâmico de temperatura, operando com estrutura de compressor aberto, acionado por motor de indução trifásico com velocidade variável, e estágio de entrada retificador com correção ativa do fator de potência. O estágio de entrada é composto por um retificador Boost monofásico com elevado fator de potência, com duas células entrelaçadas, operando no modo de condução crítica, empregando técnica de comutação não dissipativa e controlado por dispositivo FPGA, associado a um estágio de saída inversor de dois níveis convencional trifásico à IGBT, o qual é controlado por um Processador Digital de Sinais (DSP - Digital Signal Processor). A técnica de comutação não dissipativa para o estágio de entrada é baseada em células ZCS (Zero-current-switching). As principais características do retificador incluem a redução da ondulação da corrente de entrada, redução da ondulação da tensão de saída retificada, utilização de componentes com reduzidos esforços, reduzido volume do filtro de entrada para Interferências Eletromagnéticas (EMI - Electromagnetic Interference), elevado Fator de Potência (FP) e reduzida Distorção Harmônica Total (DHT) da corrente de entrada, atendendo os limites da norma IEC61000-3-2. O controle digital para o estágio de saída inversor foi desenvolvido usando duas diferentes técnicas, incluindo a técnica convencional controle escalar Volts/Hertz (V/Hz) e o controle Vetorial com Orientação pelo Fluxo do estator, com o propósito de verificar a aplicabilidade e a performance dos controles digitais propostos, para o controle contínuo da temperatura, aplicados a um protótipo de sistema de refrigeração.
This work presents a new proposal for refrigeration systems with dynamic control of temperature, working with structure of open compressor, driving a three-phase induction motor with variable speed, and input rectifier with active power factor correction. The proposed system is composed of a single-phase high-power-factor boost rectifier, with two cells in interleaved connection, operating in critical conduction mode, and employing a softswitching technique, controlled by a Field Programmable Gate Array (FPGA), associated with a conventional three-phase IGBT bridge inverter (VSI - Voltage Source Inverter), controlled by a Digital Signal Processor (DSP). The soft-switching technique for the input stage is based on zero-current-switching (ZCS) cells. The rectifier s features include reduction in input current ripple, reduction in output voltage ripple, use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller for the output stage inverter has been developed using two different techniques, the conventional Voltage-Frequency control (scalar V/Hz control), and a simplified stator oriented vector control, in order to verify the feasibility and performance of the proposed digital controls, for continuous temperature control, applied at a refrigerator prototype.
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Pellegrino, Gregory S. "Design of a Low-Cost Data Acquisition System for Rotordynamic Data Collection." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/1978.
Full textAbstract:
A data acquisition system (DAQ) was designed based on the use of a STM32 microcontroller. Its purpose is to provide a transparent and low-cost alternative to commercially available DAQs, providing educators a means to teach students about the process through which data are collected as well as the uses of collected data. The DAQ was designed to collect data from rotating machinery spinning at a speed up to 10,000 RPM and send this data to a computer through a USB 2.0 full-speed connection. Multitasking code was written for the DAQ to allow for data to be simultaneously collected and transferred over USB. Additionally, a console application was created to control the DAQ and read data, and MATLAB code written to analyze the data. The DAQ was compared against a custom assembled National Instruments CompactDAQ system. Using a Bentley-Nevada RK 4 Rotor Kit, data was simultaneously collected using both DAQs. Analysis of this data shows the capabilities and limitations of the low cost DAQ compared to the custom CompactDAQ.
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Leandro, Eduardo. "Um novo sistema de refrigeração com controle de temperatura, compressor aberto, máquina de indução trifásica com velocidade variável e correção ativa do fator de potência do estágio de entrada /." Ilha Solteira : [s.n.], 2006. http://hdl.handle.net/11449/87222.
Full textAbstract:
Resumo: Este trabalho apresenta uma nova proposta para sistema de refrigeração com controle dinâmico de temperatura, operando com estrutura de compressor aberto, acionado por motor de indução trifásico com velocidade variável, e estágio de entrada retificador com correção ativa do fator de potência. O estágio de entrada é composto por um retificador Boost monofásico com elevado fator de potência, com duas células entrelaçadas, operando no modo de condução crítica, empregando técnica de comutação não dissipativa e controlado por dispositivo FPGA, associado a um estágio de saída inversor de dois níveis convencional trifásico à IGBT, o qual é controlado por um Processador Digital de Sinais (DSP - Digital Signal Processor). A técnica de comutação não dissipativa para o estágio de entrada é baseada em células ZCS (Zero-current-switching). As principais características do retificador incluem a redução da ondulação da corrente de entrada, redução da ondulação da tensão de saída retificada, utilização de componentes com reduzidos esforços, reduzido volume do filtro de entrada para Interferências Eletromagnéticas (EMI - Electromagnetic Interference), elevado Fator de Potência (FP) e reduzida Distorção Harmônica Total (DHT) da corrente de entrada, atendendo os limites da norma IEC61000-3-2. O controle digital para o estágio de saída inversor foi desenvolvido usando duas diferentes técnicas, incluindo a técnica convencional controle escalar Volts/Hertz (V/Hz) e o controle Vetorial com Orientação pelo Fluxo do estator, com o propósito de verificar a aplicabilidade e a performance dos controles digitais propostos, para o controle contínuo da temperatura, aplicados a um protótipo de sistema de refrigeração.Abstract: This work presents a new proposal for refrigeration systems with dynamic control of temperature, working with structure of open compressor, driving a three-phase induction motor with variable speed, and input rectifier with active power factor correction. The proposed system is composed of a single-phase high-power-factor boost rectifier, with two cells in interleaved connection, operating in critical conduction mode, and employing a softswitching technique, controlled by a Field Programmable Gate Array (FPGA), associated with a conventional three-phase IGBT bridge inverter (VSI - Voltage Source Inverter), controlled by a Digital Signal Processor (DSP). The soft-switching technique for the input stage is based on zero-current-switching (ZCS) cells. The rectifiers features include reduction in input current ripple, reduction in output voltage ripple, use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller for the output stage inverter has been developed using two different techniques, the conventional Voltage-Frequency control (scalar V/Hz control), and a simplified stator oriented vector control, in order to verify the feasibility and performance of the proposed digital controls, for continuous temperature control, applied at a refrigerator prototype.
Orientador: Carlos Alberto Canesin
Coorientador: Flávio Alessandro Serrão Gonçalves
Banca: Fabio Toshiaki Wakabayashi
Banca: João Onofre Pereira Pinto
Mestre
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Jaume, Bennasar Andrés. "Las nuevas tecnologías en la administración de justicia. La validez y eficacia del documento electrónico en sede procesal." Doctoral thesis, Universitat de les Illes Balears, 2009. http://hdl.handle.net/10803/9415.
Full textAbstract:
La tesis se encarga de analizar, por un lado, la integración y el desarrollo de las nuevas tecnologías en la Administración de Justicia; y, por otro, los parámetros que constituyen la validez y eficacia del documento electrónico. La primera cuestión se centra en la configuración de los Sistemas de Información de la Oficina Judicial y del Ministerio Fiscal, así como de la informatización de los Registros Civiles, donde el art. 230 LOPJ es la pieza clave. Se estudian sus programas, aplicaciones, la videoconferencia, los ficheros judiciales y las redes de telecomunicaciones que poseen la cobertura de la firma electrónica reconocida, donde cobran gran relevancia los convenios de colaboración tecnológica. La digitalización de las vistas quizá sea una de las cuestiones con más trascendencia, teniendo en cuenta que el juicio es el acto que culmina el proceso. Aunque no todos los proyectos adoptados en el ámbito de la e.justicia se han desarrollado de forma integral, ni han llegado a la totalidad de los órganos judiciales. El objetivo final es lograr una Justicia más ágil y de calidad, a lo cual aspira el Plan Estratégico de Modernización de la Justicia 2009-2012 aprobado recientemente.
En referencia a la segunda perspectiva, no cabe duda que el Ordenamiento jurídico y los tribunales, en el ámbito de la justicia material, otorgan plena validez y eficacia al documento electrónico. Nuestra línea de investigación se justifica porque cada vez son más los procesos que incorporan soportes electrónicos de todo tipo, ya sea al plantearse la acción o posteriormente como medio de prueba (art. 299.2 LEC). Entre otros temas examinamos el documento informático, la problemática que rodea al fax, los sistemas de videograbación y el contrato electrónico.
La tesi s'encarrega d'analitzar, per una part, la integració i el desenvolupament de les noves tecnologies dins l´Administració de Justícia; i, per l'altra, els paràmetres que constitueixen la validesa i l'eficàcia del document electrònic.
La primera qüestió es centra en la configuració dels Sistemes d´Informació de l´Oficina Judicial i del Ministeri Fiscal, així com de la informatització dels Registres Civils, on l'art. 230 LOPJ es la peça clau. S'estudien els seus programes, aplicacions, la videoconferència, el fitxers judicials i les xarxes de telecomunicacions que tenen la cobertura de la firma electrònica reconeguda, on cobren gran rellevància els convenis de col·laboració tecnològica. La digitalització de les vistes tal vegada sigui una de les qüestions amb més transcendència, tenint amb compte que el judici es l'acte que culmina el procés. Però no tots el projectes adoptats en l'àmbit de la e.justicia s'han desenvolupat d'una manera integral ni han arribat a la totalitat dels òrgans judicials. L'objectiu final es assolir una Justícia més àgil i de qualitat, al que aspira el Pla Estratègic de Modernització de la Justícia 2009-2012 aprovat recentment.
En referència a la segona perspectiva, no hi ha dubte que l´Ordenament jurídic i els tribunals, en l'àmbit de la justícia material, donen plena validesa i eficàcia al document electrònic. La nostra línia d'investigació es justifica perquè cada vegada son més el processos que incorporen suports electrònics de tot tipus, ja sigui quant es planteja l'acció o posteriorment como a medi de prova (art. 299.2 LEC). Entre altres temes examinem el document informàtic, la problemàtica que envolta al fax, els sistemes de videogravació i el contracte electrònic.
The thesis seeks to analyse, on the one hand, the integration and development of the new technologies in the Administration of Justice; and, on the other, the parameters which constitute the validity and efficiency of the electronic document.
The first question centres on the configuration of the Information Systems of the Judicial Office and the Public Prosecutor, as well as the computerisation of the Civil Registers, where the art. 230 LOPJ it's the part key. Their programmes, applications, the Video Conferencing, the judicial registers and the telecommunication networks which are covered by the recognised electronic signatures, are studied, where the agreements on technological collaboration gain great relevance. The digitalisation of evidence might perhaps be one of the questions with most consequence, bearing in mind that the judgment is the act by which the process is culminated. Although not all the projects adopted within the compass of e.justice have developed completely nor have reached all the judicial organs. The final objective is to achieve an agile, quality Justice, to which the recently approved Strategic Plan for the Modernisation of Justice aspires.
With reference to the second perspective, there is no doubt that the juridical Ordinance and the tribunals within the compass of material justice grant full validity and efficacy to the electronic document. Our line of investigation is justified because there are more and more processes which are sustained by electronic supports of all kinds, whether it be at the establishment of the action or later, as a proof of it (art. 299.2 LEC). Amongst other things, we examine the computerised document, the problems which surround the fax, the systems for video recording and the electronic contract.
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Ching-ChangChen and 陳慶昌. "Design and Implementation of Optical Image Stabilizer and Keystone Corrector for Digital Consumer Electronic Devices." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/69275054539970001027.
Full textAbstract:
博士國立成功大學
電機工程學系碩博士班
101
This dissertation discusses the digital consumer electronic devices, and presents the sensor-shift optical image stabilizer (OIS) system and the automatic keystone correction (AKC) system. In general, the precise estimation of the hand-shake vibration and controller performance are the most crucial factors of the stabilization performance. This dissertation proposes a frequency adaptive OIS (FAOIS) system which utilizes a fuzzy sliding-mode controller (FSMC) to compensate the nonlinearities of voice coil motor (VCM) and stabilize the dual-axis OIS module. The FSMC does have good robustness while the system has large gravity fluctuation in vertical axis. An extended Kalman filter (EKF) is designed to estimate the tremor frequency in real-time and tune the hand-shake detector online. A fuzzy EKF (FEKF) is used to improve the settling-time of the EKF-based hand-shake detector. The bandwidth of the OIS system with time-varying hand tremor is expended by improving the phase-shift phenomenon and the settling-time of the hand-shake detector. Furthermore, the AKC system adopts the projector-camera pair to provide a visual feedback for monitoring the keystone distortion, a feature extractor and an inclination classifier to determine the projection inclination between the projector and the projection screen, and a pre-warping process to compensate the keystone distortion, caused by non-normal projection poses. Finally, the stabilization performance and frequency adaption of the FAOIS are illustrated by OIS experiments with time-varying hand tremor. All the mobile projection experiments demonstrate that z-axis rotation does not affect the proposed AKC system.
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Lin, Shih-Che, and 林士哲. "Fundamental System Frequency Detection and Flicker Analysis Mechanism for Intelligent Electronic Devices and Digital Protection Relays." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/14445518048256812265.
Full textAbstract:
碩士國立中正大學
電機工程研究所
101
With the widespread use of nonlinear loads in the power system, pollutions of power quality have become serious. Besides, the power unbalance between the generation and the load demand would make the fundamental frequency varying with time. These disturbances may introduce operational problems of power system equipment. When a fault occurs, the protection relay will be fast operated. Then, the protection relays will isolate the faulted zone to reduce the extent of damage to the equipment so that the power system remains stable and protects the safety of the system and staff. Protection relays need to rely on accurate measurement of basic parameters. Therefore, the protection relays will make the most appropriate decisions. These parameters include voltage, current, and fundamental frequency. Many controls and protections of the power system need to have accurate measurements of the fundamental frequency, which is one of the most important index in power quality and protection relays. For quick measuring fundamental frequency of system and study the influence of power quality on the performance of protection relays, this thesis proposes a mechanism which is applied for fundamental frequency measurement and flicker analysis in intelligent electronic devices (IED) or digital protection relays. In this thesis, the flickermeter combines with frequency tracking methods in which the flickermeter is based on IEC (International Electrotechnical Committee) standard 61000-4-15. Therefore, the mechanism not only evaluates the flicker severity in voltage signal but also detects fundamental frequency. Finally, this mechanism is written into DSP F2812 and an arbitrary waveform generator is used to produce actual signals as inputs to LabVIEW and DSP F2812 to verify the mechanism’s effectiveness and usefulness.
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(6630425), Mounica Patnala. "HIGH PERFORMANCE GNRFET DEVICES FOR HIGH-SPEED LOW-POWER ANALOG AND DIGITAL APPLICATIONS." Thesis, 2019.
Find full textAbstract:
Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followedsuccessfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices offered alternative approach, featuring small size
and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the
Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed
signals based systems.
Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices
for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation.
GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design
Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power
amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as
low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW.
Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power
amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as
low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW.
These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic
Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and
digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.
Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and
digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.
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Narayana, T. Badiri. "Shaped Superconducting Films For Electronic Functions." Thesis, 1997. http://etd.iisc.ernet.in/handle/2005/1815.
Full text
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Mohan, Anand. "A reconfigurable high speed analog to digital converter architecture for ultra wideband devices." Thesis, 2010. https://vuir.vu.edu.au/15996/.
Full textAbstract:
In a world where wires still dominate high speed low power data communication, Ultra Wideband (UWB) medium has the potential to revolutionise wireless data transmission and reception. A core component of any communications device is its ability to convert real time analog signals to discrete values for fast and efficient processing. This gate that links the digital backend with the analogue front end in is the Analogue to Digital Converter.
This thesis presents the design and implementation of two unique high speed analog to digital converters for Ultra Wideband radio. The first design is a custom fully differential Flash based analogue to digital converter with a finite output resolution of 4 bits and an effective sampling rate of 5 Gsps. The second design implemented is a novel fully differential reconfigurable analog to digital converter.
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"Hardware emulation board based on field programmable gate arrays (FPGAs) and programmable interconnections." Chinese University of Hong Kong, 1994. http://library.cuhk.edu.hk/record=b5888211.
Full textAbstract:
by Lo Wing-yee.Thesis (M.Phil.)--Chinese University of Hong Kong, 1994.
Includes bibliographical references (leaves vii-ix).
ABSTRACT --- p.i
LIST OF TABLES --- p.iv
LIST OF FIGURES --- p.v
Chapter 1. --- INTRODUCTION --- p.1
Chapter 1.1 --- Traditional Design Prototyping --- p.1
Chapter 1.2 --- In-Circuit Rapid Prototyping System --- p.2
Chapter 1.3 --- A Summary of Prototyping Systems Available --- p.5
Chapter 1.4 --- Universal Prototyping Board (UPB) --- p.6
Chapter 2. --- HARDWARE DESIGNS --- p.9
Chapter 2.1 --- Bus Interconnection --- p.9
Chapter 2.1.1 --- Fixed buses --- p.9
Chapter 2.1.2 --- Programmable buses --- p.12
Chapter 2.2 --- Architectural Features --- p.15
Chapter 2.2.1 --- Field programmable gate array --- p.15
Chapter 2.2.2 --- Microprocessor --- p.15
Chapter 2.2.3 --- Memory --- p.16
Chapter 2.2.4 --- Buffers --- p.18
Chapter 3. --- SOFTWARE TOOLS --- p.20
Chapter 3.1 --- Critical Path Analysis --- p.20
Chapter 3.1.1 --- Algorithm of critical path analysis --- p.21
Chapter 3.1.2 --- Computation time --- p.21
Chapter 3.2 --- Circuit Partitioning --- p.23
Chapter 3.2.1 --- Partitioning algorithm --- p.24
Chapter 3.2.2 --- Effects of partitioning --- p.36
Chapter 3.2.3 --- Partitioning parameters --- p.38
Chapter 3.2.4 --- Pseudo-code of partitioner --- p.39
Chapter 3.3 --- IO Assignments --- p.40
Chapter 3.3.1 --- Connect 4 FPGAs --- p.40
Chapter 3.3.2 --- Connect 3 FPGAs --- p.42
Chapter 3.3.3 --- Connect 2 FPGAs --- p.44
Chapter 3.3.4 --- System IO (Connect 1 FPGA) --- p.47
Chapter 3.4 --- Other Tools --- p.48
Chapter 4. --- STRUCTURE ANALYSIS --- p.49
Chapter 5. --- RESULTS --- p.52
Chapter 6. --- FUTURE DIRECTION --- p.73
Chapter 6.1 --- Other Possible Configurations --- p.73
Chapter 6.2 --- Programmable Interconnection --- p.73
Chapter 6.3 --- Expandability of UPB --- p.74
Chapter 7. --- CONCLUSION --- p.75
BIBLIOGRAPHY --- p.vii
APPENDICES --- p.x
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(9356939), Jui-wei Tsai. "Digital Signal Processing Architecture Design for Closed-Loop Electrical Nerve Stimulation Systems." Thesis, 2020.
Find full textAbstract:
Electrical nerve stimulation (ENS) is an emerging therapy for many neurological disorders. Compared with conventional one-way stimulations, closed-loop ENS approaches increase the stimulation efficacy and minimize patient's discomfort by constantly adjusting the stimulation parameters according to the feedback biomarkers from patients. Wireless neurostimulation devices capable of both stimulation and telemetry of recorded physiological signals are welcome for closed-loop ENS systems to improve the quality and reduce the costs of treatments, and real-time digital signal processing (DSP) engines processing and extracting features from recorded signals can reduce the data transmission rate and the resulting power consumption of wireless devices. Electrically-evoked compound action potential (ECAP) is an objective measure of nerve activity and has been used as the feedback biomarker in closed-loop ENS systems including neural response telemetry (NRT) systems and a newly proposed autonomous nerve control (ANC) platform. It's desirable to design a DSP engine for real-time processing of ECAP in closed-loop ENS systems.
This thesis focuses on developing the DSP architecture for real-time processing of ECAP, including stimulus artifact rejection (SAR), denoising, and extraction of nerve fiber responses as biomedical features, and its VLSI implementation for optimal hardware costs. The first part presents the DSP architecture for real-time SAR and denoising of ECAP in NRT systems. A bidirectional-filtered coherent averaging (BFCA) method is proposed, which enables the configurable linear-phase filter to be realized hardware efficiently for distortion-free filtering of ECAPs and can be easily combined with the alternating-polarity (AP) stimulation method for SAR. Design techniques including folded-IIR filter and division-free averaging are incorporated to reduce the computation cost. The second part presents the fiber-response extraction engine (FREE), a dedicated DSP engine for nerve activation control in the ANC platform. FREE employs the DSP architecture of the BFCA method combined with the AP stimulation, and the architecture of computationally efficient peak detection and classification algorithms for fiber response extraction from ECAP. FREE is mapped onto a custom-made and battery-powered wearable wireless device incorporating a low-power FPGA, a Bluetooth transceiver, a stimulation and recording analog front-end and a power-management unit. In comparison with previous software-based signal processing, FREE not only reduces the data rate of wireless devices but also improves the precision of fiber response classification in noisy environments, which contributes to the construction of high-accuracy nerve activation profile in the ANC platform. An application-specific integrated circuit (ASIC) version of FREE is implemented in 180-nm CMOS technology, with total chip area and core power consumption of 19.98 mm2 and 1.95 mW, respectively.
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Shi, Jiajun. "Architecting NP-Dynamic Skybridge." 2015. https://scholarworks.umass.edu/masters_theses_2/171.
Full textAbstract:
With the scaling of technology nodes, modern CMOS integrated circuits face severe fundamental challenges that stem from device scaling limitations, interconnection bottlenecks and increasing manufacturing complexities. These challenges drive researchers to look for revolutionary technologies beyond the end of CMOS roadmap. Towards this end, a new nanoscale 3-D computing fabric for future integrated circuits, Skybridge, has been proposed [1]. In this new fabric, core aspects from device to circuit style, connectivity, thermal management and manufacturing pathway are co-architected in a 3-D fabric-centric manner.
However, the Skybridge fabric uses only n-type transistors in a dynamic circuit style for logic and memory implementations. Therefore, it requires complicated clocking schemes to overcome signal monotonicity associated with cascading dynamic logic gates. For Skybridge’s large-scale circuits, the dynamic circuit style requires cascaded stages to be micro-pipelined, which results in large number of buffers used for storing minterms causing significant overhead in terms of area and power. Moreover, implementation of logic is limited to NAND or AND-of-NAND based logic expressions, which does not always result in compact circuits. In this work, we propose an extension of original Skybridge fabric, called NP-Dynamic-Skybridge, to solve these challenges by using both n-and p-type transistors in an innovative circuit style. Here, every stage in a given circuit is implemented by either n-type or p-type dynamic logic.
Cascading n- and p-type dynamic logic effectively avoids signal monotonicity problem, and allows combinational-like circuit implementation. This helps to simplify the clocking scheme for cascaded logics requiring only one set of global precharge and evaluate clock signals. And also it expands the degree of expressing logic enabling expressions such as NOR, OR-of-NORs, in addition to those previously mentioned. Furthermore, the number of pipeline stages is significantly reduced for a given logic function, and buffer requirements are less compared with Skybridge 3D fabric thus improving on area and power metrics. Initial evaluation for NP-Dynamic-Skybridge’s 4-bit carry look-ahead adder shows up to 2x density benefits over Skybridge 3-D fabric and at least 17% power/throughput benefit.
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Wickremasuriya, Boosabaduge Achintha Hiruwan. "Development of a laboratory facility and experiments to support learning IEC 61850 based substation automation." 2016. http://hdl.handle.net/1993/30992.
Full textAbstract:
IEC 61850 is rapidly becoming the internationally recognized standard for substation automation systems making it an indispensable element in power system protection and automation education. In order to facilitate teaching this very practical subject, a laboratory setup was developed to demonstrate IEC 61850 station bus inter Intelligent Electronic Device (IED) communication. In this setup, an electrical substation was implemented in a real time digital simulator (RTDS) and protection schemes were implemented in IEC 61850 station bus compliant IEDs from different vendors. Trip signals and breaker statuses were exchanged between RTDS and IEDs using GOOSE (Generic Object Oriented Substation Event) messages. Several protection applications including a novel backup bus protection scheme were developed based on the setup to demonstrate the use of GOOSE messages in time critical applications. The developed test setup along with the designed laboratory exercises will undoubtedly enhance teaching, training and research in this important field.February 2016