Journal articles: 'Digital converters'

1

Borgmans, Jonas, and Pieter Rombouts. "Toward ‘digital’ analogue‐to‐digital converters." Electronics Letters 55, no. 10 (May 2019): 568–69. http://dx.doi.org/10.1049/el.2019.1269.

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Skup, Konrad, Paweł Grudziński, and Piotr Orleański. "Application of Digital Control Techniques for Satellite Medium Power DC-DC Converters." International Journal of Electronics and Telecommunications 57, no. 1 (March 1, 2011): 77–83. http://dx.doi.org/10.2478/v10177-011-0011-1.

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Application of Digital Control Techniques for Satellite Medium Power DC-DC Converters The objective of this paper is to present a work concerning a digital control loop system for satellite medium power DC-DC converters that is done in Space Research Centre. The whole control process of a described power converter is based on a high speed digital signal processing. The paper presents a development of a FPGA digital controller for voltage and current mode stabilization that was implemented using VHDL. The described controllers are based on a classical digital PID controller. The converter used for testing is a 200 kHz, 750W buck converter with 50V/15A output. A high resolution digital PWM approach is presented. Additionally a simple and effective solution of filtering of an analog-to-digital converter output is presented.

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Bin Le, T. W. Rondeau, J. H. Reed, and C. W. Bostian. "Analog-to-digital converters." IEEE Signal Processing Magazine 22, no. 6 (November 2005): 69–77. http://dx.doi.org/10.1109/msp.2005.1550190.

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Malev, N. A., O. V. Pogoditsky, O. V. Kozelkov, and A. S. Malacion. "Digital algorithm monitoring functioning of electromechanical dc converter." Power engineering: research, equipment, technology 24, no. 1 (May 24, 2022): 126–40. http://dx.doi.org/10.30724/1998-9903-2022-24-1-126-140.

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The parameters of electromechanical converters functioning as part of working sets can change as a result of the influence externa factors, such as changes in the characteristics of the environment. Changes in parameters also occur due to parametric disturbances caused by changes in the physical characteristics of the elements electromechanical converters. In this regard, the development of methods and algorithms that provide analysis and control of the functioning electromechanical converters is an urgent task. The article discusses a digital algorithm for monitoring the functioning of an electromechanical DC converter, based on obtaining characteristics in a tabular-graphic form. These characteristics reflect the relationship between the vector of unstable parameters of the research object χ and the generalized integral criterion Q as a function of the discrepancy between the output coordinates of the electromechanical converter and its reference model. Discrete transfer functions of the reference model and sensitivity models are obtained for the monitored unstable parameters of the electromechanical converter. Based on the decomposition of discrete models, the corresponding direct programming schemes in the Frobenius form are constructed. The digital algorithms of the obtained models are represented by the difference equations of state and output. The structural scheme calculation of the generalized integral criterion Q and point dependencies χ (Q) is given. Discrete approximation was carried out using a bilinear transformation (Tustin's formula). A computer experiment for obtaining point χ-dependencies was carried out with varying degrees of accuracy, depending on the step of variations monitored parameters of the electromechanical converter within a given range of variation. The results obtained make it possible to assess the monitored unstable parameters of electromechanical DC converters with the required accuracy.

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Kroics, Kaspars. "Digital Control of Variable Frequency Interleaved DC-DC Converter." Environment. Technology. Resources. Proceedings of the International Scientific and Practical Conference 2 (August 8, 2015): 124. http://dx.doi.org/10.17770/etr2013vol2.854.

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This paper represents a design and implementation of a digital control of variable frequency interleaved DC-DC converter using a digital signal processor (DSP). The digital PWM generation, current and voltage sensing, user interface and the new period and pulse width value calculation with DSP STM32F407VGT6 are considered. Typically, the multiphase interleaved DC - DC converters require a current control loop in each phase to avoid imbalanced current between phases. This increases system costs and control complexity. In this paper the converter which operates in discontinuous conduction mode is designed in order to reduce costs and remove the current control loop in each phase. High current ripples associated with this mode operation are then alleviated by interleaving. Pulse width modulation (PWM) is one of the most conventional modulation techniques for switching DC - DC converters. It compares the error signal with the sawtooth wave to generate the control pulse. This paper shows how six PWM signals phase-shifted by 60 degrees can be generated from calculated values. To ensure that the measured values do not contain disturbances and in order to improve the system stability the digital signal is filtered. The analog to digital converter's (ADC) sampling time must not coincide with the power transistor's switching time, therefore the sampling time must be calculated correctly as well. Digital control of the DC-DC converter makes it easy and quickly to configure. It is possible for this device to communicate with other devices in a simple way, to realize data input by using buttons and keyboard, and to display information on LED, LCD displays, etc.

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Hazell, Philippa, Peter Mather, Andrew Longstaff, and Simon Fletcher. "Digital System Performance Enhancement of a Tent Map-Based ADC for Monitoring Photovoltaic Systems." Electronics 9, no. 9 (September 22, 2020): 1554. http://dx.doi.org/10.3390/electronics9091554.

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Efficient photovoltaic installations require control systems that detect small signal variations over large measurement ranges. High measurement accuracy requires data acquisition systems with high-resolution analogue-to-digital converters; however, high resolutions and operational speeds generally increase costs. Research has proven low-cost prototyping of non-linear chaotic Tent Map-based analogue-to-digital converters (which fold and amplify the input signal, emphasizing small signal variations) is feasible, but inherent non-ideal Tent Map gains reduce the output accuracy and restrict adoption within data acquisition systems. This paper demonstrates a novel compensation algorithm, developed as a digital electronic system, for non-ideal Tent Map gain, enabling high accuracy estimation of the analogue-to-digital converter analogue input signal. Approximation of the gain difference compensation values (reducing digital hardware requirements, enabling efficient real-time compensation), were also investigated via simulation. The algorithm improved the effective resolution of a 16, 20 and 24 Tent Map-stage analogue-to-digital converter model from an average of 5 to 15.5, 19.2, and 23 bits, respectively, over the Tent Map gain range of 1.9 to 1.99. The simulated digital compensation system for a seven Tent Map-stage analogue-to-digital converter enhanced the accuracy from 4 to 7 bits, confirming real-time compensation for non-ideal gain in Tent Map-based analogue-to-digital converters was achievable.

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Wawryn, K., and R. Suszynski. "Low power 9-bit pipelined A/D and 8-bit self-calibrated D/A converters for a DSP system." Bulletin of the Polish Academy of Sciences: Technical Sciences 61, no. 4 (December 1, 2013): 979–88. http://dx.doi.org/10.2478/bpasts-2013-0105.

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Abstract A low power, low voltage current mode 9 bit pipelined a/d converter and 8 bit self-calibrated d/a converter to interface a DSP system are presented in the paper. The a/d converter is built of 1.5 bit stages with digital error correction logic. The d/a converter is composed of 3 LSBs fine and 5 MSBs coarse current mode converters. The a/d and d/a converters were designed in 0.35 μm technology, then fabricated to verify the proposed concept. The performances of both converters are compared to the performances of known converter structures. The main advantages of the proposed converters are low power consumption and small chip area.

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Eguchi, Kei, Ya Nan Zhang, Shinya Terada, and Ichirou Oota. "A Symmetrical Digital Selecting Type DC-DC Converter with Power Saving Techniques." Applied Mechanics and Materials 666 (October 2014): 77–81. http://dx.doi.org/10.4028/www.scientific.net/amm.666.77.

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To achieve various conversion ratios with high power efficiency, a symmetrical digital selecting type switched-capacitor (SC) DC-DC converter with power saving techniques is proposed in this paper. Unlike conventional SC DC-DC converters, the voltage ratio of capacitors is expressed as the ratio of a power of two. By combining some of these capacitors in series, the proposed converter can achieve a larger number of conversion ratios than conventional converters. Furthermore, by employing a symmetrical structure with power saving techniques, the proposed converter can alleviate energy loss due to stray parasitic capacitance. The theoretical analysis and SPICE simulations show the effectiveness of the proposed converter.

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Suszynski, R., and K. Wawryn. "Rapid prototyping of algorithmic A/D converters based on FPAA devices." Bulletin of the Polish Academy of Sciences: Technical Sciences 61, no. 3 (September 1, 2013): 691–96. http://dx.doi.org/10.2478/bpasts-2013-0073.

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Abstract A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of the field programmable analog array (FPAA) to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. Three converter architectures have been selected and implemented FPAA device. To verify and illustrate converters operation and prototyping capabilities, implemented converters have been excited by a sinusoidal signal. Analog sinusoidal excitations, digital responses and sinusoidal waveforms after reconstruction are presented.

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Bojja Venkatakrishnan, Satheesh, Elias A. Alwan, and John L. Volakis. "Challenges in Clock Synchronization for On-Site Coding Digital Beamformer." International Journal of Reconfigurable Computing 2017 (2017): 1–8. http://dx.doi.org/10.1155/2017/7802735.

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Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.

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Chulkov, V. A. "Interpolating time-to-digital converters." Optoelectronics, Instrumentation and Data Processing 44, no. 6 (December 2008): 567–75. http://dx.doi.org/10.3103/s8756699008060125.

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12

Valley, George C. "Photonic analog-to-digital converters." Optics Express 15, no. 5 (2007): 1955. http://dx.doi.org/10.1364/oe.15.001955.

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Mukhanov, O. A., D. Gupta, A. M. Kadin, and V. K. Semenov. "Superconductor analog-to-digital converters." Proceedings of the IEEE 92, no. 10 (October 2004): 1564–84. http://dx.doi.org/10.1109/jproc.2004.833660.

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14

Pilotto, L. A. S., M. Roitman, and J. E. R. Alves. "Digital Control of HVDC Converters." IEEE Power Engineering Review 9, no. 5 (May 1989): 68. http://dx.doi.org/10.1109/mper.1989.4310712.

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15

Paramonov, V. S., S. N. Ryndov, G. A. Solov'ev, and G. M. Shmulevich. "Calibrating CAMAC analog-digital converters." Measurement Techniques 34, no. 11 (November 1991): 1097–99. http://dx.doi.org/10.1007/bf00979677.

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Pilotto, L. A. S., M. Roitman, and J. E. R. Alves. "Digital control of HVDC converters." IEEE Transactions on Power Systems 4, no. 2 (May 1989): 704–11. http://dx.doi.org/10.1109/59.193846.

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17

Gusel'nikov, V. G. "Digital converters of physical quantities." Measurement Techniques 29, no. 10 (October 1986): 978–79. http://dx.doi.org/10.1007/bf00862460.

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Hashemifar, Seyed Mohammad. "Design of a Single-Core Digital-to-Analog Converter with Ultra-Wideband and Low Power Consumption for CUWB-IR Applications." Tehnički glasnik 16, no. 3 (June 23, 2022): 311–14. http://dx.doi.org/10.31803/tg-20220405104325.

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Data converters are intermediate circuits used to connect between two analog and digital ranges. Data converters are not only used for converting audio into a microphone or speaker, but also for converting audio into a camera or display, transferring information to a computer or digital signal processor. At these times, the need for data converters is not invested in every aspect of life. Digital to analog converters is a leading part of these converters, which are widely used in most audio and video circuits. In this thesis, we have proposed a 4-bit 1GS/s DAC for CUWB-IR usage. To enhance the above performance with superior speed and the need for linearity, every significant block containing the convenient sources, current switches, and deglitcher were designed optimally and a new DAC converter circuit was developed which improves the linearity. The designed DAC was performed using a commercial 130 nm CMOS process. DAC INL/DNL≤0.22LSB features more than high Nyquist bandwidth at extremely low power losses of 0.45 mW. The proposed DAC achieves the best FoMs at the right time for advanced DACs

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Gbolagade, Kazeem Alagbe. "New Adder-Based RNS-to-Binary Converters for the Moduli Set." ISRN Signal Processing 2011 (June 29, 2011): 1–7. http://dx.doi.org/10.5402/2011/272768.

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We investigate Residue Number System (RNS) to binary conversion, which is an important issue concerning the utilization of RNS numbers in Digital Signal Processing (DSP) applications. We propose two new reverse converters for the moduli set . First, we simplify the Chinese Remainder Theorem (CRT) to obtain a reverse converter that uses mod- operations instead of mod- operations required by other state-of-the-art equivalent converters. Next, we further reduce the hardware complexity by making the resulting reverse converter architecture adder based. Two hybrid Cost-Efficient (CE) and Speed-Efficient (SE) reverse converters are proposed. These two hybrid converters are obtained by combining the best state-of-the-art converter with the newly introduced area-delay efficient scheme. The proposed hybrid CE converter outperforms the best state-of-the-art CE converter in terms of delay with similar area cost. Additionally, the proposed hybrid SE converter requires less area cost with smaller delay when compared to the best state-of-the-art equivalent SE converter.

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Saeidiyan, Zeinab, Mohammad Hosein Fatehi, Mehdi Taghizadeh, and Mohammad Mehdi Ghanbarian. "Enhancing the Accuracy and Speed of Sampling in Image Sensors by Designing Analog to Digital Converter with Power Decrease Approach." Journal of Sensors 2022 (January 24, 2022): 1–16. http://dx.doi.org/10.1155/2022/5075823.

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Analog to digital converters (ADCs) enable the processing of real-world analog signals in the digital realm. These converters are widely used in sensor systems, medical components, multimedia systems, image sensors, and wireless sensor nodes. Today, in portable devices that are powered by batteries, low power consumption and small area are a major and important need. Therefore, methods that can reduce power consumption and area have a variety of applications and are of great importance. Power consumption is one of the most important features of an integrated analog to digital converter. In this paper, a new design of low-power and fast analog to digital converter is presented. This design is used for specific applications for image processing. The suggested approach for rereading the image for limited number of pixels was designed and simulated, showing a considerable power decrease compared to the suggested state that depends on the pixel values.

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Pratte, Jean-François, Frédéric Nolet, Samuel Parent, Frédéric Vachon, Nicolas Roy, Tommy Rossignol, Keven Deslandes, Henri Dautet, Réjean Fontaine, and Serge A. Charlebois. "3D Photon-To-Digital Converter for Radiation Instrumentation: Motivation and Future Works." Sensors 21, no. 2 (January 16, 2021): 598. http://dx.doi.org/10.3390/s21020598.

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Analog and digital SiPMs have revolutionized the field of radiation instrumentation by replacing both avalanche photodiodes and photomultiplier tubes in many applications. However, multiple applications require greater performance than the current SiPMs are capable of, for example timing resolution for time-of-flight positron emission tomography and time-of-flight computed tomography, and mitigation of the large output capacitance of SiPM array for large-scale time projection chambers for liquid argon and liquid xenon experiments. In this contribution, the case will be made that 3D photon-to-digital converters, also known as 3D digital SiPMs, have a potentially superior performance over analog and 2D digital SiPMs. A review of 3D photon-to-digital converters is presented along with various applications where they can make a difference, such as time-of-flight medical imaging systems and low-background experiments in noble liquids. Finally, a review of the key design choices that must be made to obtain an optimized 3D photon-to-digital converter for radiation instrumentation, more specifically the single-photon avalanche diode array, the CMOS technology, the quenching circuit, the time-to-digital converter, the digital signal processing and the system level integration, are discussed in detail.

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Chang, Changyuan, and Jidong Liu. "Design of Dual-Sampling and Adaptive Predictive PID Controller for Buck DC–DC Converters." Journal of Circuits, Systems and Computers 28, no. 11 (October 2019): 1950195. http://dx.doi.org/10.1142/s0218126619501950.

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In this paper, based on the combination scheme of dual-sampling and adaptive predictive PID control, a digital controller for improving the transient performance of Buck DC–DC converters is designed. Due to the inherent loop delay in analog-to-digital (A/D) conversion, the calculation process of the digital controller and digital pulse width modulator (DPWM) of conventional digitally-controlled Buck DC–DC converters limits the system bandwidth and this makes the transient response lower. The designed digital controller can reduce the delay time in analog-to-digital converter (ADC), the digital controller and DPWM of digitally-controlled Buck DC–DC converters. Adaptive predictive control is used to eliminate the delay time of ADC and the digital controller, while dual-sampling scheme is used to reduce the delay time of DPWM in this paper. These are two new control schemes, and they show better performance in improving the transient response than other existing control schemes. Both simulation and experimental results demonstrate that the designed digital controller based on dual-sampling and adaptive predictive PID control is effective in improving the transient performance of Buck DC–DC converters. During experimental verification, for a load step between 0.5[Formula: see text]A and 1.0[Formula: see text]A, the fastest transient recovery time and the overshoot voltage are found to be 102[Formula: see text][Formula: see text]s and 120[Formula: see text]mV, respectively. Compared with the conventional digital PID controller, the transient recovery time and the overshoot voltage of the digital controller designed in this paper are decreased by 40.0% and 27.3%, respectively.

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Jovanović, Jelena, and Dragan Denić. "A Cost-effective Method for Resolution Increase of the Twostage Piecewise Linear ADC Used for Sensor Linearization." Measurement Science Review 16, no. 1 (February 1, 2016): 28–34. http://dx.doi.org/10.1515/msr-2016-0005.

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Abstract A cost-effective method for resolution increase of a two-stage piecewise linear analog-to-digital converter used for sensor linearization is proposed in this paper. In both conversion stages flash analog-to-digital converters are employed. Resolution increase by one bit per conversion stage is performed by introducing one additional comparator in front of each of two flash analog-to-digital converters, while the converters’ resolutions remain the same. As a result, the number of employed comparators, as well as the circuit complexity and the power consumption originating from employed comparators are for almost 50 % lower in comparison to the same parameters referring to the linearization circuit of the conventional design and of the same resolution. Since the number of employed comparators is significantly reduced according to the proposed method, special modifications of the linearization circuit are needed in order to properly adjust reference voltages of employed comparators.

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Yadav, Nandakishor, Youngbae Kim, Mahmoud Alashi, and Kyuwon Ken Choi. "Sensitive, Linear, Robust Current-To-Time Converter Circuit for Vehicle Automation Application." Electronics 9, no. 3 (March 16, 2020): 490. http://dx.doi.org/10.3390/electronics9030490.

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Voltage-to-time and current-to-time converters have been used in many recent works as a voltage-to-digital converter for artificial intelligence applications. In general, most of the previous designs use the current-starved technique or a capacitor-based delay unit, which is non-linear, expensive, and requires a large area. In this paper, we propose a highly linear current-to-digital converter. An optimization method is also proposed to generate the optimal converter design containing the smallest number of PMOS and sensitive circuits such as a differential amplifier. This enabled our design to be more stable and robust toward negative bias temperature instability (NBTI) and process variation. The proposed converter circuit implements the point-wise conversion from current-to-time, and it can be used directly for a variety of applications, such as analog-to-digital converters (ADC), used in built-in computational random access (C-RAM) memory. The conversion gain of the proposed circuit is 3.86 ms/A, which is 52 times greater than the conversion gains of state-of-the-art designs. Further, various time-to-digital converter (TDC) circuits are reviewed for the proposed current-to-time converter, and we recommend one circuit for a complete ADC design.

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Mukhanov, O. A., and S. V. Rylov. "Time-to-digital converters based on RSFQ digital counters." IEEE Transactions on Appiled Superconductivity 7, no. 2 (June 1997): 2669–72. http://dx.doi.org/10.1109/77.621788.

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26

Lee, S. H., and B. S. Song. "Digital-domain calibration of multistep analog-to-digital converters." IEEE Journal of Solid-State Circuits 27, no. 12 (1992): 1679–88. http://dx.doi.org/10.1109/4.173093.

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27

Harris, M. S. "Integrated analog-to-digital and digital-to-analog converters." Microelectronics Journal 25, no. 5 (August 1994): 405–6. http://dx.doi.org/10.1016/0026-2692(94)90096-5.

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Shukla, Mohit. "A 13.42ps Resolution, Low-Power Time-to-Digital Converter and 0.519fJ Energy-Efficient Novel Voltage-to-Time Converter for High-Speed Time-Based ADC Application." Journal of University of Shanghai for Science and Technology 24, no. 02 (February 19, 2022): 1020–30. http://dx.doi.org/10.51201/jusst/21/10878.

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Voltage domain ADC architectures require high gain and high bandwidth opamps to amplify the signal for successive stages. The opamp design gets a bit challenging due to noise, small gain and lower overdrive voltage. Due to these limitations, the inclination shifted towards high-speed converters which don’t require opamps. Time based Analog to Digital Converters (TBADC) is one such category of circuits. TBADCs are constituted from VTC followed by TDC with an encoder in the end. This work is concerned around the design of a high-resolution time to digital converter (TDC) and proposing a novel high-speed, low power consuming voltage to time converter (VTC) circuit. Both the circuits were implemented in Cadence Virtuoso EDA tool version 6.1.7 and Spectre was employed for running the simulations. TDC circuits had resolution of 13.425 ps and consume power of 1.873 μW. Process corner analysis and Monte Carlo analysis were performed on VTC design to determine worst possible deviations in performance. The proposed VTC exhibited delay of 23.79 ps with power consumption of 21.83 μW at 1 Volt. The presented TDC and VTC circuits can be used to design high-speed time-based Analog to Digital Converters.

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Elgreatly, Ahmed, Ahmed Dessouki, Hassan Mostafa, Rania Abdalla, and El-sayed El-Rabaie. "A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing." Electronics 9, no. 12 (December 1, 2020): 2033. http://dx.doi.org/10.3390/electronics9122033.

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Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.

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Zhang, Xianyu, Xiaoqiang Qiao, Tao Liang, and Kang An. "Secure performance analysis and pilot spoofing attack detection in cell-free massive MIMO systems with finite-resolution ADCs." International Journal of Distributed Sensor Networks 18, no. 1 (January 2022): 155014772110677. http://dx.doi.org/10.1177/15501477211067743.

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In this article, the secure communication in cell-free massive multiple-input multiple-output system with low-resolution analog-to-digital converters is investigated in the presence of an active eavesdropper. Specifically, in this article, the deterioration caused by the analog-to-digital converter imperfections on the accuracy of the channel estimation and secure transmission performance is studied. Besides, the additive quantization noise model is utilized to analyze the impacts of the low-resolution analog-to-digital converters. The minimum mean square error channel estimation results show that there is a nonzero floor caused by the coarse analog-to-digital converters. Then, the closed-form expressions for both the legitimate users achievable ergodic rate and the information leakage to the eavesdropper are derived, respectively. Moreover, tight approximated ergodic secrecy rate expression is also presented with respect to analog-to-digital converters quantization bits, number of antennas, pilot power, and so on. To degrade the impacts of the pilot spoofing attack, an active attack detection approach based on random matrix theory is proposed which can only be operated at one access point. Simulation results are provided to corroborate the obtained results and analyze the impacts of various parameters on system secrecy performance. Also, the superiority of the proposed active attacks detection method is confirmed via simulation results.

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Dent, A. C., and C. F. N. Cowan. "Linearization of analog-to-digital converters." IEEE Transactions on Circuits and Systems 37, no. 6 (June 1990): 729–37. http://dx.doi.org/10.1109/31.55031.

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Juodawlkis, P. W., J. C. Twichell, G. E. Betts, J. J. Hargreaves, R. D. Younger, J. L. Wasserman, F. J. O'Donnell, K. G. Ray, and R. C. Williamson. "Optically sampled analog-to-digital converters." IEEE Transactions on Microwave Theory and Techniques 49, no. 10 (2001): 1840–53. http://dx.doi.org/10.1109/22.954797.

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Genat, J. F. "High resolution time-to-digital converters." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 315, no. 1-3 (May 1992): 411–14. http://dx.doi.org/10.1016/0168-9002(92)90737-o.

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Mooney, James, Simon Effler, Mark Halton, and Abdulhussain Mahdi. "DSP-Based Control of Multi-Rail DC-DC Converter Systems with Non-Integer Switching Frequency Ratios." Iraqi Journal for Electrical and Electronic Engineering 7, no. 1 (June 1, 2011): 9–13. http://dx.doi.org/10.37917/ijeee.1.3.

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This paper examines the use of non-integer switching frequency ratios in digitally controlled DC-DC converters. In particular the execution of multiple control algorithms using a Digital Signal Processor (DSP) for this application is analyzed. The variation in delay from when the Analog to Digital Converter (ADC) samples the output voltage to when the duty cycle is updated is identified as a critical factor to be considered when implementing the digital control system. Fixing the delay to its maximum value is found to produce reasonable performance using a conventional DSP. A modification of the DSP’s interrupt control logic is proposed here that minimizes the delay and thereby yields improved performance compared with that given by a standard interrupt controller. Applying this technique to a multi-rail power supply system provides the designer with the flexibility to choose arbitrary switching frequencies for individual converters, thereby allowing optimization of the efficiency and performance of the individual converters.

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Mooney, James, Simon Effler, Mark Halton, and Abdulhussain Mahdi. "DSP-Based Control of Multi-Rail DC-DC Converter Systems with Non-Integer Switching Frequency Ratios." Iraqi Journal for Electrical and Electronic Engineering 7, no. 1 (June 1, 2011): 9–13. http://dx.doi.org/10.37917/ijeee.7.1.3.

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This paper examines the use of non-integer switching frequency ratios in digitally controlled DC-DC converters. In particular the execution of multiple control algorithms using a Digital Signal Processor (DSP) for this application is analyzed. The variation in delay from when the Analog to Digital Converter (ADC) samples the output voltage to when the duty cycle is updated is identified as a critical factor to be considered when implementing the digital control system. Fixing the delay to its maximum value is found to produce reasonable performance using a conventional DSP. A modification of the DSP’s interrupt control logic is proposed here that minimizes the delay and thereby yields improved performance compared with that given by a standard interrupt controller. Applying this technique to a multi-rail power supply system provides the designer with the flexibility to choose arbitrary switching frequencies for individual converters, thereby allowing optimization of the efficiency and performance of the individual converters.

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Shilin, A. N., B. V. Mac, and I. A. Koptelova. "DIGITAL PYROMETER OF SPECTRAL RATIO." Kontrol'. Diagnostika, no. 285 (March 2022): 52–57. http://dx.doi.org/10.14489/td.2022.03.pp.052-057.

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The article provides a comparative analysis of the main optoelectronic pyrometers: radiation and spectral ratio. The main error of optoelectronic pyrometers is a methodological component, which is due to the inconstancy of the radiation coefficient of the surface of the material of the product, which depends on the material, the state of the surface of the material and temperature. When measuring temperature, it is difficult to take into account this dependence, since there are no analytical expressions. In practice, the radiation coefficient of the surface of the material of the product is determined approximately using reference books. From the analysis of the two main optoelectronic pyrometers, it follows that the methodological error of spectral ratio pyrometers is less than that of radiation pyrometers, and when measuring the temperature of gray bodies, this component of the error is absent. To substantiate the technical implementation, the analysis of existing information processing schemes of spectral ratio pyrometers - ratiometric converters was carried out. The analysis revealed that it is advisable to use a converter with push-pull integration to implement a digital pyrometer of spectral ratio. This digital pyrometer of spectral ratio, in comparison with the known implementation scheme, performs three functions, namely the functions of two analog-to-digital converters (ADC) and a digital ratiometric converter of the unit. In addition, such a digital pyrometer of spectral ratio has good protection against network interference and can significantly reduce the influence on the measurement error of factors having a multiplicative nature. A technique for selecting the wavelengths of light filters and radiation detectors with the required spectral characteristics for a given range of measured temperatures is presented.

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Galton, I. "Digital cancellation of D/A converter noise in pipelined A/D converters." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 47, no. 3 (March 2000): 185–96. http://dx.doi.org/10.1109/82.826744.

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Quenzer-Hohmuth, Samuel, Thoralf Rosahl, Steffen Ritzmann, and Bernhard Wicht. "Challenges and implementation aspects of switched-mode power supplies with digital control for automotive applications." Advances in Radio Science 14 (September 28, 2016): 85–90. http://dx.doi.org/10.5194/ars-14-85-2016.

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Abstract. Switched-mode power supplies (SMPS) convert an input DC-voltage into a higher or lower output voltage. In automotive, analog control is mostly used in order to keep the required output voltages constant and resistant to disturbances. The design of robust analog control for SMPS faces parameter variations of integrated and external passive components. Using digital control, parameter variations can be eliminated and the required area for the integrated circuit can be reduced at the same time. Digital control design bears challenges like the prevention of limit cycle oscillations and controller-wind-up. This paper reviews how to prevent these effects. Digital control loops introduce new sources for dead times in the control loop, for example the latency of the analog-to-digital-converter (ADC). Dead times have negative influence on the stability of the control loop, because they lead to phase delays. Consequently, low latency is one of the key requirements for analog-to-digital-converters in digitally controlled SMPS. Exploiting the example of a 500 kHz-buck converter with a crossover frequency of 70 kHz, this paper shows that the 5 µs-latency of a ΔΣ-analog-to-digital-converter leads to a reduction in phase margin of 126°. The latency is less critical for boost converters because of their inherent lower crossover frequencies. Finally, the paper shows a comparison between analog and digital control of SMPS with regard to chip area and test costs.

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Suzuki, Tekehiro, Kohji Higuchi, and Kamon Jirasereeamornkul. "Design of A2DOF Controller with Smith Predictor for LLC Current-Resonant DC-DC Converters." Applied Mechanics and Materials 781 (August 2015): 422–26. http://dx.doi.org/10.4028/www.scientific.net/amm.781.422.

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LLC current-resonant converters have greater non-linear characteristics as compared to conventional DC-DC converters. Thus controlling LLC converters is difficult. In particular, the influence of an input delay time isn’t negligible at heavy load. In this paper, an A2DOF (Approximate 2-Degree-Of Freedom) controller with Simith predictor is proposed to compensate the input delay time of LLC current-resonant DC-DC converter. Experimental studies using a microprocessor for the controller demonstrate that this type of digital controller is effective to suppress the influences of the input delay time and the output variations at the sudden load change.

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Osman, Lobna, Sameh Rehan, and Abdel-Fattah Abdel-Fattah. "Improved hybrid SET/MOS Digital-Analog and Analog-Digital Converters." Bulletin of the Faculty of Engineering. Mansoura University 40, no. 1 (July 5, 2020): 16–25. http://dx.doi.org/10.21608/bfemu.2020.100768.

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Zjajo, Amir, Manuel J. Barragan, and Jose Pineda de Gyvez. "Digital Adaptive Calibration of Multi-Step Analog to Digital Converters." Journal of Low Power Electronics 8, no. 2 (April 1, 2012): 182–96. http://dx.doi.org/10.1166/jolpe.2012.1183.

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Gao, Guoqing, Wanjun Lei, Yao Cui, Kai Li, Ling Shi, and Shiyuan Yin. "Modeling and Stability Analysis of Model Predictive Control Dual Active Bridge Converter." Energies 12, no. 16 (August 13, 2019): 3103. http://dx.doi.org/10.3390/en12163103.

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Digital control has been widely used in dual active bridge (DAB) converters, which are pivotal parts of electric vehicles and distributed generation systems. However, the time delays introduced by the digital control could affect the performance or even lead to the instability of the digitally controlled DAB converter. In order to reduce the effect of time delay on the dynamics and stability of the system, the model predictive control (MPC) of the DAB converter is proposed based on the discrete-time iteration in this paper to compensate for the digital control delay. According to the obtained discrete-time model, the instability mechanism of the MPC DAB converters with different parameters is revealed. The simulation and theoretical analysis indicate that this method could reduce the influence of the digital control delay and increase the stable range of the system compared with the conventional control strategy. The proposed method is also revealed to have a strong compatibility and portability. In addition, the accurately predicted stability boundaries can be applied to the practical parameter design and guarantee the stable operation of the system. The experimental results are consistent with the theoretical analysis and verify the proposed method.

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GHARBIYA, AHMED, TREVOR C. CALDWELL, and D. A. JOHNS. "HIGH-SPEED OVERSAMPLING ANALOG-TO-DIGITAL CONVERTERS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 297–317. http://dx.doi.org/10.1142/s0129156405003211.

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This paper is mainly tutorial in nature and discusses architectures for oversampling converters with a particular emphasis on those which are well suited for high frequency input signal bandwidths. The first part of the paper looks at various architectures for discrete-time modulators and looks at their performance when attempting high speed operation. The second part of this paper presents some recent advancements in time-interleaved oversampling converters. The next section describes the design and challenges in continuous-time modulators. Finally, conclusions are made and a brief summary of the recent state of the art of high-speed converters is presented.

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Mattada, Mahantesh P., and Hansraj Guhilot. "Time‐to‐digital converters—A comprehensive review." International Journal of Circuit Theory and Applications 49, no. 3 (January 18, 2021): 778–800. http://dx.doi.org/10.1002/cta.2936.

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Wei, Qi, Fei Qiao, and Huazhong Yang. "New Development of Analog-to-Digital Converters." Recent Patents on Electrical Engineeringe 4, no. 3 (September 1, 2011): 214–20. http://dx.doi.org/10.2174/1874476111104030214.

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Voiter, A. P., M. I. Doronin, A. M. Kovalev, and I. O. Maznyj. "Tester for spectrometric analog-to-digital converters." Nuclear Physics and Atomic Energy 19, no. 1 (March 25, 2018): 74–79. http://dx.doi.org/10.15407/jnpae2018.01.074.

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Rudyakova, A. N., A. Yu Lipinsky, and V. V. Danilov. "PRESENT-DAY PHOTON DIGITAL-TO-ANALOG CONVERTERS." Telecommunications and Radio Engineering 70, no. 2 (2011): 159–69. http://dx.doi.org/10.1615/telecomradeng.v70.i2.80.

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Matsumoto, H., and K. Watanabe. "Switched-capacitor algorithmic digital-to-analog converters." IEEE Transactions on Circuits and Systems 33, no. 7 (July 1986): 721–24. http://dx.doi.org/10.1109/tcs.1986.1085975.

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Geurkov, Vadim, and Lev Kirischian. "Concurrent Testing of Analog-to-Digital Converters." i-manager's Journal on Electronics Engineering 1, no. 1 (November 15, 2010): 8–14. http://dx.doi.org/10.26634/jele.1.1.1193.

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Brandolini, A., and A. Gandelli. "Testing methodologies for analog-to-digital converters." IEEE Transactions on Instrumentation and Measurement 41, no. 5 (1992): 595–603. http://dx.doi.org/10.1109/19.177328.

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Journal articles on the topic 'Digital converters'

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