Dissertations / Theses on the topic 'Digital converters'

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1

Andersson, Ola. "Modeling and Implementation of Current-Steering Digital-to-Analog Converters." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.

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Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.
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2

Tsai, Tsung-Heng. "Time-interleaved analog-to-digital converters for digital communications /." For electronic version search Digital dissertations database. Restricted to UC campuses. Access is free to UC campus dissertations, 2005. http://uclibs.org/PID/11984.

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3

Savla, Anup. "Digital calibration algorithms for nyquist-rate analog to digital converters." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1087588301.

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Thesis (Ph. D.)--Ohio State University, 2004.
Title from first page of PDF file. Document formatted into pages; contains xxi, 246 p.; also includes graphics. Includes bibliographical references (p. 211-214).
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4

Luo, F. L. "Digital control of power semiconductor converters." Thesis, University of Cambridge, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383314.

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5

Khilo, Anatol (Anatol M. ). "Integrated photonic analog-to-digital converters." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/68490.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 161-172).
Accurate conversion of wideband multi-GHz analog signals into the digital domain has long been a target of analog-to-digital converter (ADC) developers, driven by applications in radar systems, software radio, medical imaging, and communication systems. Aperture jitter has been a major bottleneck on the way towards higher speeds and better accuracy. Photonic ADCs, which perform sampling using ultra-stable optical pulse trains generated by mode-locked lasers, have been investigated as a promising approach to overcome the jitter problem and bring ADC performance to new levels. This work demonstrates that the photonic approach can deliver on its promise by digitizing a 41 GHz signal with 7.0 effective bits and 52 dBc spur-free dynamic range (SFDR) using a discrete-component photonic ADC. This corresponds to 15 fs jitter, a 4-5 times improvement over the jitter of the best electronic ADCs, and an order of magnitude improvement over the jitter of electronic ADCs operating above 10 GHz. The feasibility of a practical photonic ADC is demonstrated by creating an integrated ADC with a modulator, filters, and photodetectors fabricated on a single silicon chip and using it to sample a 10 GHz signal with 3.5 effective bits and 39 dBc SFDR. In both experiments, a sample rate of 2.1 GSa/s was obtained by interleaving two 1.05 GSa/s channels; higher sample rates can be achieved by increasing the channel count. A key component of a multi-channel ADC - a dual multi-channel high-performance filter bank - is successfully implemented. A concept for broadband linearization of the silicon modulator, which is another critical component of the photonic ADC, is proposed. Nonlinear phenomena in silicon microring filters and their impact on ADC performance are analyzed, and methods to reduce this impact are proposed. The results presented in the thesis suggest that a practical integrated photonic ADC, which successfully overcomes the electronic jitter bottleneck, is possible today.
by Anatol Khilo.
Ph.D.
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6

Paul, Susanne A. (Susanne Anita). "Pipelined oversampling analog-to-digital converters." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/7981.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 223-226).
Oversampling and noise-shaping techniques, such as [delta sigma] modulation, are widely used in analog-to-digital conversion to achieve accuracy that exceeds that of integrated-circuit components. Such converters have an inherent tradeoff between accuracy and speed, whereby resolution in amplitude is achieved at the expense of resolution in time. Although much attention has been focused on improving the speed and power of [delta sigma] analog-to-digital converters, data rates remain limited to less than a few MHz and are not easily extended. A pipelined oversampling architecture is described that circumvents the speed-resolution tradeoff of conventional oversampling converters by performing spatial, rather than temporal, oversampling. It combines high-resolution capabilities of [delta sigma] techniques with the high speed of pipelined architectures so that both of these attributes are achievable. The architecture also differs from conventional oversampling in that it performs Nyquist-rate sampling. Power is improved as a result of a charge-domain implementation, reduced sensitivity to thermal noise, simplified decimation, and reduced circuit speed, which permits voltage scaling and use of low-power technologies. Circuit techniques for implementation of a pipelined oversampling converter are also presented. Although CCDs are not essential to the concept, such converters are most practically built using a combination of CCD and CMOS circuits. CCDs make analog pipelines with hundreds of stages feasible by providing fully-depleted operations which are highly accurate, low power, simple, and compact. Other operations are performed using nondepleted circuits.
(cont.) A circuit technique, referred to as dynamic double sampling, is presented, which provides improved linearity and speed over existing techniques and forms a core circuit element for these nondepleted operations. Two prototype converters have been demonstrated. They were built in standard CMOS processes and show that moderate to high performance is possible from CCD circuits and can be achieved without custom processing. The first prototype uses a 1.2-[mu]m process and operates at an 18-MHz data rate. It achieves 78-dB SFDR, DNL < ±0.15 LSB at 13 bits, 74-dB SNR over a 9-MHz bandwidth, and 324 mW power dissipation. The second prototype uses a 0.6-[mu]m design rule and operates at a 30-MHz data rate. It achieves 70-dB SFDR and 66-dB SNR over a 15-MHz bandwidth.
by Susanne A. Paul.
Ph.D.
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7

Delic-Ibukic, Alma. "Digital Background Calibration Techniques for High-Resolution, Wide Bandwidth Analog-to-Digital Converters." Fogler Library, University of Maine, 2008. http://www.library.umaine.edu/theses/pdf/Delic-IbukicA2008.pdf.

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8

Garcia, Julian. "Digitally Enhanced Continuous-Time Sigma-Delta Analogue-to-Digital Converters." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-95447.

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The continuous downscaling of CMOS technology presents advantagesand difficulties for IC design. While it allows faster, denser and more energy efficient digital circuits, it also imposes several challenges which limit the performance of analogue circuits. Concurrently, applications are continuously pushing the boundaries of power efficiency and throughput of electronic systems. Accordingly, IC design is increasingly shifting into highly digital systems with few necessary analogue components. Particularly, continuous-time (CT) sigma-delta (ΣΔ) analogue-to-digital converters (ADCs) have recently received a growing interest, covering high-resolution medium-speed requirementsor offering low power alternatives to low speed applications. However, there are still several aspects that deserve further investigation so as to enhancethe ADC’s performance and functionality. The objective of the research performed in this thesis is the investigation of digital enhancement solutions for CT ΣΔ ADCs. In particular, two aspects are considered in this work. First, highly digital techniques are investigated to minimize circuit impairments, with the objective of providing solutions with reduced analogue content. In this regard, a multi-bit CT ΣΔ modulator with reduced number of feedback levels is explored to minimize the use of linearisation techniques in the DAC. The proposed architecture is designed and validated through behavioural simulations targeting a mobile application. Additionally, a novel self-calibration technique, using test-signal injection and digital cancellation, is proposed to counteract process variations affecting single loop CT implementations. The effectiveness of the calibration technique is confirmed through corner simulations using behavioural models and shows that stability issues are minimized and that a 7 dB SNDR degradation can be avoided. The second aspect of this thesis investigates the use of high order CT modulators in incremental ΣΔ (IΣΔ) and extended-range IΣΔ ADCs, with the objective of offering low-power alternatives for low-speed high-resolution multi-channel applications. First, a 3rd order single loop CT IΣΔ ADC, targeting an 8-channel 500 Ksamples/sec rate per channel recording system for neuropotential sensors, is proposed, fabricated and tested. The proposed architecture lays the theoretical groundwork and demonstrates a competitive performance of high-order CT IΣΔ ADCs for low-power multi-channel applications. The ADC achieves 65.3 dB/64 dB SNR/SNDR and 68.2 dB dynamic range. The modulator consumes 96 μW from a 1.6 V power supply. Additionally, the use of extended range approach in CT IΣΔ ADCs is investigated,so as to reduce the required number of cycles per conversion while benefiting from the advantages of a CT implementation. The operation, influence of filter topology and impact of circuit non-idealities are first analysed using a general approach and later validated through a test-case. It was found that, by applying analogue-digital compensation in the digital domain, it is possible to minimize the noise leakage due to analogue-digital transfer function mismatches and benefit from relaxed amplifiers’ finite gain-bandwidth product and finite DC gain, allowing, as a consequence, a power conscious alternative.
QC 20120528
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9

Majidi, Rabeeh. "DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-dissertations/275.

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With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington,MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100kSps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich,RI.
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10

Dent, Alan Christopher. "Linearisation of analogue to digital and digital to analogue converters." Thesis, University of Edinburgh, 1990. http://hdl.handle.net/1842/13621.

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11

Law, Waisiu. "Digital calibration of non-ideal pipelined analog-to-digital converters /." Thesis, Connect to this title online; UW restricted, 2003. http://hdl.handle.net/1773/5846.

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12

Gong, Pu, and Hua Guo. "Post-Correction of Analog to Digital Converters." Thesis, University of Gävle, Department of Technology and Built Environment, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-805.

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As the rapid development of the wireless communication system and mobile video devices, the integrated chip with low power consuming and high conversion efficiency is widely needed. ADC and DAC are playing an important role in these applications.

The aim of this thesis is to verify a post-correction method which is used for improving the performance of ADC. First of all, this report introduces the development and present status of ADC, and expatiate its important parameters from two different classes (static performance and dynamic performance). Based on the fundamental principle, the report then focuses on the dynamic integral non-linearity modeling of ADC. Refer to this model, one post-correction method is described and verified.

Upon the face of post-correction, this method is to modify the output signals which have been converted from analog to digital format by adding a correction term. Improvement made by the post-correction needs to be checked out. Thus the performance analysis mainly relay on the measures of total harmonic distortion and signal to noise and distortion ratio is also included in this thesis.

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13

Lundin, Henrik. "Post-correction of analog-to-digital converters." Licentiate thesis, KTH, Signals, Sensors and Systems, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-1587.

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This thesis deals with digital post-correction ofanalog-to-digital converters (ADCs). The performance ofpractical ADCs is deteriorated by nonidealities and flaws inthe converter. Methods for mitigating these errors by applyingdigital signal processing to the output of the converter havebeen proposed in the past. These methods are often referred toas postcorrection methods. This work is mainly concerned withpost-correction methods based on look-up tables.

Practical ADCs often exhibit dynamical error behavior,meaning that the error is dependent on the dynamics of theinput signal. In this thesis an extension of previouslyproposed post-correction methods is proposed. The method usesthe present sample in conjunction with a number of past samplesto form the table index. In order to reduce the number of indexbits, and thereby the size of the table, the method comprises a‘bit mask’, which selects a subset of the availablebits to be used in the index. Evaluations using experimentalADC data show that the proposed method improves the converterperformance, but also that the choice of index bits has asignificant impact on the outcome of the correction. Theincorporation of a bit mask enables an analysis of the effectof different bit masks. The analysis results in a framework forcomparing different correction tables.

The framework is then applied in an optimization problem.The goal is to find the best allocation of a fixed number ofindex bits. Two different criterions are applied: minimizationof the total harmonic distortion and maximization of thesignal-to-noise and distortion ratio. The results of theoptimization, performed with experimental data, show that theoptimal bit allocation is different depending on whichcriterion is used. Moreover, the performance of a correctionscheme deteriorates only slowly with decreasing table size, ifappropriate index bits are selected.

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14

Wikner, J. Jacob. "Studies on CMOS digital-to-analog converters /." Linköping : Univ, 2001. http://www.bibl.liu.se/liupubl/disp/disp2001/tek667s.pdf.

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15

Danesh, Seyed Amir Ali. "Time interleaved counter analog to digital converters." Thesis, University of Edinburgh, 2011. http://hdl.handle.net/1842/5790.

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The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration.
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Bee, Sarah Caroline. "Radiation effects in analogue to digital converters." Thesis, University College London (University of London), 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.298887.

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17

Dacy, Susan (Susan Mary) 1975. "Analog to digital converters for CMOS imagers." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46276.

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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
Includes bibliographical references (leaves 80-82).
A/D converters for single chip CMOS imagers have often been designed using the column-parallel approach, employing a slow A/D converter for each column of the sensor array. This thesis investigates a serial approach utilizing a single fast A/D converter to process all of the imager pixels. If power scales linearly with frequency in a given A/D architecture, power dissipation for the two approaches should be comparable. However, the serial approach should occupy less area since only the cost of one A/D converter is incurred. A figure of merit 1/power*area is introduced to verify this theory by comparing previously reported A/D approaches after appropriate technology, speed, and supply scaling. Camera system specifications require a single serial A/D converter to have 10b resolution at a 3MHz sampling rate for a CIF (352x288) imager array running at 30 frames/second Area minimization, power minimization, and the ability to build the A/D in a standard CMOS process are extremely important for consumer product applications. A single slope A/D architecture with a subnanosecond time digitizer shows promise for optimizing figure of merit over pipelined and folding interpolating approaches. This work focuses on the design issues of the 3MHz single-slope based A/D converter. Architectures appropriate for extending this A/D converter to 12MHz for four times CIF image arrays (704x576) are discussed. The 3MHz converter was designed, simulated, and laid out in a 0.35um CMOS technology. At 3.3V supply, 25°C and nominal process conditions, the converter dissipates 29 mW while occupying 0.3 mm2 . A 12MHz trislope extension of this converter is estimated to dissipate 37 mW in 0.4 mm2.
by Susan Dacy.
M.Eng.
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18

Zareba, Grzegorz Szczepan. "Behavioral simulation of analog to digital converters." Diss., The University of Arizona, 2005. http://hdl.handle.net/10150/290152.

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The design of high-speed and high-resolution data converters is very difficult due to complexity of architectures used for converting analog signals into their digital representation. Since the introduction of the simplest conversion technique called parallel or flash technique numerous other architectures have been developed, for example n-stage pipeline, reference feed-forward architecture, folding and interpolating technique. The variety of A/D converter architectures additionally complicates design process due to fact that there is no available behavioral simulator, which can be utilized to support verification of particular converter's design. Many effects and imperfections present in A/D converters influence their performance, for example: switching imperfections, finite gain, clock jitter, and switching and coupling (Electro-Magnetic and substrate perturbations). In most cases several simulation tools have to be used to very performance of designed A/D converter. In this work a new methodology for behavioral simulation of A/D converters has been presented. Novel approach in behavioral modeling of A/D converters is based on utilization of Dynamic Linked Libraries (DLLs) to encapsulate behavior of basic modules of A/D converters. Predefined Basic Building Modules (BBMs) of A/D converters such as comparators, folding circuits, analog switches, binary encoders and many others are used to form a behavioral model of various types of A/D converters. Imperfections of BBMs are separated from the simulator framework and included into behavioral description of BBMs kept in DLL modules. Utilization of DLL modules gives a very convenient way for modifying BBMs independently from the simulator framework, and because DLL modules are executable files simulation time is significantly reduced (no translation or interpretation of simulation language commands is needed). Developed Behavioral Simulator of A/D converters is implemented in Visual C++ language and is partially based on an event driven simulation scheme and a data flow technique. The data flow technique was introduced into the simulator architecture to reduce number of events generated during simulation process, which additionally reduces simulation time. Several BBMs have been defined and constructed as DLL modules to support simulation of various types of A/D converters including flash, multi-stage, pipelined, and folding A/D converters.
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Biglarbegian, Mehrdad. "High Frequency GaN Power Converters Digital Twin." Thesis, The University of North Carolina at Charlotte, 2018. http://pqdtopen.proquest.com/#viewpdf?dispub=10979304.

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There is a need for a foundation of a research study aimed at investigations on near real-time reliability awareness of Gallium Nitride devices in high-frequency power converters for which we need advanced hardware and algorithms. This dissertation is moving beyond traditional reliability analysis and looking to more applicable and accurate analytical tools by introducing deep learning techniques and advanced sensing solutions. The computational structures will be applied at the edge of the power converter through online sensing and data processing units as well as on a remote server. They will provide an iterative ability to predict the time until the device may fail or reach a pre-defined degradation threshold.

With the availability of the most granular information deduced from advanced devices, a new data-driven scheme is proposed for system monitoring and possible lifetime extension Gallium Nitride power converters. The approach relies on the real-time on-resistance data extraction from the power converter, and calibration of an adaptive model using multi-physics co-simulations under power cycling. More specifically, the focus is on deploying machine learning algorithms to exploit for the parameter estimation in power electronics engineering reliability. The proposed techniques in this work are quite new and have not yet been developed and analyzed for high-frequency power converters specifically with Gallium Nitride power semiconductor devices.

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Cartina, Dragos. "Characterization and digital correction of multi-stage analog-to-digital converters." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0012/MQ27012.pdf.

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Cartina, Dragos Carleton University Dissertation Engineering Electronics. "Characterization and digital correction of multi-stage analog-to- digital converters." Ottawa, 1997.

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Delic-Ibukic, Alma. "Continuous Digital Calibration of Pipelined A/D Converters." Fogler Library, University of Maine, 2004. http://www.library.umaine.edu/theses/pdf/Delic-IbukicA2004.pdf.

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23

張華 and Hua Zhang. "Digital vector control of forced-commutated cycloconverter drives." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1994. http://hub.hku.hk/bib/B31234574.

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Zhang, Hua. "Digital vector control of forced-commutated cycloconverter drives /." [Hong Kong] : University of Hong Kong, 1994. http://sunzi.lib.hku.hk/hkuto/record.jsp?B1594847X.

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Saucier, Scott. "Multiband Analog-to-Digital Conversion." Fogler Library, University of Maine, 2002. http://www.library.umaine.edu/theses/pdf/SaucierS2002.pdf.

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Carter, Nathan R. "A 12-b 50Msample/s Pipeline Analog to Digital Converter." Digital WPI, 2000. https://digitalcommons.wpi.edu/etd-theses/749.

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This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage structure. Correction of the pipeline is accomplished by measuring the offset and gain of each of the first six stages using subsequent stages. The measured values are used to calculate digtal values the compensate for the inaccuracies of the analog pipeline. Corrected digital values for each stage are stored in the pipeline and used to create corrected output codes. Errors caused by measuring the first six stages using uncalibrated stages are minimized by using extra switching circuitry during calibration.
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Docef, Alen. "Efficient structures for oversampling A/D conversion." Thesis, Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/14975.

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Barton, Patrick Randal. "A synthesis program for CMOS successive approximation A/D and D/A converters." Thesis, Georgia Institute of Technology, 1986. http://hdl.handle.net/1853/15347.

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Sadeghifar, Mohammad Reza. "On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters." Licentiate thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-114274.

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High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element. In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work. ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement. Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line. In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.
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30

Lundin, Henrik. "Characterization and Correction of Analog-to-Digital Converters." Doctoral thesis, KTH, School of Electrical Engineering (EES), 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-547.

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Denna avhandling behandlar analog-digitalomvandling. I synnerhet behandlas postkorrektion av analog-digitalomvandlare (A/D-omvandlare). A/D-omvandlare är i praktiken behäftade med vissa fel som i sin tur ger upphov till distorsion i omvandlarens utsignal. Om felen har ett systematiskt samband med utsignalen kan de avhjälpas genom att korrigera utsignalen i efterhand. Detta verk behandlar den form av postkorrektion som implementeras med hjälp av en tabell ur vilken korrektionsvärden hämtas.

Innan en A/D-omvandlare kan korrigeras måste felen i den mätas upp. Detta görs genom att estimera omvandlarens överföringsfunktion. I detta arbete behandlas speciellt problemet att skatta kvantiseringsintervallens mittpunkter. Det antas härvid att en referenssignal finns tillgänglig som grund för skattningen. En skattare som baseras på sorterade data visas vara bättre än den vanligtvis använda skattaren baserad på sampelmedelvärde.

Nästa huvudbidrag visar hur resultatet efter korrigering av en A/D-omvandlare kan predikteras. Omvandlaren antas här ha en viss differentiell olinjäritet och insignalen antas påverkad av ett slumpmässigt brus. Ett postkorrektionssystem, implementerat med begränsad precision, korrigerar utsignalen från A/D-omvandlaren. Ett utryck härleds som beskriver signal-brusförhållandet efter postkorrektion. Förhållandet visar sig bero på den differentiella olinjäritetens varians, det slumpmässiga brusets varians, omvandlarens upplösning samt precisionen med vilken korrektionstermerna beskrivs.

Till sist behandlas indexering av korrektionstabeller. Valet av metod för att indexera en korrektionstabell påverkar såväl tabellens storlek som förmågan att beskriva och korrigera dynamiska fel. I avhandlingen behandlas i synnerhet tillståndsmodellbaserade metoder, det vill säga metoder där tabellindex bildas som en funktion utav flera på varandra följande sampel. Allmänt gäller att ju fler sampel som används för att bilda ett tabellindex, desto större blir tabellen, samtidigt som förmågan att beskriva dynamiska fel ökar. En indexeringsmetod som endast använder en delmängd av bitarna i varje sampel föreslås här. Vidare så påvisas hur valet av indexeringsbitar kan göras optimalt, och experimentella utvärderingar åskådliggör att tabellstorleken kan reduceras avsevärt utan att fördenskull minska prestanda mer än marginellt.

De teorier och resultat som framförs här har utvärderats med experimentella A/D-omvandlardata eller genom datorsimuleringar.


Analog-to-digital conversion and quantization constitute the topic of this thesis. Post-correction of analog-to-digital converters (ADCs) is considered in particular. ADCs usually exhibit non-ideal behavior in practice. These non-idealities spawn distortions in the converters output. Whenever the errors are systematic, it is possible to mitigate them by mapping the output into a corrected value. The work herein is focused on problems associated with post-correction using look-up tables. All results presented are supported by experiments or simulations.

The first problem considered is characterization of the ADC. This is in fact an estimation problem, where the transfer function of the converter should be determined. This thesis deals with estimation of quantization region midpoints, aided by a reference signal. A novel estimator based on order statistics is proposed, and is shown to have superior performance compared with the sample mean traditionally used.

The second major area deals with predicting the performance of an ADC after post-correction. A converter with static differential nonlinearities and random input noise is considered. A post-correction is applied, but with limited (fixed-point) resolution in the corrected values. An expression for the signal-to-noise and distortion ratio after post-correction is provided. It is shown that the performance is dependent on the variance of the differential nonlinearity, the variance of the random noise, the resolution of the converter and the precision of the correction values.

Finally, the problem of addressing, or indexing, the correction look-up table is dealt with. The indexing method determines both the memory requirements of the table and the ability to describe and correct dynamically dependent error effects. The work here is devoted to state-space--type indexing schemes, which determine the index from a number of consecutive samples. There is a tradeoff between table size and dynamics: more samples used for indexing gives a higher dependence on dynamic, but also a larger table. An indexing scheme that uses only a subset of the bits in each sample is proposed. It is shown how the selection of bits can be optimized, and the exemplary results show that a substantial reduction in memory size is possible with only marginal reduction of performance.

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31

Skjellnes, Tore. "Digital Control of Converters for Distributed Power Generations." Doctoral thesis, Norwegian University of Science and Technology, Department of Electrical Power Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-2126.

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Pulse width modulated converters are becoming increasingly popular as their cost decreases and power rating increases. The new trend of smallscale power producers, often using renewable energy sources, has created new demands for delivery of energy to the grid.

A major advantage of the pulse width modulated converter is the ability to control the output voltage at any point in the voltage period. This enables rapid response to load changes and non-linear loads. In addition it can shape the voltage in response to the output current to create an outward appearance of a source impedance. This is called a virtual impedance.

This thesis presents a controller for a voltage controlled three phase pulse width modulated converter. This controller enables operation in standalone mode, in parallel with other converters in a microgrid, and in parallel with a strong main grid.

A time varying virtual impedance is presented which mainly attenuates reactive currents. A method of investigating the overall impedance including the virtual impedance is presented.

New net standards have been introduced, requiring the converter to operate even during severe dips in the grid voltage. Experiments are presented verifying the operation of the controller during voltage dips.

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32

Björsell, Niclas. "Modeling Analog to Digital Converters at Radio Frequency." Doctoral thesis, KTH, Signalbehandling, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4523.

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Det här arbetet handlar om att ta fram beteendemodeller av analog till digital omvandlare avsedda för tillämpningar i radiofrekvensområdet. Det gäller tillämpningar inom telekommunikation men även in test- och mätinstrument där omvandlingen från analoga till digitala signaler ofta är en prestandamässig flaskhals. Modellerna är avsedda att användas för att efterbehandla utdata från omvandlaren och på så sätt förbättra prestanda på den digitala signalen. Genom att skapa modeller av verkliga omvandlare och hur dessa avviker från ett idealt beteende kan ofullständigheter korrigeras genom så kallad postkorrigering. Beteendemodeller innebär att genererar en lämplig insignal, mäta utdata och beräkna en modell. För omvandlare i radiofrekvensområdet ställs höga krav på instrumentering. Den testutrustningen som används är baserad på moderna högprestanda instrument som har kompletterats med specialbyggd utrustning för signalkonditionering och datainsamling. I avhandlingen har även olika insignaler utvärderats med såväl teoretisk som experimentell analys. Det finns ett flertal olika varianter av modeller för att modulera ett olinjär, dynamisk system. För att få en parametereffektiv modell har utgångspunkten varit att utgå från en Volterramodell som på ett optimalt sätt beskriver svagt olinjära dynamiska system, så som analog till digital omvandlare, men som är alltför omfattande i antal parametrar. Volterramodellens har sedan reducerats till en mindre parameterintensiv, modellerstruktur på så sätt att Volterrakärnans symmetriegenskaper jämförts med symmetrierna hos andra modeller. En alternativ metod är att använda en Kautz-Volterramodell. Den har samma generella egenskaper som Volterramodellen, men är inte lika parameterkrävande. I den här avhandlingen redovisas experimentella resultat av Kautz-Volterramodellen som i framtiden kommer att vara intressanta att använda för postkorrigeringen. För att kunna beskriva beteenden som en dynamiska olinjära modellen inte klarar av har modellen kompletterats med en statisk styckvis linjär modellkomponent. I avhandlingen presenteras en sluten lösning för att identifiera samtliga paramervärden i modellen. Vidare har det i avhandlingen genomförs en analys av hur respektive komponent påverkar prestanda på utsignalen. Därigenom erhålls ett mått på den maximala prestandaförbättring som kan uppnås om felet kan elimineras.
This work considers behavior modeling of analog to digital converters with applications in the radio frequency range, including the field of telecommunication as well as test and measurement instrumentation, where the conversion from analog to digital signals often is a bottleneck in performance. The models are intended to post-process output data from the converter and thereby improve the performance of the digital signal. By building a model of practical converters and the way in which they deviate from ideal, imperfections can be corrected using post-correction methods. Behavior modeling implies generation of a suitable stimulus, capturing the output data, and characterizing a model. The demands on the test setup are high for converters in the radio frequency range. The test-bed used in this thesis is composed of commercial state-of-the-art instruments and components designed for signal conditioning and signal capture. Further, in this thesis, different stimuli are evaluated, theoretically as well as experimentally. There are a large number of available model structures for dynamic nonlinear systems. In order to achieve a parameter efficient model structure, a Volterra model was used as a starting-point, which can describe any weak nonlinear system with fading memory, such as analog to digital converters. However, it requires a large number of coefficients; for this reason the Volterra model was reduced to a model structure with fewer parameters, by comparing the symmetry properties of the Volterra kernels with the symmetries from other models. An alternative method is the Kautz-Volterra model, which has the same general properties as the Volterra model, but with fewer parameters. This thesis gives experimental results of the Kautz-Volterra model, which will be interesting to apply in a post-correction algorithm in the future. To cover behavior not explained by the dynamic nonlinear model, a complementary piecewise linear model component is added. In this thesis, a closed form solution to the estimation problem for both these model components is given. By gradually correcting for each component the performance will improve step by step. In this thesis, the relation between a given component and the performance of the converter is given, as well as potential for improvement of an optimal post-correction.
QC 20100629
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33

Peng, Hao. "Digital current mode control of DC-DC converters." Diss., Connect to online resource, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3207767.

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34

Björsell, Niclas. "Modeling analog to digital converters at radio frequency /." Stockholm : Signalbehandling, Kungliga Tekniska högskolan, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4523.

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35

Chan, Kok Lim. "High-speed, high-resolution digital-to-analog converters." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3294746.

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Thesis (Ph. D.)--University of California, San Diego, 2007.
Title from first page of PDF file (viewed March 14, 2008). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references.
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36

Tchapmi, Petse Lyne. "Wide-bandwidth digital controller for multi-phase converters." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/100672.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (page 63).
DC-DC converters with high bandwidth are essential for today's high efficiency and high-speed micro-processing applications. In order to satisfy the requirements of those systems, we propose the implementation of a practical wide bandwidth digital controller for multiphase buck converters. Traditional implementations of multiphase converters have a performance comparable to single-phase implementations, with a bandwidth limited to a fraction of the per-phase switching frequency Fsw. The goal of this project is to take advantage of multiphase to achieve a higher bandwidth for any given switching frequency. Specifically, we target a bandwidth that scales with N x Fsw, rather than Fsw, with N being the number of phases in the system. This work focuses on the evaluation of a previously proposed digital modulator that is able to react to duty cycle changes at a speed equal to N x Fsw. Using this modulator, we design a few digital controllers and compare their performance to that of traditional digital controllers.
by Lyne Petse Tchapmi.
M. Eng.
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37

Mobaraz, Hiwa. "Modelling and Design of Digital DC-DC Converters." Thesis, Linköpings universitet, Institutionen för systemteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-127713.

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Digital Switched mode power supplies are nowadays popular enough to be the obvious choice in many applications. Among all set-up and control techniques, the current mode DC-DC converter is often considered when performance and stability are of interest. This has also motivated all the “on chip” and ASIC implementations seen on the market, where current mode control technique is used. However, the development of FPGAs has created an important alternative to ASICs and DSPs. The flexibility and integration possibility is two important advantages among others. In this thesis report, an FPGA-based current mode buck/boost DC-DC converter is built in a stepwise manner, starting from the mathematical model. The goal is a simulation model which creates a basis for discussion about the advantages and disadvantages of current mode DC-DC converters, implemented in FPGAs.
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38

Petrie, Alexander Craig. "Ultra-Low-Supply-Voltage Analog-to-Digital Converters." BYU ScholarsArchive, 2019. https://scholarsarchive.byu.edu/etd/9122.

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This thesis presents techniques to implement analog-to-digital converters (ADCs) under an ultra-low-supply-voltage of 0.2 V to reduce the power consumption. The thesis proposes a dynamic bulk biasing circuit to adjust the PMOS bulk voltage to balance the NMOS and PMOS drain currents to guarantee functionality in the presence of process, voltage, and temperature variations. The dynamic bulk bias circuit is analyzed rigorously to show its functionality. This thesis also describes a new comparator suitable for a 0.2-V supply using ac-coupling, stacked input pairs, and voltage-boosted load capacitor. A 10-bit 5-kS/s successive-approximation-register (SAR) ADC in a 180-nm CMOS process with a supply voltage of 0.2 V demonstrates these ideas. The ADC exhibits a differential nonlinearity (DNL) and integral nonlinearity (INL) within +0.42/-0.45 and +0.62/-0.67 LSB, respectively. The measured SFDR and SNDR at 5 kS/s with a Nyquist-frequency input are 65.9 dB and 52.1 dB, respectively. The entire ADC and dynamic bulk biasing circuitry consume 22 nW including leakage power to yield a figure-of-meirt (FoM) of 8.8 fJ/conv.-step. Measurements of multiple chips show the proposed dynamic bulk biasing fully recovers the ADC performance when the supply voltage is varied. The nW power consumption makes the design well suited for wireless sensor node and energy harvester applications.
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Iroaga, Echere. "Pipelined analog-to-digital converters using incomplete settling /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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40

Wen, Yangyang. "MODELING AND DIGITAL CONTROL OF HIGH FREQUENCY DC-DC POWER CONVERTERS." Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3671.

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The power requirements for leading edge digital integrated circuits have become increasingly demanding. Power converter systems must be faster, more flexible, more precisely controllable and easily monitored. Meanwhile, in addition to control process, the new functions such as power sequencing, communication with other systems, voltage dynamic programming,load line specifications, phase current balance, protection, power status monitoring and system diagnosis are going into today's power supply systems. Digital controllers, compared withanalog controllers, are in a favorable position to provide basic feedback control as well as those power management functions with lower cost and great flexibility. The dissertation gives an overview of digital controlled power supply systems bycomparing with conventional analog controlled power systems in term of system architecture,modeling methods, and design approaches. In addition, digital power management, as one of the most valuable and "cheap" function, is introduced in Chapter 2. Based on a leading-edge digital controller product, Chapter 3 focuses on digital PID compensator design methodologies, design issues, and optimization and development of digital controlled single-phase point-of-load (POL)dc-dc converter. Nonlinear control is another valuable advantage of digital controllers over analogcontrollers. Based on the modeling of an isolated half-bridge dc-dc converter, a nonlinear control method is proposed in Chapter 4. Nonlinear adaptive PID compensation scheme is implemented based on digital controller Si8250. The variable PID coefficient during transients improves power system's transient response and thus output capacitance can be reduced to save cost. In Chapter 5, another nonlinear compensation algorithm is proposed for asymmetric flybackforward half bridge dc-dc converter to reduce the system loop gain's dependence on the input voltage, and improve the system's dynamic response at high input line. In Chapter 6, a unified pulse width modulation (PWM) scheme is proposed to extend the duty-cycle-shift (DCS) control, where PWM pattern is adaptively generated according to the input voltage level, such that the power converter's voltage stress are reduced and efficiency is improved. With the great flexibility of digital PWM modulation offered by the digital controller Si8250, the proposed control scheme is implemented and verified. Conclusion of the dissertation work and suggestions for future work in related directions are given in final Chapter.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
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41

Karanicolas, Andrew N. (Andrew Nicholas). "Digital self-calibration techniques for high-accuracy, high speed analog-to-digital converters." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/12010.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (leaves 219-224).
by Andrew Nicholas Karanicolas.
Ph.D.
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42

Medawar, Samer. "Modeling and post-correction of pipeline analog-digital converters." Licentiate thesis, Stockholm : Skolan för elektro- och systemteknik, Kungliga Tekniska högskolan, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-12003.

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43

Strak, Adam. "Timing Uncertainty in Sigma-Delta Analog-to-Digital Converters." Doctoral thesis, Stockholm : Elektronik, dator- och programvarusystem Electronic, Computer, and Software Systems, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4243.

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44

Batarseh, Majd. "DIGITAL PULSE WIDTH MODULATOR TECHNIQUES FOR DC - DC CONVERTERS." Doctoral diss., University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4358.

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Recent research activities focused on improving the steady-state as well as the dynamic behavior of DC-DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed microprocessors, flexibility and immunity to noise and environmental variations. Furthermore, increased interest in Field Programmable Gate Arrays (FPGA) makes it a convenient design platform for digitally controlled converters. The objective of this research is to propose new digital control schemes, aiming to improve the steady-state and transient responses of a high switching frequency FPGA-based digitally controlled DC-DC converters. The target is to achieve enhanced performance in terms of tight regulation with minimum power consumption and high efficiency at steady-state, as well as shorter settling time with optimal over- and undershoots during transients. The main task is to develop new and innovative digital PWM techniques in order to achieve: 1. Tight regulation at steady-state: by proposing high resolution DPWM architecture, based on Digital Clock Management (DCM) resources available on FPGA boards. The proposed architecture Window-Masked Segmented Digital Clock Manager-FPGA based Digital Pulse Width Modulator Technique, is designed to achieve high resolution operating at high switching frequencies with minimum power consumption. 2. Enhanced dynamic response: by applying a shift to the basic saw-tooth DPWM signal, in order to benefit from the best linearity and simplest architecture offered by the conventional counter-comparator DPWM. This proposed control scheme will help the compensator reach the steady-state value faster. Dynamically Shifted Ramp Digital Control Technique for Improved Transient Response in DC-DC Converters, is projected to enhance the transient response by dynamically controlling the ramp signal of the DPWM unit.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
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45

Paul, Susanne A. (Susanne Anita). "Analysis, design, and implementation of charge-to-digital converters." Thesis, Microsystems Technology Laboratories, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/10086.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
Caption title.
Includes bibliographical references (p. 209-215).
Sponsored in part by a National Science Foundation Graduate Fellowship.
Susanne A. Paul.
M.S.
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46

Panigada, Andrea. "Harmonic distortion correction in pipelined analog to digital converters." Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p3355107.

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Thesis (Ph. D.)--University of California, San Diego, 2009.
Title from first page of PDF file (viewed June 10, 2009). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references.
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47

Zhang, Dai. "Design of Ultra-Low-Power Analog-to-Digital Converters." Licentiate thesis, Linköpings universitet, Elektroniska komponenter, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79276.

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Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, typically requirelow-speed, medium-resolution ADCs. The successive approximation register (SAR) ADC exhibits significantly high energy efficiency compared to other prevalent ADC architectures due to its good tradeoffs among power consumption, conversion accuracy, and design complexity. To design an energy-efficient SAR ADC, an understanding of its error sources as well as its power consumption bounds is essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at low resolution, the power consumption is bounded by digital switching power; 2) at medium-to-high resolution, the power consumption is bounded by thermal noise if digital assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by capacitor mismatch.  Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently fast components in advanced CMOS technologies. Moreover, the leakage current degrades the sampling accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. Two SAR ADCs have been implemented in this thesis. The first ADC, implemented in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the ultra-low-power operation necessitates maximum simplicity in the ADC architecture.
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48

Wong, Si Seng. "Design of analog-to-digital converters with binary search algorithm and digital calibration techniques." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2493310.

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Chang, Yu-Lun, and 張育綸. "Design and Application of Analog-to-Digital Converters and Digital-to-Analog Converters." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/05299852035715640542.

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碩士
國立臺灣大學
電子工程學研究所
98
In Chapter 3, a 6-bit, 1MHz, low power DAC is presented. This chip is designed to be an arbitrary waveform generator for the neural stimulator. In Chapter 4, a 10-bit, 1MHz, low power DAC using the proposed “C-R hybrid architecture” is presented. With this architecture, the DAC can achieve high resolution while using lower power and smaller area comparing with other architecture. In Chapter 5, a 10-bit, 50MHz, pipelined ADC is presented. By using the “opamp current reuse technique”, the analog power consumption is reduced by half comparing with the conventional pipelined ADC. All chips in this thesis are designed and fabricated using TSMC 2P4M 0.35μm CMOS technology.
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50

Shu, Shaofeng. "Oversampling digital-to-analog converters." Thesis, 1995. http://hdl.handle.net/1957/34610.

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Abstract:
Oversampling and noise-shaping methods for digital-to-analog (D/A) conversion have been widely accepted as methods of choice in high performance data conversion applications. In this thesis, the fundamentals of D/A conversion and oversampling D/A conversion were discussed, along with the detailed analysis and comparison of the reported state-of-the-art oversampling D/A converters. Conventional oversampling D/A converters use 1-bit internal D/A conversion. Complex analog filters and/or large oversampling ratios are usually needed in these 1-bit oversampling D/A converters. Using multi-bit internal D/A conversion, the analog filter can be much simpler and the oversampling ratio can be greatly reduced. However, the linearity of the multi-bit D/A converter has to be at least the same as that required by the overall system. The dual-quantization technique developed in the course of this research provides a good alternative for implementing multi-bit oversampling D/A converters. The system uses two internal D/A converters; one is single-bit and the other is multi-bit. The single-bit D/A converter is used in a path called the signal path while the multi-bit D/A converter is used in a path called the correction path. Since the multi-bit D/A converter is not directly placed in the signal path, its nonlinearity error can be noise shaped by an analog differentiator so that the in-band noise contribution from the nonlinearity error is very small at the system output, greatly reducing the linearity requirement on the multi-bit internal D/A converter. An experimental implementation of an oversampling D/A converter using the dual-quantization technique was carried out to verify the concept. Despite about 10 dB higher noise than expected and the high second-order harmonic distortion due to practical problems in the implementation, the implemented system showed that the corrected output had more than 20 dB improvement over the uncorrected output in both signal-to-noise ratio and dynamic range, demonstrating the validity of the concept.
Graduation date: 1996
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