Relevant bibliographies by topics / Digital converters

Academic literature on the topic 'Digital converters'

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Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Digital converters"

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Borgmans, Jonas, and Pieter Rombouts. "Toward ‘digital’ analogue‐to‐digital converters." Electronics Letters 55, no. 10 (May 2019): 568–69. http://dx.doi.org/10.1049/el.2019.1269.

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Skup, Konrad, Paweł Grudziński, and Piotr Orleański. "Application of Digital Control Techniques for Satellite Medium Power DC-DC Converters." International Journal of Electronics and Telecommunications 57, no. 1 (March 1, 2011): 77–83. http://dx.doi.org/10.2478/v10177-011-0011-1.

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Application of Digital Control Techniques for Satellite Medium Power DC-DC Converters The objective of this paper is to present a work concerning a digital control loop system for satellite medium power DC-DC converters that is done in Space Research Centre. The whole control process of a described power converter is based on a high speed digital signal processing. The paper presents a development of a FPGA digital controller for voltage and current mode stabilization that was implemented using VHDL. The described controllers are based on a classical digital PID controller. The converter used for testing is a 200 kHz, 750W buck converter with 50V/15A output. A high resolution digital PWM approach is presented. Additionally a simple and effective solution of filtering of an analog-to-digital converter output is presented.
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Bin Le, T. W. Rondeau, J. H. Reed, and C. W. Bostian. "Analog-to-digital converters." IEEE Signal Processing Magazine 22, no. 6 (November 2005): 69–77. http://dx.doi.org/10.1109/msp.2005.1550190.

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Malev, N. A., O. V. Pogoditsky, O. V. Kozelkov, and A. S. Malacion. "Digital algorithm monitoring functioning of electromechanical dc converter." Power engineering: research, equipment, technology 24, no. 1 (May 24, 2022): 126–40. http://dx.doi.org/10.30724/1998-9903-2022-24-1-126-140.

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The parameters of electromechanical converters functioning as part of working sets can change as a result of the influence externa factors, such as changes in the characteristics of the environment. Changes in parameters also occur due to parametric disturbances caused by changes in the physical characteristics of the elements electromechanical converters. In this regard, the development of methods and algorithms that provide analysis and control of the functioning electromechanical converters is an urgent task. The article discusses a digital algorithm for monitoring the functioning of an electromechanical DC converter, based on obtaining characteristics in a tabular-graphic form. These characteristics reflect the relationship between the vector of unstable parameters of the research object χ and the generalized integral criterion Q as a function of the discrepancy between the output coordinates of the electromechanical converter and its reference model. Discrete transfer functions of the reference model and sensitivity models are obtained for the monitored unstable parameters of the electromechanical converter. Based on the decomposition of discrete models, the corresponding direct programming schemes in the Frobenius form are constructed. The digital algorithms of the obtained models are represented by the difference equations of state and output. The structural scheme calculation of the generalized integral criterion Q and point dependencies χ (Q) is given. Discrete approximation was carried out using a bilinear transformation (Tustin's formula). A computer experiment for obtaining point χ-dependencies was carried out with varying degrees of accuracy, depending on the step of variations monitored parameters of the electromechanical converter within a given range of variation. The results obtained make it possible to assess the monitored unstable parameters of electromechanical DC converters with the required accuracy.
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Kroics, Kaspars. "Digital Control of Variable Frequency Interleaved DC-DC Converter." Environment. Technology. Resources. Proceedings of the International Scientific and Practical Conference 2 (August 8, 2015): 124. http://dx.doi.org/10.17770/etr2013vol2.854.

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This paper represents a design and implementation of a digital control of variable frequency interleaved DC-DC converter using a digital signal processor (DSP). The digital PWM generation, current and voltage sensing, user interface and the new period and pulse width value calculation with DSP STM32F407VGT6 are considered. Typically, the multiphase interleaved DC - DC converters require a current control loop in each phase to avoid imbalanced current between phases. This increases system costs and control complexity. In this paper the converter which operates in discontinuous conduction mode is designed in order to reduce costs and remove the current control loop in each phase. High current ripples associated with this mode operation are then alleviated by interleaving. Pulse width modulation (PWM) is one of the most conventional modulation techniques for switching DC - DC converters. It compares the error signal with the sawtooth wave to generate the control pulse. This paper shows how six PWM signals phase-shifted by 60 degrees can be generated from calculated values. To ensure that the measured values do not contain disturbances and in order to improve the system stability the digital signal is filtered. The analog to digital converter's (ADC) sampling time must not coincide with the power transistor's switching time, therefore the sampling time must be calculated correctly as well. Digital control of the DC-DC converter makes it easy and quickly to configure. It is possible for this device to communicate with other devices in a simple way, to realize data input by using buttons and keyboard, and to display information on LED, LCD displays, etc.
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Hazell, Philippa, Peter Mather, Andrew Longstaff, and Simon Fletcher. "Digital System Performance Enhancement of a Tent Map-Based ADC for Monitoring Photovoltaic Systems." Electronics 9, no. 9 (September 22, 2020): 1554. http://dx.doi.org/10.3390/electronics9091554.

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Efficient photovoltaic installations require control systems that detect small signal variations over large measurement ranges. High measurement accuracy requires data acquisition systems with high-resolution analogue-to-digital converters; however, high resolutions and operational speeds generally increase costs. Research has proven low-cost prototyping of non-linear chaotic Tent Map-based analogue-to-digital converters (which fold and amplify the input signal, emphasizing small signal variations) is feasible, but inherent non-ideal Tent Map gains reduce the output accuracy and restrict adoption within data acquisition systems. This paper demonstrates a novel compensation algorithm, developed as a digital electronic system, for non-ideal Tent Map gain, enabling high accuracy estimation of the analogue-to-digital converter analogue input signal. Approximation of the gain difference compensation values (reducing digital hardware requirements, enabling efficient real-time compensation), were also investigated via simulation. The algorithm improved the effective resolution of a 16, 20 and 24 Tent Map-stage analogue-to-digital converter model from an average of 5 to 15.5, 19.2, and 23 bits, respectively, over the Tent Map gain range of 1.9 to 1.99. The simulated digital compensation system for a seven Tent Map-stage analogue-to-digital converter enhanced the accuracy from 4 to 7 bits, confirming real-time compensation for non-ideal gain in Tent Map-based analogue-to-digital converters was achievable.
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Wawryn, K., and R. Suszynski. "Low power 9-bit pipelined A/D and 8-bit self-calibrated D/A converters for a DSP system." Bulletin of the Polish Academy of Sciences: Technical Sciences 61, no. 4 (December 1, 2013): 979–88. http://dx.doi.org/10.2478/bpasts-2013-0105.

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Abstract A low power, low voltage current mode 9 bit pipelined a/d converter and 8 bit self-calibrated d/a converter to interface a DSP system are presented in the paper. The a/d converter is built of 1.5 bit stages with digital error correction logic. The d/a converter is composed of 3 LSBs fine and 5 MSBs coarse current mode converters. The a/d and d/a converters were designed in 0.35 μm technology, then fabricated to verify the proposed concept. The performances of both converters are compared to the performances of known converter structures. The main advantages of the proposed converters are low power consumption and small chip area.
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Eguchi, Kei, Ya Nan Zhang, Shinya Terada, and Ichirou Oota. "A Symmetrical Digital Selecting Type DC-DC Converter with Power Saving Techniques." Applied Mechanics and Materials 666 (October 2014): 77–81. http://dx.doi.org/10.4028/www.scientific.net/amm.666.77.

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To achieve various conversion ratios with high power efficiency, a symmetrical digital selecting type switched-capacitor (SC) DC-DC converter with power saving techniques is proposed in this paper. Unlike conventional SC DC-DC converters, the voltage ratio of capacitors is expressed as the ratio of a power of two. By combining some of these capacitors in series, the proposed converter can achieve a larger number of conversion ratios than conventional converters. Furthermore, by employing a symmetrical structure with power saving techniques, the proposed converter can alleviate energy loss due to stray parasitic capacitance. The theoretical analysis and SPICE simulations show the effectiveness of the proposed converter.
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Suszynski, R., and K. Wawryn. "Rapid prototyping of algorithmic A/D converters based on FPAA devices." Bulletin of the Polish Academy of Sciences: Technical Sciences 61, no. 3 (September 1, 2013): 691–96. http://dx.doi.org/10.2478/bpasts-2013-0073.

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Abstract A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of the field programmable analog array (FPAA) to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. Three converter architectures have been selected and implemented FPAA device. To verify and illustrate converters operation and prototyping capabilities, implemented converters have been excited by a sinusoidal signal. Analog sinusoidal excitations, digital responses and sinusoidal waveforms after reconstruction are presented.
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Bojja Venkatakrishnan, Satheesh, Elias A. Alwan, and John L. Volakis. "Challenges in Clock Synchronization for On-Site Coding Digital Beamformer." International Journal of Reconfigurable Computing 2017 (2017): 1–8. http://dx.doi.org/10.1155/2017/7802735.

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Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.
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Dissertations / Theses on the topic "Digital converters"

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Andersson, Ola. "Modeling and Implementation of Current-Steering Digital-to-Analog Converters." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.

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Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.
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Tsai, Tsung-Heng. "Time-interleaved analog-to-digital converters for digital communications /." For electronic version search Digital dissertations database. Restricted to UC campuses. Access is free to UC campus dissertations, 2005. http://uclibs.org/PID/11984.

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Savla, Anup. "Digital calibration algorithms for nyquist-rate analog to digital converters." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1087588301.

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Thesis (Ph. D.)--Ohio State University, 2004.
Title from first page of PDF file. Document formatted into pages; contains xxi, 246 p.; also includes graphics. Includes bibliographical references (p. 211-214).
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Luo, F. L. "Digital control of power semiconductor converters." Thesis, University of Cambridge, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383314.

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Khilo, Anatol (Anatol M. ). "Integrated photonic analog-to-digital converters." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/68490.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 161-172).
Accurate conversion of wideband multi-GHz analog signals into the digital domain has long been a target of analog-to-digital converter (ADC) developers, driven by applications in radar systems, software radio, medical imaging, and communication systems. Aperture jitter has been a major bottleneck on the way towards higher speeds and better accuracy. Photonic ADCs, which perform sampling using ultra-stable optical pulse trains generated by mode-locked lasers, have been investigated as a promising approach to overcome the jitter problem and bring ADC performance to new levels. This work demonstrates that the photonic approach can deliver on its promise by digitizing a 41 GHz signal with 7.0 effective bits and 52 dBc spur-free dynamic range (SFDR) using a discrete-component photonic ADC. This corresponds to 15 fs jitter, a 4-5 times improvement over the jitter of the best electronic ADCs, and an order of magnitude improvement over the jitter of electronic ADCs operating above 10 GHz. The feasibility of a practical photonic ADC is demonstrated by creating an integrated ADC with a modulator, filters, and photodetectors fabricated on a single silicon chip and using it to sample a 10 GHz signal with 3.5 effective bits and 39 dBc SFDR. In both experiments, a sample rate of 2.1 GSa/s was obtained by interleaving two 1.05 GSa/s channels; higher sample rates can be achieved by increasing the channel count. A key component of a multi-channel ADC - a dual multi-channel high-performance filter bank - is successfully implemented. A concept for broadband linearization of the silicon modulator, which is another critical component of the photonic ADC, is proposed. Nonlinear phenomena in silicon microring filters and their impact on ADC performance are analyzed, and methods to reduce this impact are proposed. The results presented in the thesis suggest that a practical integrated photonic ADC, which successfully overcomes the electronic jitter bottleneck, is possible today.
by Anatol Khilo.
Ph.D.
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Paul, Susanne A. (Susanne Anita). "Pipelined oversampling analog-to-digital converters." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/7981.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 223-226).
Oversampling and noise-shaping techniques, such as [delta sigma] modulation, are widely used in analog-to-digital conversion to achieve accuracy that exceeds that of integrated-circuit components. Such converters have an inherent tradeoff between accuracy and speed, whereby resolution in amplitude is achieved at the expense of resolution in time. Although much attention has been focused on improving the speed and power of [delta sigma] analog-to-digital converters, data rates remain limited to less than a few MHz and are not easily extended. A pipelined oversampling architecture is described that circumvents the speed-resolution tradeoff of conventional oversampling converters by performing spatial, rather than temporal, oversampling. It combines high-resolution capabilities of [delta sigma] techniques with the high speed of pipelined architectures so that both of these attributes are achievable. The architecture also differs from conventional oversampling in that it performs Nyquist-rate sampling. Power is improved as a result of a charge-domain implementation, reduced sensitivity to thermal noise, simplified decimation, and reduced circuit speed, which permits voltage scaling and use of low-power technologies. Circuit techniques for implementation of a pipelined oversampling converter are also presented. Although CCDs are not essential to the concept, such converters are most practically built using a combination of CCD and CMOS circuits. CCDs make analog pipelines with hundreds of stages feasible by providing fully-depleted operations which are highly accurate, low power, simple, and compact. Other operations are performed using nondepleted circuits.
(cont.) A circuit technique, referred to as dynamic double sampling, is presented, which provides improved linearity and speed over existing techniques and forms a core circuit element for these nondepleted operations. Two prototype converters have been demonstrated. They were built in standard CMOS processes and show that moderate to high performance is possible from CCD circuits and can be achieved without custom processing. The first prototype uses a 1.2-[mu]m process and operates at an 18-MHz data rate. It achieves 78-dB SFDR, DNL < ±0.15 LSB at 13 bits, 74-dB SNR over a 9-MHz bandwidth, and 324 mW power dissipation. The second prototype uses a 0.6-[mu]m design rule and operates at a 30-MHz data rate. It achieves 70-dB SFDR and 66-dB SNR over a 15-MHz bandwidth.
by Susanne A. Paul.
Ph.D.
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Delic-Ibukic, Alma. "Digital Background Calibration Techniques for High-Resolution, Wide Bandwidth Analog-to-Digital Converters." Fogler Library, University of Maine, 2008. http://www.library.umaine.edu/theses/pdf/Delic-IbukicA2008.pdf.

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Garcia, Julian. "Digitally Enhanced Continuous-Time Sigma-Delta Analogue-to-Digital Converters." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-95447.

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The continuous downscaling of CMOS technology presents advantagesand difficulties for IC design. While it allows faster, denser and more energy efficient digital circuits, it also imposes several challenges which limit the performance of analogue circuits. Concurrently, applications are continuously pushing the boundaries of power efficiency and throughput of electronic systems. Accordingly, IC design is increasingly shifting into highly digital systems with few necessary analogue components. Particularly, continuous-time (CT) sigma-delta (ΣΔ) analogue-to-digital converters (ADCs) have recently received a growing interest, covering high-resolution medium-speed requirementsor offering low power alternatives to low speed applications. However, there are still several aspects that deserve further investigation so as to enhancethe ADC’s performance and functionality. The objective of the research performed in this thesis is the investigation of digital enhancement solutions for CT ΣΔ ADCs. In particular, two aspects are considered in this work. First, highly digital techniques are investigated to minimize circuit impairments, with the objective of providing solutions with reduced analogue content. In this regard, a multi-bit CT ΣΔ modulator with reduced number of feedback levels is explored to minimize the use of linearisation techniques in the DAC. The proposed architecture is designed and validated through behavioural simulations targeting a mobile application. Additionally, a novel self-calibration technique, using test-signal injection and digital cancellation, is proposed to counteract process variations affecting single loop CT implementations. The effectiveness of the calibration technique is confirmed through corner simulations using behavioural models and shows that stability issues are minimized and that a 7 dB SNDR degradation can be avoided. The second aspect of this thesis investigates the use of high order CT modulators in incremental ΣΔ (IΣΔ) and extended-range IΣΔ ADCs, with the objective of offering low-power alternatives for low-speed high-resolution multi-channel applications. First, a 3rd order single loop CT IΣΔ ADC, targeting an 8-channel 500 Ksamples/sec rate per channel recording system for neuropotential sensors, is proposed, fabricated and tested. The proposed architecture lays the theoretical groundwork and demonstrates a competitive performance of high-order CT IΣΔ ADCs for low-power multi-channel applications. The ADC achieves 65.3 dB/64 dB SNR/SNDR and 68.2 dB dynamic range. The modulator consumes 96 μW from a 1.6 V power supply. Additionally, the use of extended range approach in CT IΣΔ ADCs is investigated,so as to reduce the required number of cycles per conversion while benefiting from the advantages of a CT implementation. The operation, influence of filter topology and impact of circuit non-idealities are first analysed using a general approach and later validated through a test-case. It was found that, by applying analogue-digital compensation in the digital domain, it is possible to minimize the noise leakage due to analogue-digital transfer function mismatches and benefit from relaxed amplifiers’ finite gain-bandwidth product and finite DC gain, allowing, as a consequence, a power conscious alternative.
QC 20120528
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Majidi, Rabeeh. "DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-dissertations/275.

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With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington,MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100kSps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich,RI.
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Dent, Alan Christopher. "Linearisation of analogue to digital and digital to analogue converters." Thesis, University of Edinburgh, 1990. http://hdl.handle.net/1842/13621.

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Books on the topic "Digital converters"

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Henzler, Stephan. Time-to-Digital Converters. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-8628-0.

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Advanced data converters. Cambridge: Cambridge University Press, 2012.

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Veeder, Kenton T. Digital converters for image sensors. Bellingham, Washington USA: SPIE Press, 2015.

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Ohnhäuser, Frank. Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters. Berlin, Heidelberg: Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-47020-6.

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Alejandro, Oliva, ed. Power-switching converters. 3rd ed. Boca Raton: CRC Press, 2010.

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Louwsma, Simon, Ed van Tuijl, and Bram Nauta. Time-interleaved Analog-to-Digital Converters. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-90-481-9716-3.

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Louwsma, Simon. Time-interleaved Analog-to-Digital Converters. Dordrecht: Springer Science+Business Media B.V., 2011.

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Rudy J. van de Plassche. Integrated analog-to-digital and digital-to-analog converters. Boston: Kluwer Academic Publishers, 1994.

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Plassche, Rudy. Integrated Analog-To-Digital and Digital-To-Analog Converters. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2748-0.

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Plassche, Rudy. Integrated Analog-To-Digital and Digital-To-Analog Converters. Boston, MA: Springer US, 1994.

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Book chapters on the topic "Digital converters"

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Plassche, Rudy. "Sigma-delta converters." In Integrated Analog-To-Digital and Digital-To-Analog Converters, 413–51. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2748-0_11.

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Plassche, Rudy. "Specifications of converters." In Integrated Analog-To-Digital and Digital-To-Analog Converters, 37–77. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2748-0_2.

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Wanhammar, Lars, and Tapio Saramäki. "Sampling Rate Converters." In Digital Filters Using MATLAB, 637–717. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-24063-9_14.

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Plassche, Rudy. "Specifications of converters." In CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 51–105. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3768-4_2.

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Leung, Bosco. "Analog-to-Digital Converters." In VLSI for Wireless Communication, 291–350. Boston, MA: Springer US, 2011. http://dx.doi.org/10.1007/978-1-4614-0986-1_6.

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Ohnhäuser, Frank. "Digital-to-Analog Converters." In Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters, 305–28. Berlin, Heidelberg: Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-47020-6_7.

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Szplet, Ryszard. "Time-to-Digital Converters." In Design, Modeling and Testing of Data Converters, 211–46. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39655-7_7.

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Taylor, H. Rosemary. "Digital to analogue converters." In Data Acquisition for Sensor Systems, 141–62. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-4905-2_8.

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Taylor, H. Rosemary. "Analogue to digital converters." In Data Acquisition for Sensor Systems, 163–211. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-4905-2_9.

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LaMeres, Brock J. "Analog to Digital Converters." In Embedded Systems Design using the MSP430FR2355 LaunchPad™, 453–71. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-40574-8_15.

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Conference papers on the topic "Digital converters"

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Park, Sangil. "Digital Sample-Rate Converters." In International Congress & Exposition. 400 Commonwealth Drive, Warrendale, PA, United States: SAE International, 1991. http://dx.doi.org/10.4271/910788.

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De Angelis, G., A. Moschitta, and P. Carbone. "Statistical efficiency of synchronous time-to-digital converters." In 2013 IEEE Nordic Mediterranean Workshop on Time-to-Digital Converters (NoMe TDC). IEEE, 2013. http://dx.doi.org/10.1109/nometdc.2013.6658240.

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Zhou, Tao, Jianping Xu, and Bruno Francois. "Analog-to-digital converter architectures for digital controller of high-frequency power converters." In IECON 2006 - 32nd Annual Conference on IEEE Industrial Electronics. IEEE, 2006. http://dx.doi.org/10.1109/iecon.2006.347576.

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Bult, Klaas. "Embedded analog-to-digital converters." In 2009 Proceedings of ESSCIRC (ESSCIRC). IEEE, 2009. http://dx.doi.org/10.1109/esscirc.2009.5325932.

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Maghari, Nima, and Un-Ku Moon. "Emerging analog-to-digital converters." In ESSCIRC 2014 - 40th European Solid State Circuits Conference. IEEE, 2014. http://dx.doi.org/10.1109/esscirc.2014.6942019.

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Shoop, Barry L. "Photonic analog-to-digital converters." In Optics in Computing '98, edited by Pierre H. Chavel, David A. B. Miller, and Hugo Thienpont. SPIE, 1998. http://dx.doi.org/10.1117/12.308935.

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Bult, Klaas. "Embedded Analog-to-Digital Converters." In 2009 Proceedings of the European Solid State Device Research Conference (ESSDERC). IEEE, 2009. http://dx.doi.org/10.1109/essderc.2009.5331357.

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Al Qubaisi, Kenaish E., and Anatol Khilo. "Photonic analog-to-digital converters." In 2014 XXXIth URSI General Assembly and Scientific Symposium (URSI GASS). IEEE, 2014. http://dx.doi.org/10.1109/ursigass.2014.6929388.

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Kogler, Helmut, Rudolf Scheidl, and Michael Ehrentraut. "A Simulation Model of a Hydraulic Buck Converter Based on a Mixed Time Frequency Domain Iteration." In ASME/BATH 2013 Symposium on Fluid Power and Motion Control. American Society of Mechanical Engineers, 2013. http://dx.doi.org/10.1115/fpmc2013-4409.

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Abstract:
Digital hydraulics is an opportunity to realize simple, robust, cheap and energy efficient hydraulic drives. In such systems digital on/off valves are used instead of proportional valves. Moreover, in hydraulic switching converters the valves are actuated within a few milliseconds, which create sharp pressure changes and, in turn, significant wave propagation effects in the pipe system. For a proper design of digital hydraulic systems a sound understanding of these effects is required to achieve the desired behavior of the switching drive system. In such converters, like the buck-, boost or boost-buck-converter, the inductance is one crucial component. It is realized by a simple pipe mainly for cost reasons. Furthermore, switching converters contain some components with nonlinear characteristics, like valves or accumulators, which prevent a comprehensive analysis in frequency domain. For a convenient analysis a qualified model of a hydraulic buck converter based on a mixed time frequency domain iteration is presented. Main parameters of this model are identified and wave propagation effects in the inductance pipe of the converter are investigated by simulation.
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De Angelis, Alessio, Satyam Dwivedi, and Peter Handel. "Application of time-to-digital converters to radio-frequency distance measurement." In 2013 IEEE Nordic Mediterranean Workshop on Time-to-Digital Converters (NoMe TDC). IEEE, 2013. http://dx.doi.org/10.1109/nometdc.2013.6658235.

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Reports on the topic "Digital converters"

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Brock, B. C. The role of noise in analog-to-digital converters. Office of Scientific and Technical Information (OSTI), November 1996. http://dx.doi.org/10.2172/419972.

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Multanen, Eric. Characterization of quantization noise in oversampled analog to digital converters. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6302.

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Mahurin, Eric, and Ray Siford. GaAs Sigma-Delta Modulator Modeling for Analog to Digital Converters (ADCS). Fort Belvoir, VA: Defense Technical Information Center, December 1992. http://dx.doi.org/10.21236/ada263419.

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Green, Malcolm. Diamond-Shaped Semiconductor Ring Lasers for Analog to Digital Photonic Converters. Fort Belvoir, VA: Defense Technical Information Center, January 2004. http://dx.doi.org/10.21236/ada421293.

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Philpott, Rick A. Development of High Performance Electronics and Optical-to-Electrical Advanced Circuitry for Photonic Analog-to-Digital Converters. Fort Belvoir, VA: Defense Technical Information Center, February 2006. http://dx.doi.org/10.21236/ada444702.

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Gouvis, Heather. Digital Biological Converter. Fort Belvoir, VA: Defense Technical Information Center, June 2013. http://dx.doi.org/10.21236/ada587382.

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Morris, Frank. Analog-to-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, July 1989. http://dx.doi.org/10.21236/ada268538.

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Morris, Frank. Analog-to-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, July 1987. http://dx.doi.org/10.21236/ada268539.

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Morris, Frank. Analog-to-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, October 1987. http://dx.doi.org/10.21236/ada268540.

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Morris, Frank. Analog-to-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, January 1991. http://dx.doi.org/10.21236/ada268541.

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