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Relevant bibliographies by topics / Digital-Based analog processing

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Academic literature on the topic 'Digital-Based analog processing'

Author: Grafiati

Published: 14 March 2023

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Journal articles on the topic "Digital-Based analog processing"

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Sharma, Sushma, Hitesh Kumar, and Charul Thareja. "Digital Signal Processing Over Analog Signal Processing." Journal of Advance Research in Electrical & Electronics Engineering (ISSN: 2208-2395) 1, no. 2 (February 28, 2014): 01–02. http://dx.doi.org/10.53555/nneee.v1i2.255.

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This paper provides a survey of digital signal processing over analog signal processing. Initially digital signal processing is developed to replace limited application based analog signal processing (ASP) of high cost. This paper describes the comparison of analog signal processing (ASP) and digital signal processing, technology under digital signal processing , application of digital signal processing, new technology of digital signal processing (DSP). This paper also focuses on the future scope of digital signal processing (DSP).

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Nasrulloh, Mohammad Dicky. "Designing a Digital Filter Based Crossover Audio System Using STM32L4." Jurnal Jartel: Jurnal Jaringan Telekomunikasi 9, no. 4 (December 25, 2019): 13–18. http://dx.doi.org/10.33795/jartel.v9i4.141.

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Analog telecommunication system equipment is now starting to develop and be replaced with digital telecommunication systems, one of them is in the audio signal processing. The focus of audio processing is audio crossover. Audio crossover in development there are still many who use analog systems. This analog system has disadvantages when adjusting the sound balance because it still uses analog filters to balance it. It is necessary to develop a technology that aims to create a digital-based crossover audio system using the STM32L4, so that by using this digital-based signal processing it is able to adjust the sound more specifically than the signal processing used analog based. This digital filter uses the Finite Impulse Response (FIR) method. Testing audio crossover using STM32L4 produces a digital-based crossover audio system design using a STM32L4 microcontroller with a voltage of 3.3V as power supply, mp3 player as sound input device, FIR filter as digital filter processing, LM386 as sound amplifier and speaker as sound output for crossover audio on rangelow frequency (200Hz to 4000Hz), high (2200Hz to 6000Hz), medium (200Hz to 4000Hz).

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Reshetnikova, I. V., S. V. Sokolov, A. A. Manin, M. V. Polyakova, and O. I. Sokolova. "Optical digital-to-analog converter for N-digit logic-based processing circuits." Journal of Physics: Conference Series 2131, no. 2 (December 1, 2021): 022129. http://dx.doi.org/10.1088/1742-6596/2131/2/022129.

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Abstract The possibility of synthesis of ultra-fast universal optical digital-to-analog converter (DAC) providing conversion of digital information into analog information in giga- and terahertz ranges, including in digital systems based on N-digit logic, is considered. The functional diagram of the optical DAC containing technologically well-developed optical elements is given, the principle of operation is described in detail. The possibility of implementing this DAC with the speed potentially possible for optical data processing circuits is shown.

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Cai, J., and G. W. Taylor. "An optoelectronic thyristor-based analog-to-digital converter for parallel processing." Applied Physics Letters 73, no. 16 (October 19, 1998): 2372–74. http://dx.doi.org/10.1063/1.122464.

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Maruta, Akihiro, and Sho-ichiro Oda. "Optical Signal Processing Based on All-Optical Analog-to-Digital Conversion." Optics and Photonics News 19, no. 4 (April 1, 2008): 30. http://dx.doi.org/10.1364/opn.19.4.000030.

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Semenov, V. K. "Digital to analog conversion based on processing of the SFQ pulses." IEEE Transactions on Applied Superconductivity 3, no. 1 (March 1993): 2637–40. http://dx.doi.org/10.1109/77.233969.

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N. Ezema, Chukwuedozie, Chukwuebuka B. Umezinwa, and Ernest O. Nonum. "Microcontroller-Based Optical Displacement Weighing Scale." International Journal of Advance Research and Innovation 4, no. 3 (2016): 27–33. http://dx.doi.org/10.51976/ijari.431606.

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Electronic weighing systems are used in industries and business establishments for weighing and segregating materials accurately for process scales. Thus, the aim of this research is to design and implement a microcontroller based optical displacement weighing scale. The electronic weighing system comprises the basic load cell suitable signal conditioners and output recorders/indicators giving both the analog and digital output for further processing. The signals from the load cell are amplified and fed to analog/digital converter, which provide an output in the digital format for display printing/processing etc. The strain gauge based load cell is the most popular weight transducer used in the electronic weighing system.

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Rajabalipanah, Hamid, Ali Abdolali, Shahid Iqbal, Lei Zhang, and Tie Jun Cui. "Analog signal processing through space-time digital metasurfaces." Nanophotonics 10, no. 6 (March 29, 2021): 1753–64. http://dx.doi.org/10.1515/nanoph-2021-0006.

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Abstract In the quest to realize analog signal processing using subwavelength metasurfaces, in this paper, we present the first demonstration of programmable time-modulated metasurface processors based on the key properties of spatial Fourier transformation. Exploiting space-time coding strategy enables local, independent, and real-time engineering of not only amplitude but also phase profile of the contributing reflective digital meta-atoms at both central and harmonic frequencies. Several illustrative examples are demonstrated to show that the proposed multifunctional calculus metasurface is capable of implementing a large class of useful mathematical operators, including 1st- and 2nd-order spatial differentiation, 1st-order spatial integration, and integro-differential equation solving accompanied by frequency conversions. Unlike the recent proposals based on the Green’s function (GF) method, the designed time-modulated signal processor effectively operates for input signals containing wide spatial frequency bandwidths with an acceptable gain level. Proof-of-principle simulations are also reported to demonstrate the successful realization of image processing functions like edge detection. This time-varying wave-based computing system can set the direction for future developments of programmable metasurfaces with highly promising applications in ultrafast equation solving, real-time and continuous signal processing, and imaging.

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Wu, Ling Fan, Li Jun Yun, Jun Sheng Shi, Kun Wang, and Zhi Hui Deng. "Design and Implementation of the HD Video Signal Converter Based on FPGA." Advanced Engineering Forum 6-7 (September 2012): 571–75. http://dx.doi.org/10.4028/www.scientific.net/aef.6-7.571.

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In this paper, based on the FPGA and with a video dedicated A / D converter chip, LVDS coding chip, the design and implementation of a SD(standard-definition) analog video signals to HD(high-definition) digital video signal converter. First, input SD analog video into digital video signals meet the ITU-BT656 standard. Then use the FPGA with the video processing chip and DDR do some corresponding processing to achieve high-definition digital video output. After the actual test, the converter output signal of the image quality is well, meets the design requirements, and to verify the effectiveness of the program.

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Wang, Li, Wenli Chen, Kai Chen, Renjun He, and Wenjian Zhou. "The Research on the Signal Generation Method and Digital Pre-Processing Based on Time-Interleaved Digital-to-Analog Converter for Analog-to-Digital Converter Testing." Applied Sciences 12, no. 3 (February 7, 2022): 1704. http://dx.doi.org/10.3390/app12031704.

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In the high-resolution analog circuit, the performance of chips is an important part. The performance of the chips needs to be determined by testing. According to the test requirements, stimulus signal with better quality and performance is necessary. The main research direction is how to generate high-resolution and high-speed analog signal when there is no suitable high-resolution and high-speed digital-to-analog converter (DAC) chip available. In this paper, we take the high-resolution analog-to-digital converter (ADC) chips test as an example; this article uses high-resolution DAC chips and multiplexers to generate high-resolution high-speed signals that can be used for testing high-resolution ADC chips based on the principle of time-alternating sampling. This article explains its method, analyzes its error and proposes a digital pre-processing method to reduce the error. Finally, the actual circuit is designed, and the method is verified on the circuit. The test results prove the effectiveness of this method for generating high-resolution ADC test signals.

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Dissertations / Theses on the topic "Digital-Based analog processing"

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Bair, Shyh-Shyong. "A high speed microprocessor-based data acquisition system." Ohio : Ohio University, 1985. http://www.ohiolink.edu/etd/view.cgi?ohiou1183748292.

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Song, Tae Joong. "A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/34760.

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This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.

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Goldberg, Jason M. "Signal processing for high resolution pulse width modulation based digital-to-analogue conversion." Thesis, King's College London (University of London), 1992. https://kclpure.kcl.ac.uk/portal/en/theses/signal-processing-for-high-resolution-pulse-width-modulation-based-digitaltoanalogue-conversion(0eb09aa0-1c54-48c3-844f-25aaa98908bf).html.

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Chen, Liang-Jen, and 陳亮仁. "Amplifier-Based Analog-to-Digital Converters Using Time-Domain Signal Processing." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/65238306735329556773.

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博士
國立臺灣大學
電子工程學研究所
104
The amplifier-based analog-to-digital converter (ADCs), such as pipelined, cyclic, and two-step architecture, are a suitable candidate for sampling rates from a few mega samples per second (MSPS) up to 100MSPS or even above, and resolutions range from 8 bits to 16 bits. However, as CMOS technology continues to shrink, the decreased supply voltage would limit the swing of the ADC, and the reduced intrinsic gain of the transistors would make the conventional operational amplifier difficult to realize. Although the early proposed open-loop architectures with the analog/digital calibration can be implemented in an advanced CMOS process, the amplifier non-linearity issue would become more severe as CMOS technology continues to scale down. A sophisticated non-linear calibration would be required and complicates the design. In addition, as the voltage swing decreases, the resolution of the conventional voltage-domain ADCs are also limited as well. To solve the issue described above, a time-domain ADC (TADC) architecture is proposed in this thesis. Since the power consumption of the digital circuit decreases, and the resolution of a time-domain signal is improved with the technology scaling, the TADC becomes a candidate for the power efficient architecture in the advanced process. Also, since the time-domain signal range would not be limited by the decreased supply voltage, the non-linearity issue in the TADC architecture could be relieved. Two prototype ICs were designed during this research. In chapter 2, the first design is a 12-bit 3.4MS/s two-step cyclic TADC implemented in a 0.18um CMOS process. The proposed TADC uses a voltage-to-time converter (VTC) with a 12dB gain amplifier and the proposed time amplifier (TA) as residue amplifiers to achieve 12-bit resolution without high gain amplifiers. In addition, non-linear calibration, and the process variation tracking blocks are also not required. The noise analysis for each TADC building block is also presented in this chapter. To verify the noise analysis further, another TADC is fabricated with different devices sizes, in order to compare the measured signal-to-noise ratio (SNR) and signal-to-noise and distortion ratio (SNDR). In chapter 3, the second design is a 10-bit 40MS/s two-step TADC implemented in a 0.18um CMOS process. The second design is realized to improve the sampling rate of the first design, and also to eliminate the use of the amplifiers. Same as the first design, non-linear calibration, and the process variation tracking blocks are also not required. Since the TADC can operate without the non-linear calibration, the hardware complexity of the digital background calibration adopted in this work can be greatly reduced. Therefore, the calibration time of the TADC requires only 622 clock cycles, which is over 10 times less than prior voltage-domain digitally-calibrated ADCs.

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Tomé, Pedro Mirassol. "Characterization, modeling and compensation of long-term memory effects in GAN HEMT based radiofrequency power amplifiers." Doctoral thesis, 2020. http://hdl.handle.net/10773/30994.

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Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) have emerged as the most compelling technology for the transmission of highpower radio-frequency (RF) signals for cellular mobile communications and radar applications. However, despite their remarkable power capabilities, the deployment of GaN HEMT-based RF power amplifiers (PAs) in the mobile communications infrastructure is often ruled out in favor of alternative siliconbased technologies. One of the main reasons for this is the pervasiveness of nonlinear long-term memory effects in GaN HEMT technology caused by thermal and charge-trapping phenomena. While these effects can be compensated for using sophisticated digital predistortion algorithms, their implementation and model-extraction complexity—as well as the power necessary for their real-time execution—make them unsuitable for modern small cells and large-scale multiple-input multiple-output transceivers, where the power necessary for the linearization of each amplification element is of great concern. In order to address these issues and further the deployment of high-powerdensity high-efficiency GaN HEMT-based RF PAs in next-generation communications and radar applications, in this thesis we propose novel methods for the characterization, modeling, and compensation of long-term memory effects in GaN HEMT-based RF PAs. More specifically, we propose a method for the characterization of the dynamic self-biasing behavior of GaN HEMTbased RF PAs; multiple behavioral models of charge trapping and their implementation as analog electronic circuits for the accurate real-time prediction of the dynamic variation of the threshold voltage of GaN HEMTs; a method for the compensation of the pulse-to-pulse instability of GaN HEMT-based RF PAs for radar applications; and a hybrid analog/digital scheme for the linearization of GaN HEMT-based RF PAs for next-generation communications applications.
Os transístores de alta mobilidade eletrónica de nitreto de gálio (GaN HEMTs) são considerados a tecnologia mais atrativa para a transmissão de sinais de radiofrequência de alta potência para comunicações móveis celulares e aplicações de radar. No entanto, apesar das suas notáveis capacidades de transmissão de potência, a utilização de amplificadores de potência (PAs) baseados em GaN HEMTs é frequentemente desconsiderada em favor de tecnologias alternativas baseadas em transístores de silício. Uma das principais razões disto acontecer é a existência pervasiva na tecnologia GaN HEMT de efeitos de memória lenta causados por fenómenos térmicos e de captura eletrónica. Apesar destes efeitos poderem ser compensados através de algoritmos sofisticados de predistorção digital, estes algoritmos não são adequados para transmissores modernos de células pequenas e interfaces massivas de múltipla entrada e múltipla saída devido à sua complexidade de implementação e extração de modelo, assim como a elevada potência necessária para a sua execução em tempo real. De forma a promover a utilização de PAs de alta densidade de potência e elevada eficiência baseados em GaN HEMTs em aplicações de comunicação e radar de nova geração, nesta tese propomos novos métodos de caracterização, modelação, e compensação de efeitos de memória lenta em PAs baseados em GaN HEMTs. Mais especificamente, nesta tese propomos um método de caracterização do comportamento dinâmico de autopolarização de PAs baseados em GaN HEMTs; vários modelos comportamentais de fenómenos de captura eletrónica e a sua implementação como circuitos eletrónicos analógicos para a previsão em tempo real da variação dinâmica da tensão de limiar de condução de GaN HEMTs; um método de compensação da instabilidade entre pulsos de PAs baseados em GaN HEMTs para aplicações de radar; e um esquema híbrido analógico/digital de linearização de PAs baseados em GaN HEMTs para comunicações de nova geração.
Programa Doutoral em Telecomunicações

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Satyanarayana, J. V. "Efficient Design of Embedded Data Acquisition Systems Based on Smart Sampling." Thesis, 2014. http://etd.iisc.ernet.in/2005/3518.

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Data acquisition from multiple analog channels is an important function in many embedded devices used in avionics, medical electronics, robotics and space applications. It is desirable to engineer these systems to reduce their size, power consumption, heat dissipation and cost. The goal of this research is to explore designs that exploit a priori knowledge of the input signals in order to achieve these objectives. Sparsity is a commonly observed property in signals that facilitates sub-Nyquist sampling and reconstruction through compressed sensing, thereby reducing the number of A to D conversions. New architectures are proposed for the real-time, compressed acquisition of streaming signals. A. It is demonstrated that by sampling a collection of signals in a multiplexed fashion, it is possible to efficiently utilize all the available sampling cycles of the analogue-to-digital converters (ADCs), facilitating the acquisition of multiple signals using fewer ADCs. The proposed method is modified to accommodate more general signals, for which spectral leakage, due to the occurrence of non-integral number of cycles in the reconstruction window, violates the sparsity assumption. When the objective is to only detect the constituent frequencies in the signals, as against exact reconstruction, it can be achieved surprisingly well even in the presence of severe noise (SNR ~ 5 dB) and considerable undersampling. This has been applied to the detection of the carrier frequency in a noisy FM signal. Information redundancy due to inter-signal correlation gives scope for compressed acquisition of a set of signals that may not be individually sparse. A scheme has been proposed in which the correlation structure in a set of signals is progressively learnt within a small fraction of the duration of acquisition, because of which only a few ADCs are adequate for capturing the signals. Signals from the different channels of EEG possess significant correlation. Employing signals taken from the Physionet database, the correlation structure of nearby EEG electrodes was captured. Subsequent to this training phase, the learnt KLT matrix has been used to reconstruct signals of all the electrodes with reasonably good accuracy from the recordings of a subset of electrodes. Average error is below 10% between the original and reconstructed signals with respect to the power in delta, theta and alpha bands: and below 15% in the beta band. It was also possible to reconstruct all the channels in the 10-10 system of electrode placement with an average error less than 8% using recordings on the sparser 10-20 system. In another design, a set of signals are collectively sampled on a finer sampling grid using ADCs driven by phase-shifted clocks. Thus, each signal is sampled at an effective rate that is a multiple of the ADC sampling rate. So, it is possible to have a less steep transition between the pass band and the stop band, thereby reducing the order of the anti-aliasing filter from 30 to 8. This scheme has been applied to the acquisition of voltages proportional to the deflection of the control surfaces in an aerospace vehicle. The idle sampling cycles of an ADC that performs compressive sub-sampling of a sparse signal, can be used to acquire the residue left after a coarse low-resolution sample is taken in the preceding cycle, like in a pipelined ADC. Using a general purpose, low resolution ADC, a DAC and a summer, one can acquire a sparse signal with double the resolution of the ADC, without having to use a dedicated pipelined ADC. It has also been demonstrated as to how this idea can be applied to achieve a higher dynamic range in the acquisition of fetal electrocardiogram signals. Finally, it is possible to combine more than one of the proposed schemes, to handle acquisition of diverse signals with di_erent kinds of sparsity. The implementation of the proposed schemes in such an integrated design can share common hardware components so as to achieve a compact design.

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Books on the topic "Digital-Based analog processing"

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Lamarche, Paul-Hugo. Field-programmable analog array implemented using delta-sigma based digital signal processing. Ottawa: National Library of Canada, 2003.

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Society, IEEE Computer, ed. Tutorial DSP-based testing of analog and mixed-signal circuits. Washington, D.C: IEEE Computer Society Press, 1987.

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Re-use based methodologies and tools in the design of analog and mixed-signal integrated circuits. Dordrecht: Springer, 2005.

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Book chapters on the topic "Digital-Based analog processing"

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Kehtarnavaz, Nasser, Shane Parris, and Abhishek Sehgal. "Analog-to-Digital Signal Conversion." In Smartphone-Based Real-Time Digital Signal Processing, 47–67. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-031-02537-2_4.

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Kehtarnavaz, Nasser, Abhishek Sehgal, Shane Parris, and Arian Azarang. "Analog-to-Digital Signal Conversion." In Smartphone-Based Real-Time Digital Signal Processing, 55–84. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-031-02543-3_4.

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Kehtarnavaz, Nasser, Abhishek Sehgal, and Shane Parris. "Analog-to-Digital Signal Conversion." In Smartphone-Based Real-Time Digital Signal Processing, 51–79. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-031-02540-2_4.

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Kilani, Dima, Baker Mohammad, Mohammad Alhawari, Hani Saleh, and Mohammed Ismail. "Ratioed Logic Comparator-Based Digital LDO Regulator." In Analog Circuits and Signal Processing, 73–95. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37884-4_5.

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Markulic, Nereo, Kuba Raczkowski, Jan Craninckx, and Piet Wambacq. "A Digital-to-Time-Converter-Based Subsampling PLL for Fractional Synthesis." In Analog Circuits and Signal Processing, 23–56. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-10958-5_2.

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Nishio, Kimihiro, and Taiki Yasuda. "Analog-Digital Circuit for Motion Detection Based on Vertebrate Retina and Its Application to Mobile Robot." In Neural Information Processing, 506–13. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24965-5_57.

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Lagerlund, Terrence D. "Digital Signal Processing." In Clinical Neurophysiology, 222–35. Oxford University Press, 2016. http://dx.doi.org/10.1093/med/9780190259631.003.0015.

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Digital computers can perform types of signal processing not readily available with analog devices, such as ordinary electrical circuits. This includes making the process of obtaining, storing, retrieving, and viewing clinical neurophysiology data easier; aiding in extracting information from waveforms that is not readily obtainable with visual analysis alone; and improving quantification of key features of waveforms. These processes are useful in accurate clinical diagnosis of electroencephalographic (EEG), electromyographic (EMG), and evoked potential studies, and it also lend themselves to serial comparisons between studies performed on the same subject at different times or between two groups of subjects in scientific investigations. Digital computers may also partially automate the interpretation of clinical neurophysiology studies. This chapter reviews the principles of digitization, the design of digitally based instruments for clinical neurophysiology, and several common uses of digital processing, including averaging, digital filtering, and some types of time-domain and frequency-domain analysis.

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Milic, Ljiljana. "Sampling Rate Converison by a Fractional Factor." In Multirate Filtering for Digital Signal Processing, 171–205. IGI Global, 2009. http://dx.doi.org/10.4018/978-1-60566-178-0.ch006.

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We have discussed so far the decimation and interpolation where the sampling rate conversion factor is an integer. However, the need for a non-integer sampling rate conversion appears when the two systems operating at different sampling rates have to be connected, or when there is a need to convert the sampling rate of the recorded data into another sampling rate for further processing or reproduction. Such applications are very common in telecommunications, digital audio, multimedia and others. In this chapter, we consider the sampling rate conversion by a rational factor, called sometimes a fractional sampling rate conversion. We use MATLAB functions from the Signal Processing and Filter Design Toolbox to demonstrate the fractional sampling rate conversion. We present the technique for constructing efficient fractional sampling rate converters based on FIR filters and the polyphase decomposition. In the sequel, we consider the sampling rate alteration with an arbitrary conversion factor. We present the polynomial-based approximation of the impulse response of a hybrid analog/digital model, and the implementation based on the Farrow structure. We also consider the fractional-delay filter problem. This chapter concludes with MATLAB exercises for individual study.

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Sheybani, Ehsan. "Real-Time Digital Signal Processing-Based Algorithm for Universal Software Radio Peripheral to Detect GPS Signal." In Strategic Innovations and Interdisciplinary Perspectives in Telecommunications and Networking, 241–54. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-8188-8.ch013.

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Software-defined radios (SDR) are gradually becoming a practical option for implementing RF communication systems due to their low cost, off-the-shelf availability, and flexibility. Although the analog limitations of the hardware devices in these systems create barriers to some applications, creative algorithms in digital signal processing (DSP) can improve the results. In some cases, this improvement is essential to establishing a robust and reliable communication. The universal software radio peripheral (USRP) is a popular hardware that can be used alongside the SDR. Among many capabilities of USRP and its changeable daughter boards is receiving GPS signals. The GPS satellites transmit data on two main frequencies, L1 (1575.42 MHz) and L2 (1227.60 MHz). In this chapter, the focus is on describing a detailed implementation of the real-time DSP-based algorithm for USRP to detect GPS signal, namely the L1 band that transmits at 1575.42 MHz.

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Teimoory, Mehri, Amirali Amirsoleimani, Arash Ahmadi, and Majid Ahmadi. "Development of Compute-in-Memory Memristive Crossbar Architecture with Composite Memory Cells." In Memristor - An Emerging Device for Post-Moore’s Computing and Applications. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.99634.

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In this chapter, we discuss the compute-in-memory memristive architectures and develop a 2M1M crossbar array which can be applied for both memory and logic applications. In the first section of this chapter, we briefly discuss compute-in-memory memristive architectural concepts and specifically investigate the current state off the art composite memristor-based switch cells. Also, we define their applications e.g. digital/analog logic, memory, etc. along with their drawbacks and implementation limitations. These composite cells can be designed to be adapted into different design needs can enhance the performance of the memristor crossbar array while preserving their advantages in terms of area and/or energy efficiency. In the second section of the chapter, we discuss a 2M1M memristor switch and its functionality which can be applied into memory crossbars and enables both memory and logic functions. In the next section of the chapter, we define logic implementation by using 2M1M cells and describe variety of in-memory digital logic 2M1M gates. In the next section of the chapter, 2M1M crossbar array performance to be utilized as memory platform is described and we conceived pure memristive 2M1M crossbar array maintains high density, energy efficiency and low read and write time in comparison with other state of art memory architectures. This chapter concluded that utilizing a composite memory cell based on non-volatile memristor devices allow a more efficient combination of processing and storage architectures (compute-in-memory) to overcome the memory wall problem and enhance the computational efficiency for beyond Von-Neumann computing platforms.

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Conference papers on the topic "Digital-Based analog processing"

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Shah, S. "A 200 MHz CMOS analogue-ROM based direct digital frequency synthesiser." In IEE Seminar Analog Signal Processing. IEE, 2000. http://dx.doi.org/10.1049/ic:20000480.

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Meng, Jiawei, Mario Miscuglio, Jonathan George, Aydin Babakhani, and Volker J. Sorger. "PIC-based Binary-Weighting Parallel Digital-to-Analog Converter." In Signal Processing in Photonic Communications. Washington, D.C.: OSA, 2021. http://dx.doi.org/10.1364/sppcom.2021.sptu4d.5.

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Fok, Mable P., Yue Tian, David Rosenbluth, Yanhua Deng, and Paul R. Prucnal. "Optical hybrid analog-digital signal processing based on spike processing in neurons." In SPIE Optical Engineering + Applications, edited by Khan M. Iftekharuddin and Abdul Ahad Sami Awwal. SPIE, 2011. http://dx.doi.org/10.1117/12.895347.

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Neuhaus, Peter, Nir Shlezinger, Meik Dorpinghaus, Yonina C. Eldar, and Gerhard Fettweis. "Task-Based Analog-to-Digital Converters for Bandlimited Systems." In 2021 29th European Signal Processing Conference (EUSIPCO). IEEE, 2021. http://dx.doi.org/10.23919/eusipco54536.2021.9616271.

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Nguyen, Nam-Trung. "Thermal Control for Droplet-Based Microfluidics." In 2008 Second International Conference on Integration and Commercialization of Micro and Nanosystems. ASMEDC, 2008. http://dx.doi.org/10.1115/micronano2008-70277.

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This paper presents our recent works on thermal control for droplet-based microfluidics. Temperature dependent properties of liquids have been use for actuation and many other applications in droplet-based microfluidics. In analogy to an analog/digital electronic circuits, a droplet-based microfluidic system consists for three main subsystems: droplet formation (analog/digital converter), droplet manipulation (digital processing) and droplet merging (digital/analog converter). This paper will present our recent achievements in thermal control of droplet formation in different configurations such as T-junction and cross junction with integrated microheaters. Furthermore, results on droplet switching will be presented. The droplet switch represent basic logic gate that can be used to construct a more complex droplet-based digital network. Thermocapillary actuation of microdroplets in one-dimensional and two-dimensional microfluidic platforms will be presented. Both numerical and experimental results will be presented in this paper.

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Sanchez, Giovanny, Thomas Jacob Koickal, T. A. Athul Sripad, Luiz Carlos Gouveia, Alister Hamilton, and Jordi Madrenas. "Spike-based analog-digital neuromorphic information processing system for sensor applications." In 2013 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2013. http://dx.doi.org/10.1109/iscas.2013.6572173.

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Liu, Xin, Yanming Xue, and Huaxin Sun. "Analog Domain Self-Interference Cancellation Method Based on Digital Aided Processing." In 2020 IEEE 9th Joint International Information Technology and Artificial Intelligence Conference (ITAIC). IEEE, 2020. http://dx.doi.org/10.1109/itaic49862.2020.9339032.

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Maruta, Akihiro, and Sho-ichiro Oda. "optical Signial Processing based on All-Optical Analog-to-Digital Conversion." In OFC/NFOEC 2007 - 2007 Conference on Optical Fiber Communication and the National Fiber Optic Engineers Conference. IEEE, 2007. http://dx.doi.org/10.1109/ofc.2007.4348683.

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Li, Y., Y. Zhang, and G. Eichmann. "An acousto-optic modulator-based analog-to-digital converter." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.tuuu9.

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Many optical signal processing and computing applications require the availability of a fast analog-to-digital (A/D) converter. As a basic building block, an electro-optic directional coupler was used for an optical A/D converter implementation. Previously we have shown that an optical theta-modulation effect could be used for an optical A/D conversion application. In this presentation, an acousto-optic theta-modulation A/D conversion architecture is proposed. An acoustooptic device is used as an optical FM modulator that maps input voltage to an output beam deflection angle. To cast the deflected optical intensity its binary format, a prefabricated intensity-coded A/D conversion mask is used. By means of a commercially available GaP acousto-optic deflector, a 1 new acousto-optic, theta-modulation A/D device in various optical signal processing and computing applications will be addressed.

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Shlezinger, Nir, Ruud J. G. van Sloun, Iris A. M. Huijben, Georgee Tsintsadze, and Yonina C. Eldar. "Learning Task-Based Analog-to-Digital Conversion for MIMO Receivers." In ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). IEEE, 2020. http://dx.doi.org/10.1109/icassp40776.2020.9053855.

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