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Journal articles on the topic 'Device-circuit co-design'

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Author: Grafiati
Published: 10 December 2022
Last updated: 28 January 2023

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1

Maheshwaram, Satish, S. K. Manhas, Gaurav Kaushal, Bulusu Anand, and Navab Singh. "Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform." IEEE Electron Device Letters 33, no. 7 (July 2012): 934–36. http://dx.doi.org/10.1109/led.2012.2197592.

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2

Aziz, Ahmedullah, and Sumeet Kumar Gupta. "Threshold Switch Augmented STT MRAM: Design Space Analysis and Device-Circuit Co-Design." IEEE Transactions on Electron Devices 65, no. 12 (December 2018): 5381–89. http://dx.doi.org/10.1109/ted.2018.2873738.

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3

Gupta, Sumeet Kumar, and Kaushik Roy. "Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs." IEEE Design & Test 30, no. 6 (December 2013): 29–39. http://dx.doi.org/10.1109/mdat.2013.2266394.

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4

Andric, Stefan, Lars Ohlsson Fhager, and Lars-Erik Wernersson. "Millimeter-Wave Vertical III-V Nanowire MOSFET Device-to-Circuit Co-Design." IEEE Transactions on Nanotechnology 20 (2021): 434–40. http://dx.doi.org/10.1109/tnano.2021.3080621.

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5

Liu, Jen-Chieh, Tzu-Yun Wu, and Tuo-Hung Hou. "Optimizing Incremental Step Pulse Programming for RRAM Through Device–Circuit Co-Design." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 5 (May 2018): 617–21. http://dx.doi.org/10.1109/tcsii.2018.2821268.

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6

Agarwal, Tarun, Gianluca Fiori, Bart Soree, Iuliana Radu, Marc Heyns, and Wim Dehaene. "Material-Device-Circuit Co-Design of 2-D Materials-Based Lateral Tunnel FETs." IEEE Journal of the Electron Devices Society 6 (2018): 979–86. http://dx.doi.org/10.1109/jeds.2018.2827164.

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7

Feng, Shi-Yu, Yong-Bo Su, Peng Ding, Jing-Tao Zhou, Song-Ang Peng, Wu-Chang Ding, and Zhi Jin. "Extrinsic equivalent circuit modeling of InP HEMTs based on full-wave electromagnetic simulation." Chinese Physics B 31, no. 4 (April 1, 2022): 047303. http://dx.doi.org/10.1088/1674-1056/ac2b1d.

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With the widespread utilization of indium-phosphide-based high-electron-mobility transistors (InP HEMTs) in the millimeter-wave (mmW) band, the distributed and high-frequency parasitic coupling behavior of the device is particularly prominent. We present an InP HEMT extrinsic parasitic equivalent circuit, in which the conductance between the device electrodes and a new gate–drain mutual inductance term L mgd are taken into account for the high-frequency magnetic field coupling between device electrodes. Based on the suggested parasitic equivalent circuit, through HFSS and advanced design system (ADS) co-simulation, the equivalent circuit parameters are directly extracted in the multi-step system. The HFSS simulation prediction, measurement data, and modeled frequency response are compared with each other to verify the feasibility of the extraction method and the accuracy of the equivalent circuit. The proposed model demonstrates the distributed and radio-frequency behavior of the device and solves the problem that the equivalent circuit parameters of the conventional InP HEMTs device are limited by the device model and inaccurate at high frequencies when being extracted.
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8

Yadav, Sameer, P. N. Kondekar, Pranshoo Upadhyay, and Bhaskar Awadhiya. "Negative capacitance based phase-transition FET for low power applications: Device-circuit co-design." Microelectronics Journal 123 (May 2022): 105411. http://dx.doi.org/10.1016/j.mejo.2022.105411.

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9

Kumar, Amresh, and Aminul Islam. "Multi-gate device and summing-circuit co-design robustness studies @ 32-nm technology node." Microsystem Technologies 23, no. 9 (July 6, 2016): 4099–109. http://dx.doi.org/10.1007/s00542-016-3055-4.

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10

Raychowdhury, A., B. C. Paul, S. Bhunia, and K. Roy. "Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 11 (November 2005): 1213–24. http://dx.doi.org/10.1109/tvlsi.2005.859590.

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11

Swain, Peeyusha Saurabha, Mayank Shrivastava, Harald Gossner, and Maryam Shojaei Baghini. "Device–Circuit Co-design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors." IEEE Transactions on Electron Devices 60, no. 11 (November 2013): 3827–34. http://dx.doi.org/10.1109/ted.2013.2283421.

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12

Yadav, Nandakishor, Ambika Prasad Shah, and Santosh Kumar Vishvakarma. "Stable, Reliable, and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-Design." IEEE Transactions on Semiconductor Manufacturing 30, no. 3 (August 2017): 276–84. http://dx.doi.org/10.1109/tsm.2017.2718029.

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13

Ham, Seok-Jin, Jeong-Heon Kim, and Kyeong-Sik Min. "Device/Circuit Co-Design Guide for Passive Memristor Array with Non-Linear Current–Voltage Behavior." Journal of Nanoscience and Nanotechnology 13, no. 9 (September 1, 2013): 6451–54. http://dx.doi.org/10.1166/jnn.2013.7629.

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14

Zheng, Shijun, Ting Liang, Yinpin Hong, Ying Li, and Jijun Xiong. "Fabrication and measurement of wireless pressure-sensitive micro-device based on high temperature co-fired ceramics technology." Sensor Review 34, no. 1 (January 14, 2014): 117–22. http://dx.doi.org/10.1108/sr-09-2012-689.

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Purpose – The paper aims to highlight a wireless pressure-sensitive micro-device with high pressure sensitivity and accuracy. It is based on the partially stabilized Zirconia (PSZ) ceramic material which is capable of excellent elasticity and robustness. Design/methodology/approach – The paper begins with a general introduction to the wireless interrogating method and then the fabrication processes of the device using high temperature co-fired ceramic (HTCC) technology are described in detail. Findings – A passive wireless micro-device made from a novel material-PSZ ceramic on pressure monitoring is fabricated and tested and the authors proved that the device possesses an advantages over some proposed wireless sensors on interrogating distance. The pressure sensitivity of the device is 336 kHz/bar at readout distance 2.5 cm and that is an excellent property. Originality/value – The paper shows a new design scheme for wireless pressure measurement. The future application of the wireless device indicates the problem on external packaging and wire connection could be avoided. The allowable interrogation distance between the device and readout circuit reaches 2.5 cm which is mentioned for the first time so far. The distance is long enough to insert a thermal insulation material which can protect the vulnerable readout circuit from harsh environment, so the research finding is meaningful for the modern measurement technology.
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15

Seon, Yoongeun, Jeesoo Chang, Changhyun Yoo, and Jongwook Jeon. "Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node." Electronics 10, no. 2 (January 15, 2021): 180. http://dx.doi.org/10.3390/electronics10020180.

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A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate controllability while making the channel in the form of a sheet. The mNS-FET has superior gate controllability for the stacked channels; consequently, it can significantly reduce the short-channel effect (SCE); however, punch-through inevitably occurs in the bottom channel portion that is not surrounded by gates, resulting in a large leakage current. Moreover, as the size of the semiconductor device decreases to several nanometers, the influence of the parasitic resistance and parasitic capacitance increases. Therefore, it is essential to apply design–technology co-optimization, which analyzes not only the characteristics from the perspective of the device but also the performance from the circuit perspective. In this study, we used Technology Computer Aided Design (TCAD) simulation to analyze the characteristics of the device and directly fabricated a model that describes the current–voltage and gate capacitance characteristics of the device by using Berkeley short-channel insulated-gate field-effect transistor–common multi-gate (BSIM–CMG) parameters. Through this model, we completed the Simulation Program with Integrated Circuit Emphasis (SPICE) simulation for circuit analysis and analyzed it from the viewpoint of devices and circuits. When comparing the characteristics according to the presence or absence of bottom oxide by conducting the above research method, it was confirmed that subthreshold slope (SS) and drain-induced barrier lowering (DIBL) are improved, and power and performance in circuit characteristics are increased.
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16

Yuan, Heng, Bo Wang, Se Hyuk Yeom, Kyu Jin Kim, Dae Hyuk Kwon, and Shin Won Kang. "VOC Gas Sensing Based on the BJT Mode of Gated LBJT Device." Advanced Materials Research 320 (August 2011): 597–600. http://dx.doi.org/10.4028/www.scientific.net/amr.320.597.

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Volatile organic compounds (VOCs) gas sensor based on gated lateral bipolar junction transistor (LBJT) was developed in this study. The device was fabricated using 0.35-μm logic process by Magnachip-Hynix Co. Ltd. under the Integrated Circuit Design education Center Multi Project Wafer (IDEC-MPW) program. Solvatochromic dye as the sensing membrane was coated on the floating gate of the device. A semiconductor test and analyzer (STA-EL421, ELECS) was used to measure the sensing results. Following the results, we found that the sensing device which used the gated LBJT device has fast responsibility and reversibility to VOC gases (acetone etc.).
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17

Gupta, S. K., and K. Roy. "(Invited) Spacer Thickness Optimization for FinFET-based Logic and Memories: A Device-Circuit Co-Design Approach." ECS Transactions 50, no. 4 (March 15, 2013): 187–92. http://dx.doi.org/10.1149/05004.0187ecst.

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18

Rathore, Rituraj Singh, and Ashwani K. Rana. "Impact of line edge roughness on the performance of 14-nm FinFET: Device-circuit Co-design." Superlattices and Microstructures 113 (January 2018): 213–27. http://dx.doi.org/10.1016/j.spmi.2017.10.038.

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19

Rana, Ashwani K. "Device circuit co-design to reduce gate leakage current in VLSI logic circuits in nano regime." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 29, no. 3 (September 4, 2015): 487–500. http://dx.doi.org/10.1002/jnm.2099.

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20

Kwon, Jisu, and Daejin Park. "Hardware/Software Co-Design for TinyML Voice-Recognition Application on Resource Frugal Edge Devices." Applied Sciences 11, no. 22 (November 22, 2021): 11073. http://dx.doi.org/10.3390/app112211073.

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On-device artificial intelligence has attracted attention globally, and attempts to combine the internet of things and TinyML (machine learning) applications are increasing. Although most edge devices have limited resources, time and energy costs are important when running TinyML applications. In this paper, we propose a structure in which the part that preprocesses externally input data in the TinyML application is distributed to the hardware. These processes are performed using software in the microcontroller unit of an edge device. Furthermore, resistor–transistor logic, which perform not only windowing using the Hann function, but also acquire audio raw data, is added to the inter-integrated circuit sound module that collects audio data in the voice-recognition application. As a result of the experiment, the windowing function was excluded from the TinyML application of the embedded board. When the length of the hardware-implemented Hann window is 80 and the quantization degree is 2−5, the exclusion causes a decrease in the execution time of the front-end function and energy consumption by 8.06% and 3.27%, respectively.
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21

Vaddi, Ramesh, Rajendra P. Agarwal, Sudeb Dasgupta, and Tony T. Kim. "Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design." Journal of Low Power Electronics and Applications 1, no. 2 (July 8, 2011): 277–302. http://dx.doi.org/10.3390/jlpea1020277.

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22

Jang, Jaeman, Jaehyeong Kim, Jaewook Lee, Chunhyung Jo, Sungwoo Jun, Hyeongjung Kim, Sunwoong Choi, et al. "P.19: Density-of-States Based Device-Circuit Co-Design Platform for Solution-Processed Organic Integrated Circuits." SID Symposium Digest of Technical Papers 44, no. 1 (June 2013): 1051–54. http://dx.doi.org/10.1002/j.2168-0159.2013.tb06404.x.

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23

Lone, Aijaz H., S. Amara, and H. Fariborzi. "Magnetic tunnel junction based implementation of spike time dependent plasticity learning for pattern recognition." Neuromorphic Computing and Engineering 2, no. 2 (March 25, 2022): 024003. http://dx.doi.org/10.1088/2634-4386/ac57a2.

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Abstract We present a magnetic tunnel junction (MTJ) based implementation of the spike time-dependent (STDP) learning for pattern recognition applications. The proposed hybrid scheme utilizes the spin–orbit torque (SOT) driven neuromorphic device-circuit co-design to demonstrate the Hebbian learning algorithm. The circuit implementation involves the (MTJ) device structure, with the domain wall motion in the free layer, acting as an artificial synapse. The post-spiking neuron behaviour is implemented using a low barrier MTJ. In both synapse and neuron, the switching is driven by the SOTs generated by the spin Hall effect in the heavy metal. A coupled model for the spin transport and switching characteristics in both devices is developed by adopting a modular approach to spintronics. The thermal effects in the synapse and neuron result in a stochastic but tuneable domain wall motion in the synapse and a superparamagnetic behaviour of in neuron MTJ. Using the device model, we study the dimensional parameter dependence of the switching delay and current to optimize the device dimensions. The optimized parameters corresponding to synapse and neuron are considered for the implementation of the Hebbian learning algorithm. Furthermore, cross-point architecture and STDP-based weight modulation scheme is used to demonstrate the pattern recognition capabilities by the proposed neuromorphic circuit.
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24

Shaik, Sadulla, K. Sri Rama Krishna, and Ramesh Vaddi. "Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD." Journal of Circuits, Systems and Computers 27, no. 03 (October 30, 2017): 1850046. http://dx.doi.org/10.1142/s0218126618500469.

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Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20[Formula: see text]nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET’s steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has [Formula: see text]91% smaller energy delay product (EDP) and [Formula: see text]84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2[Formula: see text]V VDD.
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25

Satipar, Den, Pattana Intani, and Winai Jaikla. "Electronically Tunable Quadrature Sinusoidal Oscillator with Equal Output Amplitudes during Frequency Tuning Process." Journal of Electrical and Computer Engineering 2017 (2017): 1–10. http://dx.doi.org/10.1155/2017/8575743.

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A new configuration of voltage-mode quadrature sinusoidal oscillator is proposed. The proposed oscillator employs two voltage differencing current conveyors (VDCCs), two resistors, and two grounded capacitors. In this design, the use of multiple/dual output terminal active building block is not required. The tuning of frequency of oscillation (FO) can be done electronically by adjusting the bias current of active device without affecting condition of oscillation (CO). The electronic tuning can be done by controlling the bias current using a digital circuit. The amplitude of two sinusoidal outputs is equal when the frequency of oscillation is tuned. This makes the sinusoidal output voltages meet good total harmonic distortions (THD). Moreover, the proposed circuit can provide the sinusoidal output current with high impedance which is connected to external load or to another circuit without the use of buffer device. To confirm that the oscillator can generate the quadrature sinusoidal output signal, the experimental results using VDCC constructed from commercially available ICs are also included. The experimental results agree well with theoretical anticipation.
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26

Wei, Baolin, and Chao Lu. "Exploring device-circuit co-design in LC VCO circuits using monolayer transition metal dischalcogenide MoS2 field-effect transistors." AEU - International Journal of Electronics and Communications 138 (August 2021): 153867. http://dx.doi.org/10.1016/j.aeue.2021.153867.

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27

Zhao, Sheng, Ujwal Radhakrishna, Jeffrey H. Lang, and Dennis Buss. "Low-voltage broadband piezoelectric vibration energy harvesting enabled by a highly-coupled harvester and tunable PSSHI circuit." Smart Materials and Structures 30, no. 12 (November 12, 2021): 125030. http://dx.doi.org/10.1088/1361-665x/ac3402.

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Abstract This paper presents a system-level design approach for widening the bandwidth and lowering the operating voltage of a piezoelectric vibration energy harvesting system (PVEHS). The proposed strategy involves co-optimization of the two constituent parts: (1) a highly-coupled piezoelectric vibration energy harvesting device (PVEHD) and (2) a phase-shift tunable parallel-SSHI (PS-PSSHI) interface power-electronic circuit. First, we analyze the interaction between them to achieve an overall reduction of system voltage and to widen bandwidth. Next, a co-designed system is experimentally demonstrated to validate the analysis. The implemented PVEHS consists of (i) a customized PVEHD designed for high electromechanical coupling and well-separated short-circuit (f SC) and open-circuit (f OC) resonances, and (ii) a tunable PS-PSSHI circuit which has an active rectification with low voltage drop to increase system efficiency. The system achieves an output power of 148 µW with a bandwidth of 81 Hz, an increase of 337% compared to conventional full-bridge rectifier. In addition, the system rectification voltage is lowered by 30% which makes it viable to power low-voltage Internet-of-Things sensor nodes.
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28

Koyyada, Ganesh, Ramesh Kumar Chitumalla, Suresh Thogiti, Jae Hong Kim, Joonkyung Jang, Malapaka Chandrasekharam, and Jae Hak Jung. "A New Series of EDOT Based Co-Sensitizers for Enhanced Efficiency of Cocktail DSSC: A Comparative Study of Two Different Anchoring Groups." Molecules 24, no. 19 (September 30, 2019): 3554. http://dx.doi.org/10.3390/molecules24193554.

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Herein, we report the design and synthesis strategy of a new class of five EDOT based co-sensitizers (CSGR1-5) by introducing different donors (2,3,4-trimethoxypheny, 2,4-dibutoxyphenyl, and 2,4-difluorophenyl) and anchoring groups (rhodamine-3-acetic acid and cyanoacetic acid) systematically. The synthesized metal-free organic co-sensitizers were employed for cocktail dye-sensitized solar cells along with N749 (black dye). The DSSC devices with a mixture of co-sensitizers (CSGR1-5) and N749 have shown a 7.95%, 8.40%, 7.81%, 6.56% and 6.99% power conversion efficiency (PCE) respectively, which was more than that of single N749 dye PCE (6.18%). Enhanced efficiency could be ascribed to the increased short circuit current (Jsc) and open circuit voltage (Voc). The increased Jsc was achieved due to enhanced light harvesting nature of N749 device upon co-sensitization with CSGR dyes and feasible energy levels of both the dyes. The Voc was improved due to better surface coverage which helps in decreasing the rate of recombination. The detailed optical and electrochemical properties were investigated and complimented with theoretical studies (DFT).
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29

Komal Kumar, V., S. K. Vishvakarma, R. C. Joshi, A. K. Saxena, and S. Dasgupta. "Small Signal Capacitance and Glitch Power Estimation of Nanoscale MGDG MOSFET Based Circuits: A Device/Circuit Co-Design Approach." Journal of Nanoelectronics and Optoelectronics 5, no. 1 (April 1, 2010): 72–78. http://dx.doi.org/10.1166/jno.2010.1068.

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30

Vaddi, Ramesh, S. Dasgupta, and R. P. Agarwal. "Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS." IEEE Transactions on Electron Devices 57, no. 3 (March 2010): 654–64. http://dx.doi.org/10.1109/ted.2009.2039529.

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31

Shaik, Sadulla. "Device-Circuit Interaction and Performance Benchmarking of Tunnel Transistor-Based Ex-OR Gates for Energy Efficient Computing." Journal of Circuits, Systems and Computers 29, no. 14 (June 30, 2020): 2050235. http://dx.doi.org/10.1142/s0218126620502357.

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This paper explores the design and analysis of 20[Formula: see text]nm tunnel transistor-based Exclusive-OR (Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy efficient and reliable computing architectures at scaled supply voltages (50–300[Formula: see text]mV). TFETs have attracted much attention recently for energy efficient system designs. The circuit interaction is made possible for designing more consistent functional architectures at the minimum power supply of 50–300[Formula: see text]mV. Using this technique, the core computational blocks of basic adder blocks and Ex-OR gates are designed with TFET as a fundamental device and the whole design procedure is elaborated in this paper. The primary classifications of Tunnel FETs, viz. Homo-junction TFET (HoJn TFET) and Hetero-junction TFETs (HeJn TFET) are investigated thoroughly under different constraints specifically at the device configurations. By considering the above-mentioned subtypes of TFETs, three variants of Ex-OR primitive gates are modeled and are named with respect to the use of transistors as static complementary TFET-12T (SC12T), Transmission Gate logic-8T (TG8T) and Improved Transmission Gate logic-6T (ITG6T) Ex-OR gate designs. The benchmarking of the proposed gates is done using double-gate Si FinFET at 20[Formula: see text]nm technology. Amongst all the three proposed Ex-OR designs of SC12T, TG8T and ITG6T in addition to that of LVT and HVT FinFET/CMOS, only ITG6T is the designer’s choice by offering the minimum power consumption as well as high energy, improved choice compared to the other two styles of designs and also when robustness and reliability are taken into account, SC12T and TG8T designs are not providing the full swing of outputs. The minute glitch with that of ITG6T designs is a lesser reliability feature and for this the best alternative is TFET TG8T by providing suppressed over shoots and enhanced transition speed. From the performed multi simulations under different critical conditions and at supply voltage of 100[Formula: see text]mV, it is being demonstrated that the energy efficient circuit option is the SC12T and ITG6T Ex-OR designs which are validated with the steep slope characteristics of TFET’s and also these two designs offer reliability advantage. The major restrictions from the energy efficiency issues are eliminated and disclosed in the HoJn TFETs and HeJn TFET by using circuit co-design methodology and TFETs steep slope characteristics.
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32

Angizi, Shaahin, Navid Khoshavi, Andrew Marshall, Peter Dowben, and Deliang Fan. "MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET." ACM Transactions on Design Automation of Electronic Systems 27, no. 2 (March 31, 2022): 1–18. http://dx.doi.org/10.1145/3484222.

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Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency ( EAT ) product on average by ~98% and ~70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.
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33

Aziz, Ahmedullah, Nikhil Shukla, Suman Datta, and Sumeet Kumar Gupta. "Steep Switching Hybrid Phase Transition FETs (Hyper-FET) for Low Power Applications: A Device-Circuit Co-design Perspective–Part I." IEEE Transactions on Electron Devices 64, no. 3 (March 2017): 1350–57. http://dx.doi.org/10.1109/ted.2016.2642884.

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34

Aziz, Ahmedullah, Nikhil Shukla, Suman Datta, and Sumeet Kumar Gupta. "Steep Switching Hybrid Phase Transition FETs (Hyper-FET) for Low Power Applications: A Device-Circuit Co-design Perspective—Part II." IEEE Transactions on Electron Devices 64, no. 3 (March 2017): 1358–65. http://dx.doi.org/10.1109/ted.2017.2650598.

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35

Liu, Shuang, Guangyao Wang, Tianshuo Bai, Kefan Mo, Jiaqi Chen, Wanru Mao, Wenjia Wang, Zihan Yuan, and Biao Pan. "Magnetic Skyrmion-Based Spiking Neural Network for Pattern Recognition." Applied Sciences 12, no. 19 (September 27, 2022): 9698. http://dx.doi.org/10.3390/app12199698.

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Spiking neural network (SNN) has emerged as one of the most powerful brain-inspired computing paradigms in complex pattern recognition tasks that can be enabled by neuromorphic hardware. However, owing to the fundamental architecture mismatch between biological and Boolean logic, CMOS implementation of SNN is energy inefficient. A low-power approach with novel “neuro-mimetic” devices offering a direct mapping to synaptic and neuronal functionalities is still an open area. In this paper, SNN constructed with novel magnetic skyrmion-based leaky-integrate-fire (LIF) spiking neuron and the skyrmionic synapse crossbar is proposed. We perform a systematic device-circuit-architecture co-design for pattern recognition to evaluate the feasibility of our proposal. The simulation results demonstrated that our device has superior lower switching voltage and high energy efficiency, two times lower programming energy efficiency in comparison with CMOS devices. This work paves a novel pathway for low-power hardware design using full-skyrmion SNN architecture, as well as promising avenues for implementing neuromorphic computing schemes.
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36

Borodin, Maksim Vladimirovich, Tatyana Anatolievna Kudinova, and Khasanov Shamil Rashidovich. "Fault indicators on the Russian market." E3S Web of Conferences 178 (2020): 01040. http://dx.doi.org/10.1051/e3sconf/202017801040.

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The article indicates the relevance of using fault indicators. Various models and manufacturers of fault indicators are presented on the Russian market. The analysis of the characteristics of various fault indicators was produced. At present, the most suitable domestic device for electric grid companies in Russia, which allows determining the open and short circuit on power lines, as well as indicating the location of the fault, is a fault indicator C134B of the ANTRAKS R&D&M Co, Ltd. The market analysis of fault indicators in Russia will allow specialists of design organizations, personnel of electric grid companies and other specialists to reduce the time spent on searching for information on fault indicators.
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37

Ren, Zhong, Qiu Lin Tan, Chen Li, Tao Luo, Ting Cai, and Ji Jun Xiong. "The Design and Simulation of Wide Range Pressure Sensor Based on HTCC for High-Temperature Applications." Key Engineering Materials 609-610 (April 2014): 1053–59. http://dx.doi.org/10.4028/www.scientific.net/kem.609-610.1053.

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A wide range pressure sensor is designed based on the theoretical basis of LC series resonance circuit model to realize the wireless passive measurement in the harsh environment, such as high temperature and high pressure. The capacitive pressure sensitive device is devised by the technology of high-temperature co-fired ceramics (HTCC) to form nine density cavities in zirconia ceramic substrates, and thick film technology to print capacitance plates and planar spiral inductors. The theoretical calculation and simulation analysis of the designed sensor are made respectively under high pressure (10MPa) and temperature (600 °C), the results of which verify the feasibility of the design in a wide range of pressure for high-temperature applications, and provide the reliable theory basis for the fabrication of wide range pressure sensor.
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Li, Kexin, and Shaloo Rakheja. "Modeling and Simulation of Quasi-Ballistic III-Nitride Transistors for RF and Digital Applications." International Journal of High Speed Electronics and Systems 28, no. 01n02 (March 2019): 1940011. http://dx.doi.org/10.1142/s0129156419400111.

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This paper presents a self-consistent analytic model to describe the current-voltage (I-V) and charge-voltage (Q-V) behavior of quasi-ballistic III-nitride transistors. We focus on two types of transistor geometries: (i) high electron mobility transistors (HEMTs) suitable for radio frequency (RF) applications and (ii) nanowire field-effect transistors (FETs) for digital applications. Our core model is based on Landauer transport theory which is combined with the calculation of charge density and velocity of charges at the top-of-the-barrier in the transistor. The effect of extrinsic device features, such as the nonlinearity of access regions and Joule heating at high currents, are included in the static I-V model. In the case of the dynamic Q-V model, we calculate intrinsic terminal charges by approximating the solution of the 2D Poisson equation in the channel over a broad bias range. The effect of fringing capacitances, prominently inner-fringing capacitance that varies nonlinearly with the gate bias, is included in our Q-V model. We amend the model electrostatics and the description of source/drain rectifying contacts in our core model to represent the I-V characteristics of III-nitride nanowire FETs. The model shows excellent match against experimentally and numerically measured characteristics of GaN transistors with gate lengths ranging from 42 nm to 274 nm. With only 38 input parameters, most of which are extracted based on straightforward device characterization, our model can be used for device-circuit co-design and optimization using a standard hierarchical circuit simulator.
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39

Labadie, Iris. "Advanced Ceramic Structures and Materials for High-Reliability Millimeter-Wave Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, CICMT (September 1, 2011): 000182–85. http://dx.doi.org/10.4071/cicmt-2011-wa22.

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Semiconductor device speeds and circuit operating frequencies have increased substantially over the past decade. Although millimeter-wave technology has been around for over 100 years, it is only within the past 5–10 years that increased demand for millimeter-wave commercial products and services has driven the development of new electronic package designs, low-loss materials, and the transformation of passive components to integrated and smaller geometries. High-reliability applications have employed millimeter-waves for several decades, but typically utilized heavy materials and distributed architectures. The transition of high-reliability millimeter-wave applications to new materials such as low-temperature co-fired ceramics requires innovative package designs to achieve comparable or better electrical performance in a much smaller form factor. Ceramic packaging technology continues to meet or exceed the performance requirements of high-reliability millimeter-wave applications with a broadened portfolio of material sets and innovative internal circuit components such as filter banks, antennas, and waveguides. Today's ceramic package design techniques and materials for applications within current and future high-reliability millimeter-wave markets will be discussed.
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40

Dabrowski, Arkadiusz, Karl Elkjaer, Louise Borregaard, Tomasz Zawada, and Leszek Golonka. "LTCC/PZT accelerometer in SMD package." Microelectronics International 31, no. 3 (August 4, 2014): 186–92. http://dx.doi.org/10.1108/mi-10-2013-0052.

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Purpose – The purpose of this paper is to develop the device made of low temperature co-fired ceramics (LTCC) and lead zirconate titanate (PZT) by co-firing both materials. In the paper, the technology and properties of a miniature uniaxial ceramic accelerometer are presented. Design/methodology/approach – Finite element method (FEM) is applied to predict properties of the sensor vs main dimensions of the sensor. The LTCC process is applied during manufacturing of the device. All the advantages of the technology are taken into account during designing three-dimensional structure of the sensor. The sensitivity and resonant frequency of the accelerometer are measured. Real material parameters of PZT are estimated according to measurement results and FEM simulations. Findings – The ceramic sensor integrated with SMD package with outer dimensions of 5 × 5 × 5 mm3 is manufactured. The accelerometer exhibits sensitivity of 0.75 pC/g measured at 100 Hz. The resonant frequency is equal to about 2 kHz. Useful frequency range is limited by 3 dB sensitivity change at about 1 kHz. Research limitations/implications – Sensitivity of the device is limited by interaction between LTCC and PZT materials during co-firing process. The estimated d parameters are ten times worse comparing to bulk Pz27 material. Further research on materials compatibility should be carried out. Practical implications – The sensor can be easily integrated into various devices made of standard electronic printed circuit boards (PCBs). Applied method of direct integration of piezoelectric transducers with LTCC material enables manufacturing of complex ceramic systems with built-in accelerometer in the substrate. Originality/value – The accelerometer is a sensor and a package simultaneously. The miniature ceramic device is compatible with surface mounting technology; hence, it can be used directly on PCBs for vibration monitoring inside electronic devices and systems.
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Zhang, Zijia, Jun Liu, and Yansong Li. "Design and Analysis of a Multi-Input Multi-Output System for High Power Based on Improved Magnetic Coupling Structure." Energies 15, no. 5 (February 24, 2022): 1684. http://dx.doi.org/10.3390/en15051684.

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Conventional inductive contactless power transfer (ICPT) systems have only one energy transmission path, which makes it challenging to meet the power transmission requirements of high-power and reliability. This study proposes a novel multiple-input multiple-output (MIMO) ICPT system. The three-dimensional finite element analysis tool COMSOL is utilised to study various magnetic coupling structures, analyse the influence of cross-coupling between coils on the same side, design the circuit based on this, propose a parameter configuration method for resonance compensation, and, finally, build an experimental platform with small magnetic coupling structures for single-input single-output systems (SISO) and MIMO systems. The results indicate that the co-directional connection of the coils of the E-shaped and UE-shaped magnetic coupling structures has a strengthening effect on the secondary side coupling. The magnetic coupling structure of the E-shaped iron core exhibits the best transmission performance. The transmission power of the MIMO system with the E-shaped magnetic coupling structure as the core device is significantly improved. In addition, the output power is unchanged after a secondary side fault, which verifies the accuracy of the proposed method.
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42

Bensalem, Yemna, and Mohamed Naceur Abdelkrim. "Modeling and Simulation of Induction Motor based on Finite Element Analysis." International Journal of Power Electronics and Drive Systems (IJPEDS) 7, no. 4 (December 1, 2016): 1100. http://dx.doi.org/10.11591/ijpeds.v7.i4.pp1100-1109.

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<p>This paper presents the development of a co-simulation platform of induction motor (IM). For the simulation, a coupled model is introduced which contains the control, the power electronics and also the induction machine. Each of these components is simulated in different software environments. So, this study provides an advanced modeling and simulation tools for IM which integrate all the components into one common simulation platform environment. In this work, the IM is created using Ansys-Maxwell based on Finite Element Analysis (FEA), whereas the power electronic converter is developed in Ansys-Simplorer and the control scheme is build in MATLAB-Simulink environment. Such structure can be useful for accurate design and allows coupling analysis for more realistic simulation. This platform is exploited to analyze the system models with faults caused by failures of different drive’s components. Here, two studies cases are presented: the first is the effects of a faulty device of the PWM inverter, and the second case is the influence of the short circuit of two stator phases. In order to study the performance of the control drive of the IM under fault conditions, a co-simulation of the global dynamic model has been proposed to analyze the IM behavior and control drives. In this work, the co-simulation has been performed; furthermore the simulation results of scalar control allowed verifying the precision of the proposed FEM platform.</p>
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43

Croce, Robert A., Santhisagar Vaddiraju, Allen Legassey, Fotios Papadimitrakopoulos, and Faquir C. Jain. "A Low-Power Miniaturized Microelectronic System for Continuous Glucose Monitoring." International Journal of High Speed Electronics and Systems 23, no. 01n02 (March 2014): 1450010. http://dx.doi.org/10.1142/s0129156414500104.

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The design and fabrication of miniaturized, implantable, low-power wireless systems for continuous glucose monitoring hold great promise for diabetes mellitus inflicted patients. This involves addressing a variety of issues including extreme circuit miniaturization, robust electrochemical sensors as well as counteracting negative tissue response and biofouling following sensor implantation. In this contribution, we present a highly miniaturized microelectronic sensor platform that fits through a hypodermic needle and holistically addresses all aforementioned tribulations. For this, a custom designed complementary metal-oxide-semiconductor electronic device employing the 0.35 µm design rule has been integrated with a high performance amperometric electrochemical glucose sensor. The fabricated electrochemical sensor utilizes the stratification of five functional layers resulting in linear amperometric response within the physiological glucose range (2 – 22mM). The sensor is encased with a thick polyvinyl alcohol (PVA) hydrogel containing poly (lactic-co-glycolic acid) (PLGA) microspheres which provides continuous, localized delivery of dexamethasone utilized to combat inflammation and fibrosis subsequent to implantation. In vivo evaluation in a rat has shown that this system accurately tracks glycemic events. Such miniature size and low power operation (0.665 mm2 and 140 µW, respectively) of the electronic system render it an ideal platform for continuous glucose monitoring and other metabolic sensing applications.
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44

Yu, Ho-Chieh (Jay), and Jason Huang. "The Direct plating copper (DPC) ceramic material on Al2O3/AlN or LTCC (Low-temperature co-fired ceramic) substrates." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (January 1, 2016): 001773–90. http://dx.doi.org/10.4071/2016dpc-wp46.

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RESEARCH BACKGROUND: The now used ceramic substrate or sub-mounted are normally based on Ag-printed, direct bonding copper (DBC) ceramic or LTCC (Low temperature co-fired ceramic)/HTCC (High temperature co-fired ceramic) technology.Due to the limit of the screen-printed process, the resolution and conducting material thickness the Ag-printed, LTCC and HTCC substrate are poor. The poor resolutions make these materials difficult to use in high density and flip-chip device design. And the related thinner conducting material (normally &lt;20um) limits the power rating of the design.DBC is now widely applied in power circuit design, however, duo to the copper lamination process requirement, more than 300um in thickness of copper layer is needed. Any lower copper thickness design should have an extra costly grind to reach. Also, the DBC material is difficult to provide to the multilayer trace design. OUR GOAL: We want to provide a solution with multilayer ceramic substrate for high power and high device density applications. Besides, the material properties, the adhesion of the metal/ceramic also be considered. Following are the material characteristics required for the development:A low electrical resistance material: Copper.A thick trace material thickness of more than 3 oz.A high thermal conductivity and stability ceramics with via-holes for TSV plating (Drilled Al2O3/AlN substrate ) or non- shrinking LTCC materialHigh metal trace resolution whose line width and space could be only 50 umWell metal/ceramic adhesion uniformity and strength is required: The voids between metal/ceramic &lt; 1%; The adhesion strength&gt; 2 kg/2*2mm2. METHODS & RESULTS: Metal trace plating: For high resolution and lower material electrical resistance request of the trace metal, we introduce electrical casting direct-plating copper (DPC) technology. The first copper is sputtered on the ceramic substrate using Ti as combined/buffer layer between copper and ceramic to provide good adhesion strength and stability. The second copper is made by electrical casting process to increase its thickness to 3 to 5 oz. (100~150um). The key technology of the metal trace plating is the material control of the sputter layers and the second copper layer stress release during plating. Multilayer Ceramic substrates: For double layers design, we use sintered Al2O3 or AlN substrates with electrical conducting via-holes design. The via-holes are made by laser drilling. And the conducting of the front and back side is connected by the following plating process. The key technology of this process is the stability of the via-holes. We have to make sure the via-holes cleaning, impurity removing and material variation during high temperature laser drilled is well controlled. For the more than three layers design, the non-shrinking LTCC is used. The dimension mismatch of the non-shrinking LTCC can controlled less than 100um., much better than that of normal LTCC/HTCC. By the correction of the following DPC process, the tolerance of the metal trace can be controlled &lt; 30 um. The key technology of this process is the non-shrinking LTCC technology and the adhesion of the DPC metal on LTCC material.
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45

Bermejo, Raul, Clemens Krautgasser, Marco Deluca, Martin Pletz, Peter Supancic, Franz Aldrian, and Robert Danzer. "Mechanical characterization of miniaturized functional substrates and components in different environments." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, CICMT (September 1, 2015): 000085–91. http://dx.doi.org/10.4071/cicmt-tp24.

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Functional components such as multilayer low temperature co-fired ceramics are examples of the combination of a ceramic-based substrate with internal electrodes as well as surface features (e.g. metallization, contacting pads, cylindrical vias, etc) employed to provide the component with a given functionality. Another example is that of functionalized silicon chips to be embedded into polymer circuit boards in order to enhance integration and save costs. The functionality of the system can be influenced by the mechanical reliability of the different components. Due to miniaturization and design complexity, no standard methods for mechanical testing can be applied for the characterization of these brittle components. In this work, an experimental approach is presented, which enables determining the strength distribution in functional components (e.g. rectangular plates as small as 2 × 2 × 0.1 mm3) in different environments at different temperatures. The method is based on localized biaxial testing using a ball-on-three-balls fixture. The high accuracy of the test allows quantifying the effect of surface quality, surface features and/or metallization (e.g. contact pads or cylindrical vias) on the component strength distribution. Experimental findings show that the strength distribution of ceramic components can be affected by environmental degradation, whereby subcritical crack growth phenomena can be enhanced in environments with high relative humidity. In addition, metallization at the surface subjected to tensile stresses can even raise the strength of the component, acting as a protective layer against environmental degradation, whereas cylindrical vias can become weak points in the design. It is shown that functionalized layers such as those used in silicon chips can have a significant effect on the strength parameters, thus influencing the lifetime of the device.
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46

Kitchen, Jennifer, Soroush Moallemi, and Sumit Bhardwaj. "Multi-chip module integration of Hybrid Silicon CMOS and GaN Technologies for RF Transceivers." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000339–82. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_tp1_010.

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Digital transceiver architectures offer the potential for achieving wireless hardware flexibility to frequency and modulation scheme for future-generation communications systems. Additionally, digital transmitters lend themselves to the use of switch-mode power amplifiers, which can have significantly higher efficiency than their linear counterparts. Two proposed architectures for realizing digital transmitters will be described in this work, both of which employ a hybrid combination of silicon integrated circuits (IC) and a power technology (e.g. GaN). This hybrid architecture takes advantage of the silicon to implement the high-complexity signal processing required for wireless communications, and uses power devices with high power density and low parasitic capacitance to sufficiently amplify the RF signals for transmission. Unfortunately, interfacing the low-power RF switching signals with off-chip high-power devices poses numerous design challenges, including: generation of integrated silicon power drivers with sufficient voltage swing for controlling power devices such as GaN, mitigation of on-chip current transients, wideband assembly interface from the silicon IC to the power device, and full system design verification using multiple process technologies. This work presents two CMOS driver architectures that can be used to interface low-power CMOS processing circuits with off-chip high-power devices. This work also details the performance limitations when assembling and interfacing multiple process technologies that are not co-located on the same IC. The main function of the driver circuitry within the digital transceiver system is to interface the low-power digital modulator to a large, high capacitance, off-chip power device. The driver must provide adequate transient current to charge/discharge the off-chip power devices' input capacitance through parasitic routing. Furthermore, the driver is designed to exhibit rise/fall times of less than 5% of the switching period and low jitter to meet RF signal quality requirements. Since silicon process technologies typically have much lower voltage breakdowns than those required to drive a power devie (e.g. GaN device), special driver architectures must be implemented to ensure the CMOS devices never exceed their breakdown voltages. Two architectures were implemented within this work to simultaneously achieve RF switching speeds and 5V signal swing from a 0.9V silicon CMOS process technology. The two architectures are: 1) a House-of-Cards configuration, and 2) a Cascode topology. These architectures will be detailed and compared with respect to performance in this presentation. Two of the most common techniques to assemble and connect a silicon IC, which includes the driver circuitry, and a (GaN) power device are: 1) direct wire bonding or flip-chip connection from the IC to the GaN, and 2) connection through a board or package interface circuit. Since most high-performance RF power devices such as GaN have negative threshold voltage, the driver (CMOS) IC must either: 1) have a supply and ground that are shifted to negative voltage values, or 2) decouple the IC's output from the GaN device's input in order to properly control the GaN. Off-chip decoupling is more easily implemented, but may limit maximum operating frequencies due to the added interface network and board/module parasitics. This work shall detail the interface models and compare the assembly procedures and potential performance limits when using both of these most common assembly techniques.
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47

Noorsal, Emilia, Asyraf Rongi, Intan Rahayu Ibrahim, Rosheila Darus, Daniel Kho, and Samsul Setumin. "Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model." Micromachines 13, no. 2 (January 25, 2022): 179. http://dx.doi.org/10.3390/mi13020179.

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Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (±360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.
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48

Kutluyarov, R. V., D. M. Fatkhiev, I. V. Stepanov, E. P. Grakhova, V. S. Lyubopytov, and A. Kh Sultanov. "Design and modeling of a photonic integrated device for optical vortex generation in a silicon waveguide." Computer Optics 45, no. 3 (June 2021): 324–30. http://dx.doi.org/10.18287/2412-6179-co-850.

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We propose and numerically verify a design of the photonic integrated circuit for in-plane generation of a 1st azimuthal order vortex mode in dielectric rectangular waveguides. Radiation is introduced into the proposed structure in a standard way through two grating couplers. Applying a mode coupling and specific phase shift, a field with the required amplitude-phase distribution is formed directly in the output waveguide. The geometric dimensions of the device are simulated and optimized to fit the technological parameters of the silicon-on-insulator platform.
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49

Griol, Amadeu, Sergio Peransi, Manuel Rodrigo, Juan Hurtado, Laurent Bellieres, Teodora Ivanova, David Zurita, et al. "Design and Development of Photonic Biosensors for Swine Viral Diseases Detection." Sensors 19, no. 18 (September 15, 2019): 3985. http://dx.doi.org/10.3390/s19183985.

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In this paper we introduce a field diagnostic device based on the combination of advanced bio-sensing and photonics technologies, to tackle emerging and endemic viruses causing swine epidemics, and consequently significant economic damage in farms. The device is based on the use of microring resonators fabricated in silicon nitride with CMOS compatible techniques. In the paper, the designed and fabricated photonic integrated circuit (PIC) sensors are presented and characterized, showing an optimized performance in terms of optical losses (30 dB per ring) and extinction ration for ring resonances (15 dB). Furthermore, the results of an experiment for porcine circovirus 2 (PCV2) detection by using the developed biosensors are presented. Positive detection for different virus concentrations has been obtained. The device is currently under development in the framework of the EU Commission co-funded project SWINOSTICS.
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50

Booth, James C., Nathan Orloff, Christian Long, Aaron Hagerstrom, Angela Stelson, Nicholas Jungwirth, and Luckshitha Suriyasena Liyanage. "(Invited, Digital Presentation) Nonlinear and Electro-Thermo-Mechanical Effects in Heterogeneous Electronics at Microwave Frequencies." ECS Meeting Abstracts MA2022-02, no. 17 (October 9, 2022): 862. http://dx.doi.org/10.1149/ma2022-0217862mtgabs.

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Materials properties are an essential component for the accurate modeling of integrated devices and circuits. The accuracy of such models depends explicitly on the accuracy of the input material parameters and interfaces between them. With the trend toward increasing heterogeneous integration, the relationships between electromagnetic, thermal, and mechanical material properties of heterogeneously integrated devices are even more important. Recent trends toward co-design emphasize the optimization of all aspects of circuit performance from the beginning, rather than sequentially optimizing the electromagnetic, thermal, mechanical characteristics. It can be critical for modeling success to understand, for example, where losses due to an electromagnetic signal are significant, as those losses can lead to energy dissipation with the subsequent temperature rise being a function of local thermal properties such as the thermal conductivity and heat capacity. Beyond losses, nonuniform temperature distributions generate mechanical stress that can impact interfaces between materials with dissimilar coefficients of thermal expansion. Furthermore, change in temperature and stress can lead to changes in the linear electromagnetic properties, resulting in changes in signal propagation and the generation of nonlinear effects. Material properties are also important as they connect device response to underlying materials physics. This connection allows one to exploit different physical phenomena to add functionality at materials level, and to understand and mitigate non-idealities such as nonlinear response. As such, it is critically important to quantify nonlinear electromagnetic and electro-thermo-mechanical properties of heterogeneous integrated devices. In Fig. 1, the Heckmann diagram shows the electro-thermo-mechanical relations in a crystal, where T, S, E, D, θ, and σ are stress, strain, electric field, electric displacement, temperature, and entropy, respectively. This diagram illustrates the various nonlinear interactions that can be important for determining the overall response of microelectronic devices composed of a wide range of material systems. Here, we present an overview of experimental efforts designed to accurately characterize the linear electromagnetic properties of materials relevant for microelectronics, including dielectrics and conductors as a function of frequency from 100 kHz through 220 GHz. Dispersion and absorption imply frequency dependence of complex quantities such as the dielectric permittivity and magnetic permeability, and this in turn necessitates broadband characterization techniques. We describe efforts to characterize broadband frequency-dependent linear electromagnetic properties over a wide range of temperatures, including cryogenic temperatures relevant for quantum computing, and augment these techniques with approaches to characterize the relevant thermal material parameters. We then describe measurements of nonlinear response of different material systems to quantify the nonlinear relationships between different thermodynamic fields in integrated structures. We conclude with a discussion of the needs for additional metrology to characterize these complex interactions inside complex 3D and packaged microelectronic devices and at buried interfaces within these heterogeneous integrated structures. Figure 1
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