Relevant bibliographies by topics / Device-circuit co-design

Academic literature on the topic 'Device-circuit co-design'

Author: Grafiati
Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Device-circuit co-design"

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Maheshwaram, Satish, S. K. Manhas, Gaurav Kaushal, Bulusu Anand, and Navab Singh. "Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform." IEEE Electron Device Letters 33, no. 7 (July 2012): 934–36. http://dx.doi.org/10.1109/led.2012.2197592.

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Aziz, Ahmedullah, and Sumeet Kumar Gupta. "Threshold Switch Augmented STT MRAM: Design Space Analysis and Device-Circuit Co-Design." IEEE Transactions on Electron Devices 65, no. 12 (December 2018): 5381–89. http://dx.doi.org/10.1109/ted.2018.2873738.

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Gupta, Sumeet Kumar, and Kaushik Roy. "Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs." IEEE Design & Test 30, no. 6 (December 2013): 29–39. http://dx.doi.org/10.1109/mdat.2013.2266394.

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Andric, Stefan, Lars Ohlsson Fhager, and Lars-Erik Wernersson. "Millimeter-Wave Vertical III-V Nanowire MOSFET Device-to-Circuit Co-Design." IEEE Transactions on Nanotechnology 20 (2021): 434–40. http://dx.doi.org/10.1109/tnano.2021.3080621.

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Liu, Jen-Chieh, Tzu-Yun Wu, and Tuo-Hung Hou. "Optimizing Incremental Step Pulse Programming for RRAM Through Device–Circuit Co-Design." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 5 (May 2018): 617–21. http://dx.doi.org/10.1109/tcsii.2018.2821268.

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Agarwal, Tarun, Gianluca Fiori, Bart Soree, Iuliana Radu, Marc Heyns, and Wim Dehaene. "Material-Device-Circuit Co-Design of 2-D Materials-Based Lateral Tunnel FETs." IEEE Journal of the Electron Devices Society 6 (2018): 979–86. http://dx.doi.org/10.1109/jeds.2018.2827164.

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Feng, Shi-Yu, Yong-Bo Su, Peng Ding, Jing-Tao Zhou, Song-Ang Peng, Wu-Chang Ding, and Zhi Jin. "Extrinsic equivalent circuit modeling of InP HEMTs based on full-wave electromagnetic simulation." Chinese Physics B 31, no. 4 (April 1, 2022): 047303. http://dx.doi.org/10.1088/1674-1056/ac2b1d.

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With the widespread utilization of indium-phosphide-based high-electron-mobility transistors (InP HEMTs) in the millimeter-wave (mmW) band, the distributed and high-frequency parasitic coupling behavior of the device is particularly prominent. We present an InP HEMT extrinsic parasitic equivalent circuit, in which the conductance between the device electrodes and a new gate–drain mutual inductance term L mgd are taken into account for the high-frequency magnetic field coupling between device electrodes. Based on the suggested parasitic equivalent circuit, through HFSS and advanced design system (ADS) co-simulation, the equivalent circuit parameters are directly extracted in the multi-step system. The HFSS simulation prediction, measurement data, and modeled frequency response are compared with each other to verify the feasibility of the extraction method and the accuracy of the equivalent circuit. The proposed model demonstrates the distributed and radio-frequency behavior of the device and solves the problem that the equivalent circuit parameters of the conventional InP HEMTs device are limited by the device model and inaccurate at high frequencies when being extracted.
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Yadav, Sameer, P. N. Kondekar, Pranshoo Upadhyay, and Bhaskar Awadhiya. "Negative capacitance based phase-transition FET for low power applications: Device-circuit co-design." Microelectronics Journal 123 (May 2022): 105411. http://dx.doi.org/10.1016/j.mejo.2022.105411.

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Kumar, Amresh, and Aminul Islam. "Multi-gate device and summing-circuit co-design robustness studies @ 32-nm technology node." Microsystem Technologies 23, no. 9 (July 6, 2016): 4099–109. http://dx.doi.org/10.1007/s00542-016-3055-4.

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Raychowdhury, A., B. C. Paul, S. Bhunia, and K. Roy. "Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 11 (November 2005): 1213–24. http://dx.doi.org/10.1109/tvlsi.2005.859590.

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Dissertations / Theses on the topic "Device-circuit co-design"

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(7025126), Ahmedullah Aziz. "Device-Circuit Co-Design Employing Phase Transition Materials for Low Power Electronics." Thesis, 2019.

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Phase transition materials (PTM) have garnered immense interest in concurrent post-CMOS electronics, due to their unique properties such as - electrically driven abrupt resistance switching, hysteresis, and high selectivity. The phase transitions can be attributed to diverse material-specific phenomena, including- correlated electrons, filamentary ion diffusion, and dimerization. In this research, we explore the application space for these materials through extensive device-circuit co-design and propose new ideas harnessing their unique electrical properties. The abrupt transitions and high selectivity of PTMs enable steep (< 60 mV/decade) switching characteristics in Hyper-FET, a promising post-CMOS transistor. We explore device-circuit co-design methodology for Hyper-FET and identify the criterion for material down-selection. We evaluate the achievable voltage swing, energy-delay trade-off, and noise response for this novel device. In addition to the application in low power logic device, PTMs can actively facilitate non-volatile memory design. We propose a PTM augmented Spin Transfer Torque (STT) MRAM that utilizes selective phase transitions to boost the sense margin and stability of stored data, simultaneously. We show that such selective transitions can also be used to improve other MRAM designs with separate read/write paths, avoiding the possibility of read-write conflicts. Further, we analyze the application of PTMs as selectors in cross-point memories. We establish a general simulation framework for cross-point memory array with PTM based selector. We explore the biasing constraints, develop detailed design methodology, and deduce figures of merit for PTM selectors. We also develop a computationally efficient compact model to estimate the leakage through the sneak paths in a cross-point array. Subsequently, we present a new sense amplifier design utilizing PTM, which offers built-in tunable reference with low power and area demand. Finally, we show that the hysteretic characteristics of unipolar PTMs can be utilized to achieve highly efficient rectification. We validate the idea by demonstrating significant design improvements in a Cockcroft-Walton Multiplier, implemented with TS based rectifiers. We emphasize the need to explore other PTMs with high endurance, thermal stability, and faster switching to enable many more innovative applications in the future.

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Book chapters on the topic "Device-circuit co-design"

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Alarcón, Eduard. "Vertical Co-design and Integration in Energy Harvesting: from Device, Circuit and System Levels to IoT Applications." In Power Management for Internet of Everything, 265–87. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003339106-10.

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Conference papers on the topic "Device-circuit co-design"

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Pajouhi, Zoha, Xuanyao Fong, and Kaushik Roy. "Device/Circuit/Architecture Co-Design of Reliable STT-MRAM." In Design, Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2015. http://dx.doi.org/10.7873/date.2015.0145.

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Jintae Kim, Ritesh Jhaveri, Jason Woo, and Chih-Kong Ken Yang. "Device-circuit co-optimization for mixed-mode circuit design via geometric programming." In 2007 IEEE/ACM International Conference on Computer-Aided Design. IEEE, 2007. http://dx.doi.org/10.1109/iccad.2007.4397309.

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Pandey, Archana, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, Sanjeev Kumar Manhas, and Anand Bulusu. "FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay." In 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID). IEEE, 2016. http://dx.doi.org/10.1109/vlsid.2016.15.

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Dasgupta, S., and B. Anand. "Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges." In 2015 28th International Conference on VLSI Design (VLSID). IEEE, 2015. http://dx.doi.org/10.1109/vlsid.2015.114.

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Wang, Junyao, Xiaobo Jiang, Xingsheng Wang, Runsheng Wang, Binjie Cheng, Asen Asenov, Lan Wei, and Ru Huang. "Variation-aware energy-delay optimization method for device/circuit co-design." In 2015 China Semiconductor Technology International Conference (CSTIC). IEEE, 2015. http://dx.doi.org/10.1109/cstic.2015.7153331.

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Jimenez, Manuel, Juan Nunez, and Maria Jose Avedillo. "An Approach to the Device-Circuit Co-Design of HyperFET Circuits." In 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2020. http://dx.doi.org/10.1109/iscas45731.2020.9180660.

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Chen, Wangyong, Linlin Cai, Gang Du, and Xiaoyan Liu. "Efficient Variability- and Reliability-aware Device-Circuit Co-Design: From Trap Behaviors to Circuit Performance." In 2019 IEEE International Electron Devices Meeting (IEDM). IEEE, 2019. http://dx.doi.org/10.1109/iedm19573.2019.8993640.

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Lu, Lu, Ju Eon Kim, Vishal Sharma, and Tony Tae-Hyoung Kim. "ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology." In 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2020. http://dx.doi.org/10.1109/apccas50809.2020.9301707.

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George, Sumitha, Ahmedullah Aziz, Xueqing Li, Moon Seok Kim, Suman Datta, John Sampson, Sumeet Gupta, and Vijaykrishnan Narayanan. "Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors." In 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2016. http://dx.doi.org/10.1109/isvlsi.2016.116.

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Mojumder, Niladri N., S. C. Song, Joseph Wang, Ken Lin, Ken Rim, Jeff Xu, and Geoffrey Yeap. "Novel Critical Path Aware transistor optimization for mobile SoC device-circuit co-design." In 2014 IEEE Symposium on VLSI Technology. IEEE, 2014. http://dx.doi.org/10.1109/vlsit.2014.6894379.

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