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Journal articles on the topic 'Delta sigma data converter'

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Author: Grafiati

Published: 10 December 2022

Last updated: 28 January 2023

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1

Galton, Ian, Richard Schreier, and Gabor C. Temes. "Book review: Delta-Sigma data converters." IEEE Solid-State Circuits Society Newsletter 10, no. 3 (September 2005): 5–6. http://dx.doi.org/10.1109/n-ssc.2005.6500102.

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2

Palumbo, G. "Understanding Delta- Sigma Data Converters [Book Review]." IEEE Circuits and Devices Magazine 22, no. 4 (July 2006): 31–32. http://dx.doi.org/10.1109/mcd.2006.1708376.

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3

Yang, Fuwen, and Mahbub Gani. "Robust Calibration of an Improved Delta-Sigma Data Converter Using Convex Optimization." IEEE Journal of Selected Topics in Signal Processing 1, no. 4 (December 2007): 678–85. http://dx.doi.org/10.1109/jstsp.2007.910280.

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4

NERURKAR, SHAILESH B., and KHALID H. ABED. "A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 407–29. http://dx.doi.org/10.1142/s0218126609005149.

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This paper presents a design of a novel cascaded third-order feed-forward delta-sigma analog-to-digital converter (ADC). This ADC is realized using fully differential switched capacitor architecture and produces a 12-bit resolution at a data output rate (DOR) of 2.5 MS/s for RF wireless applications. The delta-sigma modulator consists of a second-order single-bit feed-forward modulator cascaded with a multi-bit first-order modulator. The cascaded feed-forward third-order (2-1) ADC is simulated using Matlab and Simulink. The delta-sigma modulator was designed using Cadence Virtuoso in TSMC 0.18 μm CMOS technology. The power consumption of the designed modulator is 12.74 mW, and the resolution is 11.85 bits for an over-sampling ratio (M = 32). The figure of merit is 1.38 pJ at a sample rate of 80 MS/s. The proposed delta-sigma modulator is compared with other state-of-the-art low-pass delta-sigma modulators in terms of their speed, power, DOR, and the proposed modulator has one of the lowest power consumption.

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5

DOLEV, NOAM, AVNER KORNFELD, and AVINOAM KOLODNY. "COMPARISON OF SIGMA–DELTA CONVERTER CIRCUIT ARCHITECTURES IN DIGITAL CMOS TECHNOLOGY." Journal of Circuits, Systems and Computers 14, no. 03 (June 2005): 515–32. http://dx.doi.org/10.1142/s0218126605002507.

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Integration of analog-to-digital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which have been presented in the literature, consisting of discrete-time and continuous-time integration in voltage-mode and in current-mode. For high resolution, superiority of switched-capacitor circuits over the alternatives is shown, based on process technology considerations. Design guidelines are outlined for selecting oversampling rate and other key parameters, in order to obtain maximal data resolution.

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6

Morozov, D. V., M. M. Pilipko, and A. S. Korotkov. "Delta-sigma modulator of the analog-to-digital converter with ternary data encoding." Russian Microelectronics 40, no. 1 (January 2011): 59–69. http://dx.doi.org/10.1134/s1063739710061034.

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7

Herkle, Andreas, Joachim Becker, and Maurits Ortmanns. "Exploiting Weak PUFs From Data Converter Nonlinearity—E.g., A Multibit CT $\Delta\Sigma$ Modulator." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 7 (July 2016): 994–1004. http://dx.doi.org/10.1109/tcsi.2016.2555238.

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8

Morozov, D. V., M. M. Pilipko, and A. S. Korotkov. "Decimation filter of the delta-sigma analog-to-digital converter with ternary data encoding." Russian Microelectronics 40, no. 5 (September 2011): 352–60. http://dx.doi.org/10.1134/s1063739711050064.

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9

Osawa, Yusuke, Daiki Hirabayashi, Naohiro Harigai, Haruo Kobayashi, Osamu Kobayashi, Masanobu Tsuji, Sadayoshi Umeda, et al. "Phase Noise Measurement and Testing with Delta-Sigma TDC." Key Engineering Materials 643 (May 2015): 149–55. http://dx.doi.org/10.4028/www.scientific.net/kem.643.149.

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This paper describes a phase noise measurement and testing technique for a clock using a delta-sigma time-to-digital converter (TDC) and verifies its effectiveness with MATLAB simulations. The proposed technique can be implemented with relatively small circuitry, based on the following: (i) The clock under test (CUT) is a repetitive signal. (ii) The time resolution with CUT and a reference clock can be finer with longer measurement time with the delta-sigma TDC. (iii) The phase noise power spectrum can be calculated from the delta-sigma TDC output data using FFT. High performance spectrum analyzers with long measurement time (several ten seconds order due to average of several-time phase measurement results), which are very costly in mass production testing, are not be needed for phase noise measurement with the proposed technique. Our simulation used the input clock of 1 MHz in several phase fluctuation cases, and we observed that the phase fluctuation spectrum at the expected frequency from TDC output power spectrum obtained by FFT. We also investigated the amount of phase fluctuation with our theoretical calculation, which agrees with the simulation results.

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10

Nahar, Ali Kareem, and Hussain K. Khleaf. "Delta-sigma ADC modulator for multibit data converters using passive adder entrenched second order noise shaping." Bulletin of Electrical Engineering and Informatics 10, no. 4 (August 1, 2021): 1952–59. http://dx.doi.org/10.11591/eei.v10i4.2934.

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This paper introduces a multi-bit data converters (MDC) modulator of the 2nd order delta-sigma analog-to-digital converter use the passive adder proposed. The noise shaping quantizer can provide feedback that has generated quantization noise and perform additional shaping noise first-order by coupling noise method.Thus, two Integrator's with ring amplifier and the MDC is shaped by noise coupling quantizer know the 2nd-order noise coupled with somewhat of a DAC modulator. At a summing point, the inputs are summed and then filtered with a low pass filter. A cyclic second order response is generated with a data weighted averaging (DWA) technique in which the DACs ' outputs are limited to one of two states in the noise shaping responses. Mainly as a result of the harmonic distortion in circuits of amplifier. Transistor rate is equipped for the fully differential switched condenser integrator used, a comparator and DWA. The modulator with proposed DWA design, almost quarterly improved timing margin. A simulated SNDR of 92dB is obtained at 20 MHz sampling frequency; while a sinusoidal output of 4.112 dBFS is tested at 90µs besides 20 MHz as the bandwidth. The power consumption is 0.33 mW while the voltage of the supply is 1.2V.

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11

Duggal, Ashwin R., Sameer Sonkusale, and John Lachapelle. "Calibration of Delta-Sigma Data Converters in Synchronous Demodulation Sensing Applications." IEEE Sensors Journal 11, no. 1 (January 2010): 16–22. http://dx.doi.org/10.1109/jsen.2010.2047012.

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12

Pavan, Shanthi, and Raviteja Theertham. "Improved Offline Calibration of DAC Mismatch Errors in Delta–Sigma Data Converters." IEEE Transactions on Circuits and Systems II: Express Briefs 66, no. 10 (October 2019): 1618–22. http://dx.doi.org/10.1109/tcsii.2019.2921777.

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13

Gao, Bo, Xin Li, Jie Sun, and Jianhui Wu. "Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM." Electronics 9, no. 1 (January 10, 2020): 137. http://dx.doi.org/10.3390/electronics9010137.

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The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.

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14

Zhang, Ai Qin, Han Cheng Liu, Yi Hu, Hang Chen, and Zhi Xu. "A Portable ECG Monitor with High Resolution Based on Cortex-M3." Advanced Materials Research 753-755 (August 2013): 2489–93. http://dx.doi.org/10.4028/www.scientific.net/amr.753-755.2489.

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In this paper we designed a portable ECG monitoring system based on Cortex-M3. The system was composed of the microcontroller LPC1788 and the analog front-end ADS1298 which provided a low-noise, 8-channel, 24-bit delta-sigma analog-to-digital converter. The monitor used SD card for data storage and USB for data transmission, which was capable of monitoring both dynamic ECG and conventional ECG. The system could work up to 24 hours with a resolution of 24 bits and 1024Hz sampling rate. The designed system embodies several characteristics including portability, low power, large capacity, and high resolution, which are quite suitable for ECG monitoring.

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15

Lin, YiQiao, and Mohammed Ismail. "Time-based all-digital sigma–delta modulators for nanometer low voltage CMOS data converters." Analog Integrated Circuits and Signal Processing 73, no. 3 (July 1, 2012): 801–8. http://dx.doi.org/10.1007/s10470-012-9901-0.

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16

Nahar, Ali Kerem, Ansam Subhi Jaddar, Hussain K. Khleaf, and Mohmmed Jawad Mortada Mobarek. "Second order noise shaping for data-weighted averaging technique to improve sigma-delta DAC performance." International Journal of Advances in Applied Sciences 10, no. 1 (March 1, 2021): 79. http://dx.doi.org/10.11591/ijaas.v10.i1.pp79-87.

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<p>In general, the noise shaping responses, a cyclic second order response is delivered by the method of data weighted averaging (DWA) in which the output of the digital-to-analog convertor (DAC) is restricted to one of two states. DWA works efficiently for rather low levels of quantizing; it begins presenting considerable difficulties when internal levels of quantizing are extended further. Though, each added bit of internal quantizing causes an exponentially increasing in power dissipation, complexity and size of the DWA logic and the DAC. This gives a controlled seconnd order response accounting for the mismatch of the elements of DAC. The multi-bit DAC is made up of numerous single-bit DACs having values thereof chosen via a digital encoder. This research presents a discussion of the influence of mismatching between unit elements of the Delta-Sigma DAC. This results in a constrained second order response accounting for mismatch of DAC elements. The results of the simulation showed how the effectiveness of DWA method is in reducing band tones. Furthermore, DWA method has proved its efficiency in solving the mismatching of DAC unit elements. The noise of the mismatching elements is enhanced 11 dB at 0.01 with the proposed DWA, thereby enhancing the efficiency of the DAC in comparison to the efficiency of the DAC with no use of the circuit of DWA</p>

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17

Samadpoor Rikan, Behnam, Sang-Yun Kim, Nabeel Ahmad, Hamed Abbasizadeh, Muhammad Riaz Ur Rehman, Khuram Shehzad, Arash Hejazi, Reza E. Rad, Deeksha Verma, and Kang-Yoon Lee. "A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR." Sensors 18, no. 12 (November 30, 2018): 4199. http://dx.doi.org/10.3390/s18124199.

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This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

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18

Kalafat Kizilkaya, Isil, Mohammed Al-Janabi, and Izzet Kale. "Design and implementation of novel FPGA based time-interleaved variable centre-frequency digital Î£âˆ’Î” modulators." ACTA IMEKO 4, no. 1 (February 5, 2015): 68. http://dx.doi.org/10.21014/acta_imeko.v4i1.165.

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Multiresolution analog-to-digital converters (MRADC) are usually used in Time Domain ElectroMagnetic Interference (TDEMI) measuring systems for very fast signal sampling with a sufficient dynamic range. The properties of the spectrum measured by the TDEMI system influenced by imperfections in the MRADC are analyzed in this paper. Errors are caused by imperfect matching of the offset and gain and phase of the circuits used in parallel input channels typical for the MRADC. For deep analyses of MRADC behavior, a precise mathematical model has been created using the concept of additive error pulses. Furthermore, a dedicated process of the identification of discrepancy parameters from experimental data is proposed. Identified parameters enter the expressions of the model and enable side to side comparison of experimental and theoretical results.Novel, multi-path, time-interleaved digital sigma-delta modulators that can operate at any arbitrary frequency from DC to Nyquist are designed, analysed and synthesized in this study. Dual- and quadruple-path fourth-order Butterworth, Chebyshev, Inverse Chebyshev and Elliptical based digital sigma-delta modulators, which offer designers the flexibility of specifying the centre-frequency, pass-band/stop-band attenuation as well as the signal bandwidth are presented. These topologies are compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity to non-idealities. Detailed simulations performed at the behavioural-level in MATLAB are compared with the experimental results of the FPGA implementation of the designed modulators. The signal-to-noise ratios between the simulated and empirical results are shown to be different by not more than 3-5 dBs. Furthermore, this paper presents the mathematical modelling and evaluation of the tones caused by the finite wordlengths of these digital multi-path sigma-delta modulators when excited by sinusoidal input signals.

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19

Wu, Chia-Yi, Haolin Li, Joris Van Kerrebrouck, Caro Meysmans, Piet Demeester, and Guy Torfs. "A Bit-Interleaved Sigma-Delta-Over-Fiber Fronthaul Network for Frequency-Synchronous Distributed Antenna Systems." Applied Sciences 11, no. 23 (December 3, 2021): 11471. http://dx.doi.org/10.3390/app112311471.

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Cell-free massive multiple-input multiple-output (MIMO) has attracted wide attention as wireless spectral efficiency has become a 6G key performance indicator. The distributed scheme improves the spectral efficiency and user fairness, but the fronthaul network must evolve to enable it. This work demonstrates a fronthaul network for distributed antenna systems enabled by the bit-interleaved sigma-delta-over-fiber (BISDoF) concept: multiple sigma-delta modulated baseband signals are time-interleaved into one non-return-to-zero (NRZ) signal, which is converted to the optical domain by a commercial QSFP and transmitted over fiber. The BISDoF concept improves the optical bit-rate efficiency while keeping the remote unit complexity sufficiently low. The implementation successfully deals with an essential challenge—precise frequency synchronization of different remote units. Moreover, owing to the straightforward data paths, all transceivers inherently transmit or receive with fixed timing offsets which can be easily calibrated. The error vector magnitudes of both the downlink and uplink data paths are less than 2.8% (–31 dB) when transmitting 40.96 MHz-bandwidth OFDM signals (256-QAM) centered around 3.6 GHz. (Optical path: 100 m multi-mode fibers; wireless path: electrical back-to-back.) Without providing an extra reference clock, the two remote units were observed to have the same carrier frequency; the standard deviation of the relative jitter was 9.43 ps.

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20

Hu, Pengfei, Li Shen, Feng Han, Fei Yang, Maojiang Song, Li Zhang, and Liping Liu. "Development of the data acquisition system for terahertz spectrometer." Transactions of the Institute of Measurement and Control 40, no. 3 (April 6, 2017): 805–11. http://dx.doi.org/10.1177/0142331217690475.

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In most Terahertz time-domain spectrometer (THz-TDS) experiments, the lock-in amplifier works with trans-impedance pre-amplifier to amplitude the terahertz pulse accepted from detector. This paper discusses the development of data acquisition system for the transmission THz-TDS. In this system, the cross-correlation software algorithm in SR830 lock-in amplifier from Stanford Research Systems, that is usually used in THz-TDS, has been replaced by parallel hardware algorithm of Field Programmable Gate Array (FPGA) chip with the parallel processing ability. This chip has a faster processing speed and higher accuracy than others. A 24 bit Delta-Sigma Analog Digital (AD) was used in place of the 16 bit successive approximation ADC of SR830. The new AD convertor can reduce the complexity of trans-impedance pre-amplifier circuit and replace the SR555 current amplifiers that designed to work with SRS lock-in amplifiers. Besides trans-impedance pre-amplifier circuit, all function circuits, such as low-pass digital filter, phase-locked loop, Direct Digital Synthesis (DDS) reference source and the core algorithms, are integrated in a FPGA chip, which make the new designed lock-in amplifier with a small volume reduce a dozen times SR830 size.

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21

K., Shahana T., Babita R. Jose, Rekha K. James, K. Poulose Jacob, and Sreela Sasi. "RNS based Programmable Decimation Filter for Multi-Standard Wireless Transceivers." ECTI Transactions on Electrical Engineering, Electronics, and Communications 6, no. 2 (December 25, 2007): 148–57. http://dx.doi.org/10.37936/ecti-eec.200862.171781.

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Current research on radio frequency transceivers focuses on multi-standard architectures to attain higher system capacities and data rates. Multiple communication standards are made adaptable by performing channel select filtering on chip at baseband in digital domain. The computationally intensive decimation filter in a sigma-delta analog-to-digital converter plays an important role in channel selection for multi-mode systems. As these architectures are targeted for portable applications, an area and power efficient recon¯gurable implementation is animplicit requirement. To this end, a multi-stage, programmable decimation ¯lter based on residue number system (RNS) that is adaptable for WCDMA and WLAN standards is presented in this research. Multi-stage decimation filter implementation offers low computational complexity and power dissipation. The FIR filters of the multi-stage decimator operating in RNS domain offers high data rate because of the carry free operations on smaller residues in parallel channels. Further power saving is achieved by reconfiguring the hardware architecture, and powering down the unused blocks in each mode of operation. For increased programmability modulo multifiplication is performed by index addition utilizing the arithmetic benefits associated with Galois ¯eld. Finally, a performance comparison of the proposed RNS based decimation ¯lter with traditional binary implementation is done in terms of area, critical path delay and power dissipation.

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22

Würfel, D., M. Ruß, R. Lerch, D. Weiler, P. Yang, and H. Vogt. "An uncooled VGA-IRFPA with novel readout architecture." Advances in Radio Science 9 (July 29, 2011): 107–10. http://dx.doi.org/10.5194/ars-9-107-2011.

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Abstract. An uncooled VGA Infrared Focal Plane Array (IRFPA) based on microbolometers with a pixel pitch of 25 μm for thermal imaging applications is presented. The IRFPA has a 16-bit digital video data output at a frame rate of 30 Hz. Thousands of Analog to Digital Converters (ADCs) are located under the microbolometer array. One ADC consists of a Sigma-Delta-Modulator (SDM) of 2nd order and a decimation filter. It is multiplexed for a certain amount of microbolometers arranged in a so called "cluster". In the 1st stage of the SDM the microbolometer current is integrated time-continuously. The feedback is applied using a switchable current source. First measurements of Noise Equivalent Temperature Difference (NETD) as a key parameter for IRFPAs will be presented.

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23

Pallarés-López, Víctor, Rafael Jesús Real-Calvo, Silvia del Rio Jiménez, Miguel González-Redondo, Isabel Moreno-García, and Isabel Santiago. "Monitoring of Energy Data with Seamless Temporal Accuracy Based on the Time-Sensitive Networking Standard and Enhanced µPMUs." Applied Sciences 11, no. 19 (September 30, 2021): 9126. http://dx.doi.org/10.3390/app11199126.

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In the energy sector, distributed synchronism and a high degree of stability are necessary for all real-time monitoring and control systems. Instantaneous response to critical situations is essential for the integration of renewable energies. The most widely used standards for clock synchronisation, such as Network Time Protocol (NTP) and Precision Time Protocol (PTP), do not allow for achieving synchronised simultaneous sampling in distributed systems. In this work, a novel distributed synchronism system based on the Time-Sensitive Networking (TSN) standard has been validated for its integration in an architecture oriented towards the high-resolution digitisation of photovoltaic (PV) generation systems. This method guarantees a time stamping with an optimal resolution that allows for the analysis of the influence of fast-evolving atmospheric fluctuations in several plants located in the same geographical area. This paper proposes an enhanced micro-phasor measurement unit (µPMU) that acts as a phasor meter and TSN master controlling the monitoring system synchronism. With this technique, the synchronism would be extended to the remaining measurement systems that would be involved in the installation at distances greater than 100 m. Several analyses were carried out with an on-line topology of four acquisition systems capturing simultaneously. The influence of the Ethernet network and the transducers involved in the acquisition process were studied. Tests were performed with Ethernet cable lengths of 2, 10, 50, and 75 m. The results were validated with 24-bit Sigma-Delta converters and high-precision resistor networks specialised in high-voltage monitoring. It was observed that with an appropriate choice of sensors and TSN synchronism, phase errors of less than ±1 µs can be guaranteed by performing distributed captures up to 50 kS/s. Statistical analysis showed that uncertainties of less than ±100 ns were achieved with 16-bit Successive Approximation Register (SAR) converters at a moderate cost. Finally, the requirements of the IEEE C37.118.1-2011 standard for phasor measurement units (PMU) were also satisfied. This standard establishes an uncertainty of ±3.1 μs for 50 Hz systems. These results demonstrate the feasibility of implementing a simultaneous sampling system for distributed acquisition systems coordinated by a µPMU.

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24

Enz, C. C., and Yuhua Cheng. "A CMOS delta-sigma true RMS converter." IEEE Journal of Solid-State Circuits 35, no. 2 (February 2000): 248–57. http://dx.doi.org/10.1109/4.823450.

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Chen, Chung-Yuan, Tai-Ping Sun, and Hsiu-Li Hsieh. "CMOS $\Sigma \Delta$ pH-to-Digital Converter." IEEE Sensors Journal 10, no. 2 (February 2010): 363–64. http://dx.doi.org/10.1109/jsen.2009.2027408.

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26

Xiao, P. H., and T. Van Duzer. "Superconducting delta-sigma oversampling A/D converter." IEEE Transactions on Applied Superconductivity 3, no. 1 (March 1993): 2625–28. http://dx.doi.org/10.1109/77.233518.

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27

Tang, Jianhua, Yinqun Hua, and Jichang Yang. "Stability analysis of a proposed charge balance A/D converter for load cell signal acquisition." International Journal of Distributed Sensor Networks 14, no. 10 (October 2018): 155014771880277. http://dx.doi.org/10.1177/1550147718802772.

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This article proposed and discussed a kind of sigma-delta A/D converter for load cell signal acquisition, which uses improved charge balance technique. The traditional charge balance sigma-delta A/D converter is stable if and only if the magnitude of the input signal current is less than one half the magnitude of the reference current, which limits the accuracy improvement of load cell. This article examined the stability of an improved version of the charge balance sigma-delta A/D converter. The proposed converter can be designed to be stable for input signals as large as the reference, which is helpful to improve load cell’s measurement accuracy.

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28

Ritoniemi, T., E. Pajarre, S. Ingalsuo, T. Husu, V. Eerola, and T. Saramiki. "A stereo audio sigma-delta A/D-converter." IEEE Journal of Solid-State Circuits 29, no. 12 (1994): 1514–23. http://dx.doi.org/10.1109/4.340425.

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29

King, E. T., A. Eshraghi, I. Galton, and T. S. Fiez. "A Nyquist-rate delta-sigma A/D converter." IEEE Journal of Solid-State Circuits 33, no. 1 (1998): 45–52. http://dx.doi.org/10.1109/4.654936.

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30

Zhao, Feng, Hong Gao, Lin Xing, Yasunori Kobori, Shu Wu, Haruo Kobayashi, Shyunsuke Miwa, Atsushi Motozawa, Zachary Nosker, and Nobukazu Takai. "Continuous-Time Delta-Sigma Controller for DC-DC Converter." Key Engineering Materials 643 (May 2015): 53–59. http://dx.doi.org/10.4028/www.scientific.net/kem.643.53.

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This paper describes applications of a Delta-Sigma (ΔΣ) modulator to control a DC-DC converter. We propose to use a continuous-time (CT) feed-forward (FF) ΔΣ controller in a DC-DC converter and show that its transient response is faster than discrete-time (DT) and/or feedback-type (FB) ΔΣ controllers. We have also performed experiments of a DC-DC converter with a first-order continuous-time feedback ΔΣ controller and show its results.

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31

Keskar, N. A., and G. A. Rincon-Mora. "A Fast, Sigma–Delta $(\Sigma \Delta)$ Boost DC–DC Converter Tolerant to Wide LC Filter Variations." IEEE Transactions on Circuits and Systems II: Express Briefs 55, no. 2 (February 2008): 198–202. http://dx.doi.org/10.1109/tcsii.2007.910801.

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32

Jeong, Jinyoung, Danbi Choi, and Jeongjin Roh. "Incremental Delta-Sigma Analog to Digital Converter for Sensor." Journal of the Institute of Electronics Engineers of Korea 49, no. 10 (October 25, 2012): 148–58. http://dx.doi.org/10.5573/ieek.2012.49.10.148.

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33

Del Signore, B. P., D. A. Kerth, N. S. Sooch, and E. J. Swanson. "A monolithic 2-b delta-sigma A/D converter." IEEE Journal of Solid-State Circuits 25, no. 6 (1990): 1311–17. http://dx.doi.org/10.1109/4.62174.

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34

Vitorino, Bruno Augusto Ferreira, Sebastian Yuri C. Catunda, Diomadson Rodrigues Belfort, and Raimundo Carlos Silverio Freire. "Autorange Thermal Sigma–Delta Converter for Incident Radiation Measurement." IEEE Transactions on Instrumentation and Measurement 68, no. 3 (March 2019): 774–81. http://dx.doi.org/10.1109/tim.2018.2857899.

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35

Benabes, Philippe, Ali Beydoun, and Jacques Oksman. "Extended frequency-band-decomposition sigma–delta A/D converter." Analog Integrated Circuits and Signal Processing 61, no. 1 (January 9, 2009): 75–85. http://dx.doi.org/10.1007/s10470-008-9274-6.

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36

Noh, Jinho, and Changsik Yoo. "Interpolated Digital Delta-Sigma Modulator for Audio D/A Converter." Journal of the Institute of Electronics Engineers of Korea 49, no. 11 (November 25, 2012): 149–56. http://dx.doi.org/10.5573/ieek.2012.49.11.149.

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37

Sonnenberg, A. H., I. Oomen, H. Hilgenkamp, G. J. Gerritsma, and H. Rogalla. "Sigma-delta A/D converter in HTS ramp edge technology." IEEE Transactions on Appiled Superconductivity 11, no. 1 (March 2001): 200–204. http://dx.doi.org/10.1109/77.919319.

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38

Lagunas, Miguel A., Ana Perez-Neira, and José Rubio. "NDM: 1-Bit Delta-Sigma Converter with Non-Linear Loop." MATEC Web of Conferences 292 (2019): 04005. http://dx.doi.org/10.1051/matecconf/201929204005.

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In this paper we propose to introduce a new processing scheme in the basic loop of a Delta Sigma (ΔΣ) analog-to-digital converter. This processing confers extra gains of the converter over both the quantization error and the channel noise. This is an advance with respect to all cases found in the literature, where the desired signal is not protected against channel noise. Also, the proposed processing is simple and contrasts with the existing architectures, which produce better quality at the expense of sensitivity to implementation imperfections due to the presence of multiples loops in the corresponding architecture. Furthermore, the in-phase/quadrature components structure of a band pass signal has not been used to improve the performance of ΔΣ converters.

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Shahana, T. K., Babita R. Jose, Poulose K. Jacob, and Sreela Sasi. "A novel Sigma–Delta based parallel analogue-to-residue converter." International Journal of Electronics 96, no. 6 (June 2009): 571–83. http://dx.doi.org/10.1080/00207210902791710.

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Hejn, Konrad, Jerzy Jędrachowicz, and Antoni Leśniewski. "B17: Oversampling Delta-Sigma converter implementation in FPAA and FPGA." IFAC Proceedings Volumes 37, no. 20 (November 2004): 257–62. http://dx.doi.org/10.1016/s1474-6670(17)30607-9.

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41

Bulzacchelli, John F., Hae-Seung Lee, James A. Misewich, and Mark B. Ketchen. "Development of superconducting bandpass delta-sigma analog-to-digital converter." Physica C: Superconductivity 412-414 (October 2004): 1539–45. http://dx.doi.org/10.1016/j.physc.2004.01.156.

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42

Sen, Tapabrata, Anoop Chandrika Sreekantan, and Siddhartha Sen. "Linearized Sigma–Delta-Based Direct Digital Converter for GMR Sensors." IEEE Transactions on Instrumentation and Measurement 70 (2021): 1–10. http://dx.doi.org/10.1109/tim.2020.3032187.

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43

Liang, Li, Li Ruzhang, Yu Zhou, Zhang Jiabin, and Zhang Jun'an. "A 16-bit cascaded sigma-delta pipeline A/D converter." Journal of Semiconductors 30, no. 5 (April 29, 2009): 055010. http://dx.doi.org/10.1088/1674-4926/30/5/055010.

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Wilson, Gerald, and Robert S. Green. "Multiplierless interpolator for a delta-sigma digital to analog converter." Journal of the Acoustical Society of America 112, no. 6 (2002): 2515. http://dx.doi.org/10.1121/1.1536480.

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45

Przybysz, J. X., D. L. Miller, and E. H. Naviasky. "Two-loop modulator for sigma-delta analog to digital converter." IEEE Transactions on Appiled Superconductivity 5, no. 2 (June 1995): 2248–51. http://dx.doi.org/10.1109/77.403033.

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Miller, D. L., J. X. Przybysz, D. L. Meier, Joonhee Kang, and A. H. Worsham. "Characterization of a superconductive sigma-delta analog to digital converter." IEEE Transactions on Appiled Superconductivity 5, no. 2 (June 1995): 2453–56. http://dx.doi.org/10.1109/77.403087.

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47

Puidokas, Vytenis, and Albinas J. Marcinkevičius. "High Resolution High Power Low Frequency Digital-to-Analog Converter." Solid State Phenomena 164 (June 2010): 133–38. http://dx.doi.org/10.4028/www.scientific.net/ssp.164.133.

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The architectural scheme of the designed Sigma-Delta DAC on the FPGA is considered. The place of the interpolator in Sigma-Delta DACs is briefly discussed. The summarized structure of the most common interpolators is presented. More applicable structures of interpolators were suggested and analyzed, providing the comparison with [1]. Having changed the structure of the incomplete interpolator and having optimized the stages, it was possible to improve the characteristic of amplitude frequency response with a smaller number of non-zero coefficients and much lower FPGA resources. The paper provides simulated results of the interpolator filter transmission characteristics as well as Sigma-Delta modulator quantization noise parameters. It is demonstrated that simulation of the complete converter system (interpolator + modulator + output filter) allows to identify places of the interpolator, where hardware resources could be saved, thereby reducing the chip area occupied by the converter, which is not always obvious when analyzing nodes separately. Therefore another version of the interpolator was proposed for the system ensuring larger suppression of the additional frequency band in the whole system compared with the previous interpolator. Simulated results related to occupied chip resources are also confirmed by the experiment, which was implemented in Xilinx Spartan FPGA.

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Lima, Evelyn Cristina de Oliveira, Antonio Wallace Antunes Soares, and Diomadson Rodrigues Belfort. "4th Order LC-Based Sigma Delta Modulators." Sensors 22, no. 22 (November 18, 2022): 8915. http://dx.doi.org/10.3390/s22228915.

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Due to the characteristic of narrow band conversion around a central radio frequency, the Sigma Delta Modulator (ΣΔM) based on LC resonators is a suitable option for use in Software-Defined Radio (SDR). However, some aspects of the topologies described in the state-of-the-art, such as noise and nonlinear sources, affect the performance of ΣΔM. This paper presents the design methodology of three high-order LC-Based single-block Sigma Delta Modulators. The method is based on the equivalence between continuous time and discrete time loop gain using a Finite Impulse Response Digital-to-Analog Converter (FIRDAC) through a numerical approach to defining the coefficients. The continuous bandpass LC ΣΔM simulations are performed at a center frequency of 432 MHz and a sampling frequency of 1.72 GHz. To the proposed modulators a maximum Signal-to-Noise Ratio (SNR) of 51.39 dB, 48.48 dB, and 46.50 dB in a 4 MHz bandwidth was achieved to respectively 4th Order Gm-LC ΣΔM, 4th Order Magnetically Coupled ΣΔM and 4th Order Capacitively Coupled ΣΔM.

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Cho, Young-Kyun, Bong Hyuk Park, and Seok-Bong Hyun. "Delta-Sigma Modulator-Based Step-Up DC–DC Converter with Dynamic Output Voltage Scaling." Electronics 9, no. 3 (March 18, 2020): 498. http://dx.doi.org/10.3390/electronics9030498.

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The switching noise and conversion efficiency of step-up DC-DC converters need to be improved to meet increasing demand. The delta-sigma modulation (DSM) technique is typically used to improve the performance of buck converters; however, this control scheme is not directly applicable for boost converters. This paper presents a boost DC–DC converter using a continuous-time delta-sigma modulator (DSM) controller for battery-powered and noise-sensitive applications. The proposed converter can adjust a wide range of output voltages dynamically by clamping the maximum duty cycle of the DSM, thus enabling stable and robust transient responses of the converter. The switching harmonics in the converter output are reduced effectively by the noise shaping property of the modulator. Moreover, the converter does not suffer from instability of mode switching due to the use of a fixed third-order DSM. Fabricated in a 180 nm CMOS, the converter occupies an active area of 0.76 mm2. It produced an output voltage ranging from 2.5 V to 5.0 V at an input voltage of 2.0 V and achieved a peak conversion efficiency of 95.5%. The output voltage ripples were maintained under 25 mV for all load conditions. A low noise output spectrum with a first spurious peak located −91 dBc from the signal was achieved.

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Tsai, Chia-Chi, Tzu-Ming Wang, and Ming-Dou Ker. "Implementation of delta—sigma analog-to-digital converter in LTPS process." Journal of the Society for Information Display 18, no. 11 (2010): 904. http://dx.doi.org/10.1889/jsid18.11.904.

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