Dissertations / Theses on the topic 'Delta sigma data converter'
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Gelhaar, B., K. Alvermann, and F. Dzaak. "A MULTICHANNEL DATA ACQUISITION SYSTEM BASED ON PARALLEL PROCESSOR ARCHITECTURES." International Foundation for Telemetering, 1992. http://hdl.handle.net/10150/608884.
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International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, CaliforniaFor research purposes on helicopter rotor acoustics a large data acquisition system called TEDAS (Transputer based Expandable Data Acquisition System) has been developed. The key features of this system are: unlimited expandability and sum data rate, local storage of data during operation, very simple analog anti aliasing filtering due to extensive digital filtering, and integrated computational power which scales with the number of channels. The sample rate is up to 50 kHz/channel, the resolution is 16 bit, 360 channels are realized now. TEDAS consists of blocks with 8 A/D converters which are controlled by one transputer T800. The size of the local memory is 4 Mbyte. Any number of blocks (IDAM = Intelligent Data Acquisition Module) can be combined to a complete system. Data preprocessing is done in parallel inside the IDAMs. As for 16 bit systems the analog antialiasing filtering becomes a dominant factor of the costs, delta sigma ADCs with oversampling and internal digital filtering are used. This produces an exact linear phase and a stop band rejection of -90 dB.
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Vijjapu, Sudheer Paarmann Larry D. "RC implementation of an audio frequency band Butterworth MASH delta-sigma analog to digital data converter." Diss., The archival copy of this thesis can be found at SOAR (password protected), 2006. http://soar.wichita.edu/dspace/handle/10057/568.
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Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering."August 2006." Title from PDF title page (viewed on May 2, 2007). Thesis adviser: Larry D. Paarmann. Includes bibliographic references (leaves 41-43).
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Baig, Shams Javid Paarmann Larry D. "RC implementation of an audio frequency band fourth-order Chebyshev type II Delta-Sigma analog to digital data converter." Diss., A link to full text of this thesis in SOAR, 2006. http://soar.wichita.edu/dspace/handle/10057/614.
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Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering.UMI Number: 1443931 "December 2006." Title from PDF title page (viewed on Sept. 18, 2007). Thesis adviser: Larry D. Paarmann. Includes bibliographic references (leaves 37-38).
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Iuzzolino, Ricardo Javier [Verfasser], and Meinhard [Akademischer Betreuer] Schilling. "Josephson Waveforms Characterization of a Sigma-Delta Analog-to-Digital Converter for Data Acquisition in Metrology / Ricardo Javier Iuzzolino ; Betreuer: Meinhard Schilling." Braunschweig : Technische Universität Braunschweig, 2011. http://d-nb.info/1175824739/34.
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Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.
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Kook, Se Hun. "Low-cost testing of high-precision analog-to-digital converters." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41170.
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The advent of deep submicron technology has resulted in a new generation of highly integrated mixed-signal system-on-chips (SoCs) and system-on-packages (SoPs). As a result, the cost of electrical products has sharply declined, and their performance has greatly improved. However, a testing throughput still remains one of the major contribution factors to final cost of the electrical products. In addition, highly precise and robust test methods and equipment are needed to promise non-defective products to customers. Hence, the testing is a critical part of the manufacturing process in the semiconductor industry. Testing such highly integrated systems and devices requires high-performance and high-cost equipment.
Analog-to-digital converters (A/D converters) are the largest volume mixed-signal circuits, and they play a key role in communication between the analog and digital domains in many mixed-signal systems. Due to the increasing complexity of the mixed-signal systems and the availability of the new generations of highly integrated systems, reliable and robust data conversion schemes are necessary for many mixed-signal designs. Many applications such as telecommunications, instrumentation, sensing, and data acquisition have demanded data converters that support ultra high-speed, wide-bandwidths, and high-precision with excellent dynamic performance and low-noise. However, as resolutions and speeds in the A/D converters increase, testing becomes much harder and more expensive.
In this research work, low-cost test strategies to reduce overall test cost for high-precision A/D converters are developed. The testing of data converters can be classified as dynamic (or alternating current (AC)) performance test and static (or direct current (DC)) performance test [1]. In the dynamic specification test, a low-cost test stimulus is generated using an optimization algorithm to stimulate high-precision sigma-delta A/D converters under test. Dynamic specifications are accurately predicted in two different ways using concepts of an alternate-based test and a signature-based test. For this test purpose, the output pulse stream of a sigma-delta modulator is made observable and useful. This technique does not require spectrally pure input signals, so the test cost can be reduced compared to a conventional test method. In addition, two low-cost test strategies for static specification testing of high-resolution A/D converters are developed using a polynomial-fitting method. The cost of testing can be significantly reduced as a result of the measurement of fewer samples than a conventional histogram test. While one test strategy needs no expensive high-precision stimulus generator, which can reduce the test cost, the other test strategy finds the optimal set of test-measurement points for the maximum fault coverage, which can use minimum-code measurement as a production test solution.
The theoretical concepts of the proposed test strategies are developed in software simulation and validated by hardware experiments using a commercially available A/D converter and designed converters on printed circuit board (PCB). This thesis provides low-cost test solutions for the high-resolution A/D converters.
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Liu, Xiyang. "Measurement of Delta-Sigma Converter." Thesis, Högskolan i Gävle, Avdelningen för elektronik, matematik och naturvetenskap, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-9701.
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With today’s technology, digital signal processing plays a major role. It is used widely in many applications. Many applications require high resolution in measured data to achieve a perfect digital processing technology. The key to achieve high resolution in digital processing systems is analog-to-digital converters. In the market, there are many types ADC for different systems. Delta-sigma converters has high resolution and expected speed because it’s special structure. The signal-to-noise-and-distortion (SINAD) and total harmonic distortion (THD) are two important parameters for delta-sigma converters. The paper will describe the theory of parameters and test method.
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Lok, Chi Fung. "Multimode switched-capacitor delta-sigma analog-to-digital converter /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LOK.
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Ertan, Sevgi 1976. "Comparison of two bandpass delta-sigma A/D converter architectures." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86435.
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Pan, Yaobin, and Xizhuo Li. "Design and Implementation of Sigma-Delta Converter : in Oversampling frequency." Thesis, Linnéuniversitetet, Institutionen för fysik och elektroteknik (IFE), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-53052.
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Nowadays, Sigma-Delta analog-to-digital converters have been widely used in the technology of analog-to-digital conversion. It depends on the merits that the approach of Sigma-Delta has. The signal converted by oversampling is precise and well-suited in signal processing systems.This thesis mainly focuses on the principles and simulations of fundamental first-order Sigma-Delta converter, and some brief introductions about other Sigma-Delta converters.The main researches of this thesis are as follows: (1)This thesis shows not only the path about development of technology of different ADCs, but also the features and principles of these ADCs and their structures. (2)The thesis discusses how the technologies of oversampling and noise shaping are used in Sigma-Delta analog-to-digital conversion. (3)Illustrate different orders Sigma-Delta converters in different bits and their advantages and disadvantages, respectively. (4)The simulation is given in Matlab(Simulink). Typical first-order SigmaDelta converter is simulated with additional noise which will impact the input signal when implement.Sigma-Delta Converter
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McGinnis, Ryan Edward. "Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1152542196.
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Chen, Wei. "Asynchronous sigma delta modulators for data conversion." Thesis, Imperial College London, 2013. http://hdl.handle.net/10044/1/23651.
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The research carried out in this thesis focuses on introducing solutions to solve issues existed in asynchronous sigma delta modulators including complex decoding scheme, lacking of noise shaping and effects of limit cycle components. These issues significantly limit the implementation of ASDMs in data conversion. The first innovation in this work is the introduction of a novel decoding circuit to digitise the output signal of the asynchronous sigma delta modulator. Compared with the conventional decoding schemes, the proposed one does not limit the input dynamic range of ASDMs, and can obtain a high resolution without a fast sample clock. The proposed decoding circuit operates asynchronously and can measure the duty cycle of the modulated square wave without measuring its instantaneous period. The second innovation of this work is the introduction of a novel architecture of the asynchronous sigma delta modulator with noise shaping without an additional loop filter. Moreover, the proposed modulator requires only a single-bit digital-to-time converter in the feedback loop even for a multi-bit quantiser. The quantiser in the modulator is realized by an eight-phase poly-phase sampler in order to reduce the requirement of the sample clock. Simulation demonstrate that the SNDR of the proposed modulator can be improved by 20dB. The final innovation of this work is the introduction of frequency compensation to the asynchronous sigma delta modulator. In this proposed modulator, the limit cycle frequency is controlled by the delay time of a novel high linear performance delay line, which is operated in current mode. The compensation is realized by adjusting the equivalent delay time for different input voltage values. The proposed one can double the signal bandwidth with the same limit cycle frequency.
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Zhao, Yixiang, and Hao Niu. "Measurement of dynamic parameters of Delta-Sigma ADC." Thesis, Högskolan i Gävle, Avdelningen för elektronik, matematik och naturvetenskap, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-12678.
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In present day, digital signal processing (DSP) is a popular technology and widely used in many fields. There have increasing number of applications that need high resolution converters. Therefore, analog-to-digital converters play a major role in DSP, and a well-performed ADC will enhance the performance of a certain system. Different types of ADCs are available for various functions. Delta-sigma converters are famous for high resolution. Dynamic parameters can be used to judge the performance of an ADC, this paper will focus on the critical parameters of spectrum analysis, which contains Signal-to-Noise-and-Distortion Ratio (SINAD), Effective Number of Bits (ENOB) and Spurious-free Dynamic Range (SFDR). The theory and test method of these critical parameters are proposed in this paper using the Evaluation Module and Matlab. The results we acquired from the Evaluation Module are SINAD=86.15dB, SFDR=109.2dB, ENOB=14.177bits; and the results we calculated from MATLAB are: SINAD=86.14dB, SFDR=108.8dB, ENOB=14bits.
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Pěček, Lukáš. "Návrh Sigma Delta AD převodníku pro senzorové aplikace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-317221.
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This diploma thesis deals with the design of a sigma delta AD converter for a sensor application of junction temperature measurement in the automotive environment. A modified continuous time current mode modulator structure was designed. Its advantage lies in shifting and extending an input voltage range to work with signals from 0 V to 1,2 with a high impedance input and a relatively low hardware complexity. The functionality was verified by a behavioral model in the Simulink environment and then by transistor level simulation in CADENCE environment using ONC18/I4T technology.
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Asibal, Romeo Lim. "Limitations of high speed sigma-delta A/D converter in GaAs technology." Diss., Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/15445.
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Guyton, Matthew C. (Matthew Christopher). "A low-voltage zero-crossing-based delta-sigma analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/60147.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 179-183).
A zero-crossing-based (ZCB) switched-capacitor technique is presented for operation under low power supply voltages without gate boosting. Voltage ramp generators maintain common-mode level at each integrator output. Correlated level-shifting is used to increase the effective output impedance of gated current sources. The technique was used to design a single-bit 4th-order delta-sigma analog-to-digital converter for audio applications. The prototype ADC was implemented in 0.13 [mu]m CMOS and achieves 11.9 ENOB for 60 kHz input bandwidth while dissipating 1.2 mW power.
by Matthew C. Guyton.
Ph.D.
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Huang, Li. "Calibration of a two-step Incremental Sigma-Delta Analog-to-Digital Converter." Thesis, université Paris-Saclay, 2020. http://www.theses.fr/2020UPAST041.
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Dans le cadre des imageurs Haute Définition, une tendance est d’intégrer un banc de convertisseurs analogiques-numériques jouxtant la matrice de pixel. La contrepartie est une contrainte sur le facteur de forme du convertisseur. Un convertisseur de type Sigma-Delta incrémental à base d’inverseur a été conçu lors de travaux précédents en respectant ces contraintes. Mais le placement-routage du circuit a abouti à une dégradation des performances à savoir une résolution de 9 bits au lieu des 14 bits escomptés. Une méthode de calibration s’imposait donc. Cette thèse propose plusieurs méthodes de correction implémentées par des filtres numériques appliqués sur les bits de sortie et sur des combinaisons des bits de sorties pour tenir compte de phénomènes non-linéaires observés en simulation « post-placement-routage ». Les méthodes ont été validées à partir des résultats de simulation « post-placement-routage » et permettent d’atteindre 14 bits de résolution. Pour aller plus loin, la thèse propose également un modèle des défauts du circuit au niveau des intégrateurs qui sont la partie la plus critique du circuit. Ce modèle, qui met en oeuvre des capacités parasites, rejoint les résultats de simulation « post-placement-routage » avec une très bonne précision ce qui permet d’envisager des voies d’amélioration pour une prochaine conceptionIn the context of High Definition imagers, a trend is to integrate a bank of analogto-digital converters adjacent to the pixel matrix. The disadvantage is a constraint on the form factor of the converter. An incremental inverter-based Sigma-Delta converter was designed during previous work while respecting these constraints. But the post-layout of the circuit resulted in a performance degradation namely a resolution of 9 bits instead of the expected 14 bits. A calibration method was therefore necessary. This thesis proposes several correction methods implemented by digital filters applied on the output bits and on combinations of the output bits to take account of non-linear phenomena observed in post-layout simulation. The methods have been validated from the post-layout simulation results and achieve 14-bit resolution. To go further, the thesis also proposes a model of the circuit defects at the level of the integrators which are the most critical part of the circuit. This model, which implements parasitic capacitances, joins the post-layout simulation results with a very high precision, which makes it possible to consider ways of improvement for a future design
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Early, Adrian Bruce. "A high-accuracy, DC-calibrated, monolithic, delta-sigma analog-to-digital converter." Diss., The University of Arizona, 1990. http://hdl.handle.net/10150/185072.
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Delta-Sigma Analog-to Digital Converters have recently become important for providing high resolution with monotonicity and reasonable signal-to-distortion ratings without the need for laser trimming techniques. This has come about because of the recent ability to combine both extensive digital computation power, and switched-capacitor analog circuitry on a monolithic chip. Delta-Sigma converters have primarily been used, however, in signal processing applications, notably digital audio, but not for instrumentation. The purpose of this dissertation is to provide a high accuracy, DC-accurate, Delta-Sigma Analog-to-Digital converter in monolithic form. Autocalibration gives endpoint correction, and chopper stabilization minimizes the effect of parameter shifts, drift, and flicker noise. A digital filter, needed for all Delta-Sigma converters, serves as a signal processor to reject out-of-band noise and resonant responses of the external system. A 3-micron, double-poly CMOS process is used. Power requirements are +/- 5 Volts. A six-pole Gaussian IIR digital filter is chosen for good transient response and no overshoot. The filter algorithm and hardware solve the difference equations of a low-pass switched-capacitor prototype filter in digital form. Due to the low bandwidth needed, an area-efficient shift-and-add architecture is used. The area is further reduced with a novel multiplication algorithm, and the logic is reused to perform the calculations required for calibration. The system level device performance is verified in FORTRAN. The analog subcircuits are simulated over process and temperature corners in HSPICE. Measurements show differential and integral linearlity, DC accuracy and noise near the 20-bit level. Power supply rejection, and out-of-band signal attenuation are good, and the step response is monotonic. The circuit is marketed as Crystal Semiconductor CSC5503 and CSC5501 (20 and 16-bit resolutions, respectively).
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Zrilić, D., D. Skendzić, S. Pajavić, R. Ghorishi, F. Fu, and G. Kandus. "A Charge-Balancing Incremental Analog to Digital Converter for Instrumental Applications." International Foundation for Telemetering, 1988. http://hdl.handle.net/10150/615013.
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International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, NevadaA switched-capacitor technique for realization of one bit serial A/D converter is presented. A conversion accuracy that is higher than 15 bits can be expected from its integrated realization. Results of simulation are presented. It is shown that arithmetic operations on bit serial signals are possible. Using arithmetic operations on delta-modulated signals, it is possible to build inexpensive options necessary in instrumentation.
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Saleem, Jawad, and Abdul Mateen Malik. "REALIZATION OF CASCADE OF RESONATORS WITH DISTRBUTED FEED-BACK SIGMA-DELTA." Thesis, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-20289.
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The Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost.
The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry.
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Ng, Sheung Yan. "A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique." The Ohio State University, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906.
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Saleem, Jawad, and Abdul Mateen Malik. "Realization of Cascade of Resonators with Distributed Feed-Back Sigma-Delta." Thesis, Linköpings universitet, Institutionen för systemteknik, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-20289.
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The Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost. The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry.
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Forejtek, Jiří. "Návrh a realizace sigma-delta převodníku AD v technice SC." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217731.
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The work deals with the design of novel high order sigma-delta AD converter using switched-capacitors approach. Model of the ideal and real architecture of the third order sigma-delta modulator was designed in MATLAB SIMULINK. The comparison of the ideal and real model of sigma delta architecture is described in this thesis. On the basis of simulation results in MATLAB SIMULINK the stages of modulator on transistors level in CMOS technology were designed. Fully differential operational amplifier, switched capacitor integrator, summing amplifier, comparator, one bit digital to analog converter and nonoverlapping clock generator were designed. The circuit of third order sigma-delta modulator was simulated in CADENCE. Layout of operational amplifier and switched capacitor integrator was made. Through the use of MATLAB was designed decimation filter as well.
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Soukup, Luděk. "Návrh digitálně-analogového převodníku typu sigma-delta v technologii CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2012. http://www.nusl.cz/ntk/nusl-219761.
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This master’s thesis deals with the issue of digital to analog conversion and possibility of its realization in digital circuits. Goal of this project is to design sigma-delta digital to analog converter with resolution of 14 bits and frequency band (0 ÷ 20) kHz. Main functional blocks: interpolator and modulator sigma-delta will be realized like digital structures. Reconstruction filter will be realized like an analog structure. For design a check of parameters of designed converter programs MATLAB and Simulink are used. Designed digital structures will be described by VHDL language.
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Jerng, Albert. "Delta-Sigma digital-RF modulation for high data rate transmitters." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/38675.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007.Includes bibliographical references (p. 157-162).
A low power, wideband wireless transmitter utilizing [Delta]-[Sigma] direct digital modulation of an RF carrier is presented. The transmitter architecture replaces high dynamic range analog circuits with high speed digital circuits and a passive LC bandpass filter, saving power and area compared to conventional IQ modulators for wideband systems. A prototype transmitter IC built in 0.13 pm CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. The modulator consumes 187 mW and occupies a die area of 0.72 mm2. A quadrature digital-IF approach eliminates modulator LO feedthrough and image spurs from the output spectrum without requiring analog circuitry or system calibration, simplifying the design of the transmitter. The largest modulator spur is measured to be -47 dBc. Measured SNDR over a 200 MHz bandwidth is 43 dB. Successful implementation of the [Delta]-[Sigma] RF modulator requires the design of a high-Q, tunable RF bandpass filter, and a low power, high speed digital [Delta]-[Sigma] modulator. A 4th order passive LC bandpass filter with center frequency of 5.25 GHz is designed and implemented using differential coupled resonators.
(cont.) Variation of the filter response over process and temperature is removed through the design of an automatic self-tuning loop that calibrates the filter center frequency to the system LO. A 2.625 GS/s, 2nd order, 3-bit digital [Delta]-[Sigma] modulator is realized through the use of a pass-gate adder circuit optimized for low power and high speed. The digital modulator is software programmable to support multiple bandwidths, frequency channels, and modulation schemes. It can be used adaptively to transmit in selected channels with variable bit-rates, depending on channel conditions. It is envisioned that the [Delta]-[Sigma] digital-RF modulator can be used as a universal transmitter for wideband systems and applications that require high data rates and low power consumption.
by Albert Jerng.
Ph.D.
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Štraus, Pavel. "Zvuková karta pro PC s obvodem FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219090.
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This project deals with implementation of a first order Sigma–Delta AD converter on the FPGA. This ADC is design for an audio signal processing. ADC is build up partially from digital blocks implemented in FPGA (programmed using VHDL) and from few analog components placed external to FPGA. Output from ADC is PCM signal. Data from ADC is created UDP datagram, which is sent to PC via network connection. Income data are received in created program, which save data to text file. This text file is processing in MATLAB.
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Hellman, Johan. "Implementation of a Low-Cost Analog-to-Digital Converter for Audio Applications Using an FPGA." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-96009.
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The aim of this master’s thesis is to implement an ADC (Analog-to-Digital Converter) foraudio applications using external components together with an FPGA (Field-ProgrammableGate Array). The focus is on making the ADC low-cost and it is desirable to achieve 16-bitresolution at 48 KS/s. Since large FPGA’s have numerous I/O-pins, there are usually someunused pins and logic available in the FPGA that can be used for other purposes. This istaken advantage of, to make the ADC as low-cost as possible.This thesis presents two solutions: (1) a - (Sigma-Delta) converter with a first order passive loop-filter and (2) a - converter with a second order active loop-filter. The solutionshave been designed on a PCB (Printed Curcuit Board) with a Xilinx Spartan-6 FPGA. Bothsolutions take advantage of the LVDS (Low-Voltage-Differential-Signaling) input buffers inthe FPGA.(1) achieves a peak SNDR (Signal-to-noise-and-distortion-ratio) of 62.3 dB (ENOB (Effectivenumber of bits) 10.06 bits) and (2) achieves a peak SNDR of 80.3 dB (ENOB 13.04). (1) isvery low-cost ($0.06) but is not suitable for high-precision audio applications. (2) costs $0.53for mono audio and $0.71 for stereo audio and is comparable with the solution used today:an external ADC (PCM1807).
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Wang, Ting-Yang, and 王鼎洋. "Continuous-Time Incremental Delta Sigma Data Converter." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/81725051881955473970.
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碩士國立臺灣大學
電子工程學研究所
103
Incremental sigma-delta data converter (IDC) has many useful applications such as DC measurement, linear feet measurement, biomedical application, sensor array application, and is suitable for any multi-channel applications. Most of the IDC today is made by discrete-time (DT) structure. But continuous-time (CT) structure consumes much less power than DT one, since continuous ramping instead of discrete settling behavior is involved in CT loop-filters. This thesis use CT structure to make the modulator faster and consume less power. A third order 3-bit CT-IDC with OSR=64 fabricated in TSMC T18 1P6M technology is proposed in the thesis. The modulator is operated at 100MHz sampling clock. It achieves peak SNDR of 73.82dB within 737 kHz bandwidth. This chip dissipates 6.6 mA from a 3.3V supply. The core area of this modulator occupies smaller than 0.25mm2.
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Hsieh, Yu-Lun, and 謝雨倫. "Continuous-Time Incremental Delta Sigma Data Converter." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/aeje7j.
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碩士國立臺灣大學
電子工程學研究所
106
Incremental delta-sigma data converter (IDC) has many useful applications including biomedical measurement and sensor array measurement, and is suitable for multi-channel platforms. This application for internet of things (IOT) always combine the characteristics of high-speed transmission and wireless network connectivity. Therefore, low power consumption is the first to be considered.This thesis presents a 3rd-order, 5-bit continuous-time incremental delta-sigma data converter (CTIDC). For low power consideration, we replace conventional FLASH ADC by power-efficient successive-approximation-register (SAR) ADC and utilizing the noise coupling (NC) technique to reduce the numbers of power-hungry op-amps for the same noise shaping effect. The excess loop delay compensation (ELDC) is also embedded in the SAR ADC without using additional DAC.Fabricated in TSMC 40 nm LP 1P6M technology, the proposed modulator is operated at 1.6MHz sampling clock. It achieves peak SNDR of 71.98 dB in IDC mode and 72.34 dB SNDR in SDM mode within 25 kHz signal bandwidth. This chip dissipates 225 μW from 1.2V/1.5V supply voltage. The active area of this modulator occupies less than 0.318mm2.
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Caldwell, Trevor. "Delta-Sigma Modulators with Low Oversampling Ratios." Thesis, 2010. http://hdl.handle.net/1807/26352.
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This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modulators and incremental data converters. The first reduced-OSR architecture is the high-order cascaded delta-sigma modulator. These delta-sigma modulators are shown to reduce the in-band noise sufficiently at OSRs as low as 3 while providing power savings. The second low OSR architecture is the high-order cascaded incremental data converter which possesses signal-to-quantization noise ratio (SQNR) advantages over equivalent delta-sigma modulators at low OSRs. The final architecture is the time-interleaved incremental data converter where two designs are identified as potential methods of increasing the throughput of low OSR incremental data converters. A prototype chip is designed in 0.18um CMOS technology which can operate in three modes by simply changing the resetting clock phases. It can operate as an 8-stage pipeline analog-to-digital (A/D) converter, an 8th-order cascaded delta-sigma modulator, and an 8th-order cascaded incremental data converter with an OSR of 3.
31
Hamoui, Anas A. "Delta-sigma data converters for broadband digital communications." 2004. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=94495&T=F.
Full text
32
Akram, Waqas. "Tunable mismatch shaping for bandpass Delta-Sigma data converters." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-05-3575.
Full textAbstract:
Oversampled digital-to-analog converters typically employ an array of unit elements to drive out the analog signal. Manufacturing defects can create errors due to mismatch between the unit elements, leading to a sharp reduction in the effective dynamic range through the converter. Mismatch noise shaping is an established technique for alleviating these effects, but usually anchors the signal band to a fixed frequency location. In order to extend these advantages to tunable applications, this work explores a series of techniques that allow the suppression band of the mismatch noise shaping function to have an adjustable center frequency. The proposed techniques are implemented in hardware and evaluated according to mismatch shaping performance, latency and hardware complexity.text
33
Bilhan, Erkan. "Very low power sigma delta modulator for WCDMA /." 2008. http://proquest.umi.com/pqdweb?did=1654494021&sid=1&Fmt=2&clientId=10361&RQT=309&VName=PQD.
Full text
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Chen, Hongbo. "Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10522.
Full textAbstract:
Nowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards usually require several Analog to Digital Converters (ADCs) with different specifications. A promising solution is adopting a power and area efficient reconfigurable ADC with tunable bandwidth and dynamic range. The advantage of the reconfigurable ADC over customized ADCs is that its power consumption can be scaled at different specifications, enabling optimized power consumption over a wide range of sampling rates and resulting in a more power efficient design. Moreover, the reconfigurable ADC provides IP reuse, which reduces design efforts, development costs and time to market.
On the other hand, software radio transceiver has been introduced to minimize RF blocks and support multiple standards in the same chip. The basic idea is to perform the analog to digital (A/D) and digital to analog (D/A) conversion as close to the antenna as possible. Then the backend digital signal processor (DSP) can be programmed to deal with the digital data. The continuous time (CT) bandpass (BP) sigma-delta ADC with good SNR and low power consumption is a good choice for the software radio transceiver.
In this work, a proposed 10-bit reconfigurable ADC is presented and the non-overlapping clock generator and state machine are implemented in UMC 90nm CMOS technology. The state machine generates control signals for each MDAC stage so that the speed can be reconfigured, while the power consumption can be scaled. The measurement results show that the reconfigurable ADC achieved 0.6-200 MSPS speed with 1.9-27 mW power consumption. The ENOB is about 8 bit over the whole speed range.
In the second part, a 2-bit quantizer with tunable delay circuit and 2-bit DACs are implemented in TSMC 0.13um CMOS technology for the 4th order CT BP sigma-delta ADC. The 2-bit quantizer and 2-bit DACs have 6dB SNR improvement and better stability over the single bit quantizer and DACs. The penalty is that the linearity of the feedback DACs should be considered carefully so that the nonlinearity doesn't deteriorate the ADC performance. The tunable delay circuit in the quantizer is designed to adjust the excess loop delay up to +/- 10% to achieve stability and optimal performance.
35
Vijjapu, Sudheer. "RC implementation of an audio frequency band Butterworth MASH delta-sigma analog to digital data converter -- FULL TEXT IS NOT AVAILABLE." Thesis, 2006. http://hdl.handle.net/10057/568.
Full textAbstract:
Most present day implementations of delta-sigma modulators are discrete-time ones using switched-capacitor circuits. A resistor-capacitor (RC) implementation of a delta-sigma analog to digital converter (ADC) does not use switched capacitor (SC) technology. While SC implementation has the advantages of being discrete-time, no resistors used and improved stability control, RC implementation has the advantage of no switches being used (other than quantizer) and therefore a simpler circuit implementation. Continuous-time implementations can achieve lower thermal noise levels than switched capacitor modulators. Butterworth Multi-stage Noise Shaping (MASH) architecture is one of the promising architectures to implement in continuous-time domain. For a convenient design and quantization noise spectrum shaping of a delta sigma data converter, it's highly desirable for the Noise Transfer Function (NTF) to take the form of a high-pass filter. The MASH architecture was introduced to overcome stability problems commonly faced beyond a second order structure. Delta-sigma data converters are new converter designs that are preferred for integrated circuits and for high-resolution applications. It is highly desirable for the NTF of delta-sigma data converters to take the form of conventional highpass filters for convenient design purposes and shaping of the quantization noise spectrum. However, conventional delta-sigma architectures allow for only low orders and very low cutoff frequencies for such highpass filters, otherwise the converter becomes unstable. In previous projects it was found that a MASH implementation (each stage being second order) of a delta-sigma data converter where the NTF of each stage is a Butterworth highpass filter holds much promise. This current project is to accomplish RC implementation of fourth-order Butterworth MASH delta-sigma data converter. The circuit design procedure will be shown, starting with the desired NTF characteristics, and yielding the required parameters for the RC integrators with gains that are determined from the desired transfer function. The circuit simulation, yielding the bit stream frequency spectrum and the signal to noise ratio, will be based on Mentor Graphics Eldo SPICE simulations. The performance and characteristics of the circuit is fully analyzed and documented for a wide variety of variations and test conditions.Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering.
"August 2006."
Includes bibliographic references (leaves 41-43).
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Lin, Jia-Ni, and 林佳霓. "A Delta-Sigma A/D Converter with Novel Data-Weighted Averaging Algorithm for Cochlear Prosthesis System." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/98195844371113668602.
Full textAbstract:
碩士國立交通大學
電機工程學系
103
In recent years, with the rapid of development of biomedical electronic systems, low power consumption and low noise have become very important research topic. The ADC plays a very important role in biomedical electronic systems. In this thesis, the design of the delta-sigma A/D converter for applications of cochlear prosthesis has been implemented. A multi-bit delta-sigma ADC uses data weighted averaging (DWA) algorithm applied to the feedback DAC. DWA algorithm has been used to suppress the harmonic distortions. The pointer selection of DAC elements is used cyclically, which has resulted in some baseband tones. A novel DWA algorithm is proposed to further reduce baseband tones than the conventional DWA. The method randomly adds 0 or 1 during the pointer selection, which has improved the performance of SFDR and SNDR. In this thesis, the measurement results show that the peak signal to noise and distortion ratio is 50.1dB and the dynamic range is 58dB. The chip was fabricated by TSMC 0.18µm 1P6M CMOS mixed signal process. The chip area is 1.168 x 0.632 mm2 and power consumption is 452µW from a 1.8-V power supply.
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Baig, Shams Javid. "RC implementation of an audio frequency band fourth order Chebyshev Type II delta-sigma analog to digital data converter -- FULL TEXT IS NOT AVAILABLE." Thesis, 2006. http://hdl.handle.net/10057/614.
Full textAbstract:
Delta sigma data converters have found to be of greater interest for almost 40
years now. Continuous time implementation of these converters, especially for high
speed and low power applications has been very challenging. Here in this thesis we have
discussed Resistor Capacitor (RC) implementation of Chebyshev Type II high pass Noise
Transfer Function (NTF). RC implementation has its own advantages compared to that of
a Switched Capacitor (SC) circuit.
While SC implementation has the advantages of being discrete-time, no resistors
used, and improved stability control, RC implementation has the advantage of no
switches being used (other than the quantizer) and therefore a simpler circuit
implementation.
In this thesis the details of the design and analysis of a fourth order RC delta
sigma data converter will be given. The NTF is that of a fourth-order Chebyshev Type II
highpass filter, where the noise is high passed and removed using a low pass filter and the
signal remains constant across the low frequency band.
The circuit implementation consists of four RC integrators with gain stages that
are determined from the desired transfer function. The feedback loop includes of a
sample and hold circuit followed by a one-bit quantizer: these are the only nonlinear
elements in the circuit design.
The circuit design procedure will be given, starting with the desired NTF
characteristics, and yielding the required gain parameters for the four integrator circuit
architecture, obtained to implement the requiredH(s). MATLAB is used for easy
computation.
The circuit simulation, yielding the bit stream frequency spectrum and the signal
to noise ratio, will be based on Mentor Graphics Eldo SPICE simulations.
The overall performance achieves the equivalent of 11 bits. This is obtained from
a fourth order circuit, using RC implementation.Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering.
Includes bibliographical references (leaves 37-38)
"December 2006."
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Hayward, Roger D. "Improving a sampled-data circuit simulator for Delta-Sigma modulator design." Thesis, 1992. http://hdl.handle.net/1957/36732.
Full textAbstract:
Delta-Sigma Modulator-based Analog-to-Digital converter design is an active
area of research. New topologies require extensive simulations to verify their
performance. A series of improvements were made to an existing circuit
simulation package in order to speed the simulation process for the designer.
Various examples of these improvements are presented in typical applications.Graduation date: 1992
39
Gharbiya, Ahmed. "Architecture Alternatives for Time-interleaved and Input-feedforward Delta-Sigma Modulators." Thesis, 2008. http://hdl.handle.net/1807/11206.
Full textAbstract:
This thesis strives to enhance the performance of delta-sigma modulators in two areas: increasing their speed and enabling their operation in a low voltage environment.
Parallelism based on time-interleaving can be used to increase the speed of delta-sigma modulators. A novel single-path time-interleaved architecture is derived and analyzed. Finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the new modulator. Two techniques are presented to mitigate the mismatch problem: a hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators and a digital calibration method.
The input-feedforward technique removes the input-signal component from the internal nodes of delta-sigma modulators. The removal of the signal component reduces the signal swing and distortion requirements for the opamps. These characteristics enable the reliable implementation of delta-sigma modulators in modern CMOS technology. Two implementation issues for modulators with input-feedforward are considered. First, the drawback of the analog adder at the quantizer input is identified and the capacitive input feedforward technique is introduced to eliminate the adder. Second, the double sampled input technique is proposed to remove the critical path generate by the input feedforward path.
Novel input-feedforward delta-sigma architecture is proposed. The new digital input feedforward (DIFF) modulator maintains the low swing and low distortion requirements of the input feedforward technique, it eliminates the analog adder at the quantizer input, and it improves the achievable resolution. To demonstrate these advantages, a configurable delta-sigma modulator which can operate as a feedback topology or in DIFF mode is implemented in 0.18μm CMOS technology. Both modulators operate at 20MHz clock with an oversampling ratio of 8. The power consumption in the DIFF mode is 22mW and in feedback mode is 19mW. However, the DIFF mode achieves a peak SNDR of 73.7dB (77.1dB peak SNR) while the feedback mode achieves a peak SNDR of 64.3dB (65.9dB peak SNR). Therefore, the energy required per conversion step for the DIFF architecture (2.2 pJ/step) is less than half of that required by the feedback architecture (5.7 pJ/step).
40
Wang, Yan. "Design techniques for wideband low-power Delta-Sigma analog-to-digital converters." Thesis, 2009. http://hdl.handle.net/1957/13664.
Full textAbstract:
Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT
structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart.
In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth.
For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications.
For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications.
Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected.Graduation date: 2010
41
Yang, Yuqing Ph D. "System oriented delta sigma analog-to-digital modulator design for ultra high precisoin data acquisition applications." 2008. http://hdl.handle.net/2152/18176.
Full textAbstract:
As high precision data acquisition systems continue to improve their performance and power efficiency to migrate into portable devices, increasing demands are placed on the performance and power efficiency of the analog-to-digital conversion modulator. On the other hand, analog-to-digital modulator performance is largely limited by several major noise sources including thermal noise, flicker noise, quantization noise leakage and internal analog and digital coupling noise. Large power consumption and die area are normally required to suppress the above noise energies, which are the major challenges to achieve power efficiency and cost targets for modern day high precision converter design. The main goal of this work is to study various approaches and then propose and validate the most suitable topology to achieve the desired performance and power efficiency specifications, up to 100 kHz bandwidth with 16-21 bits of resolution. This work will first study various analog-to-digital conversion architectures ranging from Nyquist converters such as flash, pipeline, to the delta sigma architecture. Advantages and limitations of each approach will be compared to develop the criteria for the optimal modulator architecture. Second, this work will study analog sub-circuit blocks such as opamp, comparator and reference voltage generator, to compare the advantages and limitations of various design approaches to develop the criteria for the optimal analog sub circuit design. Third, this work will study noise contributions from various sources such as thermal noise, flicker noise and coupling noise, to explore alternative power and die area efficient approaches to suppress the noise. Finally, a new topology will be proposed to meet all above criteria and adopt the new noise suppression concepts, and will be demonstrated to be the optimal approach. The main difference between this work from previous ones is that current work places emphasis on the integration of the modulator architecture design and analog sub-circuit block research efforts. A high performance stereo analog-to-digital modulator is designed based on the new approach and manufactured in silicon. The chip is measured in the lab and the measurement results reported in the dissertation.text
42
Reis, Luís Filipe Brochado. "CMOS RF Sigma-Delta Converter." Master's thesis, 2017. https://repositorio-aberto.up.pt/handle/10216/107273.
Full text
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Reis, Luís Filipe Brochado. "CMOS RF Sigma-Delta Converter." Dissertação, 2017. https://repositorio-aberto.up.pt/handle/10216/107273.
Full text
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Chuang, Bob, and 莊博智. "Sigma-Delta Analog to Digital Converter." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/22995366967144993753.
Full textAbstract:
碩士國立中興大學
電機工程學系所
98
A signal output with natural variations in energy retrieved by sensors is the analog type, while the subsequent circuit processing belongs to the digital type. Hence, to enable a smooth transition between analog and digital circuits requires A/D converters. Types of A/D converters are available for different applications. Practitioners regard Sigma-Delta A/D converters, which have been developed and improved for several decades, among the best converters available with wide applications in devices such as sphygmomanometers, ear thermometers, body weight scales, and audio frequency circuits. For mid to low speed, high bit A/D converter circuits, the advantage is that quantizer and digital filter processes can be completed using digital circuits. Current research has developed the integrator and comparator of the analog part with OP AMP, followed by creating the quantizer and decimation filter with a Complex-programmable Logic Device (CPLD), thus, obtaining a complete Sigma-Delta A/D digital converter. Finally, measuring instruments have evaluated important characteristics, such as integral non-linearity/differential non-linearity (INL/DNL) and the effective number of bits (ENOB).The measurement result: DNL is -1 to +0.9 LSB avg0.005 LSB, INL is -4 to +2 LSB avg-1.7 LSB, , ENOBAvg 5.4 bit.
45
Fonseca, Diogo Dinis da. "Low-pass CMOS Sigma-Delta Converter." Master's thesis, 2018. https://hdl.handle.net/10216/114123.
Full textAbstract:
A crescente necessidade em dar-se uma melhor saúde à população obriga ao desenvolvimento de novos e melhores dispositivos médicos. Atualmente, uma área de desenvolvimento importante é a de dispositivos portáteis para análise de sinais biológicos, tais como o eletrocardiograma ou o electroencefalograma, ajudando os profissionais de saúde a fazer rápidos diagnósticos no terreno, ou mesmo para serem usados por cidadãos que necessitem de vigilância constante.
O desenvolvimento destes aparelhos traz novos desafios para a comunidade cientifica, nomeadamente na interface analógico/digital, na qualidade dos dados obtidos e no gasto energético. Para se conceber um bom dispositivos médico é necessário um conversor analógico/digital para frequências baixas, com baixo consumo energético e elevada resolução.
Esta dissertação começa por fornecer ao leitor a teoria básica sobre conversores analógico/digital (ADC) e estado de arte. Como principal objetivo do trabalho desenvolvido, é descrito o desenho de um ADC baseado numa arquitetura Sigma-Delta que vá de encontro aos requisitos mencionados. O conversor foi implementado numa tecnologia 130 nm CMOS, usando uma frequência de amostragem de 1 MHz, com uma largura de banda de 1 kHz e tensão de alimentação 1,2 V. É usada, nos integradores do sigma-delta, uma invulgar tipologia de Opamp de forma a obter um ganho elevado, sem recurso a técnicas cascode. O quantizador possui uma resolução de 1,5 bits e é realizado com dois comparadores dinâmicos, de forma a minimizar o consumo energético.The growing need to provide better health for the population requires the development of new and better medical devices. Portable devices for the analysis of biological signals, such as the electrocardiogram or electroencephalogram, is nowadays an important development, helping health professionals to come up with fast diagnoses on the field, or even for use by citizens who require constant vigilance . Developing these devices brings new challenges to the scientific community, namely at the analog/digital interface, the quality of data and power consumption. In order to design a good medical device it is necessary an analog/digital converter for low frequencies, with low power consumption and high resolution. This dissertation begins by providing the reader with the basic theory of analog/digital (ADC) and its state of the art. The main goal of the work is the design of an ADC based on a Sigma-Delta architecture that meets the necessary medical requirements. The converter was implemented in a 130 nm CMOS technology using a sampling frequency of 1 MHz, with a bandwidth of 1 kHz, and a source voltage of 1.2 V. The integrators of sigma-delta employs an unusual Opamp typology in order to reach a high gain, without resourcing to cascode techniques. The quantizer has a resolution of 1.5 bits and is realized with two dynamic comparators, in order to minimize power consumption.
46
Fonseca, Diogo Dinis da. "Low-pass CMOS Sigma-Delta Converter." Dissertação, 2018. https://hdl.handle.net/10216/114123.
Full textAbstract:
A crescente necessidade em dar-se uma melhor saúde à população obriga ao desenvolvimento de novos e melhores dispositivos médicos. Atualmente, uma área de desenvolvimento importante é a de dispositivos portáteis para análise de sinais biológicos, tais como o eletrocardiograma ou o electroencefalograma, ajudando os profissionais de saúde a fazer rápidos diagnósticos no terreno, ou mesmo para serem usados por cidadãos que necessitem de vigilância constante.
O desenvolvimento destes aparelhos traz novos desafios para a comunidade cientifica, nomeadamente na interface analógico/digital, na qualidade dos dados obtidos e no gasto energético. Para se conceber um bom dispositivos médico é necessário um conversor analógico/digital para frequências baixas, com baixo consumo energético e elevada resolução.
Esta dissertação começa por fornecer ao leitor a teoria básica sobre conversores analógico/digital (ADC) e estado de arte. Como principal objetivo do trabalho desenvolvido, é descrito o desenho de um ADC baseado numa arquitetura Sigma-Delta que vá de encontro aos requisitos mencionados. O conversor foi implementado numa tecnologia 130 nm CMOS, usando uma frequência de amostragem de 1 MHz, com uma largura de banda de 1 kHz e tensão de alimentação 1,2 V. É usada, nos integradores do sigma-delta, uma invulgar tipologia de Opamp de forma a obter um ganho elevado, sem recurso a técnicas cascode. O quantizador possui uma resolução de 1,5 bits e é realizado com dois comparadores dinâmicos, de forma a minimizar o consumo energético.The growing need to provide better health for the population requires the development of new and better medical devices. Portable devices for the analysis of biological signals, such as the electrocardiogram or electroencephalogram, is nowadays an important development, helping health professionals to come up with fast diagnoses on the field, or even for use by citizens who require constant vigilance . Developing these devices brings new challenges to the scientific community, namely at the analog/digital interface, the quality of data and power consumption. In order to design a good medical device it is necessary an analog/digital converter for low frequencies, with low power consumption and high resolution. This dissertation begins by providing the reader with the basic theory of analog/digital (ADC) and its state of the art. The main goal of the work is the design of an ADC based on a Sigma-Delta architecture that meets the necessary medical requirements. The converter was implemented in a 130 nm CMOS technology using a sampling frequency of 1 MHz, with a bandwidth of 1 kHz, and a source voltage of 1.2 V. The integrators of sigma-delta employs an unusual Opamp typology in order to reach a high gain, without resourcing to cascode techniques. The quantizer has a resolution of 1.5 bits and is realized with two dynamic comparators, in order to minimize power consumption.
47
Fonseca, Diogo Dinis da. "Low-pass CMOS Sigma-Delta Converter." Dissertação, 2002. https://repositorio-aberto.up.pt/handle/10216/114123.
Full textAbstract:
A crescente necessidade em dar-se uma melhor saúde à população obriga ao desenvolvimento de novos e melhores dispositivos médicos. Atualmente, uma área de desenvolvimento importante é a de dispositivos portáteis para análise de sinais biológicos, tais como o eletrocardiograma ou o electroencefalograma, ajudando os profissionais de saúde a fazer rápidos diagnósticos no terreno, ou mesmo para serem usados por cidadãos que necessitem de vigilância constante.O desenvolvimento destes aparelhos traz novos desafios para a comunidade cientifica, nomeadamente na interface analógico/digital, na qualidade dos dados obtidos e no gasto energético. Para se conceber um bom dispositivos médico é necessário um conversor analógico/digital para frequências baixas, com baixo consumo energético e elevada resolução.Esta dissertação começa por fornecer ao leitor a teoria básica sobre conversores analógico/digital (ADC) e estado de arte. Como principal objetivo do trabalho desenvolvido, é descrito o desenho de um ADC baseado numa arquitetura Sigma-Delta que vá de encontro aos requisitos mencionados. O conversor foi implementado numa tecnologia 130 nm CMOS, usando uma frequência de amostragem de 1 MHz, com uma largura de banda de 1 kHz e tensão de alimentação 1,2 V. É usada, nos integradores do sigma-delta, uma invulgar tipologia de Opamp de forma a obter um ganho elevado, sem recurso a técnicas cascode. O quantizador possui uma resolução de 1,5 bits e é realizado com dois comparadores dinâmicos, de forma a minimizar o consumo energético.The growing need to provide better health for the population requires the development of new and better medical devices. Portable devices for the analysis of biological signals, such as the electrocardiogram or electroencephalogram, is nowadays an important development, helping health professionals to come up with fast diagnoses on the field, or even for use by citizens who require constant vigilance .Developing these devices brings new challenges to the scientific community, namely at the analog/digital interface, the quality of data and power consumption. In order to design a good medical device it is necessary an analog/digital converter for low frequencies, with low power consumption and high resolution.This dissertation begins by providing the reader with the basic theory of analog/digital (ADC) and its state of the art. The main goal of the work is the design of an ADC based on a Sigma-Delta architecture that meets the necessary medical requirements. The converter was implemented in a 130 nm CMOS technology using a sampling frequency of 1 MHz, with a bandwidth of 1 kHz, and a source voltage of 1.2 V. The integrators of sigma-delta employs an unusual Opamp typology in order to reach a high gain, without resourcing to cascode techniques. The quantizer has a resolution of 1.5 bits and is realized with two dynamic comparators, in order to minimize power consumption.
48
Chen, Shr-Lung, and 陳仕龍. "CMOS Delta Sigma Magnetic to Digital Converter." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/89670513080719273701.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
89
In this thesis, we have proposed several magnetic to digital converters designed with MAGFET, and we have successfully transferred the magnetic signal into frequency domain, time domain, and voltage domain respectively. These application circuits are implemented in UMC 0.5mm DPDM CMOS process and SHARP 0.35mm DPDM CMOS process. In chapter2, the “double MOSFET method” has been applied to implement the linear resistor pairs in MOP, and this gives the possibility of implementing a fully integrated magnetic sensor interface. In chapter3, a magnetically controlled ring oscillator has been proposed. In particular, it exhibits the highest sensitivity/power ratio reported to date for a silicon magnetic field sensor based on oscillator. Another magnetic to pulse width digitizer has also been realized, which can reach a very small equivalent resolution. After off-line calibration, the offset can be reduced and gain error can be further minimized. Transferring the magnetic signal to frequency and time domain pave the way for the low voltage operation in the future. In chapter 4, We combined the MOP with the integrator of the modulator in the first order MDC, thus saving power and area because one opamp is spared. Combining this method with the pseudo two path technique, we presented a very compact second order MDC system using only opamp for low cost applications. In chapter5, the MAGFET offset canceling technique and differencing sampling technique are applied along with the design of MOP and integrator. The goal of reduced offset and gain factor enhancement are achieved. To sum up, we demonstrated the potential of oversampling techniques (in particular sigma-delta modulators and incremental A/D converters) for implementing very flexible, robust and performant sensor interface circuits. The measurement results have verified the correctness and feasibility of designed circuits. Such MDCs have the potential for low cost magnetic sensor applications.
49
Jen, Yung-Hsin, and 任永星. "An Integrated Sigma-Delta Noise-Spread Buck Converter." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/61695217339044281618.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
96
An integrated sigma.delta noise-spread buck converter using a discrete-time second order single.bit sigma-delta modulator (DT-SDM2) is presented. The DT-SDM2 buck converter and a compared PWM controller are designed and fabricated on a standard TSMC 0.35μm 3.3V CMOS process. Compared to a traditional PWM controller switching at 200 kHz, the DT-SDM2 sampling at 1M Hz suppresses the noise tone by 50dB at PWM switching frequency, spreads the noise floor by 53dB at DT-SDM2 sampling frequency,and decreases total noise power by 12.5% in 2M Hz with 95.6% efficiency and 0.83% output voltage ripple. The operating frequency of the proposed DT-SDM2 ranges from 400 KHz to 1 MHz. Simulation results show that DT-SDM2 has better noise performance than PWM and continuous.time SDM2 (CT-SDM2) buck converter.
50
Chuang, Chao-Hsun, and 莊肇勳. "The Delta-Sigma D/A converter of FPGA." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/23097676004884092553.
Full textAbstract:
碩士南台科技大學
電子工程系
99
The technique of low bandwidth, high resolution over-sampling interpolation delta-sigma modulator has been used extensively in digital to analog converter. The purpose of this thesis is to design a Delta-Sigma digital to analog converter which can be applied to voice signal. The architecture of this system is made up with an FIR filter and a 2nd order Delta-Sigma Modulator. This system focuses on the voice band signal with 10-bit digital data format, 20Hz to 3.4kHz frequency range, 8kHz input sampling rate and 32X over-sampling rate. The output is one digital bit to simplify the system circuit. Regarding to the design of this system, firstly, we use MATLAB to calculate the FIR coefficients and then simulate the whole system to confirm the feasibility and efficiency of this system. Secondly, we use verilog hardware description language to design the system circuits and also devise a test mechanism to verify the circuits.