Journal articles: 'Custom Processor Design'

1

Shinghal, Kshitij, Arti Noor, Neelam Srivastava, and Raghuvir Singh. "Custom Single Purpose Processor Design: For Low Power WSN Node." International Journal of Recent Trends in Electrical & Electronics Engineering 1, no. 1 (September 1, 2011): 15–24. http://dx.doi.org/10.7323/ijrte/v1_i1/04.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Trajkovic, Jelena, Samar Abdi, Gabriela Nicolescu, and Daniel D. Gajski. "Automated Generation of Custom Processor Core from C Code." Journal of Electrical and Computer Engineering 2012 (2012): 1–26. http://dx.doi.org/10.1155/2012/862469.

Full text

Abstract:

We present a method for construction of application-specific processor cores from a given C code. Our approach consists of three phases. We start by quantifying the properties of the C code in terms of operation types, available parallelism, and other metrics. We then create an initial data path to exploit the available parallelism. We then apply designer-guided constraints to an interactive data path refinement algorithm that attempts to reduce the number of the most expensive components while meeting the constraints. Our experimental results show that our technique scales very well with the size of the C code. We demonstrate the efficiency of our technique on wide range of applications, from standard academic benchmarks to industrial size examples like the MP3 decoder. Each processor core was constructed and refined in under a minute, allowing the designer to explore several different configurations in much less time than needed for manual design. We compared our selection algorithm to the manual selection in terms of cost/performance and showed that our optimization technique achieves better cost/performance trade-off. We also synthesized our designs with programmable controller and, on average, the refined core have only 23% latency overhead, twice as many block RAMs and 36% fewer slices compared to the respective manual designs.

APA, Harvard, Vancouver, ISO, and other styles

3

Bi, Zhuo, and Yijun Dai. "Datapath Design and Full Custom Implementation of Radix-2 CORDIC Processor." Procedia Engineering 15 (2011): 3848–53. http://dx.doi.org/10.1016/j.proeng.2011.08.720.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

S, Jamuna, Dinesha P, K. PShashikala, and Kishore Kumar K. "Design and Implementation of Runtime Reconfigurable Encryption Algorithms using Custom ICAP Processor." International Journal of Computer Network and Information Security 11, no. 12 (December 8, 2019): 10–16. http://dx.doi.org/10.5815/ijcnis.2019.12.02.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Bard, K., B. Dewey, Mei-Ting Hsu, T. Mitchell, K. Moody, V. Rao, R. Rose, J. Soreff, and S. Washburn. "Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM." Proceedings of the IEEE 95, no. 3 (March 2007): 530–54. http://dx.doi.org/10.1109/jproc.2006.889385.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Zou, Yong Yang, Ming Chen, and Kang Lin Wei. "Design of Custom AXI4 IP Based on AXI4 Protocol." Applied Mechanics and Materials 687-691 (November 2014): 2326–30. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.2326.

Full text

Abstract:

In addition to its own function, the realization of the custom AXI4 IP ,to a large extent,depends on the development tools.The method of custom AXI4 IP is mainly introduced in this paper.The Xilinx Vivado Design Suite is the development environment for custom AXI4 IP.The generated IP is a AXI4 slave IP which implements the data access.In order to accurately verify the AXI4 slave IP,an embedded system on a chip is created to make a processor and the generated slave IP link together.TheZynq-7000 All Programmable SoC is fully taken advantage of to prove that the AXI4 slave IP functions well.A simple application program runs in a SoC.The terminal that can display output results shows the slave IP work well and gets the desired results.

APA, Harvard, Vancouver, ISO, and other styles

7

ISSAD, M., B. BOUDRAA, M. ANANE, and N. ANANE. "SOFTWARE/HARDWARE CO-DESIGN OF MODULAR EXPONENTIATION FOR EFFICIENT RSA CRYPTOSYSTEM." Journal of Circuits, Systems and Computers 23, no. 03 (March 2014): 1450032. http://dx.doi.org/10.1142/s0218126614500327.

Full text

Abstract:

This paper presents an implementation of Rivest, Shamir and Adleman (RSA) cryptosystem based on hardware/software (HW/SW) co-design. The main operation of RSA is the modular exponentiation (ME) which is performed by repeated modular multiplications (MMs). In this work, the right-to-left (R2L) algorithm is used for the implementation of the ME as a programmable system on chip (PSoC). The processor MicroBlaze of Xilinx is used for flexibility. The R2L method is often suggested to improve the timing performance, since it is based on parallel computations of MMs. However, if the optimization of HW resources is a constraint, this method can be executed sequentially using a single modular multiplier as a custom intellectual property (IP). Consequently, the execution time of the ME becomes dependent of three factors, namely the capability of the custom IP to perform the MMs, the nonzero bit string of the exponent and the communication link between the processor and the custom IP. In order to achieve the best trade-off between area, speed and flexibility, we propose three implementations in this work. The first one is a pure software solution. The second one takes benefit of a HW accelerator dedicated to the MM execution. The last one is based on a dual strategy. Two parallel MMs are implemented within a custom IP and local memories are used close to the arithmetic units to minimize the communication link influence. The results show that in the application to RSA 1024-bits, the ME runs in 22,25 ms, while using only 1,848 slices.

APA, Harvard, Vancouver, ISO, and other styles

8

Chen, Cheng, Qian Huang, Yan Yan Yu, Wen Long Li, and Jun Yang. "Design and Implementation Based the SOPC of the 2D-FFT Processor." Applied Mechanics and Materials 513-517 (February 2014): 1030–33. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.1030.

Full text

Abstract:

This paper analyzed the principle of the two-dimensional FFT algorithm, and adopted the time domain extracted base 2D-FFT algorithm and CORDIC to achieve a one-dimensional FFT IP core in Quartus II platform, then used this IP core matrix transposition module to structure 2D-FFT core processing unit desired. In SOPC system, we adopted custom components and IP core packaging technology and adding the integration of the module. Completed the design of SOPC system, which was simulated and downloaded to the development board for verification and the test results were compared to the Matlab operation results. The simulation and test results showed that this design had a simple hardware structure, high throughput, high stability and a good prospect.

APA, Harvard, Vancouver, ISO, and other styles

9

Dramicanin, Dejan, Dejan Rakic, Slobodan Denic, and Veljko Vlahovic. "FPGA-based prototyping of IEEE 802.11a base band processor." Serbian Journal of Electrical Engineering 1, no. 3 (2004): 125–36. http://dx.doi.org/10.2298/sjee0403125d.

Full text

Abstract:

In technical literature and especially in domestic, predominant way to examine performance of 802.11a-based systems are experiments in simulations. In this paper, we present FPGA based 802.11a prototype, which gave us a possibility to gain closer insight into the problems of OFDM system implementation. A specific design of base band modem physical layer is discussed, along with the presentation of the FPGA prototyping platform on which it was developed. Prototype is implemented on the latest generation of FPGA chips, using state-of-the-art tools for DSP development. Custom made development environment, and design flow optimized for rapid prototyping of software defined radios, are also presented in the paper.

APA, Harvard, Vancouver, ISO, and other styles

10

Nishikant Sadafale, Minal Deshmukh, Prasad Khandekar,. "AN EFFICIENT FPGA OVERLAY FOR COLOR TRANSFORMATION FUNCTION USING HIGH LEVEL SYNTHESIS." INFORMATION TECHNOLOGY IN INDUSTRY 9, no. 1 (March 1, 2021): 280–87. http://dx.doi.org/10.17762/itii.v9i1.130.

Full text

Abstract:

Image Processing is a significantly desirable in commercial, industrial, and medical applications. Processor based architectures are inappropriate for real time applications as Image processing algorithms are quite intensive in terms of computations. To reduce latency and limitation in performance due to limited amount of memory and fixed clock frequency for synthesis in processor-based architecture, FPGA can be used in smart devices for implementing real time image processing applications. To increase speed of real time image processing custom overlays (Hardware Library of programmable logic circuit) can be designed to run on FPGA fabric. The IP core generated by the HLS (High Level Synthesis) can be implemented on a reconfigurable platform which allows effective utilization of channel bandwidth and storage. In this paper we have presented FPGA overlay design for color transformation function using Xilinx’s python productivity board PYNQ-Z2 to get benefit in performance over a traditional processor. Performance comparison of custom overlay on FPGA and Processor based platform shows FPGA execution yields minimum computation time.

APA, Harvard, Vancouver, ISO, and other styles

11

Bao, Ji Long, and Peng An. "The RF Amplifier Remote Monitoring System Based on Gigabit Ethernet." Advanced Materials Research 694-697 (May 2013): 2616–19. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.2616.

Full text

Abstract:

Based on the Gigabit Ethernet Protocol, the RF (Radio Frequency) power amplifier remote monitoring system was designed. The system collect digital signal from predistortion module, transmit the gigabit Ethernet network to outside, and improve the system efficiency. It adopts the SOPC technology hardcore and softcore, which makes the whole system realized in the single piece of chip. Softcore is the Alteras IP core--Nios II processor, design processors, make use of the custom parts and programs gigabit Ethernet transceiver and internal driving in processor. The integration and reliability of the system are in great improvement. Through testing, system function can satisfy transmission requirements of normal transceiver RF power amplifier state information and control information.

APA, Harvard, Vancouver, ISO, and other styles

12

Shi, Weiwei, An Pan, Shi Yu, and Chiu-Sing Choy. "A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 1 (January 2018): 159–67. http://dx.doi.org/10.1109/tcad.2017.2764073.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Krawczyk, Kamil, Paweł Tomaszewicz, and Mariusz Rawski. "Whirlpool SoPC Implementation - Hardware/Software Co-Design Example." International Journal of Electronics and Telecommunications 58, no. 1 (March 1, 2012): 21–26. http://dx.doi.org/10.2478/v10177-012-0003-9.

Full text

Abstract:

Whirlpool SoPC Implementation - Hardware/Software Co-Design Example The aim of this work was to design a System on Programmable Chip (SoPC), that implements the Whirlpool Hash Function (WHF) algorithm. An assumption of the project was to use an embedded soft-processor NIOS II controlling the whole system, which functionality was extended by a custom logic in order to improve the used algorithm efficiency. This paper presents the Whirlpool Hash Function realized in several SoPC configurations, which differ in implementation complexity and performance.

APA, Harvard, Vancouver, ISO, and other styles

14

Zhou, Qing Fang, Qian Huang, Ying Yuan, and Jun Yang. "Design and Implementation of Reconfigurable Encryption and Decryption System Based on SOPC." Applied Mechanics and Materials 347-350 (August 2013): 2979–82. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.2979.

Full text

Abstract:

The system is based on DES/3DES, AES cipher algorithm as the research object.According to the characteristics of the algorithm, designs a configuration mode which can share resource in space and configurate algorithm in time. Then it uses hardware description language Verilog HDL to realize and optimize the design, and completes a custom reconfigurable DES/3DES/AES encryption/decryption IP core. By SOPC technology, the IP core, Nios II processor, network controller and other function. The design hardware structureis simple, flexibility, security, which can be widely used in the field of informationsecurity.

APA, Harvard, Vancouver, ISO, and other styles

15

Santos, P. V., José Carlos Alves, and João Canas Ferreira. "A Reconfigurable Custom Machine for Accelerating Cellular Genetic Algorithms." U.Porto Journal of Engineering 2, no. 2 (March 20, 2018): 2–13. http://dx.doi.org/10.24840/2183-6493_002.002_0002.

Full text

Abstract:

In this work we present a reconfigurable and scalable custom processor array for solving optimization problems using cellular genetic algorithms (cGAs), based on a regular fabric of processing nodes and local memories. Cellular genetic algorithms are a variant of the well-known genetic algorithm that can conveniently exploit the coarse-grain parallelism afforded by this architecture. To ease the design of the proposed computing engine for solving different optimization problems, a high-level synthesis design flow is proposed, where the problem-dependent operations of the algorithm are specified in C++ and synthesized to custom hardware. A spectrum allocation problem was used as a case study and successfully implemented in a Virtex-6 FPGA device, showing relevant figures for the computing acceleration.

APA, Harvard, Vancouver, ISO, and other styles

16

Lin, Hai, and Yunsi Fei. "Resource Sharing of Pipelined Custom Hardware Extension for Energy-Efficient Application-Specific Instruction Set Processor Design." ACM Transactions on Design Automation of Electronic Systems 17, no. 4 (October 2012): 1–20. http://dx.doi.org/10.1145/2348839.2348843.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Wong, Tingh Wee, Bryan Ng, and Chee Onn Wong. "Encoding Custom Instruction Generation as Satisfiability Problem." Advanced Materials Research 403-408 (November 2011): 502–10. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.502.

Full text

Abstract:

The emergence of Application-specific Instruction-set Processor (ASIP) has encouraged the proliferation of tool-chains used to streamline its design flow. One of the features much sought-after in these tool-chains is notably the automatic generation of Application-specific Functional Units (AFUs) which, in turn, involves the custom instruction generation as a crucial step. Whereupon an additional step is assumed to pipeline the patterns identified for fulfilling the I/O constraint, custom instructions that correspond to maximal valid subgraphs are mostly beneficial to the speedup gain. Therefore, we present in this paper a propositional satisfiability approach to efficiently identify the custom instructions which contain a large number of valid nodes. Our approach is different substantially from the previous works where it uses an edge classification method to reduce the search space for convexity checking. The experiment results show that our method can, in a matter of few seconds, identify a set of custom instructions that speed up the application to a few times faster.

APA, Harvard, Vancouver, ISO, and other styles

18

Sideris, Argyrios, Theodora Sanida, and Minas Dasygenis. "High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor." Technologies 8, no. 1 (February 10, 2020): 15. http://dx.doi.org/10.3390/technologies8010015.

Full text

Abstract:

Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak algorithm is the winner of the NIST competition for the adoption of the new standard SHA-3 hash algorithm. In this work, we present hardware throughput optimization techniques for the SHA-3 algorithm using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) programming language for all output lengths in the Keccak hash function (224, 256, 384 and 512). Our experiments were performed with the Nios II processor on the FPGA Arria 10 GX (10AX115N2P45E1SG). We applied two architectures, one without custom instruction and one with floating point hardware 2. Finally, we compare the results with other existing similar designs and found that the proposed design with floating point 2 optimizes throughput (Gbps) compared to existing FPGA implementations.

APA, Harvard, Vancouver, ISO, and other styles

19

Ranjith, C., and S. P. Joy Vasantha Rani. "A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware–Software Co-Design." Journal of Circuits, Systems and Computers 29, no. 01 (April 4, 2019): 2050014. http://dx.doi.org/10.1142/s0218126620500140.

Full text

Abstract:

Recent studies show the impact of genetic algorithms (GA) in the design of evolutionary finite impulse response (FIR) filters. Studies have shown hardware and software method of GA implementation for design. Hardware method improves speed due to parallelism, pipelining and the absence of the function calls compared to software implementation. But area constraint was the main issue of hardware implementation. Therefore, this paper illustrates a hardware–software co-design concept to implement an Adaptive GA processor (AGAP) for FIR filter design. The architecture of AGAP uses adaptive crossover and mutation probabilities to speed up the convergence of the GA process. The AGAP architecture was implemented using Verilog Hardware Description Language (HDL) and instantiated as a custom intellectual property (IP) core to the soft-core MicroBlaze processor of Spartan 6 (XC6SLX45-3CSG324I) FPGA. The MicroBlaze processor controls the AGAP IP core and other interfaces using Embedded C programs. The experiment demonstrated a significant 134% improvement in speed over hardware implementation but with a marginal increase in area. The complete evaluation and evolution of the filter coefficients were executed on a single FPGA. The system on chip (SoC) concept enables a robust and flexible system.

APA, Harvard, Vancouver, ISO, and other styles

20

Tsai, Pang Wei, Hou Yi Chou, Mon Yen Luo, and Chu Sing Yang. "Design a Flexible Software Development Environment on NetFPGA Platform." Applied Mechanics and Materials 411-414 (September 2013): 1665–69. http://dx.doi.org/10.4028/www.scientific.net/amm.411-414.1665.

Full text

Abstract:

Among numerous embedded platforms, NetFPGA provides developers with a freely programmable FPGA component to design custom functionalities in networking. However, most hardware projects are developed based on reference designs without embedded operating system. For hybrid developments on multi-layers, there will be some difficulties to apply. On the other hand, due to the limited resources on embedded platform, both performance and flexibility need to be concerned on implementation. And for networking processing, it is quite difficult to adjust control parameters without software environment. Therefore, this paper proposes an integrated architecture using PowerPC processor on NetFPGA and embedded Linux operating system on NetFPGA platform. This not only provides developers with an environment for software execution which added more flexibility, but also enhanced the system to provide more applied possibilities on development.

APA, Harvard, Vancouver, ISO, and other styles

21

Bailey, Donald G. "Image Processing Using FPGAs." Journal of Imaging 5, no. 5 (May 10, 2019): 53. http://dx.doi.org/10.3390/jimaging5050053.

Full text

Abstract:

Nine articles have been published in this Special Issue on image processing using field programmable gate arrays (FPGAs). The papers address a diverse range of topics relating to the application of FPGA technology to accelerate image processing tasks. The range includes: Custom processor design to reduce the programming burden; memory management for full frames, line buffers, and image border management; image segmentation through background modelling, online K-means clustering, and generalised Laplacian of Gaussian filtering; connected components analysis; and visually lossless image compression.

APA, Harvard, Vancouver, ISO, and other styles

22

Avasare, Prabhat, Jeroen Declerck, Miguel Glassee, Amir Amin, Erik Umans, Praveen Raghavan, and Martin Palkovic. "Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication." International Journal of Embedded and Real-Time Communication Systems 4, no. 1 (January 2013): 42–63. http://dx.doi.org/10.4018/jertcs.2013010103.

Full text

Abstract:

In current era of complex chip designs targeting wireless mobile terminals, architects and designers need to conform to tight design constraints – both in terms of performance (e.g. execution time, silicon area, energy consumption) and time-to-market. Further, additional flexibility is required in these designs to handle multiple wireless standards, sometimes even concurrently. To achieve these challenging goals, the authors introduce a platform architecture that uses a decentralized control to minimize communication and control overhead while keeping timing predictable by using state-of-the-art components and a novel interconnect. The authors demonstrate three main achievements in running multiple wireless standards on their platform: 1.053Gbps 4x4 80MHz WLAN 802.11ac receiver data path meeting the SIFS timing with a latency of 12.5µs, dual concurrent 173Mbps 2x2 20MHz Cat-4 3GPP-LTE receiver and platform reconfiguration from WLAN 11n receiver to 3GPP-LTE one in 52µs. Further the authors describe the design flow used to prepare main components of our platform architecture for a tape-out, while especially keeping a close eye on energy consumption. We believe that our chip design flow is generic and can be used in other custom processor chip designs even outside wireless domain.

APA, Harvard, Vancouver, ISO, and other styles

23

Baklouti, Mouna, and Mohamed Abid. "Multi-Softcore Architecture on FPGA." International Journal of Reconfigurable Computing 2014 (2014): 1–13. http://dx.doi.org/10.1155/2014/979327.

Full text

Abstract:

To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs) are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication).

APA, Harvard, Vancouver, ISO, and other styles

24

DOKOUZYANNIS, STAVROS P., and ARGIRIS P. MOKIOS. "A NEW PLATFORM FOR THE IMPLEMENTATION OF REGULAR ITERATIVE ALGORITHMS INTO FPGAs." Journal of Circuits, Systems and Computers 20, no. 06 (October 2011): 975–99. http://dx.doi.org/10.1142/s0218126611007712.

Full text

Abstract:

The implementation of regular iterative algorithms (RIAs) in important scientific fields such as image processing, computer arithmetic, cryptography and their implementation in processor arrays architectures, has been extensively studied over the last three decades. Numerous design methodologies and tools have been proposed, mostly targeting custom very large scale integration (VLSI) chips. The advent of field-programmable gate arrays (FPGAs) has attracted many researchers to incorporate previously acquired knowledge and experience in designing VLSI chips, to this new technology. This paper addresses the issue of the implementation of regular algorithms into FPGAs and presents a novel design tool for the implementation of RIAs, formulated as dependence graphs (DGs), on systolic arrays. Furthermore, a platform scheme for the systolic arrays hardware realization is proposed.

APA, Harvard, Vancouver, ISO, and other styles

25

Wang, Zheng Dong, Kai He, Hai Tao Fang, and Ru Xu Du. "Design of Embedded Controller with Flexible Programming for Industrial Robot." Applied Mechanics and Materials 457-458 (October 2013): 1390–95. http://dx.doi.org/10.4028/www.scientific.net/amm.457-458.1390.

Full text

Abstract:

This paper presents an embedded controller of low cost and high performance for industrial robot. The ARM microprocessor is chosen as the main controller for the processor. Based on the 7-segment cubic spline interpolation algorithm, a real-time control for the robot is implemented. This proposed trajectory method can perfectly generates speed S-curve shape for a start-stop process of the robot. In this article a programming language, G-code, is developped for the robots motion control by using the editing interface we designed specially on PC platform. With all the features for 2-4 degree of freedom robot application, the editing interface has been developed for editing and compiling G-code, which can be downloaded into the microprocessor with the custom communication protocol through communication interface. The programming method of the G-code language is easy to learn and use for the non-professional users. The paper describes the design and implementation in detail for the controller, which was validated on our designed SCARA robot, and it worked reliably.

APA, Harvard, Vancouver, ISO, and other styles

26

MAJZOUB, S., and H. DIAB. "INSTRUCTION-SET EXTENSION FOR CRYPTOGRAPHIC APPLICATIONS ON RECONFIGURABLE PLATFORM." Journal of Circuits, Systems and Computers 16, no. 06 (December 2007): 911–27. http://dx.doi.org/10.1142/s0218126607004076.

Full text

Abstract:

Reconfigurable Systems represent a middle trade-off between speed and flexibility in the processor design world. It provides performance close to the custom-hardware and yet preserves some of the general-purpose processor flexibility. Recently, the area of reconfigurable computing has received considerable interest in both its forms: the FPGA and coarse-grain hardware. Since the field is still in its developing stage, it is important to perform hardware analysis and evaluation of certain key applications on target reconfigurable architectures to identify potential limitations and improvements. This paper presents the mapping and performance analysis of two encryption algorithms, namely Rijndael and Twofish, on a coarse grain reconfigurable platform, namely MorphoSys. MorphoSys is a reconfigurable architecture targeted for multimedia applications. Since many cryptographic algorithms involve bitwise operations, bitwise instruction set extension was proposed to enhance the performance. We present the details of the mapping of the bitwise operations involved in the algorithms with thorough analysis. The methodology we used can be utilized in other systems.

APA, Harvard, Vancouver, ISO, and other styles

27

d’Agostino, L., and A. J. Acosta. "A Cavitation Susceptibility Meter With Optical Cavitation Monitoring—Part One: Design Concepts." Journal of Fluids Engineering 113, no. 2 (June 1, 1991): 261–69. http://dx.doi.org/10.1115/1.2909490.

Full text

Abstract:

This work is concerned with the design of a Cavitation Susceptibility Meter based on the use of a venturi tube for the measurement of the active cavitation nuclei concentration in water samples as a function of the applied tension. The operation of the Cavitation Susceptibility Meter is analyzed and the main considerations leading to the proposed design are illustrated and critically discussed. The results of this analysis indicate that the operational range is mainly limited by nuclei interference, flow separation and saturation (choking), and suggest to develop a Cavitation Susceptibility Meter where: (a) the flow possesses a laminar potential core throughout the venturi throat section in all operational conditions; (b) the pressure at the venturi throat is determined from the upstream pressure and the local flow velocity; (c) the detection of cavitation and the measurement of the flow velocity are carried out optically by means of a Laser Doppler Velocimeter; (d) a custom-made electronic Signal Processor incorporating a frequency counter is used for real time data generation and temporary storage; (e) a computerized system performs the final acquisition and reduction of the data.

APA, Harvard, Vancouver, ISO, and other styles

28

DAVALLE, DANIELE, RICCARDO CASSETTARI, SERGIO SAPONARA, LUCA FANUCCI, LUCA CUCCHI, FRANCO BIGONGIARI, and WALTER ERRICO. "DESIGN, IMPLEMENTATION AND TESTING OF A FLEXIBLE FULLY-DIGITAL TRANSPONDER FOR LOW-EARTH ORBIT SATELLITE COMMUNICATIONS." Journal of Circuits, Systems and Computers 23, no. 10 (October 14, 2014): 1450148. http://dx.doi.org/10.1142/s0218126614501485.

Full text

Abstract:

This paper presents a flexible Telemetry, Tracking & Command (TT&C) transponder for Earth Observation (EO) small satellites. The proposed device adds to the state-of-the-art EO TT&C transponders the possibility of scientific data transfer thanks to the high downlink data-rate (up to 40 Mbps) and in-flight reconfigurability via Telecomand (TC). The integration of these features in one single device represents a considerable optimization in terms of mass budget, which is important for EO small satellites. Furthermore, in-flight reconfigurability of communication parameters via TC is important for in-orbit link optimization, which is especially useful for Low-Earth Orbit (LEO) satellites where visibility can be as short as few hundreds of seconds. The proposed transponder is a digital radio unit working at 70 MHz intermediate frequency (IF). A new custom and configurable hardware accelerator was developed to cover intensive radio DSP functions at IF. The custom hardware is integrated in a single FPGA with a space-compliant processor core, for control, configuration and interface with the other satellite subsystems. All the quantization parameters were fine-tailored to reach a trade-off between hardware complexity and implementation loss (IL). The IF RX/TX ports require eight bits and seven bits, respectively. The IL is 0.5 dB at BER = 10-5 for the RX chain. A system proof-of-concept was implemented on the Xilinx Virtex 6 VLX75T-FF484 FPGA. The total device occupation is 82%. The power consumption of the design fitted in FPGA is less than 2 W. The power consumption of the whole demonstrator board is less than 9 W.

APA, Harvard, Vancouver, ISO, and other styles

29

Wu, Yu En, Kuo Chan Huang, and Chih Lung Shen. "Application of Embedded System in Energy Management System." Advanced Materials Research 875-877 (February 2014): 1949–53. http://dx.doi.org/10.4028/www.scientific.net/amr.875-877.1949.

Full text

Abstract:

In this paper, a custom-made energy management system based on embedded system with a touch panel/LCD/FPGA and microprocessor is implemented, it not only solve the problem of energy waste, control scattered energy supply and saving, but also generate a user-friendly control platform. The life of the proposed system is also longer than an EMS with personal computer. In the proposed embedded EMS, a simulation of FPGA is firstly designed and processed with the control circuit of touch panel, RENESASs micro-processor, and communication panels of ZIGBEE and CAN BUS to constitute the system hardware. Analysis and allocation of energy is then done to complete the software design. Finally, experimental results are used to verify the feasibility and reliability of the proposed EMS.

APA, Harvard, Vancouver, ISO, and other styles

30

Janssen, Curtis L., Helgi Adalsteinsson, Scott Cranford, Joseph P. Kenny, Ali Pinar, David A. Evensky, and Jackson Mayo. "A Simulator for Large-Scale Parallel Computer Architectures." International Journal of Distributed Systems and Technologies 1, no. 2 (April 2010): 57–73. http://dx.doi.org/10.4018/jdst.2010040104.

Full text

Abstract:

Efficient design of hardware and software for large-scale parallel execution requires detailed understanding of the interactions between the application, computer, and network. The authors have developed a macro-scale simulator (SST/macro) that permits the coarse-grained study of distributed-memory applications. In the presented work, applications using the Message Passing Interface (MPI) are simulated; however, the simulator is designed to allow inclusion of other programming models. The simulator is driven from either a trace file or a skeleton application. Trace files can be either a standard format (Open Trace Format) or a more detailed custom format (DUMPI). The simulator architecture is modular, allowing it to easily be extended with additional network models, trace file formats, and more detailed processor models. This paper describes the design of the simulator, provides performance results, and presents studies showing how application performance is affected by machine characteristics.

APA, Harvard, Vancouver, ISO, and other styles

31

Ezhumalai, P., A. Chilambuchelvan, and C. Arun. "Novel NoC Topology Construction for High-Performance Communications." Journal of Computer Networks and Communications 2011 (2011): 1–6. http://dx.doi.org/10.1155/2011/405697.

Full text

Abstract:

Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systems-on-chip (SoC) design. We proposed an idea on building customizing synthesis network—on-chip with the better flow partitioning and also considered power and area reduction as compared to the already presented regular topologies. Hence to improve the performance of SoC, first, we did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, we observed that the overall latency and throughput of the EBFT is better compared to other topologies, The next best in case of latency and throughput is BFT. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieved reduction in power consumption and average hop count over custom topology implementation.

APA, Harvard, Vancouver, ISO, and other styles

32

Kim, Justin Y., Zendai Kashino, Tyler Colaco, Goldie Nejat, and Beno Benhabib. "Design and implementation of a millirobot for swarm studies –mROBerTO." Robotica 36, no. 11 (July 30, 2018): 1591–612. http://dx.doi.org/10.1017/s0263574718000589.

Full text

Abstract:

SUMMARYThe use of millirobots, particularly in swarm studies, would enable researchers to verify their proposed autonomous cooperative behavior algorithms under realistic conditions with a large number of agents. While multiple designs for such robots have been proposed, they, typically, require custom-made components, which make replication and manufacturing difficult, and, mostly, employ non-modular integral designs. Furthermore, these robots' proposed small sizes tend to limit sensory perception capabilities and operational time. Some have resolved few of the above issues through the use of extensions that, unfortunately, add to their size.In contribution to the pertinent field, thus, a novel millirobot with an open-source design, addressing the above concerns, is presented in this paper. Our proposed millirobot has a modular design and uses easy to source, off-the-shelf components. Themilli-robot-Toronto (mROBerTO) also includes a variety of sensors and has a 16 × 16 mm2footprint.mROBerTO's wireless communication capabilities include ANT™, Bluetooth Smart, or both simultaneously. Data-processing is handled by an ARM processor with 256 KB of flash memory. Additionally, the sensing modules allow for extending or changing the robot's perception capabilities without adding to the robot's size. For example, the swarm-sensing module, designed to facilitate swarm studies, allows for measuring proximity and bearing to neighboring robots and performing local communications.Extensive experiments, some of which are presented herein, have illustrated the capability ofmROBerTOunits for use in implementing a variety of commonly proposed swarm algorithms.

APA, Harvard, Vancouver, ISO, and other styles

33

Saha, Rajib Kumar, Madhumita Ray, and Chao Zhang. "Computational fluid dynamics simulation and parametric study of an open channel ultra-violet wastewater disinfection reactor." Water Quality Research Journal 50, no. 1 (October 17, 2014): 58–71. http://dx.doi.org/10.2166/wqrjc.2014.034.

Full text

Abstract:

The disinfection characteristics of an open channel ultra-violet (UV) disinfection reactor is investigated numerically. The computational fluid dynamics (CFD) model used in this study is based on the volume of fluid (VOF) method to capture the water–air interface. The Lagrangian particle tracking method is used to calculate the microbial particle trajectory and the discrete ordinate (DO) model is used to calculate the UV intensity field inside the reactor. A commercial CFD software package ANSYS FLUENT is used to solve the governing equations. Custom user defined functions (UDFs) are developed to calculate the UV doses. A post-processor is developed in MATLAB to implement the inactivation kinetics of the microbes. The post-processor provides the probabilistic dose distribution and reduction equivalent dose (RED) values achievable in the reactor. The numerical predictions are compared with available experimental data to validate the CFD model. A parametric study is performed to understand the effects of different parameters on disinfection performance of the reactor. The low/high dosed particle trajectories, which can provide an insight for hydraulic and optical characteristics of the reactor for possible design improvements, are identified.

APA, Harvard, Vancouver, ISO, and other styles

34

Zając, Piotr. "Compact Thermal Modelling Tool for Fast Design Space Exploration of 3D ICs with Integrated Microchannels." Energies 13, no. 9 (May 2, 2020): 2217. http://dx.doi.org/10.3390/en13092217.

Full text

Abstract:

Integrated microchannel cooling is a very promising concept for thermal management of 3D ICs, because it offers much higher cooling performance than conventional forced-air convection. The thermo-fluidic simulations of such chips are usually performed using a computational fluid dynamics (CFD) approach. However, due to the complexity of the fluid flow modelling, such simulations are typically very long and faster models are therefore considered. This paper demonstrates the advantages of TIMiTIC—a compact thermal simulator for chips with liquid cooling—and shows its practical usefulness in design space exploration of 3D ICs with integrated microchannels. Moreover, thermal simulations of a 3D processor model using the proposed tool are used to estimate the optimal power dissipation profile in the chip and to prove that such an optimal profile allows for a very significant (more than 10 °C) peak temperature reduction. Finally, a custom correlation metric is introduced which allows the comparison of the power distribution profiles in terms of the peak chip temperature that they produce. Statistical analysis of the simulation results demonstrates that this metric is very accurate and can be used for example in thermal-aware task scheduling or dynamic voltage and frequency scaling (DVFS) algorithms.

APA, Harvard, Vancouver, ISO, and other styles

35

BHATTACHARYA, ARUP K., and SYED S. HAIDER. "A VLSI IMPLEMENTATION OF THE INVERSE DISCRETE COSINE TRANSFORM." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (April 1995): 303–14. http://dx.doi.org/10.1142/s0218001495000146.

Full text

Abstract:

The Inverse Discrete Cosine Transform (IDCT) is an important function in HDTV, digital TV and multimedia systems complying with JPEG or MPEG standards for video compression. However, the IDCT is computationally intensive and therefore very expensive to implement in VLSI using direct matrix multiplication. By properly arranging the input coefficient sequence and the output data, the rows and columns of the transform matrix can be reordered to build modular regularity suitable for custom implementation in VLSI. This regularity can be exploited, so that a single permutation can be used to derive each output column from the previous one using a circular shift of an accumulator’s input data multiplied in a special sequence. This technique, using only one 1-dimensional IDCT processor and seven constant multipliers, and its implementation are presented. Operation of 58 MHz under worst case conditions is easily achieved, thus making the design applicable to a wide range of video and real time image processing applications. Fabricated in 0.5 micron triple metal CMOS technology, the IDCT contains 70,000 transistors occupying 7 mm2 square silicon. The design has been used on an AT&T MPEG video decoder chip.

APA, Harvard, Vancouver, ISO, and other styles

36

Beaman, Brian, and Jean Audet. "High Current Testing and Simulation for Land Grid Array Sockets." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000659–62. http://dx.doi.org/10.4071/isom-2017-poster3_002.

Full text

Abstract:

Abstract Land grid array (LGA) sockets are commonly used for industry standard and custom microprocessors to meet the increased performance challenges for a variety of server applications. Along with the need for increased high speed signaling capabilities comes the challenge to support lower voltages and higher currents. Typical testing that is conducted by the LGA socket suppliers does not provide an accurate assessment of the maximum current capabilities in a real product application due to the test card design and construction limitations. Typical test card designs use daisy chain connections to wire multiple LGA socket contacts in series. The daisy chain wiring in the test card adds to the resistive heating and results in an inaccurate maximum current rating. Also, the test cards typically do not have a cross section construction that is representative of a real product application with multiple ground planes that provide improved thermal dissipation of the heat generated by the LGA socket interface. Hardware testing was conducted to better understand the performance limitations for a new product application. The test card was designed to use multiple voltage and ground planes in the circuit card cross section to provide a low impedance path for current flow and a low voltage drop through the LGA socket interface. In addition to the test card construction, the test hardware included a special test module with a shorted chip to provide a more accurate power distribution path through the socket and processor package. The test variables included different plating metallurgy options for the LGA socket and the processor module along with different configurations for the voltage supply and ground return contacts. Electrical and thermal modeling techniques were used to simulate the test hardware configuration with good correlation between the hardware and modeling results. Based on the positive correlation results, additional modeling was conducted to simulate the worst case power mapping conditions for the processor chip along with a more accurate power distribution. The additional modeling results provided further insights into the maximum current capabilities for the LGA socket based on the temperature increase from the resistive heating in the socket contacts.

APA, Harvard, Vancouver, ISO, and other styles

37

Purushottama and Kishore C. "DIAGNOSIS OF DIABETIC RETINOPATHY THROUGH SCREENING OF RETINAL IMAGES." International Journal of Research -GRANTHAALAYAH 5, no. 4RACEEE (April 30, 2017): 92–104. http://dx.doi.org/10.29121/granthaalayah.v5.i4raceee.2017.3330.

Full text

Abstract:

Diabetic Retinopathy (DR) is progressive dysfunction of the retinal blood vessels caused by chronic hyperglycemia which can be a complication of diabetes type 1 or diabetes type 2. Initially, DR is asymptomatic, if not treated though it can cause low vision and blindness. Diabetic retinopathy is responsible for 1.8 million of the 37 million cases of blindness throughout the world. So the early detection of Diabetic retinopathy through proper screening is essential. The paper presents a Diabetic Retinopathy Screening System which can be used as a primary diagnosis tool by ophthalmologists in the screening process to detect symptoms of Diabetic Retinopathy. The system uses the anatomical structures such as blood vessels, exudates and microaneurysms in retinal images. The retinal images are segmented and classified as normal or DR affected images by extracting features from segmented images and the Gray Level Co-occurrence Matrix (GLCM). The classifier used is Support Vector Machine (SVM) which gives a better accuracy. The system is implemented and tested in MATLAB and LabView for the standard database and need to be optimized for real time screening of images. LabView creates distributable .EXE files and .DLL files which can be downloaded into the FPGA/DSP processor. Hardware implementation on LabView FPGA presents a small learning curve which drastically reduces development time and eliminates the need for custom hardware design.

APA, Harvard, Vancouver, ISO, and other styles

38

Russek, Paweł, Ernest Jamro, Agnieszka Dąbrowska-Boruch, and Kazimierz Wiatr. "A study of the loops control for reconfigurable computing with OpenCL in the LABS local search problem." International Journal of High Performance Computing Applications 34, no. 1 (August 12, 2019): 103–14. http://dx.doi.org/10.1177/1094342019868515.

Full text

Abstract:

In this article, we study the steepest descent local search (SDLS) algorithm that is used as the improvement step in the memetic algorithms for the search of low autocorrelation binary sequences (LABS). We address the method of reconfigurable computing, as the algorithm is of the field programmable gate array (FPGA) type as it features the integer operations, bit-wise data representation, regular execution flow, and huge computational complexity. It contains four levels of nested loops, but its direct parallel implementation as a custom processor leads to typical problems because the loops expose a dynamic range and too many iterations. This inhibits a simple parallel data path that is typically produced by the method of the loop unrolling. We have examined the four architectures that mitigate the found obstacles, and we provide the results of their implementation. The solutions take advantages of the loop pipelining, reordering of the loops, and dynamic reconfiguration. The recently available development tool was involved in our study as we have used the OpenCL (OCL) platform for FPGAs to draw practical conclusions. The given proposals are characterized by their performance and capacity for a problem size. Consequently, the speed/size trade-off is highlighted, as an FPGA size is a design constraint. The performance of the FPGA-based solutions is compared to the CPU speed, and the maximum reported speed-up is 750. Readers can further develop and/or use the presented OCL solutions for efficient LABS discovery as we provide the corresponding software repository.

APA, Harvard, Vancouver, ISO, and other styles

39

Chen, Xiaoyong, Douglas L. Maskell, and Yang Sun. "Fast Identification of Custom Instructions for Extensible Processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 2 (February 2007): 359–68. http://dx.doi.org/10.1109/tcad.2006.883915.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Papanu, Victor. "Comparative Test Data for TIM Materials for LED Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (January 1, 2012): 000655–83. http://dx.doi.org/10.4071/2012dpc-ta41.

Full text

Abstract:

Developments in thermal interface materials (TIMs) continue across the industry with a variety of different types of materials. Thermal and mechanical design engineers are often confronted with the need to select which type or category of TIM material is the most appropriate for a specific LED module application, which can be confusing, and how to determine which materials provide the best thermal performance. The next step is understanding which TIM material types meet requirements for ease of shipping, handling, placement, cost, and rework. These are important distinctions, in addition to thermal performance. This presentation will illustrate comparative testing results for a set of thermal interface materials (TIMs) in different categories, using different TIM testing procedures. Test data prepared using three different test methods will be compared:1. ASTM D5470-06 with known temperatures and clamping forces;2. In-situ testing with industry-standard semiconductor modules, at known temperatures and estimated clamping forces;3. In-situ testing utilizing a thermal test vehicle (TTV) for TIM2 performance for a processor module. In-situ testing has been performed at an independent power semiconductor manufacturer, using both industry-standard and commonly-available modules and a custom-designed module with a relatively small footprint, capable of high operating junction temperatures. This testing data can illustrate how different types of TIM materials perform in laboratory testing conditions, for precise comparisons on thermal performance alone; and how different types of materials perform in what are termed as “in-situ” test procedures. This term is used for application-specific conditions, where additional variables are encountered in the testing (such as non-flat surface conditions and unknown clamping force values), which is significantly different from the laboratory conditions used to generate ASTM D-5470 test values. The comparative testing that has been undertaken will be described, showing that images of various power semiconductors with several different materials tend to correlate with the thermal resistance of materials measured with the ASTM D 5470-06 method. These thermal interface materials were also tested on a TTV supplied by a major processor module. The relevance of the thermal imaging, the TTV and the ASTM values will be discussed. This presentation is intended to illustrate the differences in experimental data from one TIM material to another, as well as the differences in testing procedures.

APA, Harvard, Vancouver, ISO, and other styles

41

Faraboschi, Paolo. "The design of a technology platform for custom VLIW embedded processors." Computer Physics Communications 139, no. 1 (September 2001): 104–8. http://dx.doi.org/10.1016/s0010-4655(01)00233-8.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Servare Junior, Marcos Wagner Jesus, Patrícia Alcântara Cardoso, Marta Monteiro da Costa Cruz, and Marcia Helena Moreira Paiva. "Mathematical model for supply chain design with time postponement." TRANSPORTES 26, no. 4 (December 28, 2018): 1–15. http://dx.doi.org/10.14295/transportes.v26i4.1324.

Full text

Abstract:

Projetar cadeia de suprimentos é uma importante decisão estratégica e seu impacto influencia diretamente na eficiência e no nível de serviço. O projeto se torna mais complexo quando o objetivo é minimizar o custo de distribuição e utilizar a postergação de tempo na cadeia de suprimentos. Os modelos matemáticos atualmente estudados na literatura de cadeia de suprimentos consideram vários atores. Entretanto, em problemas reais existem diferentes combinações desses atores, criando fluxos próprios de transportes e aumentando a complexidade da cadeia de suprimentos. Este artigo propõe um modelo matemático para projetar a cadeia de suprimentos com postergação de tempo a partir da programação não linear inteira mista para minimizar o custo total, considerando os custos de transportes, abertura de instalações e operacionais. O modelo permite a possibilidade de uma instalação híbrida, ou seja, dois tipos de instalações abertas no mesmo local, sendo uma importante oportunidade de redução de custos. Diferentes conjuntos de instâncias foram simulados para buscar a solução ótima e analisar o comportamento da cadeia de suprimentos em diferentes tamanhos de cenários, os quais foram resolvidos usando um solver comercial e suas performances foram estudadas. O modelo proposto apresenta viabilidade em seu uso para instâncias pequenas e médias com tempo computacional suficiente para auxílio no processo de tomada de decisão.

APA, Harvard, Vancouver, ISO, and other styles

43

NAKAMURA, Y., and K. HOSOKAWA. "Fast FPGA-Emulation-Based Simulation Environment for Custom Processors." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, no. 12 (December 1, 2006): 3464–70. http://dx.doi.org/10.1093/ietfec/e89-a.12.3464.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Kameyama, Michitaka. "Special Issue on Computer Architecture for Robotics." Journal of Robotics and Mechatronics 2, no. 6 (December 20, 1990): 417. http://dx.doi.org/10.20965/jrm.1990.p0417.

Full text

Abstract:

In the realization of intelligent robots, highly intelligent manipulation and movement techniques are required such as intelligent man-machine interfaces, intelligent information processing for path planning and problem solutions, practical robot vision, and high-speed sensor signal processing. Thus, very high-speed processing to cope with vast amounts of data as well as the development of various algorithms has become important subjects. To fulfill such requirements, the development of high-performance computer architecture using advanced microelectronics technology is required. For these purposes, the development of implementing computer systems’ for robots will be classified as follows: (a) Use of general-purpose computers As the performance of workstations and personal computers is increased year by year, software development is the major task without requiring hardware development except the interfaces with peripheral equipment. Since current high-level languages and software can be applied, the approach is excellent in case of system development, but the processing performance is limited. (b) Use of commercially available (V) LSI chips This is an approach to design a computer system by the combination of commercially available LSIs. Since the development of both hardware and software is involved in this system development, the development period tends to be longer than in (a). These chips include general-purpose microprocessors, memory chips, digital signal processors (DSPs) and multiply-adder LSIs. Though the kinds of available chips are limited to some degree, the approach can cope with a considerably high-performance specifications because a number of chips can be flexibly used. (c) Design, development and system configuration of VLSI chips This is an approach to develop new special-purpose VLSI chips using ASIC (Application Specific Integrated Circuit) technology, that is, semicustom or full-custom technology. If these attain practical use and are marketed, they will be widely used as high-performance VLSI chips of the level (b). Since a very high-performance specification must be satisfied, the study of very high performance VLSI computer architecture becomes very important. But this approach involving chip development requires a very long period in the design-development from the determination of processor specifications to the system configuration using the fabricated chips. For the above three approaches, the order from the viewpoint of ease of development will be (a), (b) and (c), while that from the viewpoint of performance will be (c), (b) and (a). Each approach is not exclusive but is complementary each other. For example, the development of new chips by (c) can also give new impact as the components of (a) and (b). Further, the common point of these approaches is that performance improvement by highly parallel architecture becomes important. This special edition introduces, from the above standpoint, the latest information on the present state and' future prospects of the computer techniques in Japan. We hope that this edition will contribute to the development of this field.

APA, Harvard, Vancouver, ISO, and other styles

45

Oprime, Pedro Carlos, Vitória Maria Miranda Pureza, and Samuel Conceição de Oliveira. "Sequenciamento sistemático de experimentos fatoriais como alternativa à ordem aleatória." Gestão & Produção 24, no. 1 (February 9, 2017): 108–22. http://dx.doi.org/10.1590/0104-530x1266-16.

Full text

Abstract:

Resumo: Este trabalho tem como objetivo principal discutir o uso de métodos sistemáticos para geração de designs de experimentos com boas propriedades estatísticas e custos baixos. O foco da pesquisa é o sequenciamento dos experimentos, de maneira que são analisados os resultados de três diferentes abordagens para construção de designs fatoriais (ortogonais e não ortogonais) com dois níveis, em que o sequenciamento é feito de forma aleatória ou sistemática. Em particular, simulou-se a condução do design gerado por cada abordagem no contexto de um processo real de fabricação de embalagens de vidro, sem a presença de efeitos de tendências lineares e com a presença desses efeitos. Os resultados das análises indicam que em relação à ordem aleatória, sequências sistemáticas podem resultar em menor número de mudanças de níveis dos fatores e maior robustez a efeitos de tendências lineares, compatibilizando, portanto, o custo e a qualidade do design.

APA, Harvard, Vancouver, ISO, and other styles

46

Majerus, Steve J. A., Daniel T. Goff, and Walter Merrill. "A 200 °C Motor Control ASIC." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000159–64. http://dx.doi.org/10.4071/hitec-wa15.

Full text

Abstract:

A custom application-specific integrated circuit (ASIC) has been designed for positional control of brushless DC or servo motors in high-temperature (>200 °C) environments. Applications would include valve and position control for aerospace and industrial systems. Patented high-temperature circuit design techniques facilitate hightemperature operation from a conventional, low-cost, 0.5-micron bulk CMOS foundry process. The ASIC is highly integrated to enable software- and processor-free local control of motor position, and uses external power MOSFETs for motor commutation. Motor position can be controlled in open- or closed-loop modes with an integrated rotational variable displacement transformer (RVDT) direct digital synthesis (DDS) waveform generator, rail-to-rail op-amp driver and demodulation circuit. The ASIC can accept both analog (0–10 V) or digital (SPI bus) position setpoint commands from an external controller. Motor position is indicated by both analog and digital output signals. The full-scale displacement of the controlled motor is programmable from 5 to 8 bits of resolution, permitting 32–256 positions of control. Safety features such as a 500-ms power-on delay, overtemperature and motor overcurrent detection, and control signal undervoltage lockout were included to minimize the need for external control. ASIC bench-test results confirmed circuit functionality at ambient temperatures up to 225 °C using room-temperature power MOSFETs and motor load. ASIC performance at the 8-bit level was demonstrated, although the clock oscillator frequency shifted by about 15% over the full temperature range. Control of the motor at 200 °C was also demonstrated, although moderate loss of motor holding torque was observed due to internal heat generation in the motor. The ASIC was combined with commercially-available off-the-shelf high-temperature components on a printed wiring board (PWB) to form a compact (4 × 3.5 inch) motor control demonstration system capable of prolonged operation at temperatures beyond 200 °C. Environmental and long-term testing of the PWB is planned to demonstrate system reliability.

APA, Harvard, Vancouver, ISO, and other styles

47

Sperhacke, Simone Lorentz, Maurício Moreira e. Silva Bernardes, and Julio Carlos de Souza Van der Linden. "Restrições de Tempo e Custo na Resolução de Problemas: Experimento com Alunos de Graduação de Design." Design e Tecnologia 5, no. 10 (December 30, 2015): 10. http://dx.doi.org/10.23972/det2015iss10pp10-17.

Full text

Abstract:

Este artigo busca refletir sobre as restrições de tempo e custos e suas possíveis relações no processo da resolução de problemas, no que tange o desenvolvimento de projetos de design. A fim de atingir os objetivos propostos, partiu-se de uma releitura de protocolo proposto por Savage et al. [19], que consiste em um estudo experimental investigativo com um delineamento com alunos de engenharia. No âmbito deste artigo, buscou-se replicar o experimento com alunos de cursos de graduação de design. Trata-se de um protocolo que é aplicado individualmente, na qual cada estudante completa três tarefas em uma entre quatro condições: controle, restrição de tempo, restrição de custo e restrição de tempo e custo. Verificou-se dentre os vários resultados da pesquisa que na situação onde não existe restrição de tempo, observou-se que o número de diferentes tipos de solução geradas foi muito similar àquelas situações com tempo restrito.

APA, Harvard, Vancouver, ISO, and other styles

48

Sun, Fei, Srivaths Ravi, Anand Raghunathan, and Niraj K. Jha. "A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 11 (November 2007): 2035–45. http://dx.doi.org/10.1109/tcad.2007.906457.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

Frankiewicz, M., and A. Kos. "Overheat protection circuit for high frequency processors." Bulletin of the Polish Academy of Sciences: Technical Sciences 60, no. 1 (March 1, 2012): 55–59. http://dx.doi.org/10.2478/v10175-012-0009-6.

Full text

Abstract:

Overheat protection circuit for high frequency processors The paper describes design and structure of the overheat protection circuit based on the PTAT sensors. The digital core of the system is driven by a 3-bit information generated by the structure. As a result, behaviour of the core differs for each temperature. The circuit was designed in LF CMOS 0.15 μm technology using full-custom technique. The presented paper focuses especially on the structure of the overheat protection circuit and simulations results of the functional blocks of the system. Layout and some parameters of the circuit are also considered.

APA, Harvard, Vancouver, ISO, and other styles

50

Vedovatto, Zamur Borges, Cinthia Mikaela de Souza, and Magali Rezende Gouvêa Meireles. "Gerenciamento dos Processos de Controle de Contribuições de Paróquias Utilizando Sistema Web." Abakós 8, no. 1 (May 30, 2020): 43–65. http://dx.doi.org/10.5752/p.2316-9451.2020v8n1p43-65.

Full text

Abstract:

As paróquias são locais para reuniões de fiéis religiosos e, nos processos organizacionais, existem práticas de controle financeiro de custos e recebimentos. Em certas paróquias, o registro dos recebimentos é feito em folhas de papel durante as missas para, posteriormente,ser transferido para planilhas informatizadas, gerando o risco de perda de informação no processo. Dentre os principais recebimentos, encontram-se as contribuições, seja em forma de pagamento de dízimo ou de doação. O presente trabalho apresenta o desenvolvimento de um sistema Web para comunidades paroquiais aperfeiçoarem o controle do recebimento de contribuições. O objetivo do trabalho foi implantar o processo de transformação digital em paróquias que possuem os seus processos manuais. Foi desenvolvida uma solução que contemplasse as reais necessidades do público-alvo, que buscam por um processo mais seguro e eficaz para o registro das contribuições. O MEAN Stack, utilizado no processo, abrange todas as tecnologias utilizadas para o desenvolvimento. O design seguiu os conceitos de User Experience (UX), visando uma melhor experiência de uso da aplicação em termos de fluidez e facilidade em realizar as operações. Constatou-se, no processo de validação, que o sistema aperfeiçoa a organização dos processos envolvidos, trazendo melhorias ao controle das atividades financeiras.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Custom Processor Design'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles