Dissertations / Theses on the topic 'Coupled Inductance'

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 95-96).
Conventional filter circuits suffer from a number of limitations, including performance degradation due to capacitor parasitic inductance and the size and cost of magnetic elements. Coupled-magnetic filters have been developed that provide increased filter order with a single magnetic component, but also suffer from parasitic inductance in the filter shunt path due to imperfectly-controlled coupling of the magnetics. This document proposes a new approach to coupled-magnetic filters that overcomes these limitations. Filter sensitivity to variations in coupling is overcome by adaptively tuning the coupling of the magnetic circuit with feedback based on the sensed filter output ripple. This active coupling control enables much greater robustness to manufacturing and environmental variations than is possible in the conventional coupled-magnetic approach, while preserving its advantages. Moreover, the proposed technique also adaptively cancels the deleterious effects of capacitor parasitic inductance, thereby providing much higher filter performance than is achievable in conventional designs. The new technique is experimentally demonstrated in a dc/dc power converter application and is shown to provide high performance.
by Daria S. Lymar.
M.Eng.

La prochaine génération d’instruments pour l'observation de la polarisation du fond diffus cosmologique est particulièrement exigeante en termes de nombre de détecteurs, de qualité de la mesure et d'efficacité de remplissage du plan focal. De plus, pour détecter les modes-B de polarisation provenant de l’inflation, il faut observer le ciel avec plusieurs bandes de fréquence afin de soustraire les avant-plans. Dans ce contexte, les détecteurs à inductance cinétique (KIDs) représentent une technologie très prometteuse en raison de leur grand facteur de multiplexage et de leur facilité de réalisation, tandis que le couplage avec une antenne peut fournir des solutions multi-bandes et double-polarisation dans un design compacte. Les KIDs à éléments localisés (LEKID) couplé à une antenne développé dans cette thèse sont sensibles à la polarisation avec deux sous-bandes à 140 GHz et 160 GHz chacune avec une bande passante de 10%. L'architecture proposée utilise une antenne à fente excitée par une ligne microruban et deux filtres passe-bande vers deux résonateurs. Ces derniers sont couplés capacitivement avec l'antenne et comprennent une ligne microruban en Aluminium comme absorbeur. Cette architecture est particulièrement simple à fabriquer, sans via et ne nécessite que de deux niveaux de métallisation. La transition ne nécessite aucun dépôt de diélectrique au-dessus du résonateur, évitant ainsi les limitations de toute source de bruit due au substrat non-monocristallin (TLS). En outre, la même technique de couplage peut être appliquée à de nombreux types d'antennes excitées par une ligne microruban, ce qui permet de s'adapter aux filtres passe-bande
Next generation telescopes for observing the Cosmic Microwave Background are demanding in terms of number of detectors and focal plane area filling efficiency. Moreover, foreground reduction in B-Mode polarimetry requires sky observation with multiple frequency bands. In this context KIDs are promising technology because of their large multiplexing rate, while antenna coupling can provide multi-band and dual-polarization solutions in compact design. The proposed polarization sensitive antenna-coupled LEKID is operating at 140 GHz and 160 GHz with a bandwidth of almost 10% for each sub-band. The design involves a microstrip excited slot antenna and two open-stub band-pass filters to direct the signal toward two resonators. These are lumped elements capacitively coupled to the antenna and include an Aluminium strip as absorber. The architecture proposed is particularly simple to fabricate, via-less and only involves two metallization levels. The transition doesn't require any dielectric deposition above the resonator, thus preventing limitations from any source of noise due to non-monocrystalline substrate (TLS). Furthermore, the same coupling technique can be applied to many types of microstrip excited antennas, which allow to accommodate band-pass filters

La conception d’un redresseur triphasé robuste et performant est un enjeu clé dans les alimentations des futurs appareils d’imagerie médicale de type scanner à rayons X pour augmenter leur puissance et leur rapidité.Cette application impose une grande variabilité de points de fonctionnements au redresseur :(i) En sortie, la charge est de type impulsionnelle avec des variations de puissance de plus de 100 kW.(ii) En entrée, la tension nominale d’entrée et l’impédance du réseau d’entrée sont variables d’une installation à l’autre.La topologie du double Vienna avec inductances couplées et commandes entrelacées est choisie pour son efficacité, sa fiabilité et son faible volume.La loi de commande choisie est constituée de trois boucles de régulations : (i) régulation de la tension de sortie totale, (ii) correction du facteur de puissance des courants d’entrée, (iii) équilibrage des deux tensions de sortie.Une contrainte forte est le changement de dynamique des courants d’entrée qui passent par différents modes de conduction sur une même période du réseau.Deux modèles linéaires des courants sont développés :le modèle moyenné linéarisé pour les modes de conduction continue, et un modèle original développé dans cette thèse pour les modes de conduction discontinue.Les performances de la régulation sont vérifiées en simulation et expérimentalement.La robustesse de la régulation est évaluée par l’analyse des réponses fréquentielles et des marges de stabilité monovariables et multivariables des modèles linéaires développées dans cette thèse sur l’ensemble des points de fonctionnement et des valeurs possibles de l’impédance réseau.La robustesse de la régulation globale aux phénomènes définis par la courbe ITIC de surtension et de chute de tension sur le réseau est confirmée en simulation
The design of a robust and efficient three-phase rectifier is a key issue in the power supplies of future medical imaging system such as X-ray scanners to increase their power and speed.This application imposes a large variability of operating points on the rectifier:(i) At the output, the load is of the pulse type with power variations of more than 100 kW.(ii) At the input, the nominal input voltage and input grid impedance are variable from one installation to another. And the instant input voltage varies normally on a +/-10% range, and abnormally from 0 to 500% of the nominal value.The double Vienna topology with coupled inductors and interleaved controls is chosen for its efficiency, reliability and low volume.The chosen control law consists of three control loops: (i) regulation of the total output voltage, (ii) power factor correction of the input currents, (iii) balancing of the two output voltages.A strong constraint is the changing dynamics of the input currents which pass through different conduction modes over the same grid period.Two linear models of the currents are developed:the linearised averaged model for the continuous conduction modes, and an original model developed in this thesis for the discontinuous conduction modes.The performance of the regulation is verified in simulation and experimentally.The robustness of the control is assessed by analysing the frequency responses and the single-variable and multivariable stability margins of the linear models developed in this thesis.The robustness of the global regulation to the phenomena defined by the ITIC curve of grid overvoltage and voltage drop is confirmed in simulation

Cette thèse traite des convertisseurs multiniveaux destinés aux applications moteurs rapides, utilisés notamment dans le domaine de l'Oil \& Gas. L'objectif est l'étude d'une structure qui permette de réduire les pertes par commutation, en comparaison avec la topologie conventionnelle NPC (Neutral Point Clamped) 3 niveaux, actuellement utilisée. De plus, la structure de convertisseur doit permettre de fournir des grandeurs d'entrée au moteur ayant un faible taux de distorsion harmonique, de manière à ne pas créer des échauffements supplémentaires dans le moteur.Après avoir effectué une étude des différentes structures existantes, la structure NPP (Neutral Point Piloted) 3 niveaux est finalement retenue au vu de ses différentes qualités. En effet, grâce à la mise en série de composants semi-conducteurs, les pertes par commutation de ces derniers sont divisées par deux par rapport aux composants homologues de la topologie NPC. Après avoir comparé les topologies NPC et NPP en termes de forme d'onde et de répartition des pertes dans les composants, l'auteur s'intéresse à la validation expérimentale de cette structure. Les performances atteintes par le convertisseur NPP sont intéressantes puisqu'elles permettent de commuter à des fréquences deux fois plus élevées que la topologie NPC pour un courant donné ou de commuter un courant plus important pour une fréquence de commutation donnée.Les schémas de commutation des différents composants du bras NPP sont étudiés afin de comprendre le gain non négligeable obtenu sur cette structure.Malgré le fait que la structure NPP permette de commuter à des fréquences deux fois plus élevées que la structure NPC, on ne peut pas s'affranchir du filtre sinus en sortie de l'onduleur de manière à respecter les contraintes harmoniques au niveau du moteur. Ainsi, une topologie de filtre sinus à inductances couplées a été introduite
This PhD thesis deals with multilevel inverters dedicated to high speed motors applications, used in Oil \& Gas applications. The main objective is to study a topology which enables reducing switching losses, in comparison with the conventional 3-level NPC (Neutral Point Clamped) topology. Moreover, the inverter has to provide motor input signals with a low harmonic distortion level, not to create undesired additional heating in the motor. After a study of the existing topologies, the 3-level NPP (Neutral Point Piloted) topology is chosen regarding all its benefits. Indeed, thanks to series connection of semi-conductor components, switching losses can be divided by two compared to homologous components on the NPC topology. After having compared NPC and NPP topologies in terms of waveforms and losses distribution in components, the author interest is the experimental validation of this topology. The performances reached by the NPP inverter are interesting because it enables to switch two times faster than for a NPC topology for a given current or to switch a higher current for a given switching frequency. The switching schemes of the NPP leg are studied to understand the gain obtained on this topology. In spite of the fact that switching frequency can be doubled on the NPP topology, the sinus filter can not be avoided in order to respect harmonic specification on the motor. A sinus filter with coupled inductances is introduced so that to responds the different sizing criteria

L'amplitude vibratoire d'une structure mince peut être réduite grâce au couplage électromécanique qu'offrent les matériaux piézoélectriques. En termes d'amortissement passif, les shunts piézoélectriques permettent une conversion de l'énergie vibratoire en énergie électrique. La présence d'une inductance dans le circuit crée une résonance électrique due à l'échange de charges avec la capacité piézoélectrique. Ainsi, l'ajustement de la fréquence propre de ce shunt résonant à celle de la structure mécanique équivaut à la mise en œuvre d'un amortisseur à masse accordée. Cette stratégie est étendue au contrôle d'une structure multimodale par multiplication du nombre de patchs piézoélectriques. Ceux-ci sont interconnectés via un réseau électrique ayant un comportement modal approximant celui de la structure à contrôler. Ce réseau multi-résonant permet donc le contrôle simultané de plusieurs modes mécaniques. La topologie électrique adéquate est obtenue par discrétisation de la structure mécanique puis par analogie électromécanique directe. Le réseau analogue fait apparaître des inductances et des transformateurs dont le nombre et les valeurs sont choisis en fonction de la bande de fréquences à contrôler. Après s'être penché sur la conception de composants magnétique adaptés, la solution de contrôle passif est appliquée à l'amortissement de structures unidimensionnelles de type barres ou poutres. La stratégie est ensuite étendue au contrôle de plaques minces par mise en œuvre d'un réseau électrique bidimensionnel
Structural vibrations can be reduced by benefiting from the electromechanical coupling that is offered by piezoelectric materials. In terms of passive damping, piezoelectric shunts allow converting the vibration energy into electrical energy. Adding an inductor in the circuit creates an electrical resonance due to the charge exchanges with the piezoelectric capacitance. By tuning the resonance of the shunt to the natural frequency of the mechanical structure, the equivalent of a tuned mass damper is implemented. This strategy is extended to the control of a multimodal structure by increasing the number of piezoelectric patches. These are interconnected through an electrical network offering modal properties that approximate the behavior of the structure to control. This multi-resonant network allows the simultaneous control of multiple mechanical modes. An adequate electrical topology is obtained by discretizing the mechanical structure and applying the direct electromechanical analogy. The analogous network shows inductors and transformers, whose numbers and values are chosen according to the frequency band of interest. After focusing on the design of suitable magnetic components, the passive control strategy is applied to the damping of one-dimensional structures as bars or beams. It is then extended to the control of thin plates by implementing a two-dimensional analogous network

L'apparition de convertisseurs multicellulaires parallèles entrelacés et magnétiquement couplés a conduit ces dernières années à améliorer les performances des convertisseurs (en termes de densité de puissance, d'efficacité, de dynamique,...). Le pendant de ces améliorations successives résulte en une nécessité d'équilibrage précis des courants de phase, ce qui entraîne une complexification de la commande des ces convertisseurs. Une première étape de détermination de la fonction de transfert d'une boucle d'équilibrage des courants nous permet de déterminer la nature des correcteurs d'équilibrage de ces courants. Cette étude nous permet d'appréhender des systèmes plus complexes avec différentes topologies de couplage magnétique entre les bras du convertisseur parallèle. Suite à une étude bibliographique mettant en avant le manque de précision des techniques actuelles de mesure des courants de bras, nous proposons une technique d'émulation analogique précise de ces courants ne nécessitant qu'un seul capteur. Deux prototypes ont été réalisés et permettent de valider cette technique. Enfin, face à l'intérêt grandissant que portent les industriels pour des architectures modulaires, deux innovations permettant de s'affranchir d'un circuit spécifique de supervision sont proposées. Dans un premier temps, une technique modulaire d'équilibrage des courants est proposée et validée expérimentalement : elle permet, entre autres, une mesure différentielle précise des courants de bras. Ensuite, une méthode de génération modulaire de porteuses triangulaires auto-alignées est proposée et validée grâce à la réalisation d'une maquette de test. L'association de ces deux techniques nous permet de proposer une architecture entièrement modulaire ne nécessitant plus de circuit de commande superviseur
Development of interleaved power converters with coupled inductors has enhanced converters performances (better power density, eciency, transient response. . .). Such improvements lead to the necessity of a precise current-sharing in the converter legs, and consequently to much more complex control strategy for those converters. First step is to determine current sharing loop transfer function in order to choose the kind of sharing corrector and calculate its parameters. State-space representation is used to consider any coupling topology. Because ux induced in coupled inductors must be controlled with accuracy, a bibliography study emphasizes the lack of precision in present current-sensing techniques. Then, a precise analogical emulation of currents in every leg, based on only one current sensor, is proposed. Two prototypes have been developed and validate this approach. Finally, because of growing interest of industrial in modular architectures, two innovations which avoid the use of central specic circuit are presented. First, a masterless and modular current sharing technique is proposed and tested : it allows a very precise dierential current measurement and regulation. Then a modular generation of self-aligned triangular carrier for interleaved converters is proposed and conrmed by test. The association of both techniques leads to a full masterless and modular approach for the control circuit of parallel converter with coupled inductors

La demande pour des appareils portables multifonctionnels encourage les manufacturiers à intégrer des microsystèmes électromécaniques (MEMS) ou optoélectromécaniques (MOEMS) à leurs produits pour réaliser de nouvelles fonctions ; les pico projecteurs constituent un excellent exemple. Or, dans le but d'utiliser ce type de composants, des tensions de polarisation variant entre 100 V et 300 V sont parfois nécessaires. La génération de ces tensions à partir de la pile de l'appareil exige des convertisseurs continu-continu (DC-DC) miniatures procurant un gain de tension de l'ordre de 100. C'est dans ce contexte général que ce projet réalisé pour Teledyne DALSA, un manufacturier de MEMS et concepteur de circuits intégrés haut voltage, a été réalisé. En intégrant ce circuit à ses circuits de contrôle de MEMS, Teledyne DALSA sera ainsi en mesure de proposer des systèmes plus complets à ses clients. Ce mémoire présente la conception d'un convertisseur DC-DC dans la technologie CO8G CMOS/DMOS haut voltage de Teledyne DALSA. Pour que la solution développée soit assez flexible, le circuit permet un ajustement de la tension de sortie entre 100 V et 300 V pour une puissance de sortie inférieure ou égale à 210 mW à partir d'une tension de batterie entre 2,7 V et 5,5 V. Afin de permettre une longue autonomie des appareils portables, ce projet vise une efficacité de transfert d'énergie de 70 % à la puissance de sortie typique de 75 mW à 220 V. De plus, la solution développée doit être la plus petite possible. À partir de l'état de l'art des circuits de gestion de l'alimentation, ce mémoire présente une conception haut niveau du circuit basée sur des raisonnements et calculs mathématiques simples. Bâtissant sur ces concepts, ce travail détaille la conception des composants de puissance, du circuit de puissance et du contrôleur nécessaire à la réalisation de ce projet. Bien que certaines difficultés, notamment le niveau moyen de l'oscillation de la tension de sortie de 1,6 V, ne permettent pas d'utiliser dès maintenant le circuit développé dans une application commerciale, la solution proposée démontre une amélioration entre 15 % et 43 % de l'efficacité de conversion par rapport au circuit flyback actuel de Teledyne DALSA. De plus, la solution proposée intègre un transistor de puissance 78 % plus petit que les transistors standards disponibles dans la technologie CO8G. Étant donnée l'innovation du circuit présenté au niveau des composants de puissance, du circuit de puissance et du contrôleur, ces résultats de l'implémentation initiale laissent envisager un bon potentiel pour cette architecture après une révision.

L'utilisation de systèmes de stockage de l'énergie électrique tels que les batteries nécessite l'assemblage de plusieurs cellules. Comme chacune de ces dernières peut avoir des caractéristiques légèrement différentes ainsi que des conditions d'environnement thermique ou de vieillissement distinctes, l'utilisation d'un système d'équilibrage permettant une bonne gestion de la répartition de l'énergie au sein des éléments qui composent le pack est nécessaire. Les travaux de recherche présentés se rapportent à l'étude et à la conception d'un tel circuit d'équilibrage à base de convertisseurs d'énergie intégrables ainsi qu'aux sollicitations électriques engendrées dans les cellules lors de son utilisation.

Cette thèse apporte une contribution à l'évaluation des potentialités de filières SiGe de type BiCMOS pour les futures applications de télécommunications en bande millimétrique. Dans ce cadre, les topologies équilibrées ou différentielles sont très attrayantes, en raison de leur bonne immunité aux perturbations électriques et électromagnétiques. La montée en fréquence des applications hyperfréquences sur silicium s'accompagne de nouvelles difficultés. Les pertes introduites par les éléments passifs augmentent et les performances des structures différentielles classiques chutent très rapidement. Il est alors nécessaire d'exploiter d'autres techniques et de rechercher des topologies innovantes permettant la réalisation de fonctions équilibrées performantes. Une première partie est consacrée à l'évaluation des potentialités des différentes technologies d'interconnexions (microruban, guides coplanaires et lignes à rubans coplanaires) exploitables pour la conception de circuits monolithiques sur silicium. Dans un second temps, une bibliothèque d'inductances optimisées pour une utilisation en bande K et Ka est constituée. Les mécanismes physiques à l'origine des pertes dans ce type d'élément sont détaillés afin de dégager les solutions permettant d'améliorer leurs performances. Une deuxième partie traite de l'optimisation des performances des circuits différentiels pour les futures applications dans la gamme 20-40 GHz. Dans un premier temps, nous détaillons les caractéristiques hautes fréquences du transistor qui pénalisent le fonctionnement d'une structure différentielle classique. Des topologies de structures différentielles originales permettant de résoudre ce problème sont ensuite proposées. Ces structures sont appliquées à la conception d'un diviseur de puissance actif 180° original, optimisé pour une fréquence centrale de fonctionnement de 20 GHz. Enfin, un convertisseur de fréquences 20 GHz vers 1 GHz a été conçu et réalisé. Celui-ci intègre, outre le mélangeur, le s trois coupleurs actifs 180° nécessaires à la génération / recombinaison des signaux différentiels utiles au mélangeur. La caractérisation de ce convertisseur de fréquences démontre la pertinence des configurations choisies pour les interconnexions ainsi que le grand intérêt des structures différentielles originales mises en Suvre.

碩士
國立交通大學
電信工程系
91
A method for computing the capacitance matrix and inductance matrix for a multiple coupled transmission line system has been presented. This system includes an arbitrary number of perfect conductors, one infinite ground plane, one dielectrics interface which is parallel to the ground plane. The closed-form expressions for the frequency-dependent parameters of this proposed semi-empirical model are derived in terms of the quasi-static capacitance matrix. The model should be useful in the computer-aided design of coupled microstrip structures at higher frequency where the dispersion effects become important.

碩士
明志科技大學
材料工程系碩士班
106
n-type and p-type hydrogenated nanocrystalline silicon (nc-Si: H) thin films were deposited by the LIA-ICP-CVD (inductively coupled plasma CVD) system. Using Langmuir Probe discussed plasma conditions effect on the thin films deposition. The films properties Si-H bond, microstructure, crystallinity and conductivity were characterized using X-Ray Diffractometer and Fourier Transform Infrared Spectroscopy, Raman spectrometry, Hall Effect Measurement System, Which enhance the quality of thin films. From the microstructure of the films, it has been found that a small cracks in the nc-Si:H films prepared by ICP-CVD, thus the carrier mobility in the film is low, but the cracks are decreases with increasing of the substrate temperature and decreasing of the total flow rate. As a result, the conductivity get increases. By SIMS analysis, it has been known that ICP-CVD is very effective for the doping of boron and phosphorus, for the amount of doping in the nc-Si:H films have reached at the solution limit. The Heterojunction with Intrinsic Thin-layer (HIT) solar cells are successfully prepared by ICP-CVD although the efficiency is 1.5%, but I-V curve can find the p-n rectifier effect, indicating the effectiveness of doping. The low efficiency is due to excessive doping. Consequently, The VOC and ISC are very small.

After nearly a decade of development, human-implantable sensors for detection of muscle activity have recently been demonstrated in the literature. The implantable sensors are powered and communicate wirelessly through the skin using coupled inductor coils. The focus of the present work has been the development of a new approach to modeling the inductively coupled link by using the finite element method (FEM) to simulate a three-dimensional representation of the coils and surrounding magnetic field. The validity of the simulation is tested by comparison to analytically-developed formulas for self-inductance, ac resistance and mutual inductance of the coils. Determination of these parameters is necessary for calculation of the coupling coefficient between the coils, and to fully define the lumped circuit model of the link. This 3D FEM approach is novel and attractive because it is able to encompass physical geometric parameters and material properties that have been traditionally been a challenge to determine. In particular the contribution of a ferrite-core, and the case of non-symmetrical relative coil positioning can be evaluated.
Graduate

abstract: Kinetic inductance springs from the inertia of charged mobile carriers in alternating electric fields and it is fundamentally different from the magnetic inductance which is only a geometry dependent property. The magnetic inductance is proportional to the volume occupied by the electric and magnetic fields and is often limited by the number of turns of the coil. Kinetic inductance on the other hand is inversely proportional to the density of electrons or holes that exert inertia, the unit mass of the charge carriers and the momentum relaxation time of these charge carriers, all of which can be varied merely by modifying the material properties. Highly sensitive and broadband signal amplifiers often broaden the field of study in astrophysics. Quantum-noise limited travelling wave kinetic inductance parametric amplifiers offer a noise figure of around 0.5 K ± 0.3 K as compared to 20 K in HEMT signal amplifiers and can be designed to operate to cover the entire W-band (75 GHz – 115 GHz).The research cumulating to this thesis involves applying and exploiting kinetic inductance properties in designing a W-band orthogonal mode transducer, quadratic gain phase shifter with a gain of ~49 dB over a meter of microstrip transmission line. The phase shifter will help in measuring the maximum amount of phase shift ∆ϕ_max (I) that can be obtained from half a meter transmission line which helps in predicting the gain of a travelling wave parametric amplifier. In another project, a microstrip to slot line transition is designed and optimized to operate at 150 GHz and 220 GHz frequencies, that is used as a part of horn antenna coupled microwave kinetic inductance detector proposed to operate from 138 GHz to 250 GHz. In the final project, kinetic inductance in a 2D electron gas (2DEG) is explored by design, simulation, fabrication and experimentation. A transmission line model of a 2DEG proposed by Burke (1999), is simulated and verified experimentally by fabricating a capacitvely coupled 2DEG mesa structure. Low temperature experiments were done at 77 K and 10 K with photo-doping the 2DEG. A circuit model of a 2DEG coupled co-planar waveguide model is also proposed and simulated.
Dissertation/Thesis
Masters Thesis Electrical Engineering 2016

Power distribution network (PDN) design was a non-existent entity during the early days of microprocessors due to the low frequency of operation. Once the switching frequencies of the microprocessors started moving towards and beyond MHz regions, the parasitic inductance of the PCB tracks and planes started playing an important role in determining the maximum voltage on a PDN. Voltage regulator module (VRM) sup-plies only the DC power for microprocessors. When the MOSFETs inside a processor switches, it consumes currents during transition time. If this current is not provided, the voltage on the supply rails can go below the specifications of the processor. For lower MHz processors few ceramic-capacitors known as ‘decoupling capacitors’ were connected between power and ground to provide this transient current demand. When the processor frequency increased beyond MHz, the number of capacitors also increased from few numbers to hundreds of them. Nowadays, the PDN is said to be comprising all components from VRM till the die location. It includes VRM, bulk capacitors, PCB power planes, capacitor mounting pads and vias, mount for the electronic package, package capacitors, die mount and internal die capacitance. So, the PDN has evolved into a very complex system over the years. A PDN should provide three distinct roles; 1) provide transient current required by the processor 2) act as a stable reference voltage for processor 3) filter out the noise currents injected by the processor. The first two are required for the correct operation of the processor. Third one is a requirement from analog or other sensitive circuits connected to the same PDN. If the noise exits the printed circuit board (PCB), it can result in conducted and radiated EMI, which can in turn result in failure of a product in EMC testing. Every PDN design starts with the calculation of a target impedance which is given as the ratio of maximum allowed ripple voltage to the maximum transient current required by the processor. The transient current is usually taken as half the average input current. The definition of target impedance assumes that the PDN is flat over the entire frequency of operation, which is true only for a resistive network. This is seldom true for a practical PDN, since it contains inductances and capacitances. Because of this, a practical PDN has an uneven impedance versus frequency envelope. Whenever two capacitors with different self resonant frequencies are connected in parallel, their equivalent impedance produces a pole between the self resonant frequencies known as antiresonance peaks. Because of this, a PDN will have phase angles associated with them. Also, these antiresonance peaks are energy reservoirs which will be excited during the normal operation of a processor by the varying currents. The transient current of a microprocessor is modeled as a gamma function, but for practical cases it can be approximated as triangular waveforms during the transition time which is normally 10% of the time period. Depending upon the micro-operations running inside the processor, the peak value of this waveform varies. This is filtered by the on-chip capacitors, package inductance and package capacitors. Due to power gating, clock gating, IO operations, matrix multiplications and magnetic memory readings the waveforms at the board will be like pulse type, and their widths are determined by these operations. In literatures, these two types of waveforms are used for PDN analysis, depending upon at which point the study is conducted. Chapter 1 introduces the need for PDN design and the main roles of a PDN. The issue of antiresonance is introduced from a PDN perspective. Different types of capacitors used on a PDN are discussed with their strengths and limitations. The general nature of the switching noise injected by a microprocessor is also discussed. This chapter discusses the thesis contributions, and the existing work related to the field. Chapter 2 introduces a new method to calculate the target impedance (Zt ) by including the phase angles of a PDN which is based on a maximum voltage calculation. This new Zt equals to conventional Zt for symmetrical triangular switching current waveforms. The value of new Zt is less than the conventional Zt for trapezoidal excitation patterns. By adding the resonance effects into this, a maximum voltage value is obtained in this chapter. The new method includes the maximum voltage produced on a PDN when multiple antiresonance peaks are present. Example simulations are provided for triangular and pulse type excitations. A measured input current wave-form for PIC16F677 microcontroller driving eight IO ports is provided to prove the assumption of pulse type waveforms. For triangular excitation waveform, the maximum voltage predicted based on the expression was ¡0.6153 V, and the simulated maximum voltage was found to be at ¡0.5412 V which is less than the predicted value. But the predicted value based on Zt method was 1.9845 V. This shows that the conventional as well as the new target impedance method leads to over estimating the maximum voltage in certain cases. This is because most of the harmonics are falling on the minimum impedance values on a PDN. If the PDN envelope is changed by temperature and component tolerances, the maximum voltage can vary. So the best option is to design with the target impedance method. When pulse current excitation was studied for a particular PDN, the maximum voltage produced was -139.39 mV. The target impedance method produced a value of -100.24 mV. The maximum voltage predicted by the equation was -237 mV. So this shows that some times the conventional target impedance method leads to under estimating the PDN voltage. From the studies, it is shown that the time domain analysis is as important as frequency domain analysis. Another important observation is that the antiresonance peaks on a PDN should be damped both in number and peak value. Chapter 3 studies the antiresonance peak suppression methods for general cases. As discussed earlier, the antiresonance peaks are produced when two capacitors with different self resonant frequencies are connected in parallel. This chapter studies the effect of magnetic coupling between the mounting loops of two capacitors in parallel. The mounting loop area contribute to the parasitic inductance of a capacitor, and it is the major contributing factor to it. Other contributing factors are equivalent series inductance (ESL) and plane spreading inductance. The ESL depends on the size and on how the internal plates of the capacitors are formed. The spreading inductance is the inductance contributed by the parts of the planes connecting the capacitor connector vias to the die connections or to other capacitor vias. If the power and ground planes are closer, the spreading inductance is lower. On one/two layer boards dedicated power/ground planes are absent. So the spreading inductance is replaced by PCB track inductances. The inductance contributed by the mounted area of the capacitor is known as mounting inductance. On one/two layer boards dedicated power/ground planes are absent. So the spreading inductance is replaced by PCB track inductances. The dependencies of various circuit parameters on antiresonance peak are studied using circuit theory. A general condition for damping the antiresonance is formulated. The antiresonance peak reduces with Q factor. The conventional critical condition for antiresonance peak damping needs modification when magnetic coupling is present between the mounting loops of two parallel unequal value capacitors. By varying the connection geometry it is possible to obtain negative and positive coupling coefficients. The connection geometries to obtain these two are shown. An example is shown for positive and negative coupling coefficient cases with simulation and experimental results. For the example discussed, RC Æ 32 - for k Æ Å0.6 and RC Æ 64 - for k Æ ¡0.6, where RC is the critical damping value and k is the magnetic coupling coefficient between the two mounting loops. The reason for this is that, the antiresonance peak impedance value is higher for negative coupling coefficient case than that for positive coupling coefficient case. Above the self resonant frequencies of both the capacitors, the equivalent impedance of the parallel capacitors become inductive. This case is studied with two equal value capacitors in parallel. It is shown that the equivalent inductance is lower for negative coupling coefficient case as compared to positive coupling coefficient case. An example is provided with simulation and experimental results. In the experimental results, parasitic inductance is observed to be 2.6 times lower for negative coupling coefficient case than that for positive coupling coefficient case. When equal value capacitors are connected in parallel, it is advantageous to use a negative coupling geometry due to this. Chapter 4 introduces a new method to damp the antiresonance peak using a magnet-ically coupled resistive loop. Reducing the Q factor is an option to suppress the peak. In this new method, the Q factor reduction is achieved by introducing losses by mag-netically coupling a resistive loop. The proposed circuit is analyzed with circuit-theory, and governing equations are obtained. The optimum value of resistance for achieving maximum damping is obtained through analysis. Simulation and experimental results are shown to validate the theory. From the experimental results approximately 247 times reduction in antiresonance peak is observed with the proposed method. Effectiveness of the new method is limited by the magnetic coupling coefficient between the two mounting loops of capacitors. The method can be further improved if the coupling coefficient can be increased at the antiresonance frequency. Chapter 5 focuses on the third objective of a PDN, that is to reduce the noise injected by the microprocessor. A new method is proposed to reduce the conducted noise from a microprocessor with switched super capacitors. The conventional switched capacitor filters are based on the concept that the flying capacitor switching at high frequency looks like a resistor at low frequency. So for using at audio frequencies the flying capacitors were switching at MHz frequencies. In this chapter the opposite of this scenario is studied; the flying capacitors are the energy storage elements of a switched capacitor converter and they switch at lower frequencies as compared to the noise frequencies. Two basic circuits (1:1 voltage conversion ratio) providing noise isolation were discussed. They have distinct steady state input current waveforms and are explained with PSPICE simulations. The inrush current through switches are capable of destroying them in a practical implementation. A practical solution was proposed using PMOS-PNP pair. The self introduced switching noise of the converter is lower when switching frequency is low and turn ON-OFF time is higher. If power metal oxide semiconductor field effect transistor (MOSFET)s are used, the turn ON and turn OFF are slow. The switching frequency can be lowered based on the voltage drop power loss. The governing equations were formulated and simulated. It is found that the switching frequency can be lowered by increasing the capacitance value without affecting the voltage drop and power loss. From the equations, it is found that the design parameters have a cyclic dependency. Noise can short through the parasitic capacitance of the switches. Two circuits were proposed to improve the noise isolation: 1) T switch 2) ¦ switch. Of these, the ¦ switch has the higher measured transfer impedance. Experimental results showed a noise reduction of (40-20) dB for the conducted frequency range of 150 kHz - 30 MHz with the proposed 1:1 switched capacitor converter. One possible improvement of this method is to combine the noise isolation with an existing switched capacitor converter (SCC) topology. The discussed example had a switching frequency of 700 Hz, and it is shown that this can isolate the switching noise in kHz and MHz regions. In a PDN there are antiresonance peaks in kHz regions. If the proposed circuit is kept close to a microprocessor, it can reduce the excitation currents of these low frequency antiresonance peaks. Chapter 6 concludes the thesis by stating the major contributions and applications of the concepts introduced in the thesis. This chapter also discusses the future scope of these concepts.

Power distribution network (PDN) design was a non-existent entity during the early days of microprocessors due to the low frequency of operation. Once the switching frequencies of the microprocessors started moving towards and beyond MHz regions, the parasitic inductance of the PCB tracks and planes started playing an important role in determining the maximum voltage on a PDN. Voltage regulator module (VRM) sup-plies only the DC power for microprocessors. When the MOSFETs inside a processor switches, it consumes currents during transition time. If this current is not provided, the voltage on the supply rails can go below the specifications of the processor. For lower MHz processors few ceramic-capacitors known as ‘decoupling capacitors’ were connected between power and ground to provide this transient current demand. When the processor frequency increased beyond MHz, the number of capacitors also increased from few numbers to hundreds of them. Nowadays, the PDN is said to be comprising all components from VRM till the die location. It includes VRM, bulk capacitors, PCB power planes, capacitor mounting pads and vias, mount for the electronic package, package capacitors, die mount and internal die capacitance. So, the PDN has evolved into a very complex system over the years. A PDN should provide three distinct roles; 1) provide transient current required by the processor 2) act as a stable reference voltage for processor 3) filter out the noise currents injected by the processor. The first two are required for the correct operation of the processor. Third one is a requirement from analog or other sensitive circuits connected to the same PDN. If the noise exits the printed circuit board (PCB), it can result in conducted and radiated EMI, which can in turn result in failure of a product in EMC testing. Every PDN design starts with the calculation of a target impedance which is given as the ratio of maximum allowed ripple voltage to the maximum transient current required by the processor. The transient current is usually taken as half the average input current. The definition of target impedance assumes that the PDN is flat over the entire frequency of operation, which is true only for a resistive network. This is seldom true for a practical PDN, since it contains inductances and capacitances. Because of this, a practical PDN has an uneven impedance versus frequency envelope. Whenever two capacitors with different self resonant frequencies are connected in parallel, their equivalent impedance produces a pole between the self resonant frequencies known as antiresonance peaks. Because of this, a PDN will have phase angles associated with them. Also, these antiresonance peaks are energy reservoirs which will be excited during the normal operation of a processor by the varying currents. The transient current of a microprocessor is modeled as a gamma function, but for practical cases it can be approximated as triangular waveforms during the transition time which is normally 10% of the time period. Depending upon the micro-operations running inside the processor, the peak value of this waveform varies. This is filtered by the on-chip capacitors, package inductance and package capacitors. Due to power gating, clock gating, IO operations, matrix multiplications and magnetic memory readings the waveforms at the board will be like pulse type, and their widths are determined by these operations. In literatures, these two types of waveforms are used for PDN analysis, depending upon at which point the study is conducted. Chapter 1 introduces the need for PDN design and the main roles of a PDN. The issue of antiresonance is introduced from a PDN perspective. Different types of capacitors used on a PDN are discussed with their strengths and limitations. The general nature of the switching noise injected by a microprocessor is also discussed. This chapter discusses the thesis contributions, and the existing work related to the field. Chapter 2 introduces a new method to calculate the target impedance (Zt ) by including the phase angles of a PDN which is based on a maximum voltage calculation. This new Zt equals to conventional Zt for symmetrical triangular switching current waveforms. The value of new Zt is less than the conventional Zt for trapezoidal excitation patterns. By adding the resonance effects into this, a maximum voltage value is obtained in this chapter. The new method includes the maximum voltage produced on a PDN when multiple antiresonance peaks are present. Example simulations are provided for triangular and pulse type excitations. A measured input current wave-form for PIC16F677 microcontroller driving eight IO ports is provided to prove the assumption of pulse type waveforms. For triangular excitation waveform, the maximum voltage predicted based on the expression was ¡0.6153 V, and the simulated maximum voltage was found to be at ¡0.5412 V which is less than the predicted value. But the predicted value based on Zt method was 1.9845 V. This shows that the conventional as well as the new target impedance method leads to over estimating the maximum voltage in certain cases. This is because most of the harmonics are falling on the minimum impedance values on a PDN. If the PDN envelope is changed by temperature and component tolerances, the maximum voltage can vary. So the best option is to design with the target impedance method. When pulse current excitation was studied for a particular PDN, the maximum voltage produced was -139.39 mV. The target impedance method produced a value of -100.24 mV. The maximum voltage predicted by the equation was -237 mV. So this shows that some times the conventional target impedance method leads to under estimating the PDN voltage. From the studies, it is shown that the time domain analysis is as important as frequency domain analysis. Another important observation is that the antiresonance peaks on a PDN should be damped both in number and peak value. Chapter 3 studies the antiresonance peak suppression methods for general cases. As discussed earlier, the antiresonance peaks are produced when two capacitors with different self resonant frequencies are connected in parallel. This chapter studies the effect of magnetic coupling between the mounting loops of two capacitors in parallel. The mounting loop area contribute to the parasitic inductance of a capacitor, and it is the major contributing factor to it. Other contributing factors are equivalent series inductance (ESL) and plane spreading inductance. The ESL depends on the size and on how the internal plates of the capacitors are formed. The spreading inductance is the inductance contributed by the parts of the planes connecting the capacitor connector vias to the die connections or to other capacitor vias. If the power and ground planes are closer, the spreading inductance is lower. On one/two layer boards dedicated power/ground planes are absent. So the spreading inductance is replaced by PCB track inductances. The inductance contributed by the mounted area of the capacitor is known as mounting inductance. On one/two layer boards dedicated power/ground planes are absent. So the spreading inductance is replaced by PCB track inductances. The dependencies of various circuit parameters on antiresonance peak are studied using circuit theory. A general condition for damping the antiresonance is formulated. The antiresonance peak reduces with Q factor. The conventional critical condition for antiresonance peak damping needs modification when magnetic coupling is present between the mounting loops of two parallel unequal value capacitors. By varying the connection geometry it is possible to obtain negative and positive coupling coefficients. The connection geometries to obtain these two are shown. An example is shown for positive and negative coupling coefficient cases with simulation and experimental results. For the example discussed, RC Æ 32 - for k Æ Å0.6 and RC Æ 64 - for k Æ ¡0.6, where RC is the critical damping value and k is the magnetic coupling coefficient between the two mounting loops. The reason for this is that, the antiresonance peak impedance value is higher for negative coupling coefficient case than that for positive coupling coefficient case. Above the self resonant frequencies of both the capacitors, the equivalent impedance of the parallel capacitors become inductive. This case is studied with two equal value capacitors in parallel. It is shown that the equivalent inductance is lower for negative coupling coefficient case as compared to positive coupling coefficient case. An example is provided with simulation and experimental results. In the experimental results, parasitic inductance is observed to be 2.6 times lower for negative coupling coefficient case than that for positive coupling coefficient case. When equal value capacitors are connected in parallel, it is advantageous to use a negative coupling geometry due to this. Chapter 4 introduces a new method to damp the antiresonance peak using a magnet-ically coupled resistive loop. Reducing the Q factor is an option to suppress the peak. In this new method, the Q factor reduction is achieved by introducing losses by mag-netically coupling a resistive loop. The proposed circuit is analyzed with circuit-theory, and governing equations are obtained. The optimum value of resistance for achieving maximum damping is obtained through analysis. Simulation and experimental results are shown to validate the theory. From the experimental results approximately 247 times reduction in antiresonance peak is observed with the proposed method. Effectiveness of the new method is limited by the magnetic coupling coefficient between the two mounting loops of capacitors. The method can be further improved if the coupling coefficient can be increased at the antiresonance frequency. Chapter 5 focuses on the third objective of a PDN, that is to reduce the noise injected by the microprocessor. A new method is proposed to reduce the conducted noise from a microprocessor with switched super capacitors. The conventional switched capacitor filters are based on the concept that the flying capacitor switching at high frequency looks like a resistor at low frequency. So for using at audio frequencies the flying capacitors were switching at MHz frequencies. In this chapter the opposite of this scenario is studied; the flying capacitors are the energy storage elements of a switched capacitor converter and they switch at lower frequencies as compared to the noise frequencies. Two basic circuits (1:1 voltage conversion ratio) providing noise isolation were discussed. They have distinct steady state input current waveforms and are explained with PSPICE simulations. The inrush current through switches are capable of destroying them in a practical implementation. A practical solution was proposed using PMOS-PNP pair. The self introduced switching noise of the converter is lower when switching frequency is low and turn ON-OFF time is higher. If power metal oxide semiconductor field effect transistor (MOSFET)s are used, the turn ON and turn OFF are slow. The switching frequency can be lowered based on the voltage drop power loss. The governing equations were formulated and simulated. It is found that the switching frequency can be lowered by increasing the capacitance value without affecting the voltage drop and power loss. From the equations, it is found that the design parameters have a cyclic dependency. Noise can short through the parasitic capacitance of the switches. Two circuits were proposed to improve the noise isolation: 1) T switch 2) ¦ switch. Of these, the ¦ switch has the higher measured transfer impedance. Experimental results showed a noise reduction of (40-20) dB for the conducted frequency range of 150 kHz - 30 MHz with the proposed 1:1 switched capacitor converter. One possible improvement of this method is to combine the noise isolation with an existing switched capacitor converter (SCC) topology. The discussed example had a switching frequency of 700 Hz, and it is shown that this can isolate the switching noise in kHz and MHz regions. In a PDN there are antiresonance peaks in kHz regions. If the proposed circuit is kept close to a microprocessor, it can reduce the excitation currents of these low frequency antiresonance peaks. Chapter 6 concludes the thesis by stating the major contributions and applications of the concepts introduced in the thesis. This chapter also discusses the future scope of these concepts.

碩士
國立東華大學
電機工程學系
93
Inductively coupled plasma (ICP) source is one of most popular research topic because of its characteristics and advantages: (1) high density plasma generation at low pressure (<10mtorr) (2) relatively simple configuration and easy design (3) no contact with electrode to get purer plasma (4) higher power-energy transformation rate compared with conventional plasma source, nevertheless, it will be an uniformity issue for the large area plasma process due to disproportionate self inductance of coil. We propose a new designed coil with lower inductance which has a tunable capacitor to adjust current deposition in the coil, differs from conventional design in current flow manner. We numerically calculate the induced electrical field distribution under some different geometric configurations to find the optimum design rules. Others, we also calculate induced electrical field in multi-coil coupling plasma situation and propose effective circuit respectively for the future reference of power match design. Simulated model has outer coil radius 12cm and inner radius 4cm. The data show 8% improvement in the uniformity compared to conventional spiral coil, and 17% improvement if the tunable capacitor add. In the multi-coil case, uniformity profile close to single coil's result, but little increased input impedance. It is assumed to have relation to mutual induction between coils.