Journal articles: 'Core Reconfiguration'

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Wanta, Damian, Waldemar T. Smolik, Jacek Kryszyn, Przemysław Wróblewski, and Mateusz Midura. "A Run-Time Reconfiguration Method for an FPGA-Based Electrical Capacitance Tomography System." Electronics 11, no. 4 (February 11, 2022): 545. http://dx.doi.org/10.3390/electronics11040545.

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A desirable feature of an electrical capacitance tomography system is the adaptation possibility to any sensor configuration and measurement mode. A run-time reconfiguration of a system for electrical capacitance tomography is presented. An original mechanism is elaborated to reconfigure, on the fly, a modular EVT4 system with multiple FPGAs installed. The outlined system architecture is based on FPGA programmable logic devices (Xilinx Spartan) and PicoBlaze soft-core processors. Soft-core processors are used for communication, measurement control and data preprocessing. A novel method of FPGA partial reconfiguration is described, in which a PicoBlaze soft-core processor is used as a reconfiguration controller. Behavioral reconfiguration of the system is obtained by providing run-time access to the program code of a soft-core control processor. The tests using EVT4 hardware and different algorithms for tomographic scanning were performed. A test object was measured using 2D and 3D sensors. The time and resources required for the examined reconfiguration procedure are evaluated.

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Abdelrahman, T., C. Thomas, A. Iorwerth, MJ Pollitt, M. Holt, and WG Lewis. "Core surgical training outcome in Wales." Bulletin of the Royal College of Surgeons of England 98, no. 10 (November 2016): 456–59. http://dx.doi.org/10.1308/rcsbull.2016.457.

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Li, Ji, Huagang Xiong, Qiao Li, Feng Xiong, and Jiaying Feng. "Run-Time Reconfiguration Strategy and Implementation of Time-Triggered Networks." Electronics 11, no. 9 (May 5, 2022): 1477. http://dx.doi.org/10.3390/electronics11091477.

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Time-triggered networks are deployed in avionics and astronautics because they provide deterministic and low-latency communications. Remapping of partitions and the applications that reside in them that are executing on the failed core and the resulting re-routing and re-scheduling are conducted when a permanent end-system core failure occurs and local resources are insufficient. We present a network-wide reconfiguration strategy as well as an implementation scheme, and propose an Integer Linear Programming based joint mapping, routing, and scheduling reconfiguration method (JILP) for global reconfiguration. Based on scheduling compatibility, a novel heuristic algorithm (SCA) for mapping and routing is proposed to reduce the reconfiguration time. Experimentally, JILP achieved a higher success rate compared to mapping-then-routing-and-scheduling algorithms. In addition, relative to JILP, SCA/ILP was 50-fold faster and with a minimal impact on reconfiguration success rate. SCA achieved a higher reconfiguration success rate compared to shortest path routing and load-balanced routing. In addition, scheduling compatibility plays a guiding role in ILP-based optimization objectives and ‘reconfigurable depth’, which is a metric proposed in this paper for the determination of the reconfiguration potential of a TT network.

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Suri, Tameesh, and Aneesh Aggarwal. "Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration." International Journal of Parallel Programming 38, no. 3-4 (January 23, 2010): 203–24. http://dx.doi.org/10.1007/s10766-010-0128-3.

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Prabhu, Gayathri R., Bibin Johnson, and J. Sheeba Rani. "Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration." International Journal of Reconfigurable Computing 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/243835.

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A Givens rotation based scalable QRD core which utilizes an efficient pipelined and unfolded 2D multiply and accumulate (MAC) based systolic array architecture with dynamic partial reconfiguration (DPR) capability is proposed. The square root and inverse square root operations in the Givens rotation algorithm are handled using a modified look-up table (LUT) based Newton-Raphson method, thereby reducing the area by 71% and latency by 50% while operating at a frequency 49% higher than the existing boundary cell architectures. The proposed architecture is implemented on Xilinx Virtex-6 FPGA for any real matrices of sizem×n, where4≤n≤8andm≥nby dynamically inserting or removing the partial modules. The evaluation results demonstrate a significant reduction in latency, area, and power as compared to other existing architectures. The functionality of the proposed core is evaluated for a variable length adaptive equalizer.

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Zuo, Nianming, Zhengyi Yang, Yong Liu, Jin Li, and Tianzi Jiang. "Core networks and their reconfiguration patterns across cognitive loads." Human Brain Mapping 39, no. 9 (April 20, 2018): 3546–57. http://dx.doi.org/10.1002/hbm.24193.

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Yi, Lim, Anh Vu Le, Balakrishnan Ramalingam, Abdullah Aamir Hayat, Mohan Rajesh Elara, Tran Hoang Quang Minh, Braulio Félix Gómez, and Lum Kai Wen. "Locomotion with Pedestrian Aware from Perception Sensor by Pavement Sweeping Reconfigurable Robot." Sensors 21, no. 5 (March 3, 2021): 1745. http://dx.doi.org/10.3390/s21051745.

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Regular washing of public pavements is necessary to ensure that the public environment is sanitary for social activities. This is a challenge for autonomous cleaning robots, as they must adapt to the environment with varying pavement widths while avoiding pedestrians. A self-reconfigurable pavement sweeping robot, named Panthera, has the mechanisms to perform reconfiguration in width to enable smooth cleaning operations, and it changes its behavior based on environment dynamics of moving pedestrians and changing pavement widths. Reconfiguration in the robot’s width is possible, due to the scissor mechanism at the core of the robot’s body, which is driven by a lead screw motor. Panthera will perform locomotion and reconfiguration based on perception sensors feedback control proposed while using an Red Green Blue-D (RGB-D) camera. The proposed control scheme involves publishing robot kinematic parameters for reconfiguration during locomotion. Experiments were conducted in outdoor pavements to demonstrate the autonomous reconfiguration during locomotion to avoid pedestrians while complying with varying pavements widths in a real-world scenario.

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Lyric, Zoairia Idris, Mohammad Sayem Mahmood, and Mohammad Abdul Motalab. "A study on TRIGA core reconfiguration with new irradiation channels." Annals of Nuclear Energy 43 (May 2012): 183–86. http://dx.doi.org/10.1016/j.anucene.2011.12.034.

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Prasad Acharya, G., and M. Asha Rani. "Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 3 (May 28, 2018): 160. http://dx.doi.org/10.11591/ijres.v6.i3.pp160-168.

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<span>This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency.</span>

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OKLOPCIC, ZORAN. "Beyond Empty, Conservative, and Ethereal: Pluralist Self-Determination and a Peripheral Political Imaginary." Leiden Journal of International Law 26, no. 3 (July 31, 2013): 509–29. http://dx.doi.org/10.1017/s0922156513000216.

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AbstractOver the last couple of years, a stream of pluralist theories of international legal order has developed at the intersection of international law and political theory, having immediate implications for conceptualizing self-determination. The understanding of self-determination under the framework ofbounded,constitutional, andradicalpluralism markedly departs from the previous wave of normative theories in the 1990s: self-determination is now evacuated from the field of national pluralism and struggles over territory.This article does not question the thrust of pluralists’ recent work, but complements their critical attunement to global disparities of power, and complicates their neglect of nationalism and rejection of territorial reconfigurations as self-determination's core meaning. In doing so, it unearths two visions that come from the (semi-)periphery of the international political order. The first belongs to Edvard Kardelj, pre-eminent Yugoslav theorist of socialist self-management and the Non-Aligned Movement. The second belongs to Leopold Sédar Senghor, the poet and politician, advocate ofnégritude, a proponent of French West African integration, and a constitutional advocate for the reconfiguration – not abolition – of the French Union, the heir to the French Empire. While they are suspicious of extensive territorial reconstruction, like contemporary pluralists, unlike them they have seen a role for territorial reconfigurations in the name of national plurality.

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Ma, Hongjia, Qing Sun, Yang Gao, and Yuan Gao. "Resource Integration, Reconfiguration, and Sustainable Competitive Advantages: The Differences between Traditional and Emerging Industries." Sustainability 11, no. 2 (January 21, 2019): 551. http://dx.doi.org/10.3390/su11020551.

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Emerging industries bear great difference from traditional industries. It is valuable to explore the effectiveness of different resource management methods in the two industries. Based on this, the purposes of this paper are first to define and distinguish two core resource management methods (i.e., resource integration and resource reconfiguration), and second to research the different impact paths of resource integration and resource reconfiguration on the sustainable competitive advantages in different industries. Primarily, in order to achieve these purposes, this paper explores the generation path of resource integration and resource reconfiguration from the perspective of organizational learning; secondly, the empirical analysis method is applied to examine the different influences between resource integration and resource reconfiguration on sustainable competitive advantages. Based on 208 samples in traditional industries and 220 samples in emerging industries, the results show that resource integration and resource reconfiguration are the consequence of organizational learning. In traditional industries, resource integration and resource reconfiguration have a positive impact on sustainable competitive advantages, respectively, resulting in a “concerto effect” on sustainable competitive advantages. While, in emerging industries, though resource integration has a positive impact on sustainable competitive advantages, however, there is an inverted U-shaped relationship between resource reconfiguration and sustainable competitive advantages. In such a situation, the “concerto effect” disappeared. This paper not only reveals the uniqueness of different resource management methods in different industries but also enriches the applications of resource management theories in different situations.

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Hamman, Joseph J., Bart Nijssen, Theodore J. Bohn, Diana R. Gergel, and Yixin Mao. "The Variable Infiltration Capacity model version 5 (VIC-5): infrastructure improvements for new applications and reproducibility." Geoscientific Model Development 11, no. 8 (August 30, 2018): 3481–96. http://dx.doi.org/10.5194/gmd-11-3481-2018.

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Abstract. The Variable Infiltration Capacity (VIC) model is a macroscale semi-distributed hydrologic model. VIC development began in the early 1990s and the model has since been used extensively for basin- to global-scale applications that include hydrologic dataset construction, trend analysis of hydrologic fluxes and states, data evaluation and assimilation, forecasting, coupled climate modeling, and climate change impact assessment. Ongoing operational applications of the VIC model include the University of Washington's drought monitoring and forecasting systems and NASA's Land Data Assimilation System. This paper documents the development of VIC version 5 (VIC-5), which includes a major reconfiguration of the legacy VIC source code to support a wider range of modern hydrologic modeling applications. The VIC source code has been moved to a public GitHub repository to encourage participation by the broader user and developer communities. The reconfiguration has separated the core physics of the model from the driver source code, whereby the latter is responsible for memory allocation, preprocessing and post-processing, and input–output (I–O). VIC-5 includes four drivers that use the same core physics modules, but which allow for different methods for accessing this core to enable different model applications. Finally, VIC-5 is distributed with robust test infrastructure, components of which routinely run during development using cloud-hosted continuous integration. The work described here provides an example to the model development community for extending the life of a legacy model that is being used extensively. The development and release of VIC-5 represents a significant step forward for the VIC user community in terms of support for existing and new model applications, reproducibility, and scientific robustness.

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Verdoscia, Lorenzo, and Roberto Giorgi. "A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs." Mathematical Problems in Engineering 2016 (May 16, 2016): 1–21. http://dx.doi.org/10.1155/2016/3190234.

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We present a new type of soft-core processor called the “Data-Flow Soft-Core” that can be implemented through FPGA technology with adequate interconnect resources. This processor provides data processing based on data-flow instructions rather than control flow instructions. As a result, during an execution on the accelerator of the Data-Flow Soft-Core, both partial data and instructions are eliminated as traffic for load and store activities. Data-flow instructions serve to describe a program and to dynamically change the context of a data-flow program graph inside the accelerator, on-the-fly. Our proposed design aims at combining the performance of a fine-grained data-flow architecture with the flexibility of reconfiguration, without requiring a partial reconfiguration or new bit-stream for reprogramming it. The potential of the data-flow implementation of a function or functional program can be exploited simply by relying on its description through the data-flow instructions that reprogram the Data-Flow Soft-Core. Moreover, the data streaming process will mirror those present in other FPGA applications. Finally, we show the advantages of this approach by presenting two test cases and providing the quantitative and numerical results of our evaluations.

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Astarloa, Armando, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, and Jaime Jiménez. "Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs." Journal of Systems Architecture 53, no. 9 (September 2007): 629–43. http://dx.doi.org/10.1016/j.sysarc.2007.01.011.

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Nolting, Stephan, Guillermo Payá-Vayá, Florian Giesemann, Holger Blume, Sebastian Niemann, and Christian Müller-Schloer. "Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture." Journal of Parallel and Distributed Computing 133 (November 2019): 391–406. http://dx.doi.org/10.1016/j.jpdc.2017.09.013.

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Kurniadi, Kezia Amanda, and Kwangyeol Ryu. "Development of Multi-Disciplinary Green-BOM to Maintain Sustainability in Reconfigurable Manufacturing Systems." Sustainability 13, no. 17 (August 24, 2021): 9533. http://dx.doi.org/10.3390/su13179533.

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The reconfigurable manufacturing system (RMS) appears to be eco-friendly while coping with rapidly changing market demands. However, there remains a lack of discussion or research regarding sustainability or environment-friendly functions within RMS. In this study, the reconfiguration planning problem is introduced to represent the core issues within the RMS. Reconfiguration occurs depending on new demands or conditions in the company by reconfiguring machines, such as removing, adding, or changing parts, giving considerable consideration to arrangement of machines, known as configurations in RMS. Therefore, reconfiguration process is always strongly connected to cost, energy consumption, and, more importantly, data management. The complexity of reconfiguration, product variation, and development processes requires tools that are capable of managing multi-disciplinary bill-of-material(BOM) or product data and providing a better collaboration support for data/information tracking while maintaining sustainability. This paper proposes a multi-disciplinary green bill-of-material (MDG-BOM)—an improved Green-BOM concept—with an additional multi-disciplinary feature to minimize emissions and hazardous materials during product development, as well as manage product information across multiple disciplines during the reconfiguration process. A smart spreadsheet for managing MDG-BOM was developed to allow multiple departments to integrate multiple sources of CAD design data and monitor/track changes throughout each step of the process.

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Shen, Lili, Ning Wu, and Gaizhen Yan. "Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches." Electronics 9, no. 2 (February 18, 2020): 346. http://dx.doi.org/10.3390/electronics9020346.

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By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.

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Liu, Fucheng, Yining Liu, Qian Liu, Zhicheng Wu, Yahui Liu, Kuangya Gao, Yafeng He, Weili Fan, and Lifang Dong. "Tunable annular plasma photonic crystals in dielectric barrier discharge." Plasma Sources Science and Technology 31, no. 2 (February 1, 2022): 025015. http://dx.doi.org/10.1088/1361-6595/ac4dde.

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Abstract We demonstrate an effective method for realization of robust, tailorable annular plasma photonic crystals (PPC) in dielectric barrier discharge with two water electrodes. Fast reconfiguration between triangular lattice, annular lattice, core-annular lattice and concentric-annular lattice has been achieved. An active control on the structure of plasma elements is realized by solely changing the applied voltage. The changes of photonic band gaps with reconfiguration of different annular PPCs have been studied both experimentally and numerically. The band gaps between 28.0–30.0 GHz for the core-annular lattice and the concentric-annular lattice are experimentally verified. A phenomenological reaction–diffusion model with two nonlinear-coupled interacting layers is established to mimic the formation of various plasma structures. Experimental observations and numerical simulation are in good agreement. Our approach provides a unique strategy to create reversibly deformable annular PPCs, which may offer new capabilities and serve as a promising platform for various applications.

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Liu, Xiaojian, Shuo Liu, and Hao Lv. "A Dynamic Reconfiguration Scheme for Embedded System Based on Multi-core DSP." Journal of Physics: Conference Series 1802, no. 4 (March 1, 2021): 042099. http://dx.doi.org/10.1088/1742-6596/1802/4/042099.

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Yalcin, Anil O., Bart de Nijs, Zhaochuan Fan, Frans D. Tichelaar, Daniël Vanmaekelbergh, Alfons van Blaaderen, Thijs J. H. Vlugt, Marijn A. van Huis, and Henny W. Zandbergen. "Core–shell reconfiguration through thermal annealing in FexO/CoFe2O4ordered 2D nanocrystal arrays." Nanotechnology 25, no. 5 (January 9, 2014): 055601. http://dx.doi.org/10.1088/0957-4484/25/5/055601.

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Li, Zheng, and Shuibing He. "Run-time timing prediction for system reconfiguration on many-core embedded systems." Journal of Systems Architecture 95 (May 2019): 47–54. http://dx.doi.org/10.1016/j.sysarc.2019.03.004.

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Charles, Subodha, Alif Ahmed, Umit Y. Ogras, and Prabhat Mishra. "Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs." ACM Transactions on Design Automation of Electronic Systems 24, no. 6 (November 14, 2019): 1–23. http://dx.doi.org/10.1145/3350422.

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Pourmohseni, Behnaz, Stefan Wildermann, Michael Glaß, and Jürgen Teich. "Hard real-time application mapping reconfiguration for NoC-based many-core systems." Real-Time Systems 55, no. 2 (January 24, 2019): 433–69. http://dx.doi.org/10.1007/s11241-019-09326-y.

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Kirchhoff, Michael, Philipp Kerling, Detlef Streitferdt, and Wolfgang Fengler. "A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor." International Journal of Reconfigurable Computing 2019 (September 22, 2019): 1–14. http://dx.doi.org/10.1155/2019/4723838.

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Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. When using the full potential of FPGAs, it is possible to dynamically reconfigure parts of them during run time without the need to stop the device. This feature is called dynamic partial reconfiguration (DPR). If the DPR approach is to be applied in a real-time application-specific soft-core processor, an architecture must be created that ensures strict compliance with the real-time constraint at all times. In this paper, a novel method that addresses this problem is introduced, and its realization is described. In the first step, an application-specializable soft-core processor is presented that is capable of solving problems while adhering to hard real-time deadlines. This is achieved by the full design time analyzability of the soft-core processor. Its special architecture and other necessary features are discussed. Furthermore, a method for the optimized generation of partial bitstreams for the DPR as well as its practical implementation in a tool is presented. This tool is able to minimize given bitstreams with the help of a differential frame bitmap. Experiments that realize the DPR within the soft-core framework are presented, with respect to the need for hard real-time capability. Those experiments show a significant resource reduction of about 40% compared to a functionally equivalent non-DPR design.

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Koukolová, Lucia. "Variability of Workplace Structures with SCARA Robot for Palletizing and Sorting Objects." Applied Mechanics and Materials 613 (August 2014): 299–303. http://dx.doi.org/10.4028/www.scientific.net/amm.613.299.

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This paper describes the design of palletizing workplace on a modular basis which can be reconfigured. First part of the paper is devoted to the definition of reconfigurable manufacturing systems and its core characteristics. Second part of the paper describes the workplace for palletization on a modular basis, its parts and possibilities of reconfiguration.

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Cozma, Ana-Maria. "On the discursive construction of the multiple meanings of francophonie/francophone viewed through the prism of argumentative semantics." Kalbotyra 74 (September 15, 2021): 49–71. http://dx.doi.org/10.15388/kalbotyra.2021.74.3.

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This paper addresses the issue of polysemy, and more precisely of multiple meanings in the case of the words francophonie/francophone from the perspective of argumentative semantics. The aim of the paper is to examine the mechanisms that account for the multiple meanings of francophonie/francophone, i.e. the semantic and discursive mechanisms involved in the (re)construction of lexical meaning as the words occur in discourse. The data analysed in this paper consists of a set of discourse fragments about francophone identity, discourses that vary according to the speaker, the geographical location and the media support. The study is carried out within the framework of the SAP theory (Semantics of Argumentative Possibilities), following a procedure based on a pre-built reference meaning – i.e. a description of the argumentative potential of the lexeme – that will be used when analysing the discursive occurrences. First, the paper briefly presents the SAP theory and the pre-built reference meaning of the lexemes francophonie/francophone (described in terms of core-elements, stereotypes and argumentative possibilities). It then illustrates several discursive mechanisms of meaning construction. The analysis highlights a series of meaning construction mechanisms: transgressive activation of the argumentative potential, reconfiguration by scission of the core-elements or by deletion of one of the elements, modality addition, transgressive reconstruction of the core meaning, and finally core circularity. Thus, the paper indicates, from the perspective of argumentative semantics, that the multiple meanings of the words francophonie/francophone, i.e. the various semantic configurations attached to these words, can be seen as reconfigurations of a single lexical meaning.

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Munaf, S., Dr A. Bharathi, and Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Electrical and Electronics Research 4, no. 1 (March 31, 2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.

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Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a con- figuration memory unit (configuration cache) for reconfiguration of its PE array. Though this architecture is meant for high performance and flexibility. Power reduction is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. We propose a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) architecture to reduce power-overhead caused by reconfiguration. The power reduction can be achieved by using the characteristics like double pumping the data bus and an I/O buffer between the memory and the data bus of DDR SDRAM. All modules have been designed at behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.

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Клименко, Оксана, Oksana Klimenko, Владимир Кулаков, Vladimir Kulakov, Сергей Трофимов, Sergey Trofimov, Алексей Ушенин, and Aleksey Ushenin. "Specifics of Implementing Project Management in State Authorities." Scientific Research and Development. Russian Journal of Project Management 7, no. 1 (April 16, 2018): 42–48. http://dx.doi.org/10.12737/article_5ac5db250a3019.43276751.

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The article deals with the possibilities of implementing different management systems in state authorities along with the process of management system reconfiguration. The article defines core benefits and drawbacks of project management and operational management, the specifics of their application in state authorities. Moreover, it evaluates the importance of corporate culture adaptation to the implementation process.

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., C. V. Borkute. "RUN TIME DYNAMIC PARTIAL RECONFIGURATION USING MICROBLAZE SOFT CORE PROCESSOR FOR DSP APPLICATIONS." International Journal of Research in Engineering and Technology 02, no. 12 (December 25, 2013): 151–54. http://dx.doi.org/10.15623/ijret.2013.0212027.

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Jaworski, Mateusz. "Солипсизм в романной поэтике Виктора Пелевина." Studia Rossica Posnaniensia, no. 42 (June 19, 2018): 5–18. http://dx.doi.org/10.14746/strp.2017.42.1.

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The philosophical doctrine of solipsism plays an extremely significant role in Viktor Pelevin’s works as a core idea which undergoes the process of formal modifications. In this paper this process is referred to as “reconfiguration”. The article presents different representations of solipsism in Pelevin’s novels. The analysis is preceded by a brief introduction to the philosophical roots of the doctrine.

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MITTAL, SPARSH, and ZHAO ZHANG. "EnCache: A DYNAMIC PROFILING-BASED RECONFIGURATION TECHNIQUE FOR IMPROVING CACHE ENERGY EFFICIENCY." Journal of Circuits, Systems and Computers 23, no. 10 (October 14, 2014): 1450147. http://dx.doi.org/10.1142/s0218126614501473.

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With each CMOS technology generation, leakage energy consumption has been dramatically increasing and hence, managing leakage power consumption of large last-level caches (LLCs) has become a critical issue in modern processor design. In this paper, we present EnCache, a novel software-based technique which uses dynamic profiling-based cache reconfiguration for saving cache leakage energy. EnCache uses a simple hardware component called profiling cache, which dynamically predicts energy efficiency of an application for 32 possible cache configurations. Using these estimates, system software reconfigures the cache to the most energy efficient configuration. EnCache uses dynamic cache reconfiguration and hence, it does not require offline profiling or tuning the parameter for each application. Furthermore, EnCache optimizes directly for the overall memory subsystem (LLC and main memory) energy efficiency instead of the LLC energy efficiency alone. The experiments performed with an ×86-64 simulator and workloads from SPEC2006 suite confirm that EnCache provides larger energy saving than a conventional energy saving scheme. For single core and dual-core system configurations, the average savings in memory subsystem energy over a shared baseline configuration are 30.0% and 27.3%, respectively.

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Cardona, Luis Andres, and Carles Ferrer. "AC_ICAP: A Flexible High Speed ICAP Controller." International Journal of Reconfigurable Computing 2015 (2015): 1–15. http://dx.doi.org/10.1155/2015/314358.

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The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller.

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Putnik, Goran, Diana Rodrigues, Cátia Alves, Paulo Ávila, Hélio Castro, and Maria Cruz-Cunha. "Analysing meta-organizations with embedded brokering services performance modelled as a call-centre for supporting dynamic reconfigurability of networked and virtual organizations." FME Transactions 48, no. 4 (2020): 725–32. http://dx.doi.org/10.5937/fme2004725p.

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Various companies choose to outsource the delivery of part of their services, so as not to deviate from its core business and improve the service level. This approach leads to a new type of organizations, so-called networked and virtual enterprises, where possibly a great number of companies work together without having direct contact but through a broker, as an intermediary, that streamlines the relationships between them. To enable high level efficiency, as well as some other functional requirements, the meta-organizations and brokering services are conceived as environments and services for networked and virtual enterprises operation and dynamic reconfigurations, representing a model of organizations-of-organizations, as an implementation of one of the Industry 4.0 models and ecosystem for networked and virtual enterprises dynamic reconfiguration. In this paper, the meta-organizations with embedded brokering services, modelled as call centres, are analyzed. Various simulations are presented, based on Erlang's formulas for some of design and performance measures parameters evaluation, such as service level, average waiting time, agent occupancy and service traffic intensity.

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Kamran, Arezoo, and Zainalabedin Navabi. "Self-Healing Many-Core Architecture: Analysis and Evaluation." VLSI Design 2016 (July 25, 2016): 1–17. http://dx.doi.org/10.1155/2016/9767139.

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More pronounced aging effects, more frequent early-life failures, and incomplete testing and verification processes due to time-to-market pressure in new fabrication technologies impose reliability challenges on forthcoming systems. A promising solution to these reliability challenges is self-test and self-reconfiguration with no or limited external control. In this work a scalable self-test mechanism for periodic online testing of many-core processor has been proposed. This test mechanism facilitates autonomous detection and omission of faulty cores and makes graceful degradation of the many-core architecture possible. Several test components are incorporated in the many-core architecture that distribute test stimuli, suspend normal operation of individual processing cores, apply test, and detect faulty cores. Test is performed concurrently with the system normal operation without any noticeable downtime at the application level. Experimental results show that the proposed test architecture is extensively scalable in terms of hardware overhead and performance overhead that makes it applicable to many-cores with more than a thousand processing cores.

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Seco, João, Ricardo Silva, and Margarida Piriquito. "Component J: A component-based programming language with dynamic reconfiguration." Computer Science and Information Systems 5, no. 2 (2008): 63–86. http://dx.doi.org/10.2298/csis0802063s.

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This paper describes an evolution of the ComponentJ programming language, a component-based Java-like programming language where composition is the chosen structuring mechanism. ComponentJ constructs allow for the high-level specification of component structures, which are the basis for the definition of compound objects. In this paper we present a new language design for ComponentJ which is more flexible and also allows the dynamic reconfiguration of objects. The manipulation of components and composition operations at the programming language level allows for the compile time verification, by a type system, of safety structural properties of ComponentJ programs. This work is based on earlier fundamental results where the main concepts are presented and justified in the form of a core component calculus. .

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Uddin, L. Q., K. S. Supekar, S. Ryali, and V. Menon. "Dynamic Reconfiguration of Structural and Functional Connectivity Across Core Neurocognitive Brain Networks with Development." Journal of Neuroscience 31, no. 50 (December 14, 2011): 18578–89. http://dx.doi.org/10.1523/jneurosci.4465-11.2011.

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Troia, Sebastian, Rodolfo Alvizu, and Guido Maier. "Reinforcement Learning for Service Function Chain Reconfiguration in NFV-SDN Metro-Core Optical Networks." IEEE Access 7 (2019): 167944–57. http://dx.doi.org/10.1109/access.2019.2953498.

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Ostroumov, Sergey, and Leonidas Tsiopoulos. "Formal Development of Hierarchical Agent-Based Monitoring Systems for Dynamically Reconfigurable NoC Platforms." International Journal of Embedded and Real-Time Communication Systems 3, no. 2 (April 2012): 40–72. http://dx.doi.org/10.4018/jertcs.2012040103.

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Sophisticated applications deployed on multi-core platforms require many resources as well as dynamic monitoring of the platform to provide efficiently and reliably the needed functionality. In this paper, the authors propose an approach to formal modelling with adequate tool support of an agent-based system whose function is to dynamically monitor the state of the multi-core platform and perform reconfiguration procedures under faults. For this purpose, the authors use the Event-B formalism which allows them to stepwise develop correct-by-construction specifications by mathematical proofs. Furthermore, the formalism enables the decomposition of a specification, which makes it possible to implement a well-structured and hierarchical agent-based monitoring system.

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Juárez-Vidales, Josué de Jesús, Jesús Pérez-Ortega, Jonathan Julio Lorea-Hernández, Felipe Méndez-Salcido, and Fernando Peña-Ortega. "Configuration and dynamics of dominant inspiratory multineuronal activity patterns during eupnea and gasping generation in vitro." Journal of Neurophysiology 125, no. 4 (April 1, 2021): 1289–306. http://dx.doi.org/10.1152/jn.00563.2020.

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By means of multielectrode recordings of preBötC neurons, we evaluated their configuration in normoxia and hypoxia, finding that the preBötC exhibits a scale-free configuration with a rich-club phenomenon. preBötC neurons produce multineuronal activity patterns that are highly stable but change during hypoxia. The preBötC contains a coactivating core network that exhibit a distinctive pattern of coactivation at the beginning of inspirations. These results reveal some network basis of inspiratory rhythm generation and its reconfiguration during hypoxia.

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KIM, YOONJIN. "POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE." Journal of Circuits, Systems and Computers 22, no. 03 (March 2013): 1350001. http://dx.doi.org/10.1142/s0218126613500011.

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Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes — one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves 56.50%/86.84% of the average power in write/read-operation of configuration cache compared to the previous design.

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Zhang, Yi, Chunjie Wang, Yuzhao Yao, Changsong Zhou, and Feiyan Chen. "Adaptive Reconfiguration of Intrinsic Community Structure in Children with 5-Year Abacus Training." Cerebral Cortex 31, no. 6 (February 13, 2021): 3122–35. http://dx.doi.org/10.1093/cercor/bhab010.

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ABSTRACT Human learning can be understood as a network phenomenon, underpinned by the adaptive reconfiguration of modular organization. However, the plasticity of community structure (CS) in resting-state network induced by cognitive intervention has never been investigated. Here, we explored the individual difference of intrinsic CS between children with 5-year abacus-based mental calculation (AMC) training (35 subjects) and their peers without prior experience in AMC (31 subjects). Using permutation-based analysis between subjects in the two groups, we found the significant alteration of intrinsic CS, with training-attenuated individual difference. The alteration of CS focused on selective subsets of cortical regions (“core areas”), predominantly affiliated to the visual, somatomotor, and default-mode subsystems. These subsystems exhibited training-promoted cohesion with attenuated interaction between them, from the perspective of individuals’ CS. Moreover, the cohesion of visual network could predict training-improved math ability in the AMC group, but not in the control group. Finally, the whole network displayed enhanced segregation in the AMC group, including higher modularity index, more provincial hubs, lower participation coefficient, and fewer between-module links, largely due to the segregation of “core areas.” Collectively, our findings suggested that the intrinsic CS could get reconfigured toward more localized processing and segregated architecture after long-term cognitive training.

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KWON, YOUNG-SU, and NAK-WOONG EUM. "APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR." Journal of Circuits, Systems and Computers 19, no. 07 (November 2010): 1435–47. http://dx.doi.org/10.1142/s0218126610006748.

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Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler integrated in memory access arbiter for the parallel memory system in a soft processor. The novel address shuffling algorithm profiles memory access pattern of the application, produces the access conflict graph, relocates decomposed memory sub-pages based on the access conflict graph, and finally generates a synthesizable code of the address shuffler. The address shuffler efficiently translates the requested memory addresses into the shuffled addresses such that the amount of simultaneous accesses to the identical physical memory block diminishes. The reconfigurability of the address shuffler enables the adaptive address shuffling depending on the memory access pattern of an application running on the soft processor. The configurable address shuffler removes 80% of access conflicts on average for benchmarks where the hardware overhead of the shuffler is 1592 LUTs which is 14% of LUT size of the processor core.

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Yang, Zhangsheng, Hirotaka Yoshioka, and John R. McCarrey. "Sequence-specific promoter elements regulate temporal-specific changes in chromatin required for testis-specific activation of the Pgk2 gene." REPRODUCTION 146, no. 5 (November 2013): 501–16. http://dx.doi.org/10.1530/rep-13-0311.

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The phosphoglycerate kinase-2 (Pgk2) gene is regulated in a tissue-, cell type-, and developmental stage-specific manner during spermatogenesis and is required for normal sperm motility and fertility in mammals. Activation ofPgk2transcription is regulated by testis-specific demethylation of DNA and binding of testis-specific transcription factors to enhancer and core promoter elements. Here, we show that chromatin remodeling including reconfiguration of nucleosomes and changes in histone modifications is also associated with transcriptional activation of thePgk2gene during spermatogenesis. Developmental studies indicate that the order of events involved in transcriptional activation of thePgk2gene includes demethylation of DNA in T1- and T2-prospermatogonia, binding of a factor to the CAAT box in type A and B spermatogonia, followed by recruitment of chromatin remodeling factors, displacement of a nucleosome from thePgk2promoter region, binding of factors to thePgk2core promoter and enhancer regions, and, finally, initiation of transcription in primary spermatocytes. Transgene studies show thatPgk2core promoter elements are required to direct demethylation of DNA and reconfiguration of nucleosomes, whereas both enhancer and core promoter elements are required to direct changes in histone modifications and initiation of transcription. These results provide novel insight into the developmental order of molecular events required to activate tissue-specific transcription of thePgk2gene, the distinct elements in the 5′-regulatory region of thePgk2gene that regulate each of these events, and the relationship among these events in that each step in this process appears to be a necessary prerequisite for the subsequent step.

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Lopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto, and José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture." Electronics 10, no. 6 (March 12, 2021): 669. http://dx.doi.org/10.3390/electronics10060669.

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Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.

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Shin, Seungryul Ryan, John Han, Klaus Marhold, and Jina Kang. "Reconfiguring the firm’s core technological portfolio through open innovation: focusing on technological M&A." Journal of Knowledge Management 21, no. 3 (May 8, 2017): 571–91. http://dx.doi.org/10.1108/jkm-07-2016-0295.

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Purpose The purpose of this study is to investigate the effects of open innovation, especially focusing on technological M&A, on subsequent innovation and changes to the firm’s core technological portfolio. Design/methodology/approach The study suggests three types of core technological areas, based on prior focus and experience in technological categories. These are 1) the existing core area, in which the acquirer firm retains its knowledge and expertise, 2) the enhanced core area, where knowledge and expertise in the acquirer firm’s insufficient areas are strengthened, and 3) the new core area, i.e. new knowledge fields in which the acquirer firm ventures into. The study then analyzes the effects of two key knowledge characteristics of the target firm, similarity and complementarity, on post-M&A innovation outcomes in each of the three core technological areas. Findings The results confirm that while none of the investigated knowledge characteristics of the target firm is advantageous for post-M&A innovation outcomes in existing core areas, similarity of the target firm does facilitate post-M&A innovation outcomes in enhanced core areas. Moreover, the results confirm that complementarity of the target firm is beneficial for post-M&A innovation outcomes in new core areas. Originality/value The study explains the reconfiguration mechanism of a firm’s core technological portfolio. It also suggests an extended framework to analyze innovation outcomes in more detail. Moreover, the study helps to explain why most M&As result in failure.

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Battard, Nicolas, Paul F. Donnelly, and Vincent Mangematin. "Organizational Responses to Institutional Pressures: Reconfiguration of Spaces in Nanosciences and Nanotechnologies." Organization Studies 38, no. 11 (January 24, 2017): 1529–51. http://dx.doi.org/10.1177/0170840616685359.

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The literature on organizational responses to institutional pressures describes responses ranging from compliance to resistance via different modes of decoupling. However, although these studies provide a greater understanding of the phenomenon, they tend to consider the different elements separately. Through a comparative case study of six research teams in the area of nanosciences and nanotechnologies, we offer three contributions. Our first contribution is to the decoupling literature by way of a complementary and cohesive framework, which shows that organizations vary in their responses by reconfiguring their physical (policy and materiality), mental (meaning) and social (identity) spaces, and that each space can be reconfigured at the core or periphery, or not be reconfigured. Our second and third contributions are through descriptions of two modes of organizational responses to institutional pressures and two factors explaining the variety of responses.

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Saeed, Ahmed, Ali Ahmadinia, and Mike Just. "Secure On-Chip Communication Architecture for Reconfigurable Multi-Core Systems." Journal of Circuits, Systems and Computers 25, no. 08 (May 17, 2016): 1650089. http://dx.doi.org/10.1142/s0218126616500894.

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Security is becoming the primary concern in today’s embedded systems. Network-on-chip (NoC)-based communication architectures have emerged as an alternative to shared bus mechanism in multi-core system-on-chip (SoC) devices and the increasing number and functionality of processing cores have made such systems vulnerable to security attacks. In this paper, a secure communication architecture has been presented by designing an identity and address verification (IAV) security module, which is embedded in each router at the communication level. IAV module verifies the identity and address range to be accessed by incoming and outgoing data packets in an NoC-based multi-core shared memory architecture. Our IAV module is implemented on an FPGA device for functional verification and evaluated in terms of its area and power consumption overhead. For FPGA-based systems, the IAV module can be reconfigured at run-time through partial reconfiguration. In addition, a cycle-accurate simulation is carried out to analyze the performance and total network energy consumption overhead for different network configurations. The proposed IAV module has presented reduced area and power consumption overhead when compared with similar existing solutions.

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Chen, Tsan-Yao, Po-Chun Huang, Yen-Fa Liao, Yu-Ting Liu, Tsung-Kuang Yeh, and Tsang-Lang Lin. "Shell thickness effects on reconfiguration of NiOcore–Ptshell anodic catalysts in a high current density direct methanol fuel cell." RSC Advances 6, no. 76 (2016): 72607–15. http://dx.doi.org/10.1039/c6ra17013g.

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Koch, Dirk, Christian Beckhoff, and Jim Torresen. "Efficient Interfacing of Partially Reconfigurable Instruction Set Extensions for Softcore CPUs on FPGAs." Journal of Integrated Circuits and Systems 6, no. 1 (December 27, 2011): 35–42. http://dx.doi.org/10.29292/jics.v6i1.336.

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Swapping just small fractions of the configuration of an FPGA can be very beneficial in many applications. This is in particular useful for reconfiguring the instruction set of embedded soft core processors. In this paper, we will sketch that present design techniques include a substantial overhead for integrating reconfigurable parts into the rest of the system. This overhead can cost more logic resources than the actual module implementations. For removing this overhead, we propose a novel technique to constrain the communication resources between the static system and the partial regions.We will demonstrate for a reconfigurable soft core processor that instructions can be integrated into the system without causing any additional logic overhead for the communication. In addition, we reveal how such systems can be easily implemented with our tool ReCoBus-Builder. Furthermore, we will analyze the overhead in terms of reconfiguration time and present a metric helping to take design decisions.

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Yavar, A. R., S. Sarmani, A. K. Wood, S. M. Fadzil, Z. Masood, and K. S. Khoo. "Neutron flux parameters for k0-NAA method at the Malaysian nuclear agency research reactor after core reconfiguration." Radiation Measurements 46, no. 2 (February 2011): 219–23. http://dx.doi.org/10.1016/j.radmeas.2010.11.014.

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Journal articles on the topic 'Core Reconfiguration'

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