Academic literature on the topic 'Controllo dV'

Node localization information plays an important role in wireless sensor networks (WSNs). To solve the problem of low localization accuracy of distance vector hop (DV-Hop) localization algorithm in wireless sensor networks, an improved localization algorithm called MAOADV-Hop based on the modified Archimedes optimization algorithm (MAOA) and DV-Hop is proposed, which can achieve the balance between the localization speed and the localization precision. Firstly, tent chaotic mapping and particle swarm optimization (PSO) algorithm are introduced into Archimedes optimization algorithm to improve the initial population diversity and change the update rules of density and volume, which improve the global convergence ability and convergence speed of the algorithm. Secondly, the MAOA is used to replace the least square part of the DV-Hop localization algorithm to improve the localization accuracy of the algorithm. Finally, MAOADV-Hop is verified through four different network environments and compared with DE_DV-Hop, BOA_DV-Hop, and DV-Hop. The simulation results show that the localization speed of the proposed approach is faster than that of DE_DV-Hop and BOA_DV-Hop, and the localization error is less than that of DV-Hop, DE_DV-Hop, and BOA_DV-Hop.

Node localization technology has become a research hotspot for wireless sensor networks (WSN) in recent years. The standard distance vector hop (DV-Hop) is a remarkable range-free positioning algorithm, but the low positioning accuracy limits its application in certain scenarios. To improve the positioning performance of the standard DV-Hop, an enhanced DV-Hop based on weighted iteration and optimal beacon set is presented in this paper. Firstly, different weights are assigned to beacons based on the per-hop error, and the weighted minimum mean square error (MMSE) is performed iteratively to find the optimal average hop size (AHS) of beacon nodes. After that, the approach of estimating the distance between unknown nodes and beacons is redefined. Finally, considering the influence of beacon nodes with different distances to the unknown node, the nearest beacon nodes are given priority to compute the node position. The optimal coordinates of the unknown nodes are determined by the best beacon set derived from a grouping strategy, rather than all beacons directly participating in localization. Simulation results demonstrate that the average localization error of our proposed DV-Hop reaches about 3.96 m, which is significantly lower than the 9.05 m, 7.25 m, and 5.62 m of the standard DV-Hop, PSO DV-Hop, and Selective 3-Anchor DV-Hop.

INTRODUÇÃO: Caracteriza-se a demência vascular (DV) como distúrbio cognitivo provocado por doença cerebrovascular ou redução do fluxo sanguíneo cerebral. A arteriosclerose, o hábito de vida e as doenças crônicas funcionam como fatores de risco para o desenvolvimento de placas ateroscleróticas, predispondo a demência nos idosos. A aterosclerose representa cerca de 15% a 20% dos casos de demência na América do Norte e Europa e 30% na Ásia. O objetivo do estudo é elucidar o papel da aterosclerose no desenvolvimento da DV, assim como os fatores relacionados à patogênese, e traçar possíveis formas de prevenção dessa enfermidade. MÉTODOS: A revisão sistemática foi realizada nas bases de dados Pubmed, entre os meses de fevereiro e abril de 2022. A partir da combinação dos descritores, definidos pelo DeCS, "risk factors" AND "Vascular Dementia", foram encontrados 176 artigos, que selecionaram-se 6. Também foi feita uma busca com a combinação de descritores “Atherosclerosis” AND “Vascular Dementia”, foram encontrados 20 artigos e selecionaram-se 2. Incluíram-se artigos completos, publicados entre 2017 e 2022, na língua inglesa, portuguesa ou espanhola. Foram excluídos estudos que abordavam experimentos em animais. Com base na leitura dos títulos e dos resumos, selecionaram-se 9 artigos relacionados ao tema, além de outros 3 estudos fora da estratégia de busca e a Diretriz Brasileira de Hipertensão Arterial de 2020. DISCUSSÃO: As anormalidades vasculares estruturais e funcionais se exacerbam com a idade e podem provocar déficits cognitivos, devido a alterações crônicas das funções neurovasculares, o que fundamenta a etiologia da DV. A DV pode ser classificada em duas síndromes principais, demência pós-AVC em que há declínio cognitivo gradual, com alterações na memória episódica e funções executivas; E a DV sem AVC recente, porém com evidência de imagem de doença cerebrovascular previamente desconhecida, geralmente o envolvimento dos pequenos vasos, em que observa-se mudanças na velocidade de processamento, além das alterações anteriores. Sintomas neuropsiquiátricos, desaceleração da marcha também podem estar presentes em ambas. A doença aterosclerotica pode desenvolver AVC e diminuição do fluxo sanguíneo, relacionados com DV. Nesse sentido, tabagismo, infarto, diabetes mellitus (DM), hipertensão arterial sistêmica, dislipidemia (DLP) - pelo acúmulo de β-amilóide (Aβ) cerebral - e sedentarismo são fatores de risco. O desenvolvimento da aterosclerose provoca alteração na regulação de miRNAs, que estão envolvidos na excitotoxicidade neuronal, neuroinflamação e aumento da permeabilidade, acarreta perda de volume tecidual cerebral, diminuição de massa branca, talâmica e de lobo temporal, além de infartos subcorticais, o que justifica distúrbios cognitivos. Além disso, estresse oxidativo e o desequilíbrio entre antioxidantes e espécies reativas de oxigênio (ERO) danificam o endotélio dos vasos, as células gliais e os neurônios. Danos na unidade neurovascular levam a hipoperfusão crônica, hipóxia, produção excessiva de fatores pró-inflamatórios e redução da utilização de óxido nítrico. Corroborando às alterações vasculares, evidencia-se nos idosos a redução do fluxo sanguíneo quando em repouso, ativando mecanismos neuro inflamatórios, que resultam em lesões da substância branca, neurodegeneração e até atrofia cerebral. Por fim, a localização da lesão aterosclerótica também tem papel na sintomatologia. O diagnóstico, a prevenção e o tratamento da DV pode ser auxiliado por medidas como a espessura da íntima média, a dilatação medida por fluxo, o índice tornozelo braquial e o cálcio da artéria coronária. CONCLUSÃO: Além do envelhecimento, a associação de comorbidades comuns na população idosa, como HAS, DM e DLP relacionam-se com a formação de placas ateroscleróticas e o desenvolvimento da DV. Assim, é essencial controlar o estilo de vida, doenças crônicas e fatores psicossociais que interferem diretamente nos fatores de risco relacionados à formação aterosclerótica, ocorrência de eventos vasculares e evolução da DV. O avanço tecnológico em genética, metabolômica, proteômica e modelos (pré-clínicos) de doenças deve contribuir para estudos mais aprofundados sobre o tema e interações patológicas que podem levar a neurodegeneração.

To increase the positioning accuracy of Distance Vector-Hop (DV-Hop) algorithm in non-uniform networks, an improved DV-Hop algorithm based on RSSI correction is proposed. The new algorithm first quantizes hops between two nodes by the ratio of the RSSI value between two nodes and the benchmark RSSI value, divides the hops continuously, calculates the average hop distance according to the Minimum Mean Square Error (MMSE) criterion of the best index based on the quantized hops, and then adds hop distance matching factor to the fitness function of each anchor node into the calculation of the hop distance fitness function to weight the fitness function. The change index value is introduced to obtain more accurate hop distance value, and then the estimation error of unknown node (UN) coordinate is modified by using the distance relationship between the UN and the nearest beacon node (BN), and the modified coordination position is further modified by using the triangle centroid to improve the accuracy of node positioning in the irregular network. The experimental results show that compared with the original DV-Hop, improved DV-Hop1, improved DV-Hop2 and improved DV-Hop3, the localization error of the improved algorithm in this paper is reduced by 58%, 45%, 34%, and 29%, respectively, on average, in the two network environments. Without increasing the hardware cost and energy consumption, the improved algorithm has excellent localization performance.

Many researchers have studied socioeconomic, health, and security variables in the developed countries; however, very few studies used multivariate analysis in developing countries. The current study contributes to the scarce literature about the determinants of the variance in socioeconomic, health, and security factors. Questions raised were whether the independent variables (IVs) of governorate and year impact the socioeconomic, health, and security dependent variables (DVs) in Jordan, whether the marginal mean of each DV in each governorate and in each year is significant, which governorates are similar in difference means of each DV, and whether these DVs vary. The main objectives were to determine the source of variances in DVs, collectively and separately, testing which governorates are similar and which diverge for each DV. The research design was time series and cross-sectional analysis. The main hypotheses are that IVs affect DVs collectively and separately. We carried out Multivariate and univariate analyses of variance to test these hypotheses. The population of 12 governorates in Jordan and the available data of 15 years (2000–2015) accrued from several Jordanian statistical yearbooks. We investigated the effect of two factors of governorate and year on the four DVs of divorce, mortality, unemployment, and crime. We used the rate of divorce, mortality, and crime, and the percentage of unemployment in the analyses. We transformed all DVs to multivariate normal distribution. We calculated descriptive statistics for each DV in each governorate and each year. We provided visual and numerical inspection of how each DV changed over time in each governorate compared with DV change in other governorates. Based on the multivariate analysis of variance, we found a significant effect in IVs on DVs with p < .001. Based on the univariate analysis, we found a significant effect of IVs on each DV with p < .001, except the effect of the year factor on unemployment, was not significant with p = .642. The grand and marginal means of each DV in each governorate and each year were significant based on a 95% confidence interval. Most governorates are not similar in DVs with p < .001. We concluded that the two factors produce significant effects on DVs, collectively and separately. Based on these findings, the government can distribute its financial and physical resources to governorates more efficiently. By identifying the sources of variance that contribute to the variation in DVs, insights can help inform focused variation prevention efforts.

Node location is one of the most important problems to be solved in practical application of WSN. As a typical location algorithm without ranging, DV-Hop is widely used in node localization of wireless sensor networks. However, in the third phase of DV-Hop, a least square method is used to solve the nonlinear equations. Using this method to locate the unknown nodes will produce large coordinate errors, poor stability of positioning accuracy, low location coverage, and high energy consumption. An improved localization algorithm based on hybrid chaotic strategy (MGDV-Hop) is proposed in this paper. Firstly, a glowworm swarm optimization of hybrid chaotic strategy based on chaotic mutation and chaotic inertial weight updating (MC-GSO) is proposed. The MC-GSO algorithm is used to control the moving distance of each firefly by chaos mutation and chaotic inertial weight when the firefly falls into a local optimum. The experimental results show that MC-GSO has better convergence and higher accuracy and avoids the premature convergence. Then, MC-GSO is used to replace the least square method in estimating node coordinates to solve the problem that the localization accuracy of the DV-Hop algorithm is not high. By establishing the error fitness function, the linear solution of coordinates is transformed into a two-dimensional combinatorial optimization problem. The simulation results and analysis confirm that the improved algorithm (MGDV-Hop) reduces the average location error, increases the location coverage, and decreases and balances the energy consumption as compared to DV-Hop and the location algorithm based on classical GSO (GSDV-Hop).

Wide-bandgap technology evolution compels the advancement of efficient pulse-width gate-driver devices. Integrated enhanced gate-driver planar transformers are a source of electromagnetic disturbances due to inter-winding capacitances, which serve as a route to common-mode(CM) currents. This paper will simulate, via ANSYS Q3D Extractor, the unforeseen parasitic effects of a pulse planar transformer integrated in a SiC MOSFET gate-driver card. Moreover, the pulse transformer will be ameliorated by adding distinctive shielding layers aiming to suppress CM noise effects and endure high dv/dt occurrences intending to validate experimental tests. The correlation between stray capacitance and dv/dt immunity results after shielding insertion will be reported.

Al giorno d'oggi il consumo mondiale di energia elettrica è in continuo aumento e più della metà dell'elettricità prodotta è consumata dai motori elettrici. Per far fronte a questo aumento, l'uso di motori a velocità variabile è fortemente incentivato nella gran parte dei paesi dalle normative sull'efficienza energetica. Questi motori sono in grado di consumare solo la quantità di elettricità necessaria. Questo è possibile grazie all’inverterizzazione: i motori a velocità variabile sono pilotati da switch di potenza collegati nella configurazione inverter-leg. Per fornire la corrente richiesta dal motore, gli switch di potenza vengono accesi e spenti alternativamente dal gate driver per generare un segnale modulato ad ampiezza di impulso nei nodi di fase del motore. I gate driver sono generalmente progettati per avere un singolo livello di corrente di uscita che viene utilizzato per caricare/scaricare le capacità parassite sulla gate dei power switch per accenderli/spegnerli. Un sistema di questo genere è molto efficiente, ma la dissipazione, anche se piccola, è sempre da considerare. Negli ultimi anni, la tecnologia superjunction (SJ) ha rivoluzionato l'industria dei dispositivi di potenza ad alta tensione migliorando il rapporto prestazioni/costi della conversione di potenza. I dispositivi SJ sono in grado di superare il Silicon Limit: il tradeoff tra tensione di breakdown e resistenza di stato on. Tuttavia, sono caratterizzati da una capacità di Miller non lineare, che fa sì che l'evento di switching inizi con dV/dt molto elevati e termini con un lunga slow-tail nelle ultime decine di volt. In un gate driver standard, il valore della corrente di gate io+ viene scelto come compromesso tra due vincoli opposti: limitare la dissipazione di potenza con un dV/dt veloce e soddisfare i vincoli di emissione condotta e radiata con un dV/dt lento. Con i dispositivi SJ non è quindi possibile usare un valore fisso di io+. Per usare i power switch in modo efficiente, viene presentato un sistema di controllo in grado di autoregolare la pendenza dV/dt, e di eliminare la slow-tail finale. Lo scopo di questo progetto di dottorato è quello di proporre una soluzione semplice ad anello chiuso dove non sia richiesta una grande larghezza di banda nè siano coinvolti elementi discreti e le non linearità dei power switch siano compensate. Si può ottenere in questo modo un dV/dt controllato che riduca la dissipazione e rispetti i vincoli di emissione condotta e radiata. Per fare ciò, come elemento di sensing viene utilizzata una capacità lineare integrata ad alta tensione collegata tra il low side e l'high side del gate driver. La corrente richiesta dalla carica e scarica di questa capacità durante l'evento di commutazione è proporzionale alla pendenza dV/dt. La corrente di gate viene quindi modificata di ciclo in ciclo in base alla pendenza rilevata per raggiungere il valore target di io+ richiesto dall'applicazione e viene forzata in tempo reale a un valore molto alto per eliminare la slow-tail negli ultimi volt. Sono stati prodotti due prototipi. Un primo chip di prova per convalidare il circuito di sensing e dimostrare l'efficacia dell'idea alla base. I risultati di misura si sono rivelati promettenti: la maggior parte del circuito ha funzionato come previsto. Per questo motivo è stato prodotto un secondo chip integrando il sensore in un gate driver con alcune piccole modifiche per migliorarne le prestazioni e per correggere alcuni difetti minori rilevati con la valutazione a banco del primo silicio. I risultati di misura relativi a questo secondo silicio hanno confermato l'efficacia della soluzione ad anello chiuso proposta, anche se prima di poter essere ampiamente utilizzato, il dispositivo necessiterà di ulteriori sviluppi e validazioni. I dettagli del progetto del circuito e la valutazione completa della misura di entrambi i prototipi saranno ampiamente discussi nel corso di questa tesi di dottorato.
Nowadays the world consumption of electrical energy is continuously increasing. More than an half of the produced electricity is consumed by electric motors. In order to cope with the increase in electricity consumption, the use of variable speed motor drives is promoted by energy efficiency regulations in most countries. These motors are able to consume only as much electricity as the application actually needs. They can do this by exploiting inverterization: variable speed drive motors are driven by power semiconductor switches connected in the inverter-leg configuration. They are alternatively switched on and off by the gate driver to generate a pulse width modulated signal on motor phase nodes used to provide the required current to the load. High voltage gate drivers are usually designed to have one single output current level used to charge/discharge the parasitic gate of external power switches to turn them on and off. Driving with a switching system is very efficient, but the dissipation, even if small, is always present and must be taken into account. In recent years, superjunction (SJ) technology has revolutionized the industry of high voltage power devices significantly improving the overall performance/cost ratio of power conversion. SJ devices are able to overcome the trade-off between breakdown voltage and on resistance, better known as the Silicon Limit. However, they are characterized by a non linear Miller capacitance, which causes the switching speed transient to start with very high dV/dt and to finish with a long slow-tail in the last few volts. In standard gate driver, the io+ driving capability is selected to find the best compromise between two opposite constraints: limiting the power dissipation with a fast dV/dt while satisfying conducted and radiated emission constraints with a slow dV/dt. With SJ devices it is not possible to meet this trade-off by simply selecting a fixed io+ value. To drive power switches with high efficiency a new driving strategy to make the whole system working in the optimum self-adjusting operating point for the fast dV/dt portion and to avoid the final slow-tail is presented. The aim of this PhD project is to propose a simple closed-loop solution where no large bandwidth neither discrete elements are required and the non-linearities of the power switching devices are compensated. In this way a controlled dV/dt transient can be achieved optimizing the trade-off between switching losses and conducted and radiated emission constraints. To do so, a linear integrated HV capacitor connected between the low side and the floating high side of the gate driver is used as sensing element. The current required by the charging and discharging of this capacitor during the active switching event is proportional to the dV/dt slope. The gate current is then changed cycle-by-cycle accordingly to the slope detected to reach the target io+ value needed by the power switches and forced in real-time to a very high value to cancel the slow-tail effect. Two silicon were taped-out. A first test chip to validate the sensing circuit and to prove the effectiveness of the core idea. The measurements were very promising: most of the circuit worked as expected. For this reason, a second tape-out was made integrating the sensor in a gate driver environment with some minor modifications to improve the performance and to fix some minor bugs detected with the bench evaluation of the first silicon. The measurements related to the second silicon confirmed the effectiveness of the proposed driving technique for hard-switching inverters stages, even though the device needs further development and validation before it can be widely employed. The details of the circuit design and the complete measurement evaluation of both the two test chips will be deeply discussed in the PhD thesis.

This work investigates the voltage scaling feasibility of several low voltage SiC MOSFET modules operated as a single series-connected switch using active gate control. Both multilevel and two-level topologies are capable of achieving higher blocking voltages in high-power converter applications. Compared to multilevel topologies, two-level switching topologies are of interest due to less complex circuitry, higher density, and simpler control techniques. In this work, to balance the voltage between series-connected MOSFETs, device turn-off speeds are dynamically controlled on active gate-drivers using active gate control. The implementation of the active gate control technique (specifically, turn-off dv/dt control) is described in this thesis. Experimental results of the voltage balancing behavior across eight 1.7 kV rated SiC MOSFET devices in series (6 kV total dc bus voltage) with the selected active dv/dt control scheme are demonstrated. Finally, the voltage balancing performance and switching behavior of series-connected SiC MOSFET devices are discussed.
Master of Science
According to ABB, 40% of the world's power demand is supplied by electrical energy. Specifically, in 2018, the world's electrical demand has grown by 4% since 2010. The growing need for electric energy makes it increasingly essential for systems that can efficiently and reliably convert and control energy levels for various end applications, such as electric motors, electric vehicles, data centers, and renewable energy systems. Power electronics are systems by which electrical energy is converted to different levels of power (voltage and current) depending on the end application. The use of power electronics systems is critical for controlling the flow of electrical energy in all applications of electric energy generation, transmission, and distribution. Advances in power electronics technologies, such as new control techniques and manufacturability of power semiconductor devices, are enabling improvements to the overall performance of electrical energy conversion systems. Power semiconductor devices, which are used as switches or rectifiers in various power electronic converters, are a critical building block of power electronic systems. In order to enable higher output power capability for converter systems, power semiconductor switches are required to sustain higher levels of voltage and current. Wide bandgap semiconductor devices are a particular new category of power semiconductors that have superior material properties compared to traditional devices such as Silicon (Si) Insulated-Gate Bipolar Junction Transistors (IGBTs). In particular, wide bandgap devices such as Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have better ruggedness and thermal capabilities. These properties provide wide bandgap semiconductor devices to operate at higher temperatures and switching frequencies, which is beneficial for maximizing the overall efficiency and volume of power electronic converters. This work investigates a method of scaling up voltage in particular for medium-voltage power conversion, which can be applied for a variety of application areas. SiC MOSFET devices are becoming more attractive for utilization in medium-voltage high-power converter systems due to the need to further improve the efficiency and density of these systems. Rather than using individual high voltage rated semiconductor devices, this thesis demonstrates the effectiveness of using several low voltage rated semiconductor devices connected in series in order to operate them as a single switch. Using low voltage devices as a single series-connected switch rather than a using single high voltage switch can lead to achieving a lower total on-state resistance, expectedly maximizing the overall efficiency of converter systems for which the series-connected semiconductor switches would be applied. In particular, this thesis focuses on the implementation of a newer approach of compensating for the natural unbalance in voltage between series-connected devices. An active gate control method is used for monitoring and regulating the switching speed of several devices operated in series in this work. The objective of this thesis is to investigate the feasibility of this method in order to achieve up to 6 kV total dc bus voltage using eight series-connected SiC MOSFET devices.

Esta tesis presenta un enfoque cuantitativo, explicativo y descriptivo, aporta un sistema de gestión de costos mediante la metodología del Resultado Operativo y las diferentes bondades que presenta para incrementar los niveles de control y planificación de obra. En el desarrollo de una obra existen diferentes factores que afectan a la utilidad planificada, como atrasos en el cronograma, derroche de insumos, compras excesivas y otros que a la larga pueden terminar con dicha utilidad. Por este motivo contar con un sistema de control se vuelve vital para ejecutar una obra. El objetivo de esta tesis fue implementar el método del Resultado Operativo a una obra civil, que permita tener en cuenta aquellos factores que afectan a la utilidad y así incrementar el control de la misma, por ello se presentó una base conceptual y el desarrollo de su metodología. La metodología propuesta permitió planificar las partidas según el cronograma de obra, optimizar los insumos, proyectar la utilidad a final de obra según Fases y Grupos de Control establecidos, orientar a tomar decisiones anticipadas y mejorar el control de la utilidad en el transcurso de obra. This thesis present a quantitative, explanatory and descriptive approach, with the aim to provide a management costs system by operating income methodology and its various benefits presented to increasing control levels and planning work. In developing a work there are different factors that affect the planned utility, as delays in the schedule, wasted inputs, excessive shopping and others who may eventually end up with this utility. Therefore having a control system becomes vital to perform any work, either smaller or larger work, requires a control. The objective of this thesis is to implement the operating result method to a civil work, to take account factors that affect the utility, in order to increase control of it, so a conceptual base and develop methodology are discussed. The proposed methodology allows scheduling the work’s steps to optimize inputs, and project the utility at the end of work according to Control Groups and Established Phases, in order to make advance decisions and improve the control of the utility in the work’s development.

Cardiovascular complications associated with elevated levels of glucose in the blood (Hyperglycemia, HG) is a growing health concern. HG is known to be associated with a variety of cardiovascular morbidities including higher incidence of electrical disturbances. Although effects of chronic HG have been widely investigated, electrophysiological effects of acute hyperglycemia are relatively less known. Further, hyperglycemic effects on adrenergic response is not widely investigated. We used excised ventricular tissues from mice to record trans-membrane potentials during a variety of pacing protocols to investigate cellular/tissue level electrophysiological effects of acute hyperglycemia and adrenergic stimulation (1µM Isoproterenol, a β-adrenergic agonist). A custom program was used to compute action potential durations (APD), maximal rates of depolarization (dv/dtmax), and action potential amplitudes (APA) from the recorded trans-membrane potentials. From these computed measures, electrical restitution and alternans threshold were quantified. Restitution was quantified using the Standard Protocol (SP; basic cycle length BCL= 200ms), Dynamic Protocol (DP; 200-40ms or until blockade) and a novel diastolic interval (DI) control protocol with Sinusoidal Changes in DI. Results from 6 mice show that acute hyperglycemia causes prolongation of the APD. Effects of adrenergic stimulation during acute hyperglycemia were partially blunted compared with non-hyperglycemic state, i.e. hyperglycemia minimized the decrease in APD that was produced by adrenergic stimulation. Similar, but less consistent (across animals) effects were seen in other electrophysiological parameters such as alternans threshold. These results show that acute hyperglycemia may itself alter cellular level electrophysiology of myocytes and importantly, modify adrenergic response. These results suggest that in addition to long term re-modeling that occurs in diabetes, acute changes in glucose levels also affect electrical function and further may contribute to systemically observed changes in diabetes by blunting adrenergic response. Therefore, further investigation into the electrophysiological effects of acute changes in glucose levels are warranted.

Abstract Scanning nonlinear dielectric microscopy is continuously developed as an AFM-derived method for 2D dopant profiling of semiconductor devices. In this paper, the authors apply 2D carrier density mapping to Si and SiC and succeed a high resolution observation of the SiC planar power MOSFET. Furthermore, they develop software that combines dC/dV and dC/dz images and expresses both density and polarity in a single distribution image. The discussion provides the details of AFM experiments that were conducted using a Hitachi environmental control AFM5300E system. The results indicated that the carrier density decreases in the boundary region between n plus source and p body. The authors conclude that although the resolutions of dC/dV and dC/dz are estimated to be 20 nm or less and 30 nm or less, respectively, there is a possibility that the resolution can be further improved by using a sharpened probe.

Accurate on-board capacity estimation is of critical importance in lithium-ion battery applications. Battery charging/discharging often occurs under a constant current load, and hence voltage vs. time measurements under this condition may be accessible in practice. This paper presents a novel diagnostic technique, Gaussian Process regression for In-situ Capacity Estimation (GP-ICE), which is capable of estimating the battery capacity using voltage vs. time measurements over short periods of galvanostatic operation. The approach uses Gaussian process regression to map from voltage values at a selection of uniformly distributed times, to cell capacity. Unlike previous works, GP-ICE does not rely on interpreting the voltage-time data through the lens of Incremental Capacity (IC) or Differential Voltage (DV) analysis. This overcomes both the need to differentiate the voltage-time data (a process which amplifies measurement noise), and the requirement that the range of voltage measurements encompasses the peaks in the IC/DV curves. Rather, GP-ICE gives insight into which portions of the voltage range are most informative about the capacity for a particular cell. We apply GP-ICE to a dataset of 8 cells, which were aged by repeated application of an ARTEMIS urban drive cycle. Within certain voltage ranges, as little as 10 seconds of charge data is sufficient to enable capacity estimates with ∼ 2% RMSE.