Journal articles on the topic 'Computers – Circuits – Performance'
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1
Blume-Kohout, Robin, and Kevin C. Young. "A volumetric framework for quantum computer benchmarks." Quantum 4 (November 15, 2020): 362. http://dx.doi.org/10.22331/q-2020-11-15-362.
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We propose a very large family of benchmarks for probing the performance of quantum computers. We call them volumetric benchmarks (VBs) because they generalize IBM's benchmark for measuring quantum volume \cite{Cross18}. The quantum volume benchmark defines a family of square circuits whose depth d and width w are the same. A volumetric benchmark defines a family of rectangular quantum circuits, for which d and w are uncoupled to allow the study of time/space performance trade-offs. Each VB defines a mapping from circuit shapes — (w,d) pairs — to test suites C(w,d). A test suite is an ensemble of test circuits that share a common structure. The test suite C for a given circuit shape may be a single circuit C, a specific list of circuits {C1…CN} that must all be run, or a large set of possible circuits equipped with a distribution Pr(C). The circuits in a given VB share a structure, which is limited only by designers' creativity. We list some known benchmarks, and other circuit families, that fit into the VB framework: several families of random circuits, periodic circuits, and algorithm-inspired circuits. The last ingredient defining a benchmark is a success criterion that defines when a processor is judged to have ``passed'' a given test circuit. We discuss several options. Benchmark data can be analyzed in many ways to extract many properties, but we propose a simple, universal graphical summary of results that illustrates the Pareto frontier of the d vs w trade-off for the processor being benchmarked.
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Childs, Andrew M., Dmitri Maslov, Yunseong Nam, Neil J. Ross, and Yuan Su. "Toward the first quantum simulation with quantum speedup." Proceedings of the National Academy of Sciences 115, no. 38 (September 6, 2018): 9456–61. http://dx.doi.org/10.1073/pnas.1801723115.
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With quantum computers of significant size now on the horizon, we should understand how to best exploit their initially limited abilities. To this end, we aim to identify a practical problem that is beyond the reach of current classical computers, but that requires the fewest resources for a quantum computer. We consider quantum simulation of spin systems, which could be applied to understand condensed matter phenomena. We synthesize explicit circuits for three leading quantum simulation algorithms, using diverse techniques to tighten error bounds and optimize circuit implementations. Quantum signal processing appears to be preferred among algorithms with rigorous performance guarantees, whereas higher-order product formulas prevail if empirical error estimates suffice. Our circuits are orders of magnitude smaller than those for the simplest classically infeasible instances of factoring and quantum chemistry, bringing practical quantum computation closer to reality.
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Fan, Yi, Jie Liu, Xiongzhi Zeng, Zhiqian Xu, Honghui Shang, Zhenyu Li, and Jinlong Yang. "Q<sup>2</sup>Chemistry: A quantum computation platform for quantum chemistry." JUSTC 52, no. 12 (2022): 2. http://dx.doi.org/10.52396/justc-2022-0118.
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Quantum computers provide new opportunities for quantum chemistry. In this article,we present a versatile, extensible, and efficient software package, named Q<sup>2</sup>Chemistry, for developing quantum algorithms and quantum inspired classical algorithms in the field of quantum chemistry. In Q<sup>2</sup>Chemistry, the wave function and Hamiltonian can be conveniently mapped into the qubit space, then quantum circuits can be generated corresponding to a specific quantum algorithm already implemented in the package or newly developed by the users. The generated circuits can be dispatched to either a physical quantum computer, if available, or to the internal virtual quantum computer realized by simulating quantum circuits on classical computers. As demonstrated by our benchmark simulations, Q<sup>2</sup>Chemistry achieves excellent performance in simulating medium scale quantum circuits using the matrix product state algorithm. Applications of Q<sup>2</sup>Chemistry to simulate molecules and periodic systems are given with performance analysis.
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Stamatopoulos, Nikitas, Daniel J. Egger, Yue Sun, Christa Zoufal, Raban Iten, Ning Shen, and Stefan Woerner. "Option Pricing using Quantum Computers." Quantum 4 (July 6, 2020): 291. http://dx.doi.org/10.22331/q-2020-07-06-291.
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We present a methodology to price options and portfolios of options on a gate-based quantum computer using amplitude estimation, an algorithm which provides a quadratic speedup compared to classical Monte Carlo methods. The options that we cover include vanilla options, multi-asset options and path-dependent options such as barrier options. We put an emphasis on the implementation of the quantum circuits required to build the input states and operators needed by amplitude estimation to price the different option types. Additionally, we show simulation results to highlight how the circuits that we implement price the different option contracts. Finally, we examine the performance of option pricing circuits on quantum hardware using the IBM Q Tokyo quantum device. We employ a simple, yet effective, error mitigation scheme that allows us to significantly reduce the errors arising from noisy two-qubit gates.
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Czarnik, Piotr, Andrew Arrasmith, Patrick J. Coles, and Lukasz Cincio. "Error mitigation with Clifford quantum-circuit data." Quantum 5 (November 26, 2021): 592. http://dx.doi.org/10.22331/q-2021-11-26-592.
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Achieving near-term quantum advantage will require accurate estimation of quantum observables despite significant hardware noise. For this purpose, we propose a novel, scalable error-mitigation method that applies to gate-based quantum computers. The method generates training data {Xinoisy,Xiexact} via quantum circuits composed largely of Clifford gates, which can be efficiently simulated classically, where Xinoisy and Xiexact are noisy and noiseless observables respectively. Fitting a linear ansatz to this data then allows for the prediction of noise-free observables for arbitrary circuits. We analyze the performance of our method versus the number of qubits, circuit depth, and number of non-Clifford gates. We obtain an order-of-magnitude error reduction for a ground-state energy problem on 16 qubits in an IBMQ quantum computer and on a 64-qubit noisy simulator.
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Liu, Xiaonan, Ming He, Junchao Wang, Haoshan Xie, and Chenyan Zhao. "Automated Quantum Volume Test." Journal of Physics: Conference Series 2221, no. 1 (May 1, 2022): 012029. http://dx.doi.org/10.1088/1742-6596/2221/1/012029.
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Abstract As a benchmark for the overall performance of quantum computers, quantum volume has the advantage of being able to reflect the depth of running quantum circuits. But, the quantum volume test code provided by IBM needs to be executed manually, and the simulation result of the quantum simulator is used as the result of the volume test, so that users cannot quickly and accurately test the quantum volume of the actual quantum computer required. In response to this problem, this paper designs an automated quantum volume test program. The program automatically generates quantum volume sequences, selects the number of executions of quantum circuits, and defines real quantum computers to facilitate users to perform quantum volume tests on quantum computers provided by the IBM Quantum Cloud Platform. Simultaneously, according to the automated test program, the quantum volume of IBM’s four small superconducting quantum computers was tested. The test results show that (1) the quantum computer is different, and the qubit layout and execution times ntrials are the same, will cause the quantum volume is uncertain; (2) the same quantum computer, whether ntrials is the same, the robustness of qubit coupling will be affected to a certain extent.
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Aaron D’costa, Mr, Dr Abdul Razak, and Dr Shazia Hasan. "Analysis and comparison of fast multiplier circuits based on different parameters." International Journal of Engineering & Technology 7, no. 3 (June 26, 2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.
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Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so as to reduce the delay of whole circuit. The main purpose is to deal with high speed and lower power consumption even after decreasing the silicon area. This makes them well-suited for numerous complex and convenient VLSI circuit implementations. The fact however, remains that area and speed are two contradictory performance restrictions. Hence, increase in speed always results in the use of more and complex hardware. Different arithmetic techniques can be used to implement different multiplier circuits. The focus of this paper is to implement various multiplier circuit and compare them. The timing signals can be observed using software such as Modelsim and Xilinx.
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Song, Gyeongju, Kyungbae Jang, Hyunji Kim, and Hwajeong Seo. "A Parallel Quantum Circuit Implementations of LSH Hash Function for Use with Grover’s Algorithm." Applied Sciences 12, no. 21 (October 27, 2022): 10891. http://dx.doi.org/10.3390/app122110891.
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Grover’s search algorithm accelerates the key search on the symmetric key cipher and the pre-image attack on the hash function. To conduct Grover’s search algorithm, the target cipher algorithm should be efficiently implemented in a quantum circuit. Currently, small quantum computers are difficult to operate with large quantum circuits due to limited performance. Therefore, if a large quantum computer that can operate Grover’s algorithm appears, it is expected that a cipher attack will be possible. In this paper, we propose a parallel structure quantum circuit for the Korean hash function standard (i.e., LSH). The proposed quantum circuit designed a parallel operation structure for the message expansion (i.e., MsgExp) function and the mix function, which are the internal structures of the LSH hash function. This approach shows an efficient result for quantum circuit implementation in terms of quantum resources by reducing the depth of the quantum circuit by about 96% through the trade-off of appropriate quantum resources compared to previous work. This result can be a reference for the implementation of a parallel quantum circuit in the future and is expected to advance the attack timing of the search algorithm for Grover’s LSH hash function.
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Bravyi, Sergey, Dan Browne, Padraic Calpin, Earl Campbell, David Gosset, and Mark Howard. "Simulation of quantum circuits by low-rank stabilizer decompositions." Quantum 3 (September 2, 2019): 181. http://dx.doi.org/10.22331/q-2019-09-02-181.
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Recent work has explored using the stabilizer formalism to classically simulate quantum circuits containing a few non-Clifford gates. The computational cost of such methods is directly related to the notion of stabilizerrank, which for a pure state ψ is defined to be the smallest integer χ such that ψ is a superposition of χ stabilizer states. Here we develop a comprehensive mathematical theory of the stabilizer rank and the related approximate stabilizer rank. We also present a suite of classical simulation algorithms with broader applicability and significantly improved performance over the previous state-of-the-art. A new feature is the capability to simulate circuits composed of Clifford gates and arbitrary diagonal gates, extending the reach of a previous algorithm specialized to the Clifford+T gate set. We implemented the new simulation methods and used them to simulate quantum algorithms with 40-50 qubits and over 60 non-Clifford gates, without resorting to high-performance computers. We report a simulation of the Quantum Approximate Optimization Algorithm in which we process superpositions of χ∼106 stabilizer states and sample from the full n-bit output distribution, improving on previous simulations which used ∼103 stabilizer states and sampled only from single-qubit marginals. We also simulated instances of the Hidden Shift algorithm with circuits including up to 64 T gates or 16 CCZ gates; these simulations showcase the performance gains available by optimizing the decomposition of a circuit's non-Clifford components.
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Ou, Qiao-Feng, Bang-Shu Xiong, Lei Yu, Jing Wen, Lei Wang, and Yi Tong. "In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory." Materials 13, no. 16 (August 10, 2020): 3532. http://dx.doi.org/10.3390/ma13163532.
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Recent progress in the development of artificial intelligence technologies, aided by deep learning algorithms, has led to an unprecedented revolution in neuromorphic circuits, bringing us ever closer to brain-like computers. However, the vast majority of advanced algorithms still have to run on conventional computers. Thus, their capacities are limited by what is known as the von-Neumann bottleneck, where the central processing unit for data computation and the main memory for data storage are separated. Emerging forms of non-volatile random access memory, such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory, and resistive random access memory, are widely considered to offer the best prospect of circumventing the von-Neumann bottleneck. This is due to their ability to merge storage and computational operations, such as Boolean logic. This paper reviews the most common kinds of non-volatile random access memory and their physical principles, together with their relative pros and cons when compared with conventional CMOS-based circuits (Complementary Metal Oxide Semiconductor). Their potential application to Boolean logic computation is then considered in terms of their working mechanism, circuit design and performance metrics. The paper concludes by envisaging the prospects offered by non-volatile devices for future brain-inspired and neuromorphic computation.
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Kumrey, G. R., and S. K. Mahobia. "STUDY AND PERFORMANCE TESTING OF TRANSISTOR WITH COMMON EMITTER AMPLIFIER CIRCUIT." International Journal of Research -GRANTHAALAYAH 4, no. 8 (August 31, 2016): 100–103. http://dx.doi.org/10.29121/granthaalayah.v4.i8.2016.2567.
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The transistor has ranking in 20th century technology. It is finding the application in all electronic devices as radios, computers. Integrated circuits are containing various transistors, which are made by silicon. The transistors are used to handle large current and/or large voltages. As example, the final audio stage in the stereo system used a power transistors amplifier to drive the various speakers. Transistors are device, which are utilizes a change in current to produce a large change in voltage, current, or power.
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Kulkarni, Jayshri Sharad. "An ultra-thin, dual band, Sub 6 GHz, 5G and WLAN antenna for next generation laptop computers." Circuit World 46, no. 4 (April 18, 2020): 363–70. http://dx.doi.org/10.1108/cw-07-2019-0076.
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Purpose The purpose of this manuscript is to present a novel, compact and ultra-thin “3”-shaped monopole antenna for wireless operations in the laptop computer. The thickness of the antenna is only 0.2 mm and is designed using only a pure copper strip of size 17.5 × 6 mm2. Design/methodology/approach The simple structure of the proposed antenna consists of two monopole radiating strips, namely, AC and CD and an open-ended rectangular tuning stub BE of length 9mm. Findings This structure inspires two resonating modes at 3.45 and 5.5 GHz and achieves the measured impedance band width as 20% (3.21-3.91) GHz in lower band (F_l) and 15% (5.05-5.85) GHz in the upper band (F_u) for voltage standing wave ratio < 2. These two bands cover 5GHz wireless local area network (WLAN) and 3.3-3.6GHz (sub 6GHz) 5G bands. The measured radiation performance including, nearly omnidirectional radiation patterns, a stable gain of around 5 dBi and excellent efficiency around 90% in both operating bands have been achieved. Furthermore, a simplified equivalent circuit model has been derived and its simulation is performed. The simulated and measured results are in good agreement, which demonstrates the applicability of the antenna structure for WiMAX/WLAN operations in the prominent ultra-thin laptop computers. Originality/value The proposed antenna is designed without using any reactive elements, vias or matching circuits for excitation of WLAN and 5G bands in the laptop computers. The design also does not require any additional ground for mounting the antenna. The proposed antenna has a very low profile, is ultra-thin, cost-effective, easy to manufacture and can be easily embedded inside next generation laptop computers.
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Chen, Wenbin. "Characterization of new materials for capacitor formation in integrated circuit technology." Boolean: Snapshots of Doctoral Research at University College Cork, no. 2010 (January 1, 2010): 26–31. http://dx.doi.org/10.33178/boolean.2010.7.
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There have been tremendous developments in electronic technology in the last 40 years as evidenced by the widespread availability of computers, mobile phones and electronic entertainment systems and their continued shrinking in size and cost. Much of the improvement in the performance of electronic systems can be traced to developments in Integrated Circuits (ICs) (“microchips”) which form the fundamental building blocks of modern electronics technology. Within an IC, the most important electronic component is the transistor and it is the transistor that is used to implement the operations associated with computer logic. With each generation of technology, the size of the transistors is reduced and more of them can fit on a single IC, which allows more powerful devices to be made that take up the same or even smaller space and draw less power from the battery. This trend regarding the scaling down in size of the transistors was ...
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Ardelean, Sebastian Mihai, and Mihai Udrescu. "Graph coloring using the reduced quantum genetic algorithm." PeerJ Computer Science 7 (January 3, 2022): e836. http://dx.doi.org/10.7717/peerj-cs.836.
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Genetic algorithms (GA) are computational methods for solving optimization problems inspired by natural selection. Because we can simulate the quantum circuits that implement GA in different highly configurable noise models and even run GA on actual quantum computers, we can analyze this class of heuristic methods in the quantum context for NP-hard problems. This paper proposes an instantiation of the Reduced Quantum Genetic Algorithm (RQGA) that solves the NP-hard graph coloring problem in O(N1/2). The proposed implementation solves both vertex and edge coloring and can also determine the chromatic number (i.e., the minimum number of colors required to color the graph). We examine the results, analyze the algorithm convergence, and measure the algorithm's performance using the Qiskit simulation environment. Our Reduced Quantum Genetic Algorithm (RQGA) circuit implementation and the graph coloring results show that quantum heuristics can tackle complex computational problems more efficiently than their conventional counterparts.
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Ismailov, T. A., H. M. Gadjiev, and A. M. Ibragimova. "Power-effective thermoelectric semiconductor heat rejection for computer processors." Herald of Dagestan State Technical University. Technical Sciences 47, no. 3 (October 1, 2020): 8–15. http://dx.doi.org/10.21822/2073-6185-2020-47-3-8-15.
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Objective. The article deals with heat removal from computer processors in order to provide the necessary thermal conditions and temperature control of heat-generating components on integrated circuits. Methods. Methods for modeling heat exchange processes during heat transfer from a heated integral crystal to the environment are applied. Results. The power efficiency of heat rejection processors increases when using radiating thermoelectric semiconductor devices since heat is absorbed in some junctions, and instead of generating heat photons of the ultraviolet range are emitted to obtain better energy characteristics to ensure the necessary power removal from the heatgenerating components of radio-electronic circuits. This approach has a significant advantage as radiation has the maximum speed when transferring energy compared to convection and conduction, which allows for non-inertial heat removal from heat-generating components to the environment. This approach also allows increasing the efficiency of the cooling system and accelerating the transfer of heat from the heated areas to prevent heat breakdown. Conclusion. The conducted research allows concluding that light-emitting thermoelectric semiconductor devices can be used for cooling with high power efficiency, which can transfer large amounts of power to the environment with low inertia. An innovative cooling system for computer processors allows increasing the degree of integration by several orders of magnitude, which will increase the performance of computers and their speed.
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Datta, Suman, Wriddhi Chakraborty, and Marko Radosavljevic. "Toward attojoule switching energy in logic transistors." Science 378, no. 6621 (November 18, 2022): 733–40. http://dx.doi.org/10.1126/science.ade7656.
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Advances in the theory of semiconductors in the 1930s in addition to the purification of germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in 1947 and initiated the era of semiconductor electronics. Gordon Moore postulated 18 years later that the number of components in an integrated circuit would double every 1 to 2 years with associated reductions in cost per transistor. Transistor density doubling through scaling—the decrease of component sizes—with each new process node continues today, albeit at a slower pace compared with historical rates of scaling. Transistor scaling has resulted in exponential gain in performance and energy efficiency of integrated circuits, which transformed computing from mainframes to personal computers and from mobile computing to cloud computing. Innovations in new materials, transistor structures, and lithographic technologies will enable further scaling. Monolithic 3D integration, design technology co-optimization, alternative switching mechanisms, and cryogenic operation could enable further transistor scaling and improved energy efficiency in the foreseeable future.
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Baldwin, Charles H., Karl Mayer, Natalie C. Brown, Ciarán Ryan-Anderson, and David Hayes. "Re-examining the quantum volume test: Ideal distributions, compiler optimizations, confidence intervals, and scalable resource estimations." Quantum 6 (May 9, 2022): 707. http://dx.doi.org/10.22331/q-2022-05-09-707.
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The quantum volume test is a full-system benchmark for quantum computers that is sensitive to qubit number, fidelity, connectivity, and other quantities believed to be important in building useful devices. The test was designed to produce a single-number measure of a quantum computer's general capability, but a complete understanding of its limitations and operational meaning is still missing. We explore the quantum volume test to better understand its design aspects, sensitivity to errors, passing criteria, and what passing implies about a quantum computer. We elucidate some transient behaviors the test exhibits for small qubit number including the ideal measurement output distributions and the efficacy of common compiler optimizations. We then present an efficient algorithm for estimating the expected heavy output probability under different error models and compiler optimization options, which predicts performance goals for future systems. Additionally, we explore the original confidence interval construction and show that it underachieves the desired coverage level for single shot experiments and overachieves for more typical number of shots. We propose a new confidence interval construction that reaches the specified coverage for typical number of shots and is more efficient in the number of circuits needed to pass the test. We demonstrate these savings with a QV=210 experimental dataset collected from Quantinuum System Model H1-1. Finally, we discuss what the quantum volume test implies about a quantum computer's practical or operational abilities especially in terms of quantum error correction.
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Rosenberg, Eliott, Paul Ginsparg, and Peter L. McMahon. "Experimental error mitigation using linear rescaling for variational quantum eigensolving with up to 20 qubits." Quantum Science and Technology 7, no. 1 (January 1, 2022): 015024. http://dx.doi.org/10.1088/2058-9565/ac3b37.
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Abstract Quantum computers have the potential to help solve a range of physics and chemistry problems, but noise in quantum hardware currently limits our ability to obtain accurate results from the execution of quantum-simulation algorithms. Various methods have been proposed to mitigate the impact of noise on variational algorithms, including several that model the noise as damping expectation values of observables. In this work, we benchmark various methods, including a new method proposed here. We compare their performance in estimating the ground-state energies of several instances of the 1D mixed-field Ising model using the variational-quantum-eigensolver algorithm with up to 20 qubits on two of IBM’s quantum computers. We find that several error-mitigation techniques allow us to recover energies to within 10% of the true values for circuits containing up to about 25 ansatz layers, where each layer consists of CNOT gates between all neighboring qubits and Y-rotations on all qubits.
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Chen, Wenhan, Haodi Tang, Yu Wang, Xianwu Hu, Yuming Lin, Tai Min, and Yufeng Xie. "E-Spin: A Stochastic Ising Spin Based on Electrically-Controlled MTJ for Constructing Large-Scale Ising Annealing Systems." Micromachines 14, no. 2 (January 19, 2023): 258. http://dx.doi.org/10.3390/mi14020258.
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With its unique computer paradigm, the Ising annealing machine has become an emerging research direction. The Ising annealing system is highly effective at addressing combinatorial optimization (CO) problems that are difficult for conventional computers to tackle. However, Ising spins, which comprise the Ising system, are difficult to implement in high-performance physical circuits. We propose a novel type of Ising spin based on an electrically-controlled magnetic tunnel junction (MTJ). Electrical operation imparts true randomness, great stability, precise control, compact size, and easy integration to the MTJ-based spin. In addition, simulations demonstrate that the frequency of electrically-controlled stochastic Ising spin (E-spin) is 50 times that of the thermal disturbance MTJ-based spin (p-bit). To develop a large-scale Ising annealing system, up to 64 E-spins are implemented. Our Ising annealing system demonstrates factorization of integers up to 264 with a temporal complexity of around O(n). The proposed E-spin shows superiority in constructing large-scale Ising annealing systems and solving CO problems.
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Simoni, Mario, Giovanni Amedeo Cirillo, Giovanna Turvani, Mariagrazia Graziano, and Maurizio Zamboni. "Towards Compact Modeling of Noisy Quantum Computers: A Molecular-Spin-Qubit Case of Study." ACM Journal on Emerging Technologies in Computing Systems 18, no. 1 (January 31, 2022): 1–26. http://dx.doi.org/10.1145/3474223.
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Classical simulation of Noisy Intermediate Scale Quantum computers is a crucial task for testing the expected performance of real hardware. The standard approach, based on solving Schrödinger and Lindblad equations, is demanding when scaling the number of qubits in terms of both execution time and memory. In this article, attempts in defining compact models for the simulation of quantum hardware are proposed, ensuring results close to those obtained with standard formalism. Molecular Nuclear Magnetic Resonance quantum hardware is the target technology, where three non-ideality phenomena—common to other quantum technologies—are taken into account: decoherence, off-resonance qubit evolution, and undesired qubit-qubit residual interaction. A model for each non-ideality phenomenon is embedded into a MATLAB simulation infrastructure of noisy quantum computers. The accuracy of the models is tested on a benchmark of quantum circuits, in the expected operating ranges of quantum hardware. The corresponding outcomes are compared with those obtained via numeric integration of the Schrödinger equation and the Qiskit’s QASMSimulator. The achieved results give evidence that this work is a step forward towards the definition of compact models able to provide fast results close to those obtained with the traditional physical simulation strategies, thus paving the way for their integration into a classical simulator of quantum computers.
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Al-Tameemi, Saif, and Mohammed Nadhim Abbas. "All-Optical Universal Logic Gates at Nano-scale Dimensions." Iraqi Journal of Nanotechnology, no. 2 (December 7, 2021): 34–43. http://dx.doi.org/10.47758/ijn.vi2.49.
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Though photonics displays an attractive solution to the speed limitation of electronics, decreasing the size of photonic devices is one of the major problems with implementing photonic integrated circuits that are regarded the challenges to produce all-optical computers. Plasmonic can solve these problems, it be a potential solution to fill the gaps in the electronics (large bandwidth and ultra-high speed) and photonics (diffraction limit due to miniaturization size). In this paper, Nano-rings Insulator-Metal-Insulator (IMI) plasmonic waveguides has been used to propose, design, simulate, and perform all-optical universal logic gates (NOR and NAND gates). By using Finite Element Method (FEM), the structure of the proposed plasmonic universal logic gates are designed and numerically simulated by two dimensions (2-D) structure. Silver and Glass materials were chosen to construct proposed structure. The function of the proposed plasmonic NOR and NAND logic gates was achieved by destructive and constructive interferences principle. The performance of the proposed device is measured by three criteria; the transmission, extension ratio, and modulation depth. Numerical simulations show that a transmission threshold (0.3) which allows achieving the proposed plasmonic universal logic gates in one structure at 1550 nm operating wavelength. The properties of this devise was as follows: The transmission exceeds 100% in one state of NAND gate, medium values of Extension Ratio, very high MD values, and very small foot print. In the future, this device will be the access to the nanophotonic integrated circuits and it has regarded fundamental building blocks for all-optical computers.
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Josipović, Lana, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, and Jordi Cortadella. "Buffer Placement and Sizing for High-Performance Dataflow Circuits." ACM Transactions on Reconfigurable Technology and Systems 15, no. 1 (March 31, 2022): 1–32. http://dx.doi.org/10.1145/3477053.
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Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches), unpredictable memory dependencies, and irregular control flow. Dataflow circuits exhibit an unconventional property: registers (usually referred to as “buffers”) can be placed anywhere in the circuit without changing its semantics, in strong contrast to what happens in traditional datapaths. Yet, although functionally irrelevant, this placement has a significant impact on the circuit’s timing and throughput. In this work, we show how to strategically place buffers into a dataflow circuit to optimize its performance. Our approach extracts a set of choice-free critical loops from arbitrary dataflow circuits and relies on the theory of marked graphs to optimize the buffer placement and sizing. Our performance optimization model supports important high-level synthesis features such as pipelined computational units, units with variable latency and throughput, and if-conversion. We demonstrate the performance benefits of our approach on a set of dataflow circuits obtained from imperative code.
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Dhakal, Pashupati. "Superconducting Radio Frequency Resonators for Quantum Computing: A Short Review." Journal of Nepal Physical Society 7, no. 3 (December 31, 2021): 1–5. http://dx.doi.org/10.3126/jnphyssoc.v7i3.42179.
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Superconducting radiofrequency (SRF) technology is being used not only in discovery science programs and basic research but also for several applications that benefit society more directly. The advantage of superconducting resonators over those made of normal-conducting metal is their ability to store electromagnetic energy with much lower dissipation. The high-quality factor and longer dissipation time provided by these superconducting resonators can deliver superior performance. Currently, the quantum processing architecture uses resonators and interconnecting circuits operating in the microwave regime with superconducting strip-line technology and low noise electronic devices for switching and communication. The performance of these devices can be enhanced by embedding them in 3D SRF cavity resonators to prolong the coherence time, which improves the utility of the device by reducing error rates and allowing more manipulations (calculations) before the quantum state decays. Here, we present a short review of current microwave technology used in quantum computers and progress towards the 3D resonators to enhance thecoherence time.
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Zhang, Hai-Tian, Tae Joon Park, A. N. M. Nafiul Islam, Dat S. J. Tran, Sukriti Manna, Qi Wang, Sandip Mondal, et al. "Reconfigurable perovskite nickelate electronics for artificial intelligence." Science 375, no. 6580 (February 4, 2022): 533–39. http://dx.doi.org/10.1126/science.abj7943.
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Reconfigurable devices offer the ability to program electronic circuits on demand. In this work, we demonstrated on-demand creation of artificial neurons, synapses, and memory capacitors in post-fabricated perovskite NdNiO 3 devices that can be simply reconfigured for a specific purpose by single-shot electric pulses. The sensitivity of electronic properties of perovskite nickelates to the local distribution of hydrogen ions enabled these results. With experimental data from our memory capacitors, simulation results of a reservoir computing framework showed excellent performance for tasks such as digit recognition and classification of electrocardiogram heartbeat activity. Using our reconfigurable artificial neurons and synapses, simulated dynamic networks outperformed static networks for incremental learning scenarios. The ability to fashion the building blocks of brain-inspired computers on demand opens up new directions in adaptive networks.
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KATZENELSON, JACOB, and ALEXANDER GOIKHMAN. "THE SUPERCOMPUTER TOOLKIT AND ITS APPLICATIONS." International Journal of High Speed Electronics and Systems 09, no. 03 (September 1998): 807–46. http://dx.doi.org/10.1142/s0129156498000336.
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The Supercomputer Toolkit is a family of hardware and software modules from which high-performance special-purpose computers for scientific/engineering use can be easily constructed and programmed. The hardware modules include processors, memory, I/O devices and communication devices. The software modules include an operating system, compilers, debuggers, simulators, scientific libraries, and high-level front ends. When faced with a suitable problem, the engineer/scientist connects the modules by means of static-interconnect technology and constructs a problem-specific parallel computation network. The network is loaded from a workstation that serves as a host. When the program is run, results are collected and displayed by the host. The host handles files, does compilation, etc. The computation network, the Toolkit, does the heavy computation. In addition to high performance, the advantage of the Toolkit is its low cost which makes it potentially affordable by small groups as their main number crunching computer. This paper is concerned with the Toolkit version built at the Technion, which is a second generation of the MIT version.1 The paper briefly describes the hardware and software of this new version and its application to elastic-plastic flow, weather prediction and the simulation of electronic circuits. The main topic of the application section is the relation between the Toolkit configuration and the computation structure of these applications. The paper discusses conclusions related to the hardware and software as well as to the techniques for applying the system.
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Fahim, Samuel R., Hany M. Hasanien, Rania A. Turky, Shady H. E. Abdel Aleem, and Martin Ćalasan. "A Comprehensive Review of Photovoltaic Modules Models and Algorithms Used in Parameter Extraction." Energies 15, no. 23 (November 25, 2022): 8941. http://dx.doi.org/10.3390/en15238941.
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Currently, solar energy is one of the leading renewable energy sources that help support energy transition into decarbonized energy systems for a safer future. This work provides a comprehensive review of mathematical modeling used to simulate the performance of photovoltaic (PV) modules. The meteorological parameters that influence the performance of PV modules are also presented. Various deterministic and probabilistic mathematical modeling methodologies have been investigated. Moreover, the metaheuristic methods used in the parameter extraction of diode models of the PV equivalent circuits are addressed in this article to encourage the adoption of algorithms that can predict the parameters with the highest precision possible. With the significant increase in the computational power of workstations and personal computers, soft computing algorithms are expected to attract more attention and dominate other algorithms. The different error expressions used in formulating objective functions that are employed in extracting the parameters of PV models are comprehensively expressed. Finally, this work aims to develop a comprehensive layout for the previous, current, and possible future areas of PV module modeling.
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Miháliková, Ivana, Martin Friák, Matej Pivoluska, Martin Plesch, Martin Saip, and Mojmír Šob. "Best-Practice Aspects of Quantum-Computer Calculations: A Case Study of the Hydrogen Molecule." Molecules 27, no. 3 (January 18, 2022): 597. http://dx.doi.org/10.3390/molecules27030597.
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Quantum computers are reaching one crucial milestone after another. Motivated by their progress in quantum chemistry, we performed an extensive series of simulations of quantum-computer runs that were aimed at inspecting the best-practice aspects of these calculations. In order to compare the performance of different setups, the ground-state energy of the hydrogen molecule was chosen as a benchmark for which the exact solution exists in the literature. Applying the variational quantum eigensolver (VQE) to a qubit Hamiltonian obtained by the Bravyi–Kitaev transformation, we analyzed the impact of various computational technicalities. These included (i) the choice of the optimization methods, (ii) the architecture of the quantum circuits, as well as (iii) the different types of noise when simulating real quantum processors. On these, we eventually performed a series of experimental runs as a complement to our simulations. The simultaneous perturbation stochastic approximation (SPSA) and constrained optimization by linear approximation (COBYLA) optimization methods clearly outperformed the Nelder–Mead and Powell methods. The results obtained when using the Ry variational form were better than those obtained when the RyRz form was used. The choice of an optimum entangling layer was sensitively interlinked with the choice of the optimization method. The circular entangling layer was found to worsen the performance of the COBYLA method, while the full-entangling layer improved it. All four optimization methods sometimes led to an energy that corresponded to an excited state rather than the ground state. We also show that a similarity analysis of measured probabilities can provide a useful insight.
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Saxena, Vishal, Xinyu Wu, Ira Srivastava, and Kehan Zhu. "Towards Neuromorphic Learning Machines Using Emerging Memory Devices with Brain-Like Energy Efficiency." Journal of Low Power Electronics and Applications 8, no. 4 (October 2, 2018): 34. http://dx.doi.org/10.3390/jlpea8040034.
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The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e., on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this article, we review the challenges involved and present a pathway to realize large-scale mixed-signal NeuSoCs, from device arrays and circuits to spike-based deep learning algorithms with ‘brain-like’ energy-efficiency.
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Zhao, Rijing, Zengpeng Wang, Yu Sun, Fei Wang, and Dong Huang. "Effect of the Number of Circuits on a Finned-Tube Heat Exchanger Performance and Its Improvement by a Reversely Variable Circuitry." Applied Sciences 12, no. 18 (September 6, 2022): 8960. http://dx.doi.org/10.3390/app12188960.
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The finned-tube heat exchanger (FTHX) works better with more circuits as an evaporator but fewer as a condenser in air-source heat pumps (ASHPs). In this article, a reversely variable circuitry is proposed to address this contradiction. The effects of the circuit number on the performance of an outdoor FTHX in an ASHP prototype was first studied numerically using the EVAP-COND 4.0 software. We showed that the evaporator capacity reached its peak with four circuits, but the condenser capacity decreased monotonously as the circuit number increased. A reversely variable circuitry was obtained by combining distributors and check valves, so that the FTHX exhibited four circuits in the evaporator mode but one and a half (two circuits merging into one) in the condenser mode, thus better matching the respective requirements of the two modes. Comparative tests showed that in the ASHP, the reversely variable FTHX had a 6.1% higher cooling capacity than the four-circuit reversely fixed exchanger and a 3.9% higher heating capacity than the 1.5-circuit reversely fixed one. Therefore, the novel design of the FTHX enhanced both the heating and the cooling performance of the ASHP.
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YEO, KIAT-SENG, ZHI-HUI KONG, NUKALA NISHANT, HAITAO FU, and WEI ZENG. "INTEGRATED CIRCUIT DESIGN RESEARCH RANKING FOR WORLDWIDE UNIVERSITIES." Journal of Circuits, Systems and Computers 17, no. 01 (February 2008): 141–67. http://dx.doi.org/10.1142/s0218126608004204.
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The proliferation of integrated circuits (ICs) in the present technological era has brought forth revolutionary digital modernization that has ultimately transformed the history and lifestyle of humankind. ICs have become the heart of practically all state-of-the-art electronic devices such as computers, cell phones, video game consoles, and cameras. This ever-flourishing IC design industry is knowledge-intensive, which in turn translates into a huge appetite for technically precocious talents. Hence, in an effort to fuel and further foster the industry with more highly skilled manpower and at the same time to vie for a share of the burgeoning industry, higher educational institutions and universities from all around the globe are placing greater than ever emphasis on IC design research. Most importantly, strenuous efforts in a holistic manner are being made by each university in order to elicit outstanding and top-notch research in IC design. The authors have conducted a detailed and extensive survey to rank the various universities of the world in the field of IC design based on their research performance. In fact, assessments in the form of ranking have gained prominence over the recent years captivating the attention of a large number of students and universities. It helps the students in knowing how each university is progressing in a particular field and in turn helps the universities in analyzing their positions globally to remain competitive. Three ranking indicators, namely the Number of Publications, Citation Counts, and Cites per Paper have been chosen. The methodology used in ranking is also reported. The universities occupying the top echelons in IC design research are identified and a proven three-pronged approach for eliciting outstanding research performance is discussed.
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Moldovan, Emilia, Nazih Khaddaj Mallat, and Serioja Ovidiu Tatu. "MHMIC Six-port Interferometer for W-band Transceivers: Design and Characterization." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 4 (August 1, 2019): 2703. http://dx.doi.org/10.11591/ijece.v9i4.pp2703-2714.
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The study has presented an extensive analysis of an integrated millimeter wave six-port interferometer, operating over a 10 GHz band, from 80 to 90 GHz. It has covered both semi-unlicensed point-to-point links (81-86 GHz), and imaging sensor system frequencies (above 85 GHz). An in-house process is used to fabricate miniaturized hybrid millimeter wave integrated circuits on a very thin ceramic substrate. Two-port S-parameter measurements are performed on a minimum number of circuits integrated on the same die, exploiting the circuit’s physical symmetry and chosen to collect enough data for full-port characterization. Based on these measurements on an integrated prototype, a six-port circuit computer model implemented and advanced system simulations performed for circuit analysis. Interferometer performances evaluated using several methods: analysis of harmonic balance, qi points’, homodyne quadrature demodulation, and error vector modulation (EVM). The analysis showed that this circuit can directly perform, without any calibration, the demodulation of various PSK and QAM signals over the 10 GHz band, with very good results.
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Dong, Hui Fen, Qing Ji Gao, and Jian Shan Liu. "Analysis on Insulation Resistance Performance in Airport Lighting Circuit." Advanced Materials Research 668 (March 2013): 500–505. http://dx.doi.org/10.4028/www.scientific.net/amr.668.500.
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The airfield lighting circuits are the important part of the airfield lighting system, and the insulation performance of the circuits directly affects the aircraft flight safety. The side insulation performance of the lighting circuit and the effect of the temperature and humidity on the insulation are analyzed in the paper. Depending on the measure data provided by the Shanghai PUDONG international airport, the curve of circuit insulation resistance changed with the time is fitted through computer, and the insulation resistance mode based on the parameter identifying is obtained. The theoretical foundation is laid for the forecast decline of insulation resistance, and a theoretical basis is provided for the maintenance of the lighting circuit.
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Larrabee, Allan R. "The P4 Parallel Programming System, the Linda Environment, and Some Experiences with Parallel Computation." Scientific Programming 2, no. 3 (1993): 23–35. http://dx.doi.org/10.1155/1993/817634.
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The first digital computers consisted of a single processor acting on a single stream of data. In this so-called "von Neumann" architecture, computation speed is limited mainly by the time required to transfer data between the processor and memory. This limiting factor has been referred to as the "von Neumann bottleneck". The concern that the miniaturization of silicon-based integrated circuits will soon reach theoretical limits of size and gate times has led to increased interest in parallel architectures and also spurred research into alternatives to silicon-based implementations of processors. Meanwhile, sequential processors continue to be produced that have increased clock rates and an increase in memory locally available to a processor, and an increase in the rate at which data can be transferred to and from memories, networks, and remote storage. The efficiency of compilers and operating systems is also improving over time. Although such characteristics limit maximum performance, a large improvement in the speed of scientific computations can often be achieved by utilizing more efficient algorithms, particularly those that support parallel computation. This work discusses experiences with two tools for large grain (or "macro task") parallelism.
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Mourad, Samiha. "Computer-Aided Testing Systems: Evaluation and Benchmark Circuits." VLSI Design 1, no. 1 (January 1, 1993): 87–97. http://dx.doi.org/10.1155/1993/89495.
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As the demand on Computer-Aided Testing Systems (CATS)—Automatic Test Pattern Generation (ATPG) and logic and fault simulations as well as testability analysis—increases and the choice becomes more varied, a need to compare the merits of the different systems emerges. Benchmark circuits are used to carry out the comparisons.In this paper, criteria for selecting the benchmark circuits are discussed. These criteria are partly based on the results of experiments carried out to characterize CATS. The focus is particularly on Automatic Test Pattern Generators. The preliminary results show that there is no general agreement on how: 1) fault collapsing is performed, and 2) fault coverage is calculated. In addition, the performance of the ATPGs depends on the circuit representation, topology and size as well as the algorithm. In order to compare the performance of the ATPGs as the circuit under test increases in complexity, it is important to use regular structures that consist of replication of medium size circuits. Practical considerations involved in benchmarking are also examined. Emphasis is on the transfer of circuits between different CATS systems and the use of EDIF as a neutral exchange language.
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Yesina, M. V., and B. S. Shahov. "Analysis of hardware implementations of electronic signature algorithms qTesla, Crystals-Dilitium and MQDSS at different levels of security." Radiotekhnika, no. 205 (July 2, 2021): 42–52. http://dx.doi.org/10.30837/rt.2021.2.205.04.
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It is known, that existing public-key cryptography algorithms based on RSA and elliptic curves provide security guarantees accompanied by complexity. Based on this one can talk about the impossibility to solve problems of integer factorization and discrete logarithm. However, experts predict that the creation of a quantum computer will be able to crack classical cryptographic algorithms. Due to this future problem, the National Institute of Standards and Technologies (NIST), together with leading scientists in the field of cryptography, began an open process of standardizing public-key algorithms for quantum attacks. An important feature of the post-quantum period in cryptography is the significant uncertainty regarding the source data for cryptanalysis and counteraction in terms of the capabilities of quantum computers, their mathematical and software, as well as the application of quantum cryptanalysis to existing cryptotransformations and cryptoprotocols. Mathematical methods of electronic signature (ES) have been chosen as the main methods of NIST USA, which have undergone significant analysis and substantiation in the process of extensive research by cryptographers and mathematicians at the highest level. These methods are described in detail and passed the research at the first stage of the international competition NIST USA PQC. Historically, in 1997, NIST sought public advice to determine the replacement of the data encryption standard (DES), Advanced Encryption Standard (AES). Since then, open cryptographic estimations have become a way of choosing cryptographic standards. For example, NESSIE (2000-2002), eSTREAM (2004-2008), CRYPTREC (2000-2002), SHA-3 (2007-2012) and CAESAR (2013-2019) have adopted this approach. Security was the main parameter in these estimations. Performance in software, performance in application-specific integrated circuits (ASICs), performance in FPGAs, and feasibility with limited resources (small microprocessors and low-power hardware) are secondary criteria. This paper presents the comparison of the hardware of three signature algorithms (qTesla, Crystals-Dilitium, MQDSS), which, in particular, are the candidates for the 2nd round of the NIST PQC competition, and the Crystals-Dilitium algorithm is the finalist of this competition. The objective of this work is to analyze and compare three hardware implementations of candidates for the second round of the NIST PQC contest for an electronic signature algorithm.
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Otten, David M., James B. Kobler, Robert E. Hillman, Steven M. Zeitels, Kevin P. Seitter, and James T. Heaton. "Development of a Closed-Loop Stimulator for Laryngeal Reanimation, Part 1: Devices." Annals of Otology, Rhinology & Laryngology 128, no. 3_suppl (January 27, 2019): 33S—52S. http://dx.doi.org/10.1177/0003489418820885.
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Objective: The goal of this work was to create implantable stimulator systems that could be used in animal experiments on laryngeal paralysis, including “closed-loop” stimulation of impaired muscles triggered by electromyographic (EMG) potentials from healthy muscles. Study Design: Iterative device design and testing. Methods: A series of microcontroller-based implantable devices were built that incorporated increasingly sophisticated features for stimulation, EMG recording, and communication across the skin. Specific engineering challenges included minimizing power consumption, achieving charge-balanced and relatively high stimulation capacity, implementing noninvasive communication across the skin, providing real-time processing of EMG signals, and mitigating effects of shock artifacts. Bench testing was used to verify performance. Results: Two prototypes are described in detail. Each system is based on an “implant” and an external “communication adapter” that interfaces both with the implant and with external computers for adjustments and monitoring. The first version described is inductively powered and referred to as the “inductive laryngeal stimulator.” It uses inductive coupling for both power and communication and performs EMG processing in the communication adapter module. The second version, a “battery-powered laryngeal stimulator,” consists of an autonomous battery-powered implant with onboard EMG processing and artifact control; it communicates by infrared light with the external communication adapter for setup and monitoring. Conclusions: The devices met design and performance specifications and have proved useful in the animal experiments that are described in Part 2 of this series. Detailed descriptions of the circuits and their firmware are made available in the Appendix. Level of Evidence: NA
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Shieh, Yeong-Ruey, and Cheng-Wen Wu. "Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults." VLSI Design 5, no. 4 (January 1, 1998): 357–72. http://dx.doi.org/10.1155/1998/24951.
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We present in this paper an approach to designing partially strongly code-disjoint (PSCD) CMOS circuits and checkers, considering transistor stuck-on faults in addition to gate-level stuck-at faults. Our design-for-testability (DFT) technique requires only a small number of extra transistors for monitoring abnormal static currents, coupled with a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry not only can detect the faults in the functional circuit but also can detect or tolerate faults in itself, making it a good candidate for checker design. Switch and circuit level simulations were performed on a sample circuit, and a sample 4-out-of-8 code checker chip using the proposed technique has been designed, fabricated, and tested, showing the correctness of the method. Performance penalty is reduced by a novel BiCMOS checker circuit.
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Podder, Deberati, and Paul Hurley. "Ionic transistor – A new generation memory device." Boolean 2022 VI, no. 1 (December 6, 2022): 215–21. http://dx.doi.org/10.33178/boolean.2022.1.35.
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We have come a long way since Alan Tuning first proposed the Artificial Intelligence (AI) in modern computers in 1950s enabling them to response like a human brain under certain conditions. But in order to perform various machine-learning operations such as image or speech recognition, huge datasets need to be processed leading to massive power consumption. Hence for the practical implementation and progress of AI with energy efficiency there is a pressing need of new class of memory devices which can mimic the performance of human brain at equivalent low energy. The focus of my PhD project is to develop such memory element by controlled incorporation of metal ions into the insulating layer in Metal Oxide Semiconductor (MOS) transistor which can be an innovative solution for muti-level (Analog; for reference, Binary system represents two levels), non-volatile (stored data retained even after power is off), Neuromorphic (mimics human brain response) memory device. Here I have reported controlled incorporation of lithium ions in an additional deposited insulating polymer layer in a metal-oxide-semiconductor capacitor and have shown that lithium ions motion in this layer can be controlled externally which enables it to modify the conductivity of the device, overall making it a promising candidate for the new generation memory element. Successfully integrating this with present silicon-based integrated circuits can lead to a breakthrough in AI in the future.
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Prajapati, Pankaj P., Anilkumar J. Kshatriya, Sureshbhai L. Bharvad, and Abhay B. Upadhyay. "Performance analysis of CMOS based analog circuit design with PVR variation." Bulletin of Electrical Engineering and Informatics 12, no. 1 (February 1, 2023): 141–48. http://dx.doi.org/10.11591/eei.v12i1.4357.
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Process, supply voltage, and temperature (PVT) are three important factors which contribute to performance variation of the complementary metal–oxide–semiconductor (CMOS) based analog circuits. In this paper, CMOS based analog circuit design with the PVT variation effects are explored. The effects of the PVT variation on the performance of CMOS based analog circuits are introduced. The optimization of CMOS based analog circuits such as differential amplifier (DA) and two-stage operational amplifier (op amp) circuits with PVT variations with different algorithms such as cockoo search (CS), particle swam optimization (PSO), hybrid CSPSO, and differential evaluation (DE) algorithms is presented. Each algorithm is implemented using the C programming language, interfaced with Ngspice circuit simulator, and tested on the Intel®core™ i5, 2.40 GHz processor with 8 GB internal RAM using the Ubuntu operating system (OS). The result shows PVT variation affects the performance of CMOS circuit.
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Singh, Jagmeet, Hugh Morison, Zhimu Guo, Bicky A. Marquez, Omid Esmaeeli, Paul R. Prucnal, Lukas Chrostowski, Sudip Shekhar, and Bhavin J. Shastri. "Neuromorphic photonic circuit modeling in Verilog-A." APL Photonics 7, no. 4 (April 1, 2022): 046103. http://dx.doi.org/10.1063/5.0079984.
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One of the significant challenges in neuromorphic photonic architectures is the lack of good tools to simulate large-scale photonic integrated circuits. It is crucial to perform simulations on a single platform to capture the circuit’s behavior in the presence of both optical and electrical components. Here, we adopted a Verilog-A based approach to model neuromorphic photonic circuits by considering both the electrical and optical properties. Verilog-A models for the primary optical devices, such as lasers, couplers, waveguides, phase shifters, and photodetectors, are discussed, along with studying the composite devices such as microring resonators. Model parameters for different optical devices are extracted and tuned by analyzing the measured data. The simulated and experimental results are also compared for validation of Verilog-A models. Finally, a single photonic neuron circuit is simulated by implementing input, weight, and non-linear activation function by using lasers, microring resonators, and modulator, respectively. Electro-optical rapid co-simulation would significantly improve the efficiency of optimizing the devices and provide an accurate simulation of the circuit performance.
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Kanazawa, Yusuke, Tetsuya Asai, and Yoshihito Amemiya. "Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses." Journal of Robotics and Mechatronics 15, no. 2 (April 20, 2003): 208–18. http://dx.doi.org/10.20965/jrm.2003.p0208.
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We discuss the integration architecture of spiking neurons, predicted to be next-generation basic circuits of neural processor and dynamic synapse circuits. A key to development of a brain-like processor is to learn from the brain. Learning from the brain, we try to develop circuits implementing neuron and synapse functions while enabling large-scale integration, so large-scale integrated circuits (LSIs) realize functional behavior of neural networks. With such VLSI, we try to construct a large-scale neural network on a single semiconductor chip. With circuit integration now reaching micron levels, however, problems have arisen in dispersion of device performance in analog IC and in the influence of electromagnetic noise. A genuine brain computer should solve such problems on the network level rather than the element level. To achieve such a target, we must develop an architecture that learns brain functions sufficiently and works correctly even in a noisy environment. As the first step, we propose an analog circuit architecture of spiking neurons and dynamic synapses representing the model of artificial neurons and synapses in a form closer to that of the brain. With the proposed circuit, the model of neurons and synapses can be integrated on a silicon chip with metal-oxide-semiconductor (MOS) devices. In the sections that follow, we discuss the dynamic performance of the proposed circuit by using a circuit simulator, HSPICE. As examples of networks using these circuits, we introduce a competitive neural network and an active pattern recognition network by extracting firing frequency information from input information. We also show simulation results of the operation of networks constructed with the proposed circuits.
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Petkovsek, Marko, and Peter Zajec. "Evaluating Common-Mode Voltage Based Trade-Offs in Differential-Ended and Single-Supplied Signal Conditioning Amplifiers." Electronics 10, no. 16 (August 17, 2021): 1982. http://dx.doi.org/10.3390/electronics10161982.
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This paper focuses on a differential voltage measurement in low-voltage automotive devices whose subunits are separated with a low-side safety switch. In contrast to conventional applications with high-side switches, a common-mode voltage (CMV) with negative polarity exists at the input of the signal conditioning circuitry. To overcome the shortage of dedicated integrated circuits capable of withstanding negative CMV, the paper investigates single- and two-stage differential circuits with single-supplied operational amplifiers to find a cost-optimized counterpart. In addition, the proposed procedure tunes the circuit parameters in such a manner to obtain the largest possible full-scale range at the output. Though, such optimization results in very uncommon values for gain and reference voltages. This issue is additionally evaluated for reference voltages that are either cost-effective or more easily accessible to increase the circuit feasibility. Since the impact of resistances on circuits’ behaviour could be diminished to a great extent using high-precision and matched pair resistors, the sensitivity analysis was investigated only for a reference voltage change. Furthermore, a reversed termination of measured voltages results in a simplified reference voltage selection without hindering circuits’ performance, proven by simulation and experimental results.
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Dolin, Georgy A., and Anastasiya Y. Kudryashova. "Modified Methods of Circuit Simulation of Radio Engineering Devices in The Time Domain." SYNCHROINFO JOURNAL 6, no. 2 (2020): 7–11. http://dx.doi.org/10.36724/2664-066x-2020-6-2-7-11.
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Today, different modeling methods are used for computer analysis of circuits of radio engineering devices (RED) in the time and frequency domains. The article provides a comparison and highlights the features of using the methods of nodal potentials and variable states. Developed methods of optimization of electrical circuits and discusses the possibility of calculating the margin of stability when changing the parameters of the circuit elements and the search of critical parameter values; theoretically and experimentally confirmed the advantages of using MEAs in the analysis of RED; proposed and implemented ways to eliminate the major disadvantages of the IPU; expanded and improved methods for obtaining the mathematical model of the circuit; the mathematical method allows to obtain the characteristic polynomial of a circuit without calculating its transfer function; the developed block for processing parameters of electrical circuit elements using scaling coefficients can significantly improve the accuracy of calculations; the use of speed-optimized algorithms makes it possible to analyze fairly complex circuits on a medium-performance PC. Developed software allows to analyze a wide class of linear, linearized, and nonlinear circuits for the RED, containing the active elements. The analysis of real electrical circuits proves the validity of all the proposed methods.
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Wairya, Subodh, Rajendra Kumar Nagaria, and Sudarshan Tiwari. "Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design." VLSI Design 2012 (April 4, 2012): 1–18. http://dx.doi.org/10.1155/2012/173079.
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This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18 m process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.
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Johnston, D. N., and K. A. Edge. "Simulation of the Pressure Ripple Characteristics of Hydraulic Circuits." Proceedings of the Institution of Mechanical Engineers, Part C: Mechanical Engineering Science 203, no. 4 (July 1989): 275–82. http://dx.doi.org/10.1243/pime_proc_1989_203_114_02.
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The pressure ripple in a hydraulic circuit is commonly a major source of noise. A computer program has been written to simulate the pressure ripple characteristics of hydraulic circuits and to aid in the design of low noise circuits. Mathematical models of flexible hose and of pump flow ripple and source impedance have been developed. Validation tests on various circuits show that the program produces good correlation with experimental measurements. A simple silencer consisting of an asymmetric pipe loop, known as a Quincke tube, was analysed. Its performance was shown to be limited, providing attenuation over very narrow bandwidths.
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Wang, Lu, Hongyu Zhu, Ze Zuo, and Dianzhong Wen. "Full-function logic circuit based on egg albumen resistive memory." Applied Physics Letters 121, no. 24 (December 12, 2022): 243505. http://dx.doi.org/10.1063/5.0124826.
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The logic gate is the basic unit of a digital circuit structure. The operation, memory, I/O, and other reading and writing functions of computer systems require logic circuits. Logic gates based on resistive memory can make existing integrated circuits denser, smaller, faster, and use fewer devices. In this paper, Al/polymethyl methacrylate (PMMA)/egg albumen (EA):Au nanoparticles/PMMA/Al multilayer biological resistive random access memory was prepared based on the natural biological material—egg albumen (EA). The device has bipolar switching behavior, a higher switching current ratio, a lower threshold voltage, and better stability. A circuit based on auxiliary logic is constructed using this device, and the logic functions of AND, OR, NOT, NAND, and NOR are realized. This device provides an effective potential solution for implementing high-performance electronic devices and large-scale integrated circuits.
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Raman, Srilata, C. L. Liu, and Larry G. Jones. "Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation." VLSI Design 4, no. 4 (January 1, 1996): 345–55. http://dx.doi.org/10.1155/1996/53238.
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In this paper we present a simple but efficient timing-driven placement algorithm for FPGAs. The algorithm computes forces acting on a logic block in the FPGA to determine its relative location with respect to other blocks. The forces depend on the criticality of nets shared between the two blocks. Unlike other net-based approaches, timing constraints are incorporated directly into the force equations to guide the placement. Slot assignment is then used to move the blocks into valid slot locations on the FPGA chip. The assignment algorithm also makes use of the delay information of nets so that the final placement is able to meet the timing criteria specified for the circuit. The novelty of the approach lies in the formulation of the force equations and the manner in which weights of the nets are dynamically altered to influence the placement. Experiments conducted on industrial test circuits and MCNC circuits give very promising results and indicate that the algorithm succeeds in significantly reducing the maximum delay in the circuit. In addition, routability is not adversely affected and running time is low.
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Lim, Taek-Kyu, Kunal Sandip Garud, Jae-Hyeong Seo, Moo-Yeon Lee, and Dong-Yeon Lee. "Experimental Study on Heating Performances of Integrated Battery and HVAC System with Serial and Parallel Circuits for Electric Vehicle." Symmetry 13, no. 1 (January 7, 2021): 93. http://dx.doi.org/10.3390/sym13010093.
Full textAbstract:
The objective of the present study is to conduct experiments for investigating heating performances of integrated system with serial and parallel circuits for battery and heating ventilation and air conditioning system (HVAC) of electric vehicles under various operating conditions. In addition, the artificial neural network (ANN) model is proposed to accurately predict the heating performances of integrated system with serial and parallel circuits for battery and HVAC. A test bench of integrated system with serial and parallel circuits has been developed for establishing the trade-off between battery heating and HVAC heating. The heating performances namely, battery out temperature, battery temperature rise rate, battery heating capacity, HVAC heating capacity and total heating capacity are evaluated experimentally for the integrated system with serial and parallel circuits. The behavior of various heating performances is evaluated under influence of flow rate and heater power. Battery out temperature reaches 40 °C within 10 min with rise rate of 2.17 °C/min for the integrated system with serial circuit and that within 20 min with rise rate of 1.22 °C/min for the integrated system with parallel circuit. Integrated system with serial circuit shows higher HVAC heating capacity than integrated system with parallel circuit which are 5726.33 W and 3869.15 W, respectively. ANN model with back-propagation algorithm, Levenberg-Marquardt training variant, Tan-sigmoidal transfer function and 20 hidden neurons presents the accurate prediction of heating performances of the integrated system with serial and parallel circuits for battery and HVAC.
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Lim, Taek-Kyu, Kunal Sandip Garud, Jae-Hyeong Seo, Moo-Yeon Lee, and Dong-Yeon Lee. "Experimental Study on Heating Performances of Integrated Battery and HVAC System with Serial and Parallel Circuits for Electric Vehicle." Symmetry 13, no. 1 (January 7, 2021): 93. http://dx.doi.org/10.3390/sym13010093.
Full textAbstract:
The objective of the present study is to conduct experiments for investigating heating performances of integrated system with serial and parallel circuits for battery and heating ventilation and air conditioning system (HVAC) of electric vehicles under various operating conditions. In addition, the artificial neural network (ANN) model is proposed to accurately predict the heating performances of integrated system with serial and parallel circuits for battery and HVAC. A test bench of integrated system with serial and parallel circuits has been developed for establishing the trade-off between battery heating and HVAC heating. The heating performances namely, battery out temperature, battery temperature rise rate, battery heating capacity, HVAC heating capacity and total heating capacity are evaluated experimentally for the integrated system with serial and parallel circuits. The behavior of various heating performances is evaluated under influence of flow rate and heater power. Battery out temperature reaches 40 °C within 10 min with rise rate of 2.17 °C/min for the integrated system with serial circuit and that within 20 min with rise rate of 1.22 °C/min for the integrated system with parallel circuit. Integrated system with serial circuit shows higher HVAC heating capacity than integrated system with parallel circuit which are 5726.33 W and 3869.15 W, respectively. ANN model with back-propagation algorithm, Levenberg-Marquardt training variant, Tan-sigmoidal transfer function and 20 hidden neurons presents the accurate prediction of heating performances of the integrated system with serial and parallel circuits for battery and HVAC.
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Ghavami, Behnam. "Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 37, no. 3 (May 8, 2018): 1189–203. http://dx.doi.org/10.1108/compel-03-2016-0118.
Full textAbstract:
Purpose Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits. Design/methodology/approach In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment. Findings Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits. Originality/value The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.