Dissertations / Theses on the topic 'Computers – Circuits – Performance'

Advances in silicon technology over the last decade have led to increased integration of analogue and digital functional blocks onto the same single chip. In such a mixed signal environment, the analogue circuits must use the same process technology as their digital neighbours. With reducing transistor sizes, the impact of process variations on analogue design has become prominent and can lead to circuit performance falling below specification and hence reducing the yield. This thesis explores the methodology and algorithms for an analogue integrated circuit automation tool that optimizes performance and yield. The trade-offs between performance and yield are analysed using a combination of an evolutionary algorithm and Monte Carlo simulation. Through the integration of yield parameter into the optimisation process, the trade off between the performance functions can be better treated that able to produce a higher yield. The results obtained from the performance and variation exploration are modelled behaviourally using a Verilog-A language. The model has been verified with transistor level simulation and a silicon prototype. For a large analogue system, the circuit is commonly broken down into its constituent sub-blocks, a process known as hierarchical design. The use of hierarchical-based design and optimisation simplifies the design task and accelerates the design flow by encouraging design reuse. A new approach for system level yield optimisation using a hierarchical-based design is proposed and developed. The approach combines Multi-Objective Bottom Up (MUBU) modelling technique to model the circuit performance and variation and Top Down Constraint Design (TDCD) technique for the complete system level design. The proposed method has been used to design a 7th order low pass filter and a charge pump phase locked loop system. The results have been verified with transistor level simulations and suggest that an accurate system level performance and yield prediction can be achieved with the proposed methodology.

With the continuous trend of reducing feature sizes, and employing continuously smaller components on integrated circuits, new challenges arise on the way of silicon CMOS circuits and devices. Emerging “nanodevices” promise the possibility of increased integration density and reduced power consumption. The emerging and new devices, partially due to their extremely small dimensions, show large variations in their behaviour. The variation shown by these devices affects their reliability and the performance of circuits made from them. The Carbon Nano-Tube (CNT) is one such device which is also the device of choice in this work. This work is concerned with building reliable systems out of these unreliable components. The work was done in HSPICE with the help of the Stanford CNFET model. Logic gates are implemented using CNT Field Effect Transistors (CNFETs) which are in turn made from CNTs with different physical attributes. Given a CNT manufacturing process, there exists a mean and standard deviation (STD) for the diameter distribution of the manufactured CNTs which depend on the accuracy of the manufacturing process. In the first part of this work, CNTs with different mean diameters and standard deviations (STD) in their diameter distribution are considered. Simulation results show that logic gates made from CNTs with larger mean and smaller STDs in their diameter distribution show less variation in their timing behaviour (propagation delay, rise and fall times) and a promise of more reliable operation. Alternative structures were then explored in the form of multiplexers and XOR gates. It is shown that these structures have the advantage over the gates studied previously in that they exhibit similar rise and fall transition times and hence are better suited to CNFET-based circuit design. The next stage of this work involves implementation and simulation of a memory structure (SRAM). Parameters such as Static Noise Margin (SNM), leakage power and read/write delays were studied and the effects of CNT diameter variation on them examined. The next contributions of this work are empirical models developed for a library of CNFET-based logic gates/circuit structures. The models can predict both the mean and standard deviation (STD) in various circuit performance parameters of a given CNFET-based logic gate/SRAM given the mean and STD of the diameter of CNTs used in their manufacture. The aim is, given a target reliability specification (timing requirements, power, speed, etc.), for various logic gates, and larger circuit components, to come up with a design strategy to suggest what physical properties the nano-device of choice should have to meet the target specification or vice versa. Best-case CNT diameter mean and STD selection scenarios are proposed to minimise circuit parameter variations. In the last part of this work, the effects of doping fluctuations in the source/drain regions of the CNFETs on the performance of logic gates made from them are studied. The work concludes that if doping concentration is kept above 1%, variation in doping concentration has a minimal effect on performance parameters.

The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier of interest during normal operation. This results in an offset voltage cancelation that is independent of other amplifier parameters and does not dissipate additional power. Two compact programmable architectures that implement a voltage reference based on the charge difference between two floating-gate transistors are introduced. The references exhibit a low temperature coefficient (TC) as all the transistors temperature dependencies are canceled. Programming the charge on the floating-gate transistors provides the flexibility of an arbitrary accurate voltage reference with a single design and allows for a high initial accuracy of the reference. Also, this work presents a novel programmable temperature compensated current reference. The proposed circuit achieves a first order temperature compensation by canceling the negative TC of an on-chip poly resistor with the positive TC of a MOS transistor operating in the ohmic region. Programmability of the ohmic resistor enables optimal temperature compensation while programmability of the reference voltage allows for an accurate current reference for a wide range of values. Finally, this work combines the already established DAC design techniques with floating-gate circuits to obtain a high precision converter. This approach enables higher accuracy along with a substantial decrease of the die size.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Includes bibliographical references (p. 85-88).
The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two. PSSL is better than domino in terms of energy and robustness, and is better than static CMOS in terms of delay. PSSL works by partially overlapping the execution of consecutive iterations through speculative evaluation. This is accomplished by presetting nodes at register boundaries before input arrival.
by Albert Ma.
Ph.D.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
Includes bibliographical references (p. 173-187).
As the critical dimensions in VLSI design continue to shrink, system performance of integrated circuits (ICs) will be increasingly dominated by interconnect delay [1]. For the technology generations approaching 50 nm and beyond, innovative system architectures and interconnect technologies will be required to meet the projected system performance [2]. Interconnect material solutions such as copper and low-k inter-level dielectric (ILD) offer only a limited improvement in system performance. Significant and scalable solutions to the interconnect delay problem will require fundamental changes in system design, architecture, and fabrication technologies. Three-dimensional (3-D) ICs can alleviate interconnect delay problems by offering flexibility in system design, placement and routing. They (3-D ICs) can be formed by vertical integration of multiple device layers using wafer bonding, recrystallization, or selective epitaxial growth. The flexibility to place devices along the vertical dimension allows higher device density and smaller form factor in 3-D ICs. The critical signal path that may limit system performance can also be shortened to achieve faster clock speed. By 3-D integration, device layers fabricated with different front-end process technologies can be stacked along the 3rd dimension to form systems-on-a-chip [3]. In this thesis work, opportunities and challenges for 3-D integration of logic networks, microprocessors, and programmable logic have been explored based on system-level modeling and analysis. A stochastic wire-length distribution model has been derived to predict interconnection complexity in 3-D ICs. As more device layers are integrated, the 3-D wire-length distribution becomes narrower compared to that of 2-D ICs, resulting in a significant reduction in the number and length of semi-global and global wires. In 3-D ICs with 2-4 device layers, 30% - 50% reduction in wire-length can be achieved. Besides performance modeling, thermal analysis has also been performed to assess power dissipation and heat removal issues in 3-D ICs. The total capacitance associated with signal interconnects and clock networks can be reduced by 3-D integration, leading to lower power dissipation for system performance comparable to that of 2-D ICs. However, for higher system performance in 3-D ICs, power dissipation increases significantly, and it is likely that innovative cooling techniques will be needed for reliable operation of devices and interconnects.
by Arifur Rahman.
Ph.D.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
Includes bibliographical references (p. 95-101).
The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in threshold voltage variation due to worsening short channel effect. This thesis will address three specific circuit design challenges arising from increased threshold voltage variation and present prospective solutions. First, with supply voltage scaling, control of die-to-die threshold voltage variation becomes critical for maintaining high yield. An analytical model will be developed for existing circuit technique that adaptively biases the body terminal of MOSFET devices to control this threshold voltage variation. Based on this model, recommendations on how to effectively use the technique in future technologies will be presented. Second, with threshold voltage scaling, sub-threshold leakage power is expected to be a significant portion of total power in future CMOS systems. Therefore, it becomes imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and a circuit technique to reduce system leakage without reducing system performance will be discussed.
(cont.) Finally, due to different processing steps and short channel effects, threshold voltage of devices of same or different polarities in the same neighborhood may not be matched. This will introduce mismatch in the device drive currents that will not be acceptable in some high performance circuits. In the last part of the thesis, voltage and current biasing schemes that minimize the impact of neighborhood threshold voltage mismatch will be introduced.
by Siva G. Narendra.
Ph.D.

In the research community, three-dimensional integrated circuit (3DIC) technology has garnered attention for its potential use as a solution to the scaling gap between MOSFET device characteristics and interconnects. The purpose of this work is to examine the performance advantages offered by 3DICs. A 3D microprocessor-based test case has been designed using an automated 3DIC design flow developed by the researchers of North Carolina State University. The test case is based on an open architecture that is exemplary of future complex System-on-Chip (SoC) designs. Specialized partitioning and floorplanning procedures were integrated into the design flow to realize the performance gains of vertical interconnect structures called 3D vias. For the post-design characterization of the 3DIC, temperature dependent models that describe circuit performance over temperature variations were developed. Together with a thermal model of the 3DIC, the performance scaling with temperature was used to predict the degree of degradation of the delay and power dissipation of the 3D test case. Using realistic microprocessor workloads, it was shown that the temperatures of the 3DIC thermal model are convergent upon a final value. The increase in delay and power dissipation from the thermal analysis was found to be negligibly small when compared to the performance improvements of the 3DIC. Timing analysis of the 3D design and its 2D version revealed a critical path delay reduction of nearly 26.59% when opting for a 3D implementation. In addition, the 3D design offered power dissipation savings of an average of 3% while running at a proportionately higher clock frequency.

Ternary content addressable memories (TCAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of TCAMs, high power consumption is one of the most critical challenges faced by TCAM designers. This work proposes circuit techniques for reducing TCAM power consumption. The main contribution of this work is divided in two parts: (i) reduction in match line (ML) sensing energy, and (ii) static-power reduction techniques. The ML sensing energy is reduced by employing (i) positive-feedback ML sense amplifiers (MLSAs), (ii) low-capacitance comparison logic, and (iii) low-power ML-segmentation techniques. The positive-feedback MLSAs include both resistive and active feedback to reduce the ML sensing energy. A body-bias technique can further improve the feedback action at the expense of additional area and ML capacitance. The measurement results of the active-feedback MLSA show 50-56% reduction in ML sensing energy. The measurement results of the proposed low-capacitance comparison logic show 25% and 42% reductions in ML sensing energy and time, respectively, which can further be improved by careful layout. The low-power ML-segmentation techniques include dual ML TCAM and charge-shared ML. Simulation results of the dual ML TCAM that connects two sides of the comparison logic to two ML segments for sequential sensing show 43% power savings for a small (4%) trade-off in the search speed. The charge-shared ML scheme achieves power savings by partial recycling of the charge stored in the first ML segment. Chip measurement results show that the charge-shared ML scheme results in 11% and 9% reductions in ML sensing time and energy, respectively, which can be improved to 19-25% by using a digitally controlled charge sharing time-window and a slightly modified MLSA. The static power reduction is achieved by a dual-VDD technique and low-leakage TCAM cells. The dual-VDD technique trades-off the excess noise margin of MLSA for smaller cell leakage by applying a smaller VDD to TCAM cells and a larger VDD to the peripheral circuits. The low-leakage TCAM cells trade off the speed of READ and WRITE operations for smaller cell area and leakage. Finally, design and testing of a complete TCAM chip are presented, and compared with other published designs.

De plus en plus de constructeurs proposent des accélérateurs de calculs à base de circuits reconfigurables FPGA, cette technologie présentant bien plus de souplesse que le microprocesseur. Valoriser cette flexibilité dans le domaine de l'accélération de calcul flottant en utilisant les langages de description de circuits classiques (VHDL ou Verilog) reste toutefois très difficile, voire impossible parfois. Cette thèse a contribué au développement du logiciel FloPoCo, qui offre aux utilisateurs familiers avec VHDL un cadre C++ de description d'opérateurs arithmétiques génériques adapté au calcul reconfigurable. Ce cadre distingue explicitement la fonctionnalité combinatoire d'un opérateur, et la problématique de son pipeline pour une précision, une fréquence et un FPGA cible donnés. Afin de pouvoir utiliser FloPoCo pour concevoir des opérateurs haute performance en virgule flottante, il a fallu d'abord concevoir des blocs de bases optimisés. Nous avons d'abord développé des additionneurs pipelinés autour des lignes de propagation de retenue rapides, puis, à l'aide de techniques de pavages, nous avons conçu de gros multiplieurs, possiblement tronqués, utilisant des petits multiplieurs. L'évaluation de fonctions élémentaires en flottant implique souvent l'évaluation en virgule fixe d'une fonction. Nous présentons un opérateur générique de FloPoCo qui prend en entrée l'expression de la fonction à évaluer, avec ses précisions d'entrée et de sortie, et construit un évaluateur polynomial optimisé de cette fonction. Ce bloc de base a permis de développer des opérateurs en virgule flottante pour la racine carrée et l'exponentielle qui améliorent considérablement l'état de l'art. Nous avons aussi travaillé sur des techniques de compilation avancée pour adapter l'exécution d'un code C aux pipelines flexibles de nos opérateurs. FloPoCo a pu ainsi être utilisé pour implanter sur FPGA des applications complètes.

L'optimisation des performances constitue un element fondamental de la conception des circuits. On est donc amene a realiser un algorithme iteratif d'approximation et d'amelioration des gradients des performances capable de concilier rapidite et precision de l'execution d'un programme

IP traffic increase has resulted in a demand for greater capacity of the underlying Ethernet network. As a consequence, not only Internet Service Providers (ISPs) but also telecom operators have migrated their mobile back-haul networks from legacy SONET/SDH circuit-switched equipment to packet-based networks. This inevitable shift brings higher through put efficiency and lower costs; however, the guaranteed QoS and minimal delay and packet delay variation (PDV) that can only be offered by circuit-switched technologies such as SONET/SDH are still essential and are becoming more vital for transport and metro networks, as well as for mobile back-haul networks, as the range and demands of applications increase. Fusion network offers "both an Ethernet wavelength transport and the ability to exploit vacant wavelength capacity using statistical multiplexing without interfering with the performance of the wavelength transport" [RVH] by dividing the traffic into two service classes while still using the capacity of the same wavelength in a wavelength routed optical network (WRON) [SBS06]: 1. A Guaranteed Service Transport (GST) service class supporting QoS demands such as no packet loss and fixed low delay for the circuit-switched traffic.   2. A statistical multiplexing (SM) service class offering high bandwidth efficiency for the best-effort packet-switched traffic.   Experimentation was carried out using two TransPacket's H1 nodes and the Spirent Test-Center as a packet generator/analyzer with the objective of demonstrating that the fusion technology, using TransPacket's H1 muxponders allow transporting GST traffic with circuit QoS; that is with no packet loss, no PDV and minimum delay independent of the insertion of statistically multiplexed traffic. Results indicated that the GST traffic performance is completely independent of the added SM traffic and its load. GST was always given absolute priority and remained with a constant average end-to-end delay of 21.47 μs, no packet loss and a minimum PDV of 50 ns while SM traffic load increased, increasing the overall 10GE lightpath utilization up to 99.5%.

Carbon nanotube field-effect transistors (CNFETs) are considered to be promising candidate beyond the conventional CMOSFET due to their higher current drive capability, ballistic transport, lesser power delay product and higher thermal stability. CNFETs show great potential to build digital systems on advanced technology nodes with big benefits in terms of power, performance and area (PPA). Hence, there is a great need to develop proven models and CAD tools for performance evaluation of CNFET-based circuits. CNFETs specific parameters, such as number of tubes, pitch (spacing between the tubes) and diameter of CNTs determine current driving capability, speed, power consumption and area of circuits and play a significant role in accurate PPA evaluation. Furthermore, count and density variations in carbon nanotubes (CNTs) due to manufacturing limitations, like the presence of metallic tubes in the CNFET channel, pose major obstacles to robust and energy-efficient CNFET digital circuit designs and degrade the anticipated PPA benefits. CNFET-based circuits can suffer from large performance variations and reduction in functional yield due to these variations in CNFETs. Moreover, modeling the CNFET parameters, CNT variations and etching techniques for CNTs create additional complexity during performance optimization. Hence, for realistic optimization of CNFET circuit's performance, it is imperative to incorporate the impact of these parameters and variations. We present a capacitance-based Logical Effort (LE) framework to investigate design issues of high-speed and low-power circuit designs implemented by considering specific requirements and challenges of the CNFET technology. The LE technique is widely recognized as a pedagogical method to quickly estimate and optimize the propagation delay and transition time in CMOS circuits equivalently without performing transient simulations and detailed delay calculations. In this thesis, we propose novel delay models [Pitch-Aware Logical Effort (PALE) and Position-Aware Pitch Factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations. 1. Ideal case (CNTs variations are not considered): During our research on CNFET-based circuits, we analyzed the impact of CNFET specific parameters, such as CNTs count, diameter and spacing between tubes, on the performance of CNFET-based circuits. The screening effect is critical to take into account for accurate performance evaluation. Hence, PALE model is developed by extending LE formulation to include influence of CNFET specific parameters. 2. Realistic case (CNTs variations are considered): We have studied CNFET-based logic gates and circuits in the presence of major CNTs variations using Monte Carlo simulations. The removal of the initially present unwanted metallic tubes, by the known processing techniques, causes non-uniformity of CNT density in the channel. Such variations in the number of CNTs impact circuit performance and functional yield. We develop variation-aware model (PAPF) based on LE technique to include impact of CNTs variations on the delay of large CNFET-based circuits. Our developed models are correlated with SPICE simulations using different types of gates and circuits with an average error of 3% and 5% for ideal and realistic cases respectively. Our framework is capable of estimating performance more than 100x faster as compared to SPICE simulations methods. Furthermore, using our models (PALE and PAPF), we present an optimization tool to minimize the area and delay product (ADP) of CNFET circuits. We deploy circuit-level techniques (CLT) prior to the optimizing the tubes (CNTs) in the logic gates to achieve highly optimized solution with global approach. For better optimization of the circuits, the impact of wire parasitic in estimating the delay of the individual gates is included as well. Our optimization tool results in maximum and average delay improvement by 27% and 17% respectively, and 2.5X reduction in area for standard ISCAS and OpenSPARC benchmark circuits. Fast and fairly accurate delay computation in our optimization framework offers great runtime benefits as compared to state-of-the-art SPICE simulation and statistical-based methods. Finally, we propose more accurate probabilistic model for yield estimation which incorporates the impact of screening effect on the functional yield after the removal of metallic tubes. Overall, the objective of this thesis is to develop comprehensive LE-based framework and optimization tool and methodology which comprehend CNFET specific parameters for accurate performance evaluation as well as estimation of delay, power, functional yield and do ADP optimization in presence of CNTs variations. Our models are easily scalable to future technology nodes.

Les FPGA (Field Programmable Gate Arrays) constituent un type de circuit reprogrammable qui, sous certaines conditions, peuvent avoir de meilleures performances que les microprocesseurs classiques. Les FPGA utilisent le circuit comme paradigme de programmation, ce qui permet d'effectuer des calculs parallèles propres à l'application visée. Ils permettent aussi d’atteindre l’efficacité arithmétique: un bit ne doit être calculé que s'il est utile dans le résultat final. Pour ce faire, l’arithmétique utilisée par les FPGA ne peut se limiter qu’à des fonctions conçues pour les microprocesseurs. Cette thèse se propose d’étudier les méthodes pour l’implémentation des fonctions gros-grain pour les FPGA à travers trois voies. De nouvelles méthodes pour évaluer des fonctions trigonométriques, telles que le sinus, cosinus et arc tangente ont été développés dans cette thèse. Chaque méthode est optimisée dans son contexte, de la manière la plus flexible et la plus souple possible. Pour que les méthodes aboutissent à leur efficacité arithmétique, il est nécessaire de procéder à une analyse d'erreurs, ainsi qu’à un choix attentif des paramétrés de la méthode et à une fine compréhension des algorithmes utilisés. Les filtres numériques constituent une famille importante d’opérateurs arithmétiques qui rassemble des fonctions élémentaires. Ils peuvent être spécifiés à un niveau élevé d'abstraction, à travers une fonction de transfert avec des contraintes sur le rapport signal/bruit. Ils peuvent être ensuite implémentés comme des chemins de données basés sur des additions et des multiplications. Le principal résultat est donc une méthode qui transforme une spécification de haut niveau en une implémentation d’une façon automatique. La première étape se rapporte au développement d'une méthode pour le calcul des produits par des constantes. Des filtres FIR et IIR peuvent être construits à l'aide de cette brique de base. Pour que les opérateurs arithmétiques atteignent leur performance maximale, on a besoin d’un pipeline correspondant au contexte donné. Même si les connaissances du développeur s’avèrent d’un grand avantage pendant le processus de création d'un pipeline d'un chemin de données, cette étape demeure complexe et facilement susceptible à des erreurs. Une méthode automatique, contrôlée par le développeur a dont été développée. Cette thèse fournit un générateur des opérateurs arithmétiques de haute qualité près à l'emploi, et qui propagent le domaine des calculs sur des FPGA à un pas plus proche de l’adoption générale. Les cœurs arithmétiques font partie d'un générateur open-source, où les fonctions peuvent être décrites par une spécification de haut niveau, comme par exemple une formule mathématique
Field-Programmable Gate Arrays (FPGAs) have been shown to sometimes outperform mainstream microprocessors. The circuit paradigm enables efficient application-specific parallel computations. FPGAs also enable arithmetic efficiency: a bit is only computed if it is useful to the final result. To achieve this, FPGA arithmetic shouldn’t be limited to basic arithmetic operations offered by microprocessors. This thesis studies the implementation of coarser operations on FPGAs, in three main directions: New FPGA-specific approaches for evaluating the sine, cosine and the arctangent have been developed. Each function is tuned for its context and is as versatile and flexible as possible. Arithmetic efficiency requires error analysis and parameter tuning, and a fine understanding of the algorithms used. Digital filters are an important family of coarse operators resembling elementary functions: they can be specified at a high level as a transfer function with constraints on the signal/noise ratio, and then be implemented as an arithmetic datapath based on additions and multiplications. The main result is a method which transforms a high-level specification into a filter in an automated way. The first step is building an efficient method for computing sums of products by constants. Based on this, FIR and IIR filter generators are constructed. For arithmetic operators to achieve maximum performance, context-specific pipelining is required. Even if the designer’s knowledge is of great help when building and pipelining an arithmetic datapath, this remains complex and error-prone. A user-directed, automated method for pipelining has been developed. This thesis provides a generator of high-quality, ready-made operators for coarse computing cores, which brings FPGA-based computing a step closer to mainstream adoption. The cores are part of an open-ended generator, where functions are described as high-level objects such as mathematical expressions

Optimisation de la conception assistee d'un circuit par une analyse statistique des performances. Pour cela on developpe des algorithmes permettant d'ameliorer la faisabilite des circuits et de reduire le temps de calcul

The design of 3D microwave devices can be improved by using computational optimization techniques combined with numerical simulations of the electromagnetic field. However, high accuracy field analysis is often computationally expensive and time consuming. One way to cut costs is to vary the accuracy level of the analysis at different stages of the optimization. This idea is based on the premise that the accuracy need not be constant throughout the optimization, and so the numerical analysis can be run more cheaply without compromising design quality.
This thesis presents a software system that minimizes the return loss of 3D microwave devices over a frequency band efficiently through accuracy control. It combines a custom gradient-based optimizer with a p-adaptive frequency-domain finite element solver. The solver computes the cost function and its gradient to a specified accuracy in a cost efficient manner. The p-adaptive solver comprises of two original components: an a-posteriori error estimator to evaluate the error in the cost function gradient, and an error indicator to identify the high error regions in the mesh. The optimizer controls the accuracy of the cost function evaluation through a link with the solver, specifying the required relative error for the gradient at each optimization step.
The combined adaption-optimization scheme was applied to 3D rectangular waveguide problems for validation: an E-plane miter bend, a U-bend, an impedance transformer and a compensated magic-T. For comparison, all the problems were also optimized using high-order finite elements at every step. Test results prove the computational efficiency of the new combined scheme at various stages of the optimization. In the early stages, when the element orders are low, the scheme is able to attain similar cost function reductions as the high-order analysis, with computational savings up to a factor of 25. Even in the late stages, when the accuracy is more stringent, the scheme manages a reduction in cumulative computation time of at least a factor of 4.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 1990.
Thesis Advisor(s): Myers, Glen. Second Reader: Ha, Tri. "September 1990." Description based on title screen as viewed on December 21, 2009. DTIC Identifiers: Direct sequence spread spectrum, data clocks, delay lock loops, sequence generators. Author(s) subject terms: Direct-sequence spread spectrum, communications, data clock recovery, M-sequence, delay-lock loop, spread spectrum, binary sequence generation. Includes bibliographical references (p. 40). Also available in print.

Cette thèse explore les possibilités algorithmiques offertes par la synthèse de haut niveau de circuits dans le cadre de la logique synchrone et à destination d'une Mémoire Active Programmable. Une chaîne de compilation expérimentale permettant de générer automatiquement un circuit reconfigurable à partir d'une spécification de haut niveau y est présentée. Le langage de haut niveau est DSL (Design Source Language). DSL est basé sur le langage fonctionnel Jazz. DSL permet de décrire tout type de circuit dans le modèle de la logique synchrone, d'en faire la simulation et la synthèse, puis de l'exécuter sur une Mémoire Active Programmable. Le compilateur procède par étapes successives pour synthétiser un circuit à partir de son code-source de haut niveau. Chacune des étapes de la compilation génère des annotations qui précisent les propriétés du circuit jusqu'à une forme synthétisable. Les annotations sont pour la plupart ajoutées automatiquement par le compilateur mais sont partie intégrante de la syntaxe de DSL et peuvent ainsi être précisées par le concepteur. DSL prend en charge la génération automatique de l'ensemble des routines systèmes qui permettent au circuit de communiquer avec son hôte. Ce système de prototypage et d'accélération matérielle automatique sur PAM est testé sur des circuits variés, comme des algorithmes de tramage, d'estimation de mouvement et de détection des points de Harris.

Future opportunities for gigascale integration will be governed by a hierarchy of theoretical and practical limits that can be codified as follows: fundamental, material, device, circuit, and system. An exponential increase in on-chip integration is driving System-on-Chip (SoC) methodologies as a dominant design solution for gigascale ICs. Therefore, a second generation generic systems simulator (GENESYS) is developed to address a need for rapid assessment of technology/architecture tradeoffs for multi-billion transistor SoCs while maintaining the depth of core modeling codified in the hierarchy of limits. A newly developed system methodology incorporates a hiearchical block-based model, a dual interconnect distribution for both local and global interconnects, a generic on-chip bus model, and cell placement algorithms. A comparison of simulation results for five commercial SoC implementations shows increased accuracy in predicting die size, clock frequency, and total power dissipation. ITRS projections for future technology requirments are applied with results indicating that increasing static power dissipation is a key impediment to making continued improvements in chip performance. Additionally, simulations of a generic chip multi-processor architecture utilizing several interconnect schemes shows that the most promising candidate for the future of on-chip global interconnect networks will be hierarchical bus structures providing a high degree of connectivity while maintaining high operating frequencies.

Dans la cryptographie à clé privée l'arithmétique joue un rôle important. En particulier, l'arithmétique des corps finis doit être très rapide étant donnée la quantité de calculs effectués en nécessitant des ressources limitées (surface de circuit, taille mémoire, consommation d'énergie) mais aussi tout en offrant un bon niveau de robustesse vis à vis des attaques physiques. L'objectif de cette thèse etait d'étudier, comparer, concevoir en matériel et enfin de valider expérimentalement et théoriquement des opérateurs arithmétiques matériels pour la cryptographie sur courbes elliptiques (ECC) sur des extensions du corps fini binaire (GF(2m)) à la fois performants, peu gourmands en énergie et robustes d'un point de sécurité contre les attaques physiques par canaux cachés (p.ex. mesure de la consommation d'énergie). Des travaux effectues aboutissent à la proposition d'opérateurs de multiplication performants (rapides, surface de circuit limitée) dans une architecture modulaire (pouvant être adaptée à des besoins spécifiques sans perte de performance). Les calculs requis par ces opérateurs sont complexes car les éléments du corps sont grands (160-580 bits) et la multiplication s'effectue modulo un polynôme irréductible. En plus la thèse presente des modification et l'optimisation des opérateurs pour les rendre plus robustes à certaines attaques par canaux cachés (de type mesure de consommation) sans perte de performance. Sécurisation d'opérateurs arithmétiques pour ECC au niveau des calculs sur le corps fini est particulièrement intéressant car c'est la première proposition de ce type. Ce travail complète un état de l'art en protections aux niveaux supérieurs (courbes, protocoles).

With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations. As IoT advances, privacy and security issues become top tier concerns in addition to the high performance requirement of embedded chips. To leverage limited resources for tiny size chips and overhead cost for complex security mechanisms, we further proposed an advanced IBUS architecture to provide a structural support for the block-based AES algorithm. Our results show that the IBUS based AES-encrypted design costs less in terms of hardware resource and dynamic energy (60.2%), and achieves higher throughput (x1.6) compared with AXI. Effectively dealing with the automation in design and verification for mixed-signal integrated circuits is a critical problem, particularly when the bus architecture is new. Therefore, we further proposed a configurable and synthesizable IBUS design methodology. The flexible structure, together with bus wrappers, direct memory access (DMA), AES engine, memory controller, several mixed-signal verification intellectual properties (VIPs), and bus performance models (BPMs), forms the basic for integrated circuit design, allowing engineers to integrate application-specific modules and other peripherals to create complex SoCs.

Une carte électronique a été réalisée à l'Institut de chimie et physique industrielles de Lyon utilisant quatre processeurs à architecture à flot de données et programmable liant ainsi puissance et souplesse d'utilisation. Pour valider cette architecture pour le traitement et l'analyse d'image, l'approche a été double : - mise en oeuvre d'algorithme à la fois coûteux et originaux scientifiquement : algorithme de Danielson, suppression de flou, reconstruction 3D. - implantation sur site industriel avec prise en compte des contraintes de temps et intégration dans une chaine complète de contrôle

Cette these propose un algorithme original de construction hierarchique d'arbres de steiner ainsi qu'une technique d'estimation de longueur au fur et a mesure de cette construction. Deux algorithmes de partitionnement d'hypergraphes, de maniere gloutonne ou par recuit simule sans rejets, y sont exposes. Elle introduit enfin un concept de directions d'attraction permettant d'effectuer un placement routage de circuits vlsi, a implanter sur des reseaux prediffuses, sous forme de systeme regule par retroaction entre le placement, le routage et l'analyse temporelle, afin d'obtenir du circuit, par un placement-routage adequat, les performances temporelles souhaitees

L'avènement des puces multicœurs repose certaines questions quant aux moyens d'écrire les programmes, qui doivent alors intégrer un degré élevé de parallélisme. Nous abordons cette question par l'intermédiaire de deux points de vue orthogonaux. Premièrement via le paradigme du vol de travail, pour lequel nous effectuons une étude visant d'une part à rechercher quelles sont les caractéristiques architecturales simples donnant les meilleures performances pour une implémentation de ce paradigme ; et d'autre part à montrer que le surcout par rapport à une parallélisation statique est faible tout en permettant des gains en performances grâce à l'équilibrage dynamique des charges. Cette question est néanmoins surtout abordée via le paradigme de programmation à base de transactions , ensemble d'instructions s'exécutant de manière atomique du point de vue des autres cœurs. Supporter cette abstraction nécessite l'implantation d'un système dit TM, souvent complexe, pouvant être logiciel ou matériel. L'étude porte premièrement sur la comparaison de systèmes TM matériels basés sur des choix architecturaux différents (protocole de cohérence de cache), puis sur l'impact d'un point de vue performances de plusieurs politiques de résolution des conflits, autrement dit des actions à prendre quand deux transactions essaient d'accéder simultanément les mêmes données
The arrival of multiprocessor chips rises again some questions about the way of writing programs, which must then include a high degree of parallelism. We tackle this problem via two orthogonal approaches. First, via the work-stealing paradigm, for which we perform a study targeting on the first hand to seek for simple architectural characteristics giving the best performances for an implementation of this paradigm; and on the second hand to show that the overhead compared to a static parallelization is low, while allowing performances improvement thanks to dynamic load balancing. This question is nevertheless especially tackled via the transaction based programming paradigm , sequence of instructions executing atomically from the other cores' point of view. Supporting this abstraction requires the implementation of a system called TM, often complex, either software or hardware. The study focuses first on the comparison between two hardware TM systems based on different architecture choices (cache coherence protocol), and then on the impact on performances of several conflict resolution policies, in other words the actions to be taken when two or more transactions try to access the same pieces of data

Ce travail se place dans le contexte de la conception, la modélisation et la simulation de systèmes hétérogènes contenant a la fois des capteurs, des composants analogiques, des composants numériques et des circuits RF.La seule manière de simuler un système avec une telle complexité avec un temps de simulation raisonnable est de faire une modélisation haut niveau.Cependant, pour que ce modèle haut niveau soit fiable, les modèles des blocs analogiques et RF doivent contenir une description précise des leurs imperfections.Dans ce travail nous proposons une méthode systématique pour la caractérisation et le raffinement des modèles des blocs analogiques et RF.Cette méthode est réalisée dans un environnement C++ base sur: - l'outil de simulation haut niveau SystemC-AMS- l'outil de résolution d'expression symbolique GiNaC- l'outil de synthèse de circuits intégrés analogique CAIRO+/CHAMSPour illustrer la validité de la méthode proposée, nous présenterons le modèle d'un nœud d'un réseau de capteurs sans fil avec une caractérisation automatique de certains blocs analogiques et RF.Les points suivant résument les contributions apportées pour ce travail.- La première implémentation d'un modèle analogique numérique mixte complexe avec le langage SystemC AMS: un nœud de réseau de capteurs sans fil.- L'introduction du raffinement pour une approche générique des modèles au niveau système.- Un outil d'évaluation précise des performances linéaires et non-linéaires des circuit analogiques pour le raffinement des modèles niveau système et l'optimisation de la conception niveau circuit.- Une méthodologie de conception niveau circuit basée sur des outils de dimensionnement et d'évaluation des performances avec précision.- Un environnement de conception multi-niveaux unifiée appliqué aux systèmes mixtes avec une très forte interaction entre la simulation niveau système et la conception optimisée niveau circuit.

La conception de l'appareillage électrique relève dune méthodologie généralement fort complexe. Les problèmes posés par la conception de l'appareillage électrique sont analysés et montrent l'inefficacité des méthodes mathématiques. Une approche ensembliste floue est exposée et permet de modéliser l'aspect heuristique du problème ainsi que les aspects scientifiques et industriels de la conception. Un système expert d'aide à la conception des disjoncteurs à arc tournant a été réalisé. Les résultats obtenus sont commentés et montrent l'intérêt d'une telle approche

Multi functional health monitoring wearable devices are quite prominent these days. Usually these devices are battery-operated and consequently are limited by their battery life (from few hours to a few weeks depending on the application). Of late, it was realized that these devices, which are currently being operated at fixed voltage and frequency, are capable of operating at multiple voltages and frequencies. By switching these voltages and frequencies to lower values based upon power requirements, these devices can achieve tremendous benefits in the form of energy savings. Dynamic Voltage and Frequency Scaling (DVFS) techniques have proven to be handy in this situation for an efficient trade-off between energy and timely behavior. Within imec, wearable devices make use of the indigenously developed MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). This system is optimized for efficient and accurate collection, processing, and transfer of data from multiple (health) sensors. MUSEIC v2 has limited means in controlling the voltage and frequency dynamically. In this thesis we explore how traditional DVFS techniques can be applied to the MUSEIC v2. Experiments were conducted to find out the optimum power modes to efficiently operate and also to scale up-down the supply voltage and frequency. Considering the overhead caused when switching voltage and frequency, transition analysis was also done. Real-time and non real-time benchmarks were implemented based on these techniques and their performance results were obtained and analyzed. In this process, several state of the art scheduling algorithms and scaling techniques were reviewed in identifying a suitable technique. Using our proposed scaling technique implementation, we have achieved 86.95% power reduction in average, in contrast to the conventional way of the MUSEIC v2 chip’s processor operating at a fixed voltage and frequency. Techniques that include light sleep and deep sleep mode were also studied and implemented, which tested the system’s capability in accommodating Dynamic Power Management (DPM) techniques that can achieve greater benefits. A novel approach for implementing the deep sleep mechanism was also proposed and found that it can obtain up to 71.54% power savings, when compared to a traditional way of executing deep sleep mode.
Nuförtiden så har multifunktionella bärbara hälsoenheter fått en betydande roll. Dessa enheter drivs vanligtvis av batterier och är därför begränsade av batteritiden (från ett par timmar till ett par veckor beroende på tillämpningen). På senaste tiden har det framkommit att dessa enheter som används vid en fast spänning och frekvens kan användas vid flera spänningar och frekvenser. Genom att byta till lägre spänning och frekvens på grund av effektbehov så kan enheterna få enorma fördelar när det kommer till energibesparing. Dynamisk skalning av spänning och frekvens-tekniker (såkallad Dynamic Voltage and Frequency Scaling, DVFS) har visat sig vara användbara i detta sammanhang för en effektiv avvägning mellan energi och beteende. Hos Imec så använder sig bärbara enheter av den internt utvecklade MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). Systemet är optimerat för effektiv och korrekt insamling, bearbetning och överföring av data från flera (hälso) sensorer. MUSEIC v2 har begränsad möjlighet att styra spänningen och frekvensen dynamiskt. I detta examensarbete undersöker vi hur traditionella DVFS-tekniker kan appliceras på MUSEIC v2. Experiment utfördes för att ta reda på de optimala effektlägena och för att effektivt kunna styra och även skala upp matningsspänningen och frekvensen. Eftersom att ”overhead” skapades vid växling av spänning och frekvens gjordes också en övergångsanalys. Realtidsoch icke-realtidskalkyler genomfördes baserat på dessa tekniker och resultaten sammanställdes och analyserades. I denna process granskades flera toppmoderna schemaläggningsalgoritmer och skalningstekniker för att hitta en lämplig teknik. Genom att använda vår föreslagna skalningsteknikimplementering har vi uppnått 86,95% effektreduktion i jämförelse med det konventionella sättet att MUSEIC v2-chipets processor arbetar med en fast spänning och frekvens. Tekniker som inkluderar lätt sömn och djupt sömnläge studerades och implementerades, vilket testade systemets förmåga att tillgodose DPM-tekniker (Dynamic Power Management) som kan uppnå ännu större fördelar. En ny metod för att genomföra den djupa sömnmekanismen föreslogs också och enligt erhållna resultat så kan den ge upp till 71,54% lägre energiförbrukning jämfört med det traditionella sättet att implementera djupt sömnläge.

在過去的十年裡，隨著便攜式通訊，電腦與消費電子市場的快速發展，以及在超大規模積體電路中，越來越多的功能實現被轉移到數字領域中，這些都引起了人們對模數轉換器研究的極大關注。
基於過採樣與量化誤差整形技術，ΣΔ模數轉換器對與類比電路中的非理想特性具有很強的容忍度。然而，爲了優化其在功耗，硅片面積與上市時間等方面的性能，ΣΔ模數轉換器的設計需要對眾多實際問題做出折中考慮。本文在不同的設計層次上提出了一些創新，包括算法，架構及電路設計，從而提升其在通訊，語音與傳感等應用領域中的性能指標。
本文第一部份提出的新技術主要解決運用於低中頻無線接收器中開關電容型正交帶通ΣΔ模數轉換器的I/Q通道的不匹配問題。這些I/Q通道的不匹配將導致位於臨近信道的鏡像信號，自鏡像信號及量化噪聲混疊至輸入信道，從而降低模數轉換器的動態範圍。為此，本文提出了一種新的動態單元匹配技術與一種雙線性技術來解決上述問題。同時通過在I/Q信道間複用運算放大器，比較器與數模轉換器，芯片的面積得到了大幅的降低。基於以上技術，在0.18微米CMOS工藝上設計實現了開關電容型正交帶通ΣΔ模數轉換器的測試樣片，其鏡像抑制比可達到73dB，這是迄今為止公開發表論文中報告的最高值。
在本文的第二部份，我們關注ΣΔ模數轉換器在音頻領域的應用。其對動態範圍與功耗提出的較高要求為級聯型連續時間ΣΔ模數轉換器帶來了機遇。然而，相比于單環型，級聯型連續時間ΣΔ模數轉換器對於電阻-電容時間常數的偏離及有限的運放低頻增益等非理想特性表現得更加敏感，因為這些不理想因素將影響量化噪聲在模擬與數字路徑中的精確抵消。為此，我們提出了使用脈寬調製技術來對片上的電阻-電容時間常數進行自動調整。基於脈寬調製技術，我們可以使用在離散時間電路中常用的相關雙採樣技術來提高運放的有效低頻增益。同時我們提出了一種有限運放帶寬補償技術來節省芯片的功耗。另外，本文對基於連續時間ΣΔ模數轉換器的脈寬調製技術，相關雙採用技術，反混疊濾波，噪聲與抖動效應等方面均做出了詳盡的仿真與分析。最後我們對一顆基於0.18微米CMOS工藝設計的樣片進行了測試。測試結果表明，採用本文提出的技術可以將ΣΔ模數轉換器的動態範圍提高28dB以上。
本文的第三部份展示了一種可用於單端或差分電容傳感器的高精度電容-數字轉換器。在傳統的電容-數字轉換器中，由電容底板開關引入的電荷注入與數字輸出結果及被感知電容的容值有關。當被感知電容的容值變化範圍較大時，這些電荷注入將產生很大的非線性。對此本文提出了一種新的開關控制與校準算法。我們對一顆基於0.18微米CMOS工藝設計的二階電容-數字轉換器樣片進行了測試。測試結果表明，其在0.5毫秒的測試時間內可達到53.2aFrms的精度。同時本文提出的技術可以在0.5pF至3.5pF的較寬電容範圍內，使得電容-數字轉換器在單端電容傳感模式下的線性度（準確度）從9.3位提高至12.3位；在差分電容傳感模式下的線性度（準確度）從10.1位提高至13.3位。最後，本文對連接微機電電容型壓力傳感器和加速度傳感器的實際應用情境進行了測試。
The rapid growth of the market for portable, battery operated systems for communications, computer and consumer electronics (3C), and the trend of moving functionality to the digital domain in very large scale integration (VLSI) systems have resulted in an enormously increasing interest in analog-to-digital converter (ADC) design.
Combining both oversampling and quantization error shaping techniques, delta sigma (ΔΣ) ADCs achieve a high degree of insensitivity to analog circuit imperfections. Nevertheless, the design of CMOS ΔΣ ADCs involves a number of practical issues and trade-offs that must be taken into account in order to optimize their performance in terms of power consumption, silicon area, and time-to-market deployment. This thesis proposes a number of novel performance-enhancement techniques on different design levels, including algorithm, architecture and circuit level, for ΔΣ ADCs in various application circumstances, such as telecom, audio, sensor, and so on.
First, novel techniques are proposed to mitigate I/Q mismatches in switched-capacitor quadrature bandpass Delta-Sigma modulators (DSMs) used in low-IF wireless receivers. The I/Q mismatches result in a nearby channel at the image frequency, the mirrored image of the desired signal around its center frequency (self-image) and the quantization noise to corrupt the desired signal, degrading the dynamic range of the modulator. A dynamic element matching scheme and a bilinear scheme are the proposed solution to reduce all the above-mentioned I/Q mismatch effects. Furthermore, a multiplexing scheme for the sharing of op-amps, quantizers and DACs between the I and Q channels is investigated for smaller chip area. A prototyping DSM was designed and fabricated in a 0.18 ưm CMOS, measuring an image rejection ratio of 73 dB, being the best reported.
Second, a pulse-width-modulation (PWM) technique is proposed for on-chip automatic RC time constant tuning for cascaded continuous-time (CT) DSMs for audio application. The demand for high signal-to-noise-plus-distortion ratio (SNDR) and low power brings a wealth of opportunities to the CT DSMs. In CT DSMs, cascading low-order stages provides an effective way to achieve stable high-order modulation. However, compared to CT single-loop modulators, CT cascaded modulators are more sensitive to variation of RC time constant and finite dc gain of the opamps as these nonidealities affect the precise cancellation of the quantization noises between the analog and digital paths. In the CT cascaded modulator presented here, we propose to apply a PWM technique for on-chip automatic RC time constant tuning. The application of PWM in turn enables the use of the correlated double sampling (CDS) technique, which is conventionally confined to discrete-time circuits, to boost the effective dc gain. The PWM further allows the use of a finite-opamp-bandwidth compensation technique for power saving. Analysis on PWM tuning, CDS, anti-aliasing filtering, noise and jitter in the CT modulator are presented and verified with extensive simulations. Measurement results on a prototype CT cascaded 2-2 DSM in a 0.18ưm CMOS show that the proposed techniques can improve the dynamic range (DR), SNDR and spurious-free dynamic range (SFDR) of the modulator by at least 28 dB.
Third, a high-precision capacitance-to-digital converter (CDC) is proposed, which can be configured to interface with single-ended or differential capacitive sensors. In the conventional CDC, charge injection from bottom-plate switches depends on the digital output and the value of the sensing capacitor. Nonlinearity is resulted especially when the varying ranging of the sensing capacitor is wide. In this thesis, new switching and calibration schemes are proposed to reduce these charge injection. A prototyping 2nd order CDC employing the proposed techniques is fabricated in a 0.18ưm CMOS process and achieves a 53.2aFrms resolution in a 0.5ms measuring time. The proposed techniques improve the CDC's linearity from 9.3 bits to 12.3 bits in the single-ended sensing mode, and from 10.1 bits to 13.3 bits in the differential sensing mode, with a wide sensing capacitor range from 0.5 to 3.5pF. The CDC is also demonstrated with real-life pressure (single-ended) and acceleration (differential) sensors.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Li, Bing.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2013.
Includes bibliographical references.
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstracts also in Chinese.
Abstracts of thesis entitled: --- p.I
摘 要 --- p.V
Contents --- p.VII
List of Figures --- p.XI
List of Tables --- p.XVI
Acknowledgement --- p.XVII
Chapter CHAPTER 1. --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Original contributions and outline of the thesis --- p.2
References --- p.1
Chapter CHAPTER 2. --- A High Image-Rejection SC Quadrature Bandpass DSM for Low-IF Receivers --- p.3
Chapter 2.1 --- Mismatch in Complex Gain Blocks --- p.6
Chapter 2.2 --- Mismatches in QBDSM --- p.8
Chapter 2.3 --- Proposed High Image-Rejection QBDSM --- p.13
Chapter 2.3.1 --- Technique to remove I/Q mismatches in the first complex resonator (for P1 in Fig. 2.6) --- p.13
Chapter 2.3.2 --- Technique to remove I/Q mismatches in the Feedback DAC (for B in Fig. 2.6) --- p.19
Chapter 2.3.3 --- Technique to remove I/Q mismatches in the Input Coefficient (for A1 in Fig. 2.6) --- p.20
Chapter 2.3.4 --- Summary and Simulation Results --- p.27
Chapter 2.4 --- I/Q Multiplexing Schemes and Circuit Implementation of the QBDSM --- p.34
Chapter 2.5 --- Measurement Results Analysis --- p.40
Chapter 2.6 --- Conclusions --- p.47
Chapter APPENDIX I: --- I/Q MISMATCHES IN LOW-IF RECEIVERS --- p.48
Chapter A. --- I/Q Mismatch in Mixer --- p.48
Chapter B. --- I/Q Mismatch in Polyphase Filter --- p.49
Chapter C. --- I/Q Mismatch in QBDSM --- p.50
Chapter D. --- I/Q Imbalance Analysis for whole receiver --- p.51
Chapter APPENDIX II: --- IRR Measurement Method --- p.52
References --- p.56
Chapter CHAPTER 3. --- A Continuous-time Cascaded Delta-Sigma Modulator with PWM-Based Automatic RC Time Constant Tuning and Correlated Double Sampling --- p.59
Chapter 3.1 --- PWM for on-chip RC Time Constant Tuning --- p.61
Chapter 3.1.1 --- Integrator Gain Error --- p.64
Chapter 3.1.2 --- Automatic Generation of PWM Clock --- p.65
Chapter 3.1.3 --- Modulator Architecture --- p.66
Chapter 3.1.4 --- Anti-aliasing Filtering --- p.68
Chapter 3.1.5 --- Noise Analysis --- p.69
Chapter 3.2 --- Proposed SRMC Integrator with CDS --- p.71
Chapter 3.2.1 --- Analysis on the opamp gain enhancement --- p.73
Chapter 3.2.2 --- Simulation Results --- p.75
Chapter 3.3 --- Compensation for Finite-Opamp-Bandwidth-Induced Error --- p.76
Chapter 3.3.1 --- Compensation for fininte opamp bandwidth --- p.77
Chapter 3.3.2 --- Behavorial Simulation Results --- p.79
Chapter 3.4 --- Jitter Analysis --- p.80
Chapter 3.4.1 --- Jitter on Rising Edges --- p.81
Chapter 3.4.2 --- Duty cycle jitter --- p.84
Chapter 3.5 --- Prototyping Modulator Design --- p.85
Chapter 3.6 --- Measurement Results --- p.89
Chapter 3.7 --- Summary --- p.95
References --- p.97
Chapter CHAPTER 4. --- A High-Linearity Capacitance to Digital Converter with Techniques Suppressing Charge Injection from Bottom-Plate Switches --- p.105
Chapter 4.1 --- Introduction --- p.105
Chapter 4.2 --- Proposed CDC Switching and Calibration Schemes --- p.107
Chapter 4.2.1 --- Single-Ended Sensing Mode --- p.107
Chapter 4.2.2 --- Differential Sensing Mode --- p.111
Chapter 4.3 --- Circuit Implementation --- p.114
Chapter 4.4 --- Measurement Results --- p.117
Chapter 4.5 --- Conclusion --- p.125
Chapter APPENDIX: The cross section of NPN transistor in triple-well CMOS process --- p.126
References --- p.127
Chapter CHAPTER 5. --- Conclusions and future works --- p.129
Chapter 5.1 --- Conclusions --- p.129
Chapter 5.2 --- Future works --- p.130
Chapter APPENDIX: --- A typical CMOS fabrication process flow (1 poly/2 M, twin well CMOS) --- p.131

Bibliography :p.269-285.
xxii, 285 p. : ill. ; 30 cm.
Describes a new method for describing asynchronous systems (free-flow asynchronism). The method is demonstrated through two applications ; a channel signalling system and amedo.
Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1998

Achieving high performance is one of the most difficult challenges in designing digital circuits. Flip-flops and adders are key blocks in most digital systems and must therefore be designed to yield highest performance. In this thesis, a new high performance serial adder is developed while power consumption is attained. Also, a statistical framework for the design of flip-flops is introduced that ensures that such sequential circuits meet timing yield under performance criteria. Firstly, a high performance serial adder is developed. The new adder is based on the idea of having a constant delay for the addition of two operands. While conventional adders exhibit logarithmic delay, the proposed adder works at a constant delay order. In addition, the new adder's hardware complexity is in a linear order with the word length, which consequently exhibits less area and power consumption as compared to conventional high performance adders. The thesis demonstrates the underlying algorithm used for the new adder and followed by simulation results. Secondly, this thesis presents a statistical framework for the design of flip-flops under process variations in order to maximize their timing yield. In nanometer CMOS technologies, process variations significantly impact the timing performance of sequential circuits which may eventually cause their malfunction. Therefore, developing a framework for designing such circuits is inevitable. Our framework generates the values of the nominal design parameters; i.e., the size of gates and transmission gates of flip-flop such that maximum timing yield is achieved for flip-flops. While previous works focused on improving the yield of flip-flops, less research was done to improve the timing yield in the presence of process variations.

碩士
南台科技大學
電子工程系
91
Wireless LAN IEEE 802.11a, which uses orthogonal frequency division multiplexing (OFDM), offers different communication data rates through 6 to 54 Mbps depended on different modulation techniques. OFDM signal is more sensitive to timing error, frequency offset, nonlinear effect of power amplifier and phase noise in oscillator. This thesis first studies the performance evaluation of the influences by timing error and frequency offset in OFDM system, and then presents detailed analysis and computer simulation by MATLAB for nonlinear effect of power amplifier and phase noise in oscillator. In the simulation of nonlinear effect of power amplifier, the power gain is assumed to be 11.5 dB and the OIP3 is 28.5 dB. If the input power of the amplifier is equal to 4 dBm, the EVM is about 7.5 %; while the input power is changed to 7 dBm, the EVM becomes 17.2 %. It can be seen that the nonlinear effect causes more EVM when driving power increases. For the simulation of phase noise, we concern the influence of ICI error using EVM and BER. In the EVM simulation, if the phase noise is equal to -90 dBc/Hz@100 kHz, the EVM is about 0.9 %; while the phase noise increases to -70 dBc/Hz, the EVM increases to 8.7 %. In the BER simulation, if BER=10-3 with AWGN channel is required in a system planning and the phase noise is -70 dBc/Hz@100 kHz, for the case of the OFDM/QPSK signal which needs about 0.5 dB more Eb/No than that without counting in phase noise. While for the case of the OFDM/16-QAM signal, more 2.2 dB Eb/No is required. It is concluded that higher transmitter power will be requested with larger value of M in M-ary QAM. These results are very useful for RF circuit/system designers in OFDM system.

by Vincent Wing-Shing Tse.
Thesis submitted in: December 1997.
Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.
Includes bibliographical references (leaves 62-[64]).
Abstract also in Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 2 --- Principles of Multirate Circuit Switching in Quantized Clos Network --- p.10
Chapter 2.1 --- Formulation of Multirate Circuit Switching --- p.11
Chapter 2.2 --- Call Level Routing in Quantized Clos Network --- p.12
Chapter 2.3 --- Cell Level Routing in Quantized Clos Network --- p.16
Chapter 2.3.1 --- Traffic Behavior in ATM Network --- p.17
Chapter 2.3.2 --- Time Division Multiplexing in Multirate Circuit Switching and Cell-level Switching in ATM Network --- p.19
Chapter 2.3.3 --- Cell Transmission Scheduling --- p.20
Chapter 2.3.4 --- Capacity Allocation and Route Assignment at Cell-level --- p.29
Chapter 3 --- Performance Evaluation of Different Implementation Schemes --- p.31
Chapter 3.1 --- Global Control and Distributed Switching --- p.32
Chapter 3.2 --- Implementation Schemes of Quantized Clos Network --- p.33
Chapter 3.2.1 --- Classification of Switch Modules --- p.33
Chapter 3.2.2 --- Bufferless Switch Modules Construction Scheme --- p.38
Chapter 3.2.3 --- Buffered Switch Modules Construction Scheme --- p.42
Chapter 3.3 --- Complexity Comparison --- p.44
Chapter 3.4 --- Delay Performance of The Two Implementation Schemes --- p.47
Chapter 3.4.1 --- Assumption --- p.47
Chapter 3.4.2 --- Simulation Result --- p.50
Chapter 4 --- Conclusions --- p.59
Bibliography --- p.62

碩士
南台科技大學
電子工程系
92
Orthogonal frequency division multiplexing (OFDM) is a promising transmission technology for high data rate communications in the future. However, the OFDM signal is more sensitive to the nonlinear effect of power amplifier, phase noise in oscillator and I-Q imbalance. Therefore, this thesis presents detailed analysis and the computer simulation by Matlab for above three imperfect effects. First, we study the improvement by the clipping method to IEEE 802.11a standard with nonlinear power amplifier and predict the error vector magnitude (EVM) by computer simulation. Secondly, we concern the influence of the I-Q imbalance in an OFDM receiver. The receiver architectures, such as direct conversion, super-heterodyne and low-IF, may be used for the front-end in an OFDM system. The direct conversion architecture will become popular since it offers one important advantage over a heterodyne counterpart, that is, the problem of image is circumvented and no image filter is required. However, this approach suffers from some impacts such as DC offset and I-Q imbalance. The second part in this thesis, we try to analyze the influence of I-Q imbalance with IEEE 802.11a standard. Finally, we focus on the phase noise. The considerations of the distortion can be separated into two parts, the common phase error and the ICI error. The former can be corrected by the pilot, so we only consider the effect of the ICI error. The simulation is based on the multi-band OFDM system, which is made by the UWB standard committee (802.15.3a task group) in 2003 and may be adopted as UWB communication standard. These simulation methods and numerical results are very useful for RF circuit/system designers in OFDM system.