Dissertations / Theses on the topic 'Computers – Circuits – Performance'
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Md, Ali Sawal Hamid. "System level performance and yield optimisation for analogue integrated circuits." Thesis, University of Southampton, 2009. https://eprints.soton.ac.uk/69724/.
Full textShahidipour, Hamed. "A study on the effects of variability on performance of CNFET based digital circuits." Thesis, University of Southampton, 2012. https://eprints.soton.ac.uk/364216/.
Full textLowe, Jeffrey. "A high-performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks." Online access for everyone, 2004. http://www.dissertations.wsu.edu/Thesis/Summer2004/j%5Flowe%5F072104.pdf.
Full textBingham, Philip R. "The effect of message length distribution on the performance of fully connected switches." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15389.
Full textAppleton, Samuel Scott. "Performance-directed design of asynchronous VLSI systems /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09pha651.pdf.
Full textKhasawneh, Shadi Turki. "Low-power high-performance register file design for chip multiprocessors." Diss., Online access via UMI:, 2006.
Find full textSerrano, Guillermo J. "High Performance Analog Circuit Design Using Floating-Gate Techniques." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19819.
Full textQiao, Hao. "Sparse hierarchical model order reduction for high speed interconnects." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:8881/R/?func=dbin-jump-full&object_id=32359.
Full textMa, Albert. "Circuits for high-performance low-power VLSI logic." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37906.
Full textIncludes bibliographical references (p. 85-88).
The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two. PSSL is better than domino in terms of energy and robustness, and is better than static CMOS in terms of delay. PSSL works by partially overlapping the execution of consecutive iterations through speculative evaluation. This is accomplished by presetting nodes at register boundaries before input arrival.
by Albert Ma.
Ph.D.
Weyer, Daniel J. "TRADEOFFS BETWEEN PERFORMANCE AND RELIABILITY IN INTEGRATED CIRCUITS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=case155508829933554.
Full textRahman, Arifur 1970. "System-level performance evaluation of three-dimensional integrated circuits." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8760.
Full textIncludes bibliographical references (p. 173-187).
As the critical dimensions in VLSI design continue to shrink, system performance of integrated circuits (ICs) will be increasingly dominated by interconnect delay [1]. For the technology generations approaching 50 nm and beyond, innovative system architectures and interconnect technologies will be required to meet the projected system performance [2]. Interconnect material solutions such as copper and low-k inter-level dielectric (ILD) offer only a limited improvement in system performance. Significant and scalable solutions to the interconnect delay problem will require fundamental changes in system design, architecture, and fabrication technologies. Three-dimensional (3-D) ICs can alleviate interconnect delay problems by offering flexibility in system design, placement and routing. They (3-D ICs) can be formed by vertical integration of multiple device layers using wafer bonding, recrystallization, or selective epitaxial growth. The flexibility to place devices along the vertical dimension allows higher device density and smaller form factor in 3-D ICs. The critical signal path that may limit system performance can also be shortened to achieve faster clock speed. By 3-D integration, device layers fabricated with different front-end process technologies can be stacked along the 3rd dimension to form systems-on-a-chip [3]. In this thesis work, opportunities and challenges for 3-D integration of logic networks, microprocessors, and programmable logic have been explored based on system-level modeling and analysis. A stochastic wire-length distribution model has been derived to predict interconnection complexity in 3-D ICs. As more device layers are integrated, the 3-D wire-length distribution becomes narrower compared to that of 2-D ICs, resulting in a significant reduction in the number and length of semi-global and global wires. In 3-D ICs with 2-4 device layers, 30% - 50% reduction in wire-length can be achieved. Besides performance modeling, thermal analysis has also been performed to assess power dissipation and heat removal issues in 3-D ICs. The total capacitance associated with signal interconnects and clock networks can be reduced by 3-D integration, leading to lower power dissipation for system performance comparable to that of 2-D ICs. However, for higher system performance in 3-D ICs, power dissipation increases significantly, and it is likely that innovative cooling techniques will be needed for reliable operation of devices and interconnects.
by Arifur Rahman.
Ph.D.
Feero, Brett Stanley. "Three dimensional networks-on-chip a performance evaluation /." Online access for everyone, 2008. http://www.dissertations.wsu.edu/Thesis/Spring2008/b_feero_042208.pdf.
Full textNarendra, Siva G. (Siva Gurusami) 1971. "Effect of MOSFET threshold voltage variation on high-performance circuits." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8341.
Full textIncludes bibliographical references (p. 95-101).
The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in threshold voltage variation due to worsening short channel effect. This thesis will address three specific circuit design challenges arising from increased threshold voltage variation and present prospective solutions. First, with supply voltage scaling, control of die-to-die threshold voltage variation becomes critical for maintaining high yield. An analytical model will be developed for existing circuit technique that adaptively biases the body terminal of MOSFET devices to control this threshold voltage variation. Based on this model, recommendations on how to effectively use the technique in future technologies will be presented. Second, with threshold voltage scaling, sub-threshold leakage power is expected to be a significant portion of total power in future CMOS systems. Therefore, it becomes imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and a circuit technique to reduce system leakage without reducing system performance will be discussed.
(cont.) Finally, due to different processing steps and short channel effects, threshold voltage of devices of same or different polarities in the same neighborhood may not be matched. This will introduce mismatch in the device drive currents that will not be acceptable in some high performance circuits. In the last part of the thesis, voltage and current biasing schemes that minimize the impact of neighborhood threshold voltage mismatch will be introduced.
by Siva G. Narendra.
Ph.D.
Peter, Shaun K. "A Performance Driven Placement System Using an Integrated Timing Analysis Engine." University of Cincinnati / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1406820542.
Full textSchoenfliess, Kory Michael. "Performance Analysis of System-on-Chip Applications of Three-dimensional Integrated Circuits." NCSU, 2006. http://www.lib.ncsu.edu/theses/available/etd-12172005-143909/.
Full textMohan, Nitin. "Low-Power High-Performance Ternary Content Addressable Memory Circuits." Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/2873.
Full textMehrotra, Vikas 1971. "Modeling the effects of systematic process variation of circuit performance." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86666.
Full textRANJAN, MUKESH. "AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496.
Full textPasca, Bogdan Mihai. "Calcul flottant haute performance sur circuits reconfigurables." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2011. http://tel.archives-ouvertes.fr/tel-00654121.
Full textGruener, Charles J. "Design and implementation of a computational cluster for high performance design and modeling of integrated circuits /." Online version of thesis, 2009. http://hdl.handle.net/1850/11204.
Full textMoukarzel, Ibrahim. "Methodologies pour l'optimisation des performances en cao des circuits." Toulouse 3, 1987. http://www.theses.fr/1987TOU30306.
Full textSundararajan, Arjun. "Development of a Computer Model to Simulate Battery Performance For Use In Renewable Energy Simulations." Wright State University / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=wright1622589070614764.
Full textSanchez, Gomez Edgar Gerardo. "Fusion Network Performance: An Integrated Packet/Circuit Hybrid Optical Network." Thesis, KTH, Kommunikationssystem, CoS, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-142652.
Full textAli, Muhammad. "Efficient Methods for Robust Circuit Design and Performance Optimization for Carbon Nanotube Field Effect Transistors." PDXScholar, 2019. https://pdxscholar.library.pdx.edu/open_access_etds/4833.
Full textTiew, Chin-Yaw. "On improving the performance of parallel fault simulation for synchronous sequential circuits." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-03042009-040323/.
Full textHe, Rongsen. "Indirect interconnection networks for high performance routers/switches." Online access for everyone, 2007. http://www.dissertations.wsu.edu/Dissertations/Summer2007/R_He_072307.pdf.
Full textIstoan, Matei Valentin. "High-performance coarse operators for FPGA-based computing." Thesis, Lyon, 2017. http://www.theses.fr/2017LYSEI030/document.
Full textField-Programmable Gate Arrays (FPGAs) have been shown to sometimes outperform mainstream microprocessors. The circuit paradigm enables efficient application-specific parallel computations. FPGAs also enable arithmetic efficiency: a bit is only computed if it is useful to the final result. To achieve this, FPGA arithmetic shouldn’t be limited to basic arithmetic operations offered by microprocessors. This thesis studies the implementation of coarser operations on FPGAs, in three main directions: New FPGA-specific approaches for evaluating the sine, cosine and the arctangent have been developed. Each function is tuned for its context and is as versatile and flexible as possible. Arithmetic efficiency requires error analysis and parameter tuning, and a fine understanding of the algorithms used. Digital filters are an important family of coarse operators resembling elementary functions: they can be specified at a high level as a transfer function with constraints on the signal/noise ratio, and then be implemented as an arithmetic datapath based on additions and multiplications. The main result is a method which transforms a high-level specification into a filter in an automated way. The first step is building an efficient method for computing sums of products by constants. Based on this, FIR and IIR filter generators are constructed. For arithmetic operators to achieve maximum performance, context-specific pipelining is required. Even if the designer’s knowledge is of great help when building and pipelining an arithmetic datapath, this remains complex and error-prone. A user-directed, automated method for pipelining has been developed. This thesis provides a generator of high-quality, ready-made operators for coarse computing cores, which brings FPGA-based computing a step closer to mainstream adoption. The cores are part of an open-ended generator, where functions are described as high-level objects such as mathematical expressions
Dubouix, Pierre. "La conception optimale des circuits en presence de contraintes statistiques." Toulouse 3, 1987. http://www.theses.fr/1987TOU30132.
Full textWang, Lei. "A Performance Evaluation of Dynamic Transport Switching for Multi-Transport Devices." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1603.pdf.
Full textNair, Dileep 1976. "An accuracy controlled combined adaption-optimization scheme for improving the performance of 3D microwave devices over a frequency band /." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=115714.
Full textThis thesis presents a software system that minimizes the return loss of 3D microwave devices over a frequency band efficiently through accuracy control. It combines a custom gradient-based optimizer with a p-adaptive frequency-domain finite element solver. The solver computes the cost function and its gradient to a specified accuracy in a cost efficient manner. The p-adaptive solver comprises of two original components: an a-posteriori error estimator to evaluate the error in the cost function gradient, and an error indicator to identify the high error regions in the mesh. The optimizer controls the accuracy of the cost function evaluation through a link with the solver, specifying the required relative error for the gradient at each optimization step.
The combined adaption-optimization scheme was applied to 3D rectangular waveguide problems for validation: an E-plane miter bend, a U-bend, an impedance transformer and a compensated magic-T. For comparison, all the problems were also optimized using high-order finite elements at every step. Test results prove the computational efficiency of the new combined scheme at various stages of the optimization. In the early stages, when the element orders are low, the scheme is able to attain similar cost function reductions as the high-order analysis, with computational savings up to a factor of 25. Even in the late stages, when the accuracy is more stringent, the scheme manages a reduction in cumulative computation time of at least a factor of 4.
BASU, SHUBHANKAR. "Performance Modeling and Optimization Techniques in the Presence of Random Process Variations to Improve Parametric Yield of VLSI Circuits." University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1209682383.
Full textHarshbarger, Stuart D. "Measured noise performance of a data clock circuit derived from the local M-sequence in direct-sequence spread spectrum systems." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA238335.
Full textThesis Advisor(s): Myers, Glen. Second Reader: Ha, Tri. "September 1990." Description based on title screen as viewed on December 21, 2009. DTIC Identifiers: Direct sequence spread spectrum, data clocks, delay lock loops, sequence generators. Author(s) subject terms: Direct-sequence spread spectrum, communications, data clock recovery, M-sequence, delay-lock loop, spread spectrum, binary sequence generation. Includes bibliographical references (p. 40). Also available in print.
Dandache, Abbas. "Conception de PLA CMOS." Phd thesis, Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37596962j.
Full textNote, Jean-Baptiste. "Compilation automatique pour les FPGAs." Phd thesis, Université Pierre et Marie Curie - Paris VI, 2007. http://tel.archives-ouvertes.fr/tel-00807973.
Full textNugent, Steven Paul. "A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC)." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6885.
Full textPamula, Danuta. "Opérateurs arithmétiques sur GF(2^m): étude de compromis performances - consommation - sécurité." Phd thesis, Université Rennes 1, 2012. http://tel.archives-ouvertes.fr/tel-00767537.
Full textYang, Xiaokun. "A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)." FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2477.
Full textBringer, Yves. "Performances de nouvelles architectures machines pour la mise en oeuvre d'algorithmes de traitement et d'analyse d'image." Saint-Etienne, 1993. http://www.theses.fr/1993STET4024.
Full textZini, Roger. "Placement, routage conjoints et hierarchiques de reseaux prediffuses." Paris 6, 1987. http://www.theses.fr/1987PA066116.
Full textMeunier, Quentin. "Étude de deux solutions pour le support matériel de la programmation parallèle dans les multiprocesseurs intégrés : vol de travail et mémoires transactionnelles." Grenoble, 2010. http://www.theses.fr/2010GRENM067.
Full textThe arrival of multiprocessor chips rises again some questions about the way of writing programs, which must then include a high degree of parallelism. We tackle this problem via two orthogonal approaches. First, via the work-stealing paradigm, for which we perform a study targeting on the first hand to seek for simple architectural characteristics giving the best performances for an implementation of this paradigm; and on the second hand to show that the overhead compared to a static parallelization is low, while allowing performances improvement thanks to dynamic load balancing. This question is nevertheless especially tackled via the transaction based programming paradigm , sequence of instructions executing atomically from the other cores' point of view. Supporting this abstraction requires the implementation of a system called TM, often complex, either software or hardware. The study focuses first on the comparison between two hardware TM systems based on different architecture choices (cache coherence protocol), and then on the impact on performances of several conflict resolution policies, in other words the actions to be taken when two or more transactions try to access the same pieces of data
Vasilevski, Michel. "Environnement de conception multi-niveaux unifiée appliqué aux systèmes mixtes." Phd thesis, Université Pierre et Marie Curie - Paris VI, 2012. http://tel.archives-ouvertes.fr/tel-00836923.
Full textBrassard, Serge. "Méthodologie et modélisation floues des connaissances dans l'activité de conception en électrotechnique : application à la réalisation d'un système expert d'aide à la conception de l'appareillage électrique." Grenoble INPG, 1989. http://www.theses.fr/1989INPG0093.
Full textMallangi, Siva Sai Reddy. "Low-Power Policies Based on DVFS for the MUSEIC v2 System-on-Chip." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-229443.
Full textNuförtiden så har multifunktionella bärbara hälsoenheter fått en betydande roll. Dessa enheter drivs vanligtvis av batterier och är därför begränsade av batteritiden (från ett par timmar till ett par veckor beroende på tillämpningen). På senaste tiden har det framkommit att dessa enheter som används vid en fast spänning och frekvens kan användas vid flera spänningar och frekvenser. Genom att byta till lägre spänning och frekvens på grund av effektbehov så kan enheterna få enorma fördelar när det kommer till energibesparing. Dynamisk skalning av spänning och frekvens-tekniker (såkallad Dynamic Voltage and Frequency Scaling, DVFS) har visat sig vara användbara i detta sammanhang för en effektiv avvägning mellan energi och beteende. Hos Imec så använder sig bärbara enheter av den internt utvecklade MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). Systemet är optimerat för effektiv och korrekt insamling, bearbetning och överföring av data från flera (hälso) sensorer. MUSEIC v2 har begränsad möjlighet att styra spänningen och frekvensen dynamiskt. I detta examensarbete undersöker vi hur traditionella DVFS-tekniker kan appliceras på MUSEIC v2. Experiment utfördes för att ta reda på de optimala effektlägena och för att effektivt kunna styra och även skala upp matningsspänningen och frekvensen. Eftersom att ”overhead” skapades vid växling av spänning och frekvens gjordes också en övergångsanalys. Realtidsoch icke-realtidskalkyler genomfördes baserat på dessa tekniker och resultaten sammanställdes och analyserades. I denna process granskades flera toppmoderna schemaläggningsalgoritmer och skalningstekniker för att hitta en lämplig teknik. Genom att använda vår föreslagna skalningsteknikimplementering har vi uppnått 86,95% effektreduktion i jämförelse med det konventionella sättet att MUSEIC v2-chipets processor arbetar med en fast spänning och frekvens. Tekniker som inkluderar lätt sömn och djupt sömnläge studerades och implementerades, vilket testade systemets förmåga att tillgodose DPM-tekniker (Dynamic Power Management) som kan uppnå ännu större fördelar. En ny metod för att genomföra den djupa sömnmekanismen föreslogs också och enligt erhållna resultat så kan den ge upp till 71,54% lägre energiförbrukning jämfört med det traditionella sättet att implementera djupt sömnläge.
"Novel performance enhancement techniques for delta sigma modulators for telecom, audio and sensor applications." 2013. http://library.cuhk.edu.hk/record=b5549777.
Full text基於過採樣與量化誤差整形技術,ΣΔ模數轉換器對與類比電路中的非理想特性具有很強的容忍度。然而,爲了優化其在功耗,硅片面積與上市時間等方面的性能,ΣΔ模數轉換器的設計需要對眾多實際問題做出折中考慮。本文在不同的設計層次上提出了一些創新,包括算法,架構及電路設計,從而提升其在通訊,語音與傳感等應用領域中的性能指標。
本文第一部份提出的新技術主要解決運用於低中頻無線接收器中開關電容型正交帶通ΣΔ模數轉換器的I/Q通道的不匹配問題。這些I/Q通道的不匹配將導致位於臨近信道的鏡像信號,自鏡像信號及量化噪聲混疊至輸入信道,從而降低模數轉換器的動態範圍。為此,本文提出了一種新的動態單元匹配技術與一種雙線性技術來解決上述問題。同時通過在I/Q信道間複用運算放大器,比較器與數模轉換器,芯片的面積得到了大幅的降低。基於以上技術,在0.18微米CMOS工藝上設計實現了開關電容型正交帶通ΣΔ模數轉換器的測試樣片,其鏡像抑制比可達到73dB,這是迄今為止公開發表論文中報告的最高值。
在本文的第二部份,我們關注ΣΔ模數轉換器在音頻領域的應用。其對動態範圍與功耗提出的較高要求為級聯型連續時間ΣΔ模數轉換器帶來了機遇。然而,相比于單環型,級聯型連續時間ΣΔ模數轉換器對於電阻-電容時間常數的偏離及有限的運放低頻增益等非理想特性表現得更加敏感,因為這些不理想因素將影響量化噪聲在模擬與數字路徑中的精確抵消。為此,我們提出了使用脈寬調製技術來對片上的電阻-電容時間常數進行自動調整。基於脈寬調製技術,我們可以使用在離散時間電路中常用的相關雙採樣技術來提高運放的有效低頻增益。同時我們提出了一種有限運放帶寬補償技術來節省芯片的功耗。另外,本文對基於連續時間ΣΔ模數轉換器的脈寬調製技術,相關雙採用技術,反混疊濾波,噪聲與抖動效應等方面均做出了詳盡的仿真與分析。最後我們對一顆基於0.18微米CMOS工藝設計的樣片進行了測試。測試結果表明,採用本文提出的技術可以將ΣΔ模數轉換器的動態範圍提高28dB以上。
本文的第三部份展示了一種可用於單端或差分電容傳感器的高精度電容-數字轉換器。在傳統的電容-數字轉換器中,由電容底板開關引入的電荷注入與數字輸出結果及被感知電容的容值有關。當被感知電容的容值變化範圍較大時,這些電荷注入將產生很大的非線性。對此本文提出了一種新的開關控制與校準算法。我們對一顆基於0.18微米CMOS工藝設計的二階電容-數字轉換器樣片進行了測試。測試結果表明,其在0.5毫秒的測試時間內可達到53.2aFrms的精度。同時本文提出的技術可以在0.5pF至3.5pF的較寬電容範圍內,使得電容-數字轉換器在單端電容傳感模式下的線性度(準確度)從9.3位提高至12.3位;在差分電容傳感模式下的線性度(準確度)從10.1位提高至13.3位。最後,本文對連接微機電電容型壓力傳感器和加速度傳感器的實際應用情境進行了測試。
The rapid growth of the market for portable, battery operated systems for communications, computer and consumer electronics (3C), and the trend of moving functionality to the digital domain in very large scale integration (VLSI) systems have resulted in an enormously increasing interest in analog-to-digital converter (ADC) design.
Combining both oversampling and quantization error shaping techniques, delta sigma (ΔΣ) ADCs achieve a high degree of insensitivity to analog circuit imperfections. Nevertheless, the design of CMOS ΔΣ ADCs involves a number of practical issues and trade-offs that must be taken into account in order to optimize their performance in terms of power consumption, silicon area, and time-to-market deployment. This thesis proposes a number of novel performance-enhancement techniques on different design levels, including algorithm, architecture and circuit level, for ΔΣ ADCs in various application circumstances, such as telecom, audio, sensor, and so on.
First, novel techniques are proposed to mitigate I/Q mismatches in switched-capacitor quadrature bandpass Delta-Sigma modulators (DSMs) used in low-IF wireless receivers. The I/Q mismatches result in a nearby channel at the image frequency, the mirrored image of the desired signal around its center frequency (self-image) and the quantization noise to corrupt the desired signal, degrading the dynamic range of the modulator. A dynamic element matching scheme and a bilinear scheme are the proposed solution to reduce all the above-mentioned I/Q mismatch effects. Furthermore, a multiplexing scheme for the sharing of op-amps, quantizers and DACs between the I and Q channels is investigated for smaller chip area. A prototyping DSM was designed and fabricated in a 0.18 ưm CMOS, measuring an image rejection ratio of 73 dB, being the best reported.
Second, a pulse-width-modulation (PWM) technique is proposed for on-chip automatic RC time constant tuning for cascaded continuous-time (CT) DSMs for audio application. The demand for high signal-to-noise-plus-distortion ratio (SNDR) and low power brings a wealth of opportunities to the CT DSMs. In CT DSMs, cascading low-order stages provides an effective way to achieve stable high-order modulation. However, compared to CT single-loop modulators, CT cascaded modulators are more sensitive to variation of RC time constant and finite dc gain of the opamps as these nonidealities affect the precise cancellation of the quantization noises between the analog and digital paths. In the CT cascaded modulator presented here, we propose to apply a PWM technique for on-chip automatic RC time constant tuning. The application of PWM in turn enables the use of the correlated double sampling (CDS) technique, which is conventionally confined to discrete-time circuits, to boost the effective dc gain. The PWM further allows the use of a finite-opamp-bandwidth compensation technique for power saving. Analysis on PWM tuning, CDS, anti-aliasing filtering, noise and jitter in the CT modulator are presented and verified with extensive simulations. Measurement results on a prototype CT cascaded 2-2 DSM in a 0.18ưm CMOS show that the proposed techniques can improve the dynamic range (DR), SNDR and spurious-free dynamic range (SFDR) of the modulator by at least 28 dB.
Third, a high-precision capacitance-to-digital converter (CDC) is proposed, which can be configured to interface with single-ended or differential capacitive sensors. In the conventional CDC, charge injection from bottom-plate switches depends on the digital output and the value of the sensing capacitor. Nonlinearity is resulted especially when the varying ranging of the sensing capacitor is wide. In this thesis, new switching and calibration schemes are proposed to reduce these charge injection. A prototyping 2nd order CDC employing the proposed techniques is fabricated in a 0.18ưm CMOS process and achieves a 53.2aFrms resolution in a 0.5ms measuring time. The proposed techniques improve the CDC's linearity from 9.3 bits to 12.3 bits in the single-ended sensing mode, and from 10.1 bits to 13.3 bits in the differential sensing mode, with a wide sensing capacitor range from 0.5 to 3.5pF. The CDC is also demonstrated with real-life pressure (single-ended) and acceleration (differential) sensors.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Li, Bing.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2013.
Includes bibliographical references.
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstracts also in Chinese.
Abstracts of thesis entitled: --- p.I
摘 要 --- p.V
Contents --- p.VII
List of Figures --- p.XI
List of Tables --- p.XVI
Acknowledgement --- p.XVII
Chapter CHAPTER 1. --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Original contributions and outline of the thesis --- p.2
References --- p.1
Chapter CHAPTER 2. --- A High Image-Rejection SC Quadrature Bandpass DSM for Low-IF Receivers --- p.3
Chapter 2.1 --- Mismatch in Complex Gain Blocks --- p.6
Chapter 2.2 --- Mismatches in QBDSM --- p.8
Chapter 2.3 --- Proposed High Image-Rejection QBDSM --- p.13
Chapter 2.3.1 --- Technique to remove I/Q mismatches in the first complex resonator (for P1 in Fig. 2.6) --- p.13
Chapter 2.3.2 --- Technique to remove I/Q mismatches in the Feedback DAC (for B in Fig. 2.6) --- p.19
Chapter 2.3.3 --- Technique to remove I/Q mismatches in the Input Coefficient (for A1 in Fig. 2.6) --- p.20
Chapter 2.3.4 --- Summary and Simulation Results --- p.27
Chapter 2.4 --- I/Q Multiplexing Schemes and Circuit Implementation of the QBDSM --- p.34
Chapter 2.5 --- Measurement Results Analysis --- p.40
Chapter 2.6 --- Conclusions --- p.47
Chapter APPENDIX I: --- I/Q MISMATCHES IN LOW-IF RECEIVERS --- p.48
Chapter A. --- I/Q Mismatch in Mixer --- p.48
Chapter B. --- I/Q Mismatch in Polyphase Filter --- p.49
Chapter C. --- I/Q Mismatch in QBDSM --- p.50
Chapter D. --- I/Q Imbalance Analysis for whole receiver --- p.51
Chapter APPENDIX II: --- IRR Measurement Method --- p.52
References --- p.56
Chapter CHAPTER 3. --- A Continuous-time Cascaded Delta-Sigma Modulator with PWM-Based Automatic RC Time Constant Tuning and Correlated Double Sampling --- p.59
Chapter 3.1 --- PWM for on-chip RC Time Constant Tuning --- p.61
Chapter 3.1.1 --- Integrator Gain Error --- p.64
Chapter 3.1.2 --- Automatic Generation of PWM Clock --- p.65
Chapter 3.1.3 --- Modulator Architecture --- p.66
Chapter 3.1.4 --- Anti-aliasing Filtering --- p.68
Chapter 3.1.5 --- Noise Analysis --- p.69
Chapter 3.2 --- Proposed SRMC Integrator with CDS --- p.71
Chapter 3.2.1 --- Analysis on the opamp gain enhancement --- p.73
Chapter 3.2.2 --- Simulation Results --- p.75
Chapter 3.3 --- Compensation for Finite-Opamp-Bandwidth-Induced Error --- p.76
Chapter 3.3.1 --- Compensation for fininte opamp bandwidth --- p.77
Chapter 3.3.2 --- Behavorial Simulation Results --- p.79
Chapter 3.4 --- Jitter Analysis --- p.80
Chapter 3.4.1 --- Jitter on Rising Edges --- p.81
Chapter 3.4.2 --- Duty cycle jitter --- p.84
Chapter 3.5 --- Prototyping Modulator Design --- p.85
Chapter 3.6 --- Measurement Results --- p.89
Chapter 3.7 --- Summary --- p.95
References --- p.97
Chapter CHAPTER 4. --- A High-Linearity Capacitance to Digital Converter with Techniques Suppressing Charge Injection from Bottom-Plate Switches --- p.105
Chapter 4.1 --- Introduction --- p.105
Chapter 4.2 --- Proposed CDC Switching and Calibration Schemes --- p.107
Chapter 4.2.1 --- Single-Ended Sensing Mode --- p.107
Chapter 4.2.2 --- Differential Sensing Mode --- p.111
Chapter 4.3 --- Circuit Implementation --- p.114
Chapter 4.4 --- Measurement Results --- p.117
Chapter 4.5 --- Conclusion --- p.125
Chapter APPENDIX: The cross section of NPN transistor in triple-well CMOS process --- p.126
References --- p.127
Chapter CHAPTER 5. --- Conclusions and future works --- p.129
Chapter 5.1 --- Conclusions --- p.129
Chapter 5.2 --- Future works --- p.130
Chapter APPENDIX: --- A typical CMOS fabrication process flow (1 poly/2 M, twin well CMOS) --- p.131
Appleton, Samuel Scott. "Performance-directed design of asynchronous VLSI systems / Samuel Scott Appleton." Thesis, 1997. http://hdl.handle.net/2440/19100.
Full textxxii, 285 p. : ill. ; 30 cm.
Describes a new method for describing asynchronous systems (free-flow asynchronism). The method is demonstrated through two applications ; a channel signalling system and amedo.
Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1998
Sadrossadat, Sayed Alireza. "High Performance Digital Circuit Techniques." Thesis, 2009. http://hdl.handle.net/10012/4844.
Full textChen, Ting-Change. "An investigation of the simulation performance of Verilog for large circuits." 2005. http://digital.library.okstate.edu/etd/umi-okstate-1327.pdf.
Full textYeh, KuoCheng, and 葉國成. "Computer Simulation and Research of RF Circuit Effect on Communication Performance of OFDM System." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/a3b64e.
Full text南台科技大學
電子工程系
91
Wireless LAN IEEE 802.11a, which uses orthogonal frequency division multiplexing (OFDM), offers different communication data rates through 6 to 54 Mbps depended on different modulation techniques. OFDM signal is more sensitive to timing error, frequency offset, nonlinear effect of power amplifier and phase noise in oscillator. This thesis first studies the performance evaluation of the influences by timing error and frequency offset in OFDM system, and then presents detailed analysis and computer simulation by MATLAB for nonlinear effect of power amplifier and phase noise in oscillator. In the simulation of nonlinear effect of power amplifier, the power gain is assumed to be 11.5 dB and the OIP3 is 28.5 dB. If the input power of the amplifier is equal to 4 dBm, the EVM is about 7.5 %; while the input power is changed to 7 dBm, the EVM becomes 17.2 %. It can be seen that the nonlinear effect causes more EVM when driving power increases. For the simulation of phase noise, we concern the influence of ICI error using EVM and BER. In the EVM simulation, if the phase noise is equal to -90 dBc/Hz@100 kHz, the EVM is about 0.9 %; while the phase noise increases to -70 dBc/Hz, the EVM increases to 8.7 %. In the BER simulation, if BER=10-3 with AWGN channel is required in a system planning and the phase noise is -70 dBc/Hz@100 kHz, for the case of the OFDM/QPSK signal which needs about 0.5 dB more Eb/No than that without counting in phase noise. While for the case of the OFDM/16-QAM signal, more 2.2 dB Eb/No is required. It is concluded that higher transmitter power will be requested with larger value of M in M-ary QAM. These results are very useful for RF circuit/system designers in OFDM system.
"Performance study of multirate circuit switching in quantized clos network." 1998. http://library.cuhk.edu.hk/record=b5889540.
Full textThesis submitted in: December 1997.
Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.
Includes bibliographical references (leaves 62-[64]).
Abstract also in Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 2 --- Principles of Multirate Circuit Switching in Quantized Clos Network --- p.10
Chapter 2.1 --- Formulation of Multirate Circuit Switching --- p.11
Chapter 2.2 --- Call Level Routing in Quantized Clos Network --- p.12
Chapter 2.3 --- Cell Level Routing in Quantized Clos Network --- p.16
Chapter 2.3.1 --- Traffic Behavior in ATM Network --- p.17
Chapter 2.3.2 --- Time Division Multiplexing in Multirate Circuit Switching and Cell-level Switching in ATM Network --- p.19
Chapter 2.3.3 --- Cell Transmission Scheduling --- p.20
Chapter 2.3.4 --- Capacity Allocation and Route Assignment at Cell-level --- p.29
Chapter 3 --- Performance Evaluation of Different Implementation Schemes --- p.31
Chapter 3.1 --- Global Control and Distributed Switching --- p.32
Chapter 3.2 --- Implementation Schemes of Quantized Clos Network --- p.33
Chapter 3.2.1 --- Classification of Switch Modules --- p.33
Chapter 3.2.2 --- Bufferless Switch Modules Construction Scheme --- p.38
Chapter 3.2.3 --- Buffered Switch Modules Construction Scheme --- p.42
Chapter 3.3 --- Complexity Comparison --- p.44
Chapter 3.4 --- Delay Performance of The Two Implementation Schemes --- p.47
Chapter 3.4.1 --- Assumption --- p.47
Chapter 3.4.2 --- Simulation Result --- p.50
Chapter 4 --- Conclusions --- p.59
Bibliography --- p.62
蔡壬勝. "Computer Simulation and Research of RF Circuit Effect on Communication System Performance of OFDM System." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/72139618226280535339.
Full text南台科技大學
電子工程系
92
Orthogonal frequency division multiplexing (OFDM) is a promising transmission technology for high data rate communications in the future. However, the OFDM signal is more sensitive to the nonlinear effect of power amplifier, phase noise in oscillator and I-Q imbalance. Therefore, this thesis presents detailed analysis and the computer simulation by Matlab for above three imperfect effects. First, we study the improvement by the clipping method to IEEE 802.11a standard with nonlinear power amplifier and predict the error vector magnitude (EVM) by computer simulation. Secondly, we concern the influence of the I-Q imbalance in an OFDM receiver. The receiver architectures, such as direct conversion, super-heterodyne and low-IF, may be used for the front-end in an OFDM system. The direct conversion architecture will become popular since it offers one important advantage over a heterodyne counterpart, that is, the problem of image is circumvented and no image filter is required. However, this approach suffers from some impacts such as DC offset and I-Q imbalance. The second part in this thesis, we try to analyze the influence of I-Q imbalance with IEEE 802.11a standard. Finally, we focus on the phase noise. The considerations of the distortion can be separated into two parts, the common phase error and the ICI error. The former can be corrected by the pilot, so we only consider the effect of the ICI error. The simulation is based on the multi-band OFDM system, which is made by the UWB standard committee (802.15.3a task group) in 2003 and may be adopted as UWB communication standard. These simulation methods and numerical results are very useful for RF circuit/system designers in OFDM system.