Books on the topic 'Computers – Circuits – Performance'

1943-, Elmasry Mohamed I., ed. Optimal VLSI architectural synthesis: Area, performance, and testability. Boston: Kluwer Academic Publishers, 1992.

M, Schoen Joel, ed. Performance and fault modeling with VHDL. Englewood Cliffs, N.J: Prentice Hall, 1992.

Roermund, Arthur H. M. van, Casier Herman, and SpringerLink (Online service), eds. Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management. Dordrecht: Springer Science+Business Media B.V., 2009.

High-performance ASIC design: Using synthesizable domino logic in an ASIC flow. Cambridge: Cambridge University Press, 2008.

1941-, Venetsanopoulos A. N., ed. Artificial neural networks: Learning algorithms, performance evaluation, and applications. Boston: Kluwer Academic, 1993.

Krishnaswamy, Smita. Design, Analysis and Test of Logic Circuits Under Uncertainty. Dordrecht: Springer Netherlands, 2013.

G, Oklobdzija Vojin, ed. Digital system clocking: High-performance and low-power aspects. New York: IEEE, 2003.

David, Hutchison. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009.

Braulio, García-Cámara, Prieto Manuel, Ruggiero Martino, Sicard Gilles, and SpringerLink (Online service), eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation: 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings. Berlin, Heidelberg: Springer-Verlag GmbH Berlin Heidelberg, 2011.

Ochotta, Emil S. Practical Synthesis of High-Performance Analog Circuits. Boston, MA: Springer US, 1998.

Gu, Richard X. High-Performance Digital VLSI Circuit Design. Boston, MA: Springer US, 1996.

1962-, Sharaf Khaled M., and Elmasry Mohamed I. 1943-, eds. High-performance digital VLSI circuit design. Boston: Kluwer Academic Publishers, 1996.

Vanderbauwhede, Wim. High-Performance Computing Using FPGAs. New York, NY: Springer New York, 2013.

Lim, Sung Kyu. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. New York, NY: Springer New York, 2013.

Lampaert, Koen. Analog Layout Generation for Performance and Manufacturability. Boston, MA: Springer US, 1999.

Stanley, J. Comparative performance of full custom circuits placed within "sea of gate" gate arrays for themanufacture of electronic circuits for computer applications. Manchester: UMIST, 1991.

High performance memories: New architecture DRAMS and SRAMS-evolulion and function. New York: John Wiley, 1996.

D, May M., Thompson P. W, Welch P. H, and INMOS Limited, eds. Networks, routers, and transputers: Function, performance, and applications. Amsterdam: IOS Press, 1993.

Chinnery, David. Closing the gap between ASIC & custom: Tools and techniques for high-performance ASIC design. Boston: Kluwer Academic Publishers, 2002.

Prince, Betty. High performance memories: New architecture DRAMs and SRAMs--evolution and function. Chichester: Wiley, 1996.

Shen, Ruijing. Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Boston, MA: Springer US, 2012.

Symposium on High Performance Interconnects (16th 2008 Stanford, Calif.). 16th Annual IEEE Symposium on High-Performance Interconnects: Proceedings, Stanford, California, August 26-28, 2008. Los Alamitos, Calif: IEEE Computer Society, 2008.

Bergé, Jean-Michel. Meta-Modeling: Performance and Information Modeling. Boston, MA: Springer US, 1996.

Symposium, on High Performance Interconnects (14th 2006 Stanford Calif ). 14th IEEE Symposium on High-Performance Interconnects: Hot Interconnects : proceedings : 23-25 August, 2005, Stanford, CA. Los Alamitos, Calif: IEEE Computer Society, 2006.

Symposium on High Performance Interconnects (15th 2007 Stanford, Calif.). Hot interconnects: 15th Annual IEEE Symposium on High-Performance Interconnects : proceedings : 22-24 August, 2007, Stanford, CA. Los Alimitos, Calif: IEEE Computer Society, 2007.

Symposium on High Performance Interconnects (15th 2007 Stanford, Calif.). Hot interconnects: 15th Annual IEEE Symposium on High-Performance Interconnects : proceedings : 22-24 August, 2007, Stanford, CA. Los Alimitos, Calif: IEEE Computer Society, 2007.

Symposium on High Performance Interconnects (15th 2007 Stanford, Calif.). Hot interconnects: 15th Annual IEEE Symposium on High-Performance Interconnects : proceedings : 22-24 August, 2007, Stanford, CA. Los Alimitos, Calif: IEEE Computer Society, 2007.

Symposium on High Performance Interconnects (15th 2007 Stanford, Calif.). Hot interconnects: 15th Annual IEEE Symposium on High-Performance Interconnects : proceedings : 22-24 August, 2007, Stanford, CA. Los Alimitos, Calif: IEEE Computer Society, 2007.

1959-, Steyaert Michiel, and Sansen Willy M. C, eds. Static and dynamic performance limitations for high speed D/A converters. Boston: Kluwer Academic Publishers, 2004.

Yoo, Hoi-Jun. Low-power NoC for high-performance SoC design. Boca Raton, Fl: Taylor & Francis, 2008.

Calif.) Annual Symposium on High-Performance Interconnects (21st 2013 San Jose. 2013 IEEE 21st Annual Symposium on High-Performance Interconnects (HOTI 2013): San Jose, California, USA, 21-23 August 2013. Piscataway, NJ: IEEE, 2013.

K, Tewksbury Stuart, ed. Microelectronic system interconnections: Performance and modeling. New York: IEEE Press, 1994.

Symposium on High Performance Interconnects (12th 2004 Stanford University). 12th Annual IEEE Symposium on High Performance Interconnects: Hot interconnects : 25-27 August, 2004, Stanford University, Stanford, California, USA : proceedings. Los Alamitos, CA: IEEE Computer Society, 2004.

International, School on Formal Methods for the Design of Computer Communication and Software Systems (7th 2007 Bertinoro Italy). Formal methods for performance evaluation: 7th International School on Formal Methods for the Design of Computer, Communication and Software Systems, SFM 2007, Bertinoro, Italy, May 28 - June 2, 2007 ; advanced lectures. Berlin: Springer, 2007.

Wang, Weixun. Dynamic Reconfiguration in Real-Time Systems: Energy, Performance, and Thermal Perspectives. New York, NY: Springer New York, 2013.

Medeiro, Fernando. Top-down design of high-performance sigma-delta modulators. New York: Springer, 2011.

Leuken, René Van. Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation: 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011.

Great Lakes Symposium on VLSI (4th 1994 Notre Dame, Ind.). Proceedings: Fourth Great Lakes Symposium on VLSI : design automation of high performance VLSI systems, GLSV '94 : University of Notre Dame, Notre Dame, Indiana, March 4-5, 1994. Los Alamitos, Calif: IEEE Computer Society Press, 1994.

Yuan, Yifei. LTE-Advanced Relay Technology and Standardization. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013.

International Workshop on Power and Timing Modelling and Optimization (3rd 1993 La Grande Motte, France). Power and timing modelling for performance of integrated circuits: Proceedings of the Third International Workshop on Power and Timing Modelling and Optimization (PATMOS '93), Oct. 11-12, 1993, La Grande Motte, France. Bruchsal: IT Press Verlag, 1993.

Li, Xin, Jiayong Le, and Lawrence T. Pileggi. Statistical Performance Modeling and Optimization. Now Publishers Inc, 2007.

Elmasry, Mohamed I., and Catherine H. Gebotys. Optimal VLSI Architectural Synthesis: Area, Performance and Testability (The Springer International Series in Engineering and Computer Science). Springer, 1991.

Oklobdzija, Vojin G., Vladimir M. Stojanovic, Dejan M. Markovic, and Nikola M. Nedovic. Digital System Clocking: High-Performance and Low-Power Aspects. Wiley & Sons, Incorporated, John, 2008.

Oklobdzija, Vojin G., Vladimir M. Stojanovic, Dejan M. Markovic, and Nikola M. Nedovic. Digital System Clocking: High-Performance and Low-Power Aspects. Wiley-IEEE Press, 2003.

P, Hayes John, Igor L. Markov, and Smita Krishnaswamy. Design, Analysis and Test of Logic Circuits Under Uncertainty. Springer, 2012.

P, Hayes John, Igor L. Markov, and Smita Krishnaswamy. Design, Analysis and Test of Logic Circuits Under Uncertainty. Springer, 2014.

Architecture and performance analysis of DIRSMIN: A fault-tolerant switch using dilated reduced-stage MIN. Hampton, VA: Institute for Computer Applications in Science and Engineering, NASA Langley Research Center, 1995.

Sahner, Robin A., Kishor Trivedi, and Antonio Puliafito. Performance and Reliability Analysis of Computer Systems: An Example-Based Approach Using the SHARPE Software Package. Springer, 1995.

Venetsanopoulos, Anastasios N., and Nicolaos Karayiannis. Artificial Neural Networks: Learning Algorithms, Performance Evaluation, and Applications (The Springer International Series in Engineering and Computer Science). Springer, 1992.

Oklobdzija, Vojin G., Vladimir M. Stojanovic, Dejan M. Markovic, and Nikola M. Nedovic. Digital System Clocking. Wiley & Sons, Incorporated, John, 2005.