Relevant bibliographies by topics / Computers – Circuits – Performance

Academic literature on the topic 'Computers – Circuits – Performance'

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Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Computers – Circuits – Performance"

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Blume-Kohout, Robin, and Kevin C. Young. "A volumetric framework for quantum computer benchmarks." Quantum 4 (November 15, 2020): 362. http://dx.doi.org/10.22331/q-2020-11-15-362.

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We propose a very large family of benchmarks for probing the performance of quantum computers. We call them volumetric benchmarks (VBs) because they generalize IBM's benchmark for measuring quantum volume \cite{Cross18}. The quantum volume benchmark defines a family of square circuits whose depth d and width w are the same. A volumetric benchmark defines a family of rectangular quantum circuits, for which d and w are uncoupled to allow the study of time/space performance trade-offs. Each VB defines a mapping from circuit shapes — (w,d) pairs — to test suites C(w,d). A test suite is an ensemble of test circuits that share a common structure. The test suite C for a given circuit shape may be a single circuit C, a specific list of circuits {C1…CN} that must all be run, or a large set of possible circuits equipped with a distribution Pr(C). The circuits in a given VB share a structure, which is limited only by designers' creativity. We list some known benchmarks, and other circuit families, that fit into the VB framework: several families of random circuits, periodic circuits, and algorithm-inspired circuits. The last ingredient defining a benchmark is a success criterion that defines when a processor is judged to have ``passed'' a given test circuit. We discuss several options. Benchmark data can be analyzed in many ways to extract many properties, but we propose a simple, universal graphical summary of results that illustrates the Pareto frontier of the d vs w trade-off for the processor being benchmarked.
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Childs, Andrew M., Dmitri Maslov, Yunseong Nam, Neil J. Ross, and Yuan Su. "Toward the first quantum simulation with quantum speedup." Proceedings of the National Academy of Sciences 115, no. 38 (September 6, 2018): 9456–61. http://dx.doi.org/10.1073/pnas.1801723115.

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With quantum computers of significant size now on the horizon, we should understand how to best exploit their initially limited abilities. To this end, we aim to identify a practical problem that is beyond the reach of current classical computers, but that requires the fewest resources for a quantum computer. We consider quantum simulation of spin systems, which could be applied to understand condensed matter phenomena. We synthesize explicit circuits for three leading quantum simulation algorithms, using diverse techniques to tighten error bounds and optimize circuit implementations. Quantum signal processing appears to be preferred among algorithms with rigorous performance guarantees, whereas higher-order product formulas prevail if empirical error estimates suffice. Our circuits are orders of magnitude smaller than those for the simplest classically infeasible instances of factoring and quantum chemistry, bringing practical quantum computation closer to reality.
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Fan, Yi, Jie Liu, Xiongzhi Zeng, Zhiqian Xu, Honghui Shang, Zhenyu Li, and Jinlong Yang. "Q<sup>2</sup>Chemistry: A quantum computation platform for quantum chemistry." JUSTC 52, no. 12 (2022): 2. http://dx.doi.org/10.52396/justc-2022-0118.

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Quantum computers provide new opportunities for quantum chemistry. In this article,we present a versatile, extensible, and efficient software package, named Q<sup>2</sup>Chemistry, for developing quantum algorithms and quantum inspired classical algorithms in the field of quantum chemistry. In Q<sup>2</sup>Chemistry, the wave function and Hamiltonian can be conveniently mapped into the qubit space, then quantum circuits can be generated corresponding to a specific quantum algorithm already implemented in the package or newly developed by the users. The generated circuits can be dispatched to either a physical quantum computer, if available, or to the internal virtual quantum computer realized by simulating quantum circuits on classical computers. As demonstrated by our benchmark simulations, Q<sup>2</sup>Chemistry achieves excellent performance in simulating medium scale quantum circuits using the matrix product state algorithm. Applications of Q<sup>2</sup>Chemistry to simulate molecules and periodic systems are given with performance analysis.
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Stamatopoulos, Nikitas, Daniel J. Egger, Yue Sun, Christa Zoufal, Raban Iten, Ning Shen, and Stefan Woerner. "Option Pricing using Quantum Computers." Quantum 4 (July 6, 2020): 291. http://dx.doi.org/10.22331/q-2020-07-06-291.

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We present a methodology to price options and portfolios of options on a gate-based quantum computer using amplitude estimation, an algorithm which provides a quadratic speedup compared to classical Monte Carlo methods. The options that we cover include vanilla options, multi-asset options and path-dependent options such as barrier options. We put an emphasis on the implementation of the quantum circuits required to build the input states and operators needed by amplitude estimation to price the different option types. Additionally, we show simulation results to highlight how the circuits that we implement price the different option contracts. Finally, we examine the performance of option pricing circuits on quantum hardware using the IBM Q Tokyo quantum device. We employ a simple, yet effective, error mitigation scheme that allows us to significantly reduce the errors arising from noisy two-qubit gates.
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Czarnik, Piotr, Andrew Arrasmith, Patrick J. Coles, and Lukasz Cincio. "Error mitigation with Clifford quantum-circuit data." Quantum 5 (November 26, 2021): 592. http://dx.doi.org/10.22331/q-2021-11-26-592.

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Achieving near-term quantum advantage will require accurate estimation of quantum observables despite significant hardware noise. For this purpose, we propose a novel, scalable error-mitigation method that applies to gate-based quantum computers. The method generates training data {Xinoisy,Xiexact} via quantum circuits composed largely of Clifford gates, which can be efficiently simulated classically, where Xinoisy and Xiexact are noisy and noiseless observables respectively. Fitting a linear ansatz to this data then allows for the prediction of noise-free observables for arbitrary circuits. We analyze the performance of our method versus the number of qubits, circuit depth, and number of non-Clifford gates. We obtain an order-of-magnitude error reduction for a ground-state energy problem on 16 qubits in an IBMQ quantum computer and on a 64-qubit noisy simulator.
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Liu, Xiaonan, Ming He, Junchao Wang, Haoshan Xie, and Chenyan Zhao. "Automated Quantum Volume Test." Journal of Physics: Conference Series 2221, no. 1 (May 1, 2022): 012029. http://dx.doi.org/10.1088/1742-6596/2221/1/012029.

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Abstract As a benchmark for the overall performance of quantum computers, quantum volume has the advantage of being able to reflect the depth of running quantum circuits. But, the quantum volume test code provided by IBM needs to be executed manually, and the simulation result of the quantum simulator is used as the result of the volume test, so that users cannot quickly and accurately test the quantum volume of the actual quantum computer required. In response to this problem, this paper designs an automated quantum volume test program. The program automatically generates quantum volume sequences, selects the number of executions of quantum circuits, and defines real quantum computers to facilitate users to perform quantum volume tests on quantum computers provided by the IBM Quantum Cloud Platform. Simultaneously, according to the automated test program, the quantum volume of IBM’s four small superconducting quantum computers was tested. The test results show that (1) the quantum computer is different, and the qubit layout and execution times ntrials are the same, will cause the quantum volume is uncertain; (2) the same quantum computer, whether ntrials is the same, the robustness of qubit coupling will be affected to a certain extent.
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Aaron D’costa, Mr, Dr Abdul Razak, and Dr Shazia Hasan. "Analysis and comparison of fast multiplier circuits based on different parameters." International Journal of Engineering & Technology 7, no. 3 (June 26, 2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.

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Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so as to reduce the delay of whole circuit. The main purpose is to deal with high speed and lower power consumption even after decreasing the silicon area. This makes them well-suited for numerous complex and convenient VLSI circuit implementations. The fact however, remains that area and speed are two contradictory performance restrictions. Hence, increase in speed always results in the use of more and complex hardware. Different arithmetic techniques can be used to implement different multiplier circuits. The focus of this paper is to implement various multiplier circuit and compare them. The timing signals can be observed using software such as Modelsim and Xilinx.
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Song, Gyeongju, Kyungbae Jang, Hyunji Kim, and Hwajeong Seo. "A Parallel Quantum Circuit Implementations of LSH Hash Function for Use with Grover’s Algorithm." Applied Sciences 12, no. 21 (October 27, 2022): 10891. http://dx.doi.org/10.3390/app122110891.

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Grover’s search algorithm accelerates the key search on the symmetric key cipher and the pre-image attack on the hash function. To conduct Grover’s search algorithm, the target cipher algorithm should be efficiently implemented in a quantum circuit. Currently, small quantum computers are difficult to operate with large quantum circuits due to limited performance. Therefore, if a large quantum computer that can operate Grover’s algorithm appears, it is expected that a cipher attack will be possible. In this paper, we propose a parallel structure quantum circuit for the Korean hash function standard (i.e., LSH). The proposed quantum circuit designed a parallel operation structure for the message expansion (i.e., MsgExp) function and the mix function, which are the internal structures of the LSH hash function. This approach shows an efficient result for quantum circuit implementation in terms of quantum resources by reducing the depth of the quantum circuit by about 96% through the trade-off of appropriate quantum resources compared to previous work. This result can be a reference for the implementation of a parallel quantum circuit in the future and is expected to advance the attack timing of the search algorithm for Grover’s LSH hash function.
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Bravyi, Sergey, Dan Browne, Padraic Calpin, Earl Campbell, David Gosset, and Mark Howard. "Simulation of quantum circuits by low-rank stabilizer decompositions." Quantum 3 (September 2, 2019): 181. http://dx.doi.org/10.22331/q-2019-09-02-181.

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Recent work has explored using the stabilizer formalism to classically simulate quantum circuits containing a few non-Clifford gates. The computational cost of such methods is directly related to the notion of stabilizerrank, which for a pure state ψ is defined to be the smallest integer χ such that ψ is a superposition of χ stabilizer states. Here we develop a comprehensive mathematical theory of the stabilizer rank and the related approximate stabilizer rank. We also present a suite of classical simulation algorithms with broader applicability and significantly improved performance over the previous state-of-the-art. A new feature is the capability to simulate circuits composed of Clifford gates and arbitrary diagonal gates, extending the reach of a previous algorithm specialized to the Clifford+T gate set. We implemented the new simulation methods and used them to simulate quantum algorithms with 40-50 qubits and over 60 non-Clifford gates, without resorting to high-performance computers. We report a simulation of the Quantum Approximate Optimization Algorithm in which we process superpositions of χ∼106 stabilizer states and sample from the full n-bit output distribution, improving on previous simulations which used ∼103 stabilizer states and sampled only from single-qubit marginals. We also simulated instances of the Hidden Shift algorithm with circuits including up to 64 T gates or 16 CCZ gates; these simulations showcase the performance gains available by optimizing the decomposition of a circuit's non-Clifford components.
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Ou, Qiao-Feng, Bang-Shu Xiong, Lei Yu, Jing Wen, Lei Wang, and Yi Tong. "In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory." Materials 13, no. 16 (August 10, 2020): 3532. http://dx.doi.org/10.3390/ma13163532.

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Recent progress in the development of artificial intelligence technologies, aided by deep learning algorithms, has led to an unprecedented revolution in neuromorphic circuits, bringing us ever closer to brain-like computers. However, the vast majority of advanced algorithms still have to run on conventional computers. Thus, their capacities are limited by what is known as the von-Neumann bottleneck, where the central processing unit for data computation and the main memory for data storage are separated. Emerging forms of non-volatile random access memory, such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory, and resistive random access memory, are widely considered to offer the best prospect of circumventing the von-Neumann bottleneck. This is due to their ability to merge storage and computational operations, such as Boolean logic. This paper reviews the most common kinds of non-volatile random access memory and their physical principles, together with their relative pros and cons when compared with conventional CMOS-based circuits (Complementary Metal Oxide Semiconductor). Their potential application to Boolean logic computation is then considered in terms of their working mechanism, circuit design and performance metrics. The paper concludes by envisaging the prospects offered by non-volatile devices for future brain-inspired and neuromorphic computation.
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Dissertations / Theses on the topic "Computers – Circuits – Performance"

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Md, Ali Sawal Hamid. "System level performance and yield optimisation for analogue integrated circuits." Thesis, University of Southampton, 2009. https://eprints.soton.ac.uk/69724/.

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Advances in silicon technology over the last decade have led to increased integration of analogue and digital functional blocks onto the same single chip. In such a mixed signal environment, the analogue circuits must use the same process technology as their digital neighbours. With reducing transistor sizes, the impact of process variations on analogue design has become prominent and can lead to circuit performance falling below specification and hence reducing the yield. This thesis explores the methodology and algorithms for an analogue integrated circuit automation tool that optimizes performance and yield. The trade-offs between performance and yield are analysed using a combination of an evolutionary algorithm and Monte Carlo simulation. Through the integration of yield parameter into the optimisation process, the trade off between the performance functions can be better treated that able to produce a higher yield. The results obtained from the performance and variation exploration are modelled behaviourally using a Verilog-A language. The model has been verified with transistor level simulation and a silicon prototype. For a large analogue system, the circuit is commonly broken down into its constituent sub-blocks, a process known as hierarchical design. The use of hierarchical-based design and optimisation simplifies the design task and accelerates the design flow by encouraging design reuse. A new approach for system level yield optimisation using a hierarchical-based design is proposed and developed. The approach combines Multi-Objective Bottom Up (MUBU) modelling technique to model the circuit performance and variation and Top Down Constraint Design (TDCD) technique for the complete system level design. The proposed method has been used to design a 7th order low pass filter and a charge pump phase locked loop system. The results have been verified with transistor level simulations and suggest that an accurate system level performance and yield prediction can be achieved with the proposed methodology.
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Shahidipour, Hamed. "A study on the effects of variability on performance of CNFET based digital circuits." Thesis, University of Southampton, 2012. https://eprints.soton.ac.uk/364216/.

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With the continuous trend of reducing feature sizes, and employing continuously smaller components on integrated circuits, new challenges arise on the way of silicon CMOS circuits and devices. Emerging “nanodevices” promise the possibility of increased integration density and reduced power consumption. The emerging and new devices, partially due to their extremely small dimensions, show large variations in their behaviour. The variation shown by these devices affects their reliability and the performance of circuits made from them. The Carbon Nano-Tube (CNT) is one such device which is also the device of choice in this work. This work is concerned with building reliable systems out of these unreliable components. The work was done in HSPICE with the help of the Stanford CNFET model. Logic gates are implemented using CNT Field Effect Transistors (CNFETs) which are in turn made from CNTs with different physical attributes. Given a CNT manufacturing process, there exists a mean and standard deviation (STD) for the diameter distribution of the manufactured CNTs which depend on the accuracy of the manufacturing process. In the first part of this work, CNTs with different mean diameters and standard deviations (STD) in their diameter distribution are considered. Simulation results show that logic gates made from CNTs with larger mean and smaller STDs in their diameter distribution show less variation in their timing behaviour (propagation delay, rise and fall times) and a promise of more reliable operation. Alternative structures were then explored in the form of multiplexers and XOR gates. It is shown that these structures have the advantage over the gates studied previously in that they exhibit similar rise and fall transition times and hence are better suited to CNFET-based circuit design. The next stage of this work involves implementation and simulation of a memory structure (SRAM). Parameters such as Static Noise Margin (SNM), leakage power and read/write delays were studied and the effects of CNT diameter variation on them examined. The next contributions of this work are empirical models developed for a library of CNFET-based logic gates/circuit structures. The models can predict both the mean and standard deviation (STD) in various circuit performance parameters of a given CNFET-based logic gate/SRAM given the mean and STD of the diameter of CNTs used in their manufacture. The aim is, given a target reliability specification (timing requirements, power, speed, etc.), for various logic gates, and larger circuit components, to come up with a design strategy to suggest what physical properties the nano-device of choice should have to meet the target specification or vice versa. Best-case CNT diameter mean and STD selection scenarios are proposed to minimise circuit parameter variations. In the last part of this work, the effects of doping fluctuations in the source/drain regions of the CNFETs on the performance of logic gates made from them are studied. The work concludes that if doping concentration is kept above 1%, variation in doping concentration has a minimal effect on performance parameters.
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Lowe, Jeffrey. "A high-performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks." Online access for everyone, 2004. http://www.dissertations.wsu.edu/Thesis/Summer2004/j%5Flowe%5F072104.pdf.

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Bingham, Philip R. "The effect of message length distribution on the performance of fully connected switches." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15389.

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Appleton, Samuel Scott. "Performance-directed design of asynchronous VLSI systems /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09pha651.pdf.

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Khasawneh, Shadi Turki. "Low-power high-performance register file design for chip multiprocessors." Diss., Online access via UMI:, 2006.

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Serrano, Guillermo J. "High Performance Analog Circuit Design Using Floating-Gate Techniques." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19819.

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The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier of interest during normal operation. This results in an offset voltage cancelation that is independent of other amplifier parameters and does not dissipate additional power. Two compact programmable architectures that implement a voltage reference based on the charge difference between two floating-gate transistors are introduced. The references exhibit a low temperature coefficient (TC) as all the transistors temperature dependencies are canceled. Programming the charge on the floating-gate transistors provides the flexibility of an arbitrary accurate voltage reference with a single design and allows for a high initial accuracy of the reference. Also, this work presents a novel programmable temperature compensated current reference. The proposed circuit achieves a first order temperature compensation by canceling the negative TC of an on-chip poly resistor with the positive TC of a MOS transistor operating in the ohmic region. Programmability of the ohmic resistor enables optimal temperature compensation while programmability of the reference voltage allows for an accurate current reference for a wide range of values. Finally, this work combines the already established DAC design techniques with floating-gate circuits to obtain a high precision converter. This approach enables higher accuracy along with a substantial decrease of the die size.
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Qiao, Hao. "Sparse hierarchical model order reduction for high speed interconnects." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:8881/R/?func=dbin-jump-full&object_id=32359.

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Ma, Albert. "Circuits for high-performance low-power VLSI logic." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37906.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Includes bibliographical references (p. 85-88).
The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two. PSSL is better than domino in terms of energy and robustness, and is better than static CMOS in terms of delay. PSSL works by partially overlapping the execution of consecutive iterations through speculative evaluation. This is accomplished by presetting nodes at register boundaries before input arrival.
by Albert Ma.
Ph.D.
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Weyer, Daniel J. "TRADEOFFS BETWEEN PERFORMANCE AND RELIABILITY IN INTEGRATED CIRCUITS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=case155508829933554.

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Books on the topic "Computers – Circuits – Performance"

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1943-, Elmasry Mohamed I., ed. Optimal VLSI architectural synthesis: Area, performance, and testability. Boston: Kluwer Academic Publishers, 1992.

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M, Schoen Joel, ed. Performance and fault modeling with VHDL. Englewood Cliffs, N.J: Prentice Hall, 1992.

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Roermund, Arthur H. M. van, Casier Herman, and SpringerLink (Online service), eds. Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management. Dordrecht: Springer Science+Business Media B.V., 2009.

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High-performance ASIC design: Using synthesizable domino logic in an ASIC flow. Cambridge: Cambridge University Press, 2008.

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1941-, Venetsanopoulos A. N., ed. Artificial neural networks: Learning algorithms, performance evaluation, and applications. Boston: Kluwer Academic, 1993.

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Krishnaswamy, Smita. Design, Analysis and Test of Logic Circuits Under Uncertainty. Dordrecht: Springer Netherlands, 2013.

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G, Oklobdzija Vojin, ed. Digital system clocking: High-performance and low-power aspects. New York: IEEE, 2003.

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David, Hutchison. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009.

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Braulio, García-Cámara, Prieto Manuel, Ruggiero Martino, Sicard Gilles, and SpringerLink (Online service), eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation: 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings. Berlin, Heidelberg: Springer-Verlag GmbH Berlin Heidelberg, 2011.

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Ochotta, Emil S. Practical Synthesis of High-Performance Analog Circuits. Boston, MA: Springer US, 1998.

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Book chapters on the topic "Computers – Circuits – Performance"

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Raoufifard, Somaye, Behnam Ghavami, Mehrdad Najibi, and Hossein Pedram. "Performance Enhancement of Asynchronous Circuits." In Communications in Computer and Information Science, 671–78. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-89985-3_82.

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Dao, Hoang Q., Bart R. Zeydel, and Vojin G. Oklobdzija. "Energy Optimization of High-Performance Circuits." In Lecture Notes in Computer Science, 399–408. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39762-5_46.

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Zlatanovici, Radu, and Borivoje Nikolić. "Power – Performance Optimization for Custom Digital Circuits." In Lecture Notes in Computer Science, 404–14. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11556930_42.

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Chattopadhyay, Ankush, Chayanika Bose, and K. Sarkar Chandan. "Performance and Circuit Analysis of Independent Gate FinFET." In Computers and Devices for Communication, 427–33. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-8366-7_63.

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Rius, Josep, José Pineda, and Maurice Meijer. "An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits." In Lecture Notes in Computer Science, 187–96. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11556930_20.

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Tajalli, Armin, Massimo Alioto, Elizabeth J. Brauer, and Yusuf Leblebici. "Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits." In Lecture Notes in Computer Science, 21–30. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-95948-9_3.

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Raji, Mohsen, Behnam Ghavami, Hamid R. Zarandi, and Hossein Pedram. "Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation." In Lecture Notes in Computer Science, 5–15. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11802-9_5.

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Jadon, Ekta, and Shyam Akashe. "Performance Analysis and Comparison of Low Power Various Full Adder Circuits." In Communications in Computer and Information Science, 312–21. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-8896-6_25.

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Tao, Jun, Fa Wang, Paolo Cachecho, Wangyang Zhang, Shupeng Sun, Xin Li, Rouwaida Kanj, Chenjie Gu, and Xuan Zeng. "Large-Scale Circuit Performance Modeling by Bayesian Model Fusion." In Machine Learning in VLSI Computer-Aided Design, 403–22. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-04666-8_14.

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Harjani, Ramesh, and Jianfeng Shao. "Feasibility and Performance Region Modeling of Analog and Digital Circuits." In The Kluwer International Series in Engineering and Computer Science, 23–43. Boston, MA: Springer US, 1996. http://dx.doi.org/10.1007/978-1-4613-1405-9_3.

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Conference papers on the topic "Computers – Circuits – Performance"

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Zatsarinny, Aleksandr, Yuriy Stepchenkov, Yuriy Diachenko, and Yuriy Rogdestvenski. "SELF-TIMED CIRCUITS AS A BASIS FOR DEVELOPING NEXT GENERATION HIGH-RELIABLE HIGH-PERFORMANCE COMPUTERS." In Mathematical modeling in materials science of electronic component. LLC MAKS Press, 2020. http://dx.doi.org/10.29003/m1535.mmmsec-2020/114-116.

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The paper proposes design and circuitry solutions for the implementation of high-performance next generation computers. They are based on self-timed circuit design methodology and provide an increase in the tolerance of computing systems to soft errors resulting from induced noises and radiation exposure.
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Paliwal, Wasundhara D., P. V. S. Shastry, and Sudarshan Dighade. "High performance using synchronous elastic circuits with lower overheads." In 2014 International Conference on Advances in Electronics, Computers and Communications (ICAECC). IEEE, 2014. http://dx.doi.org/10.1109/icaecc.2014.7002453.

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Thakur, Ravikant, Ajay Kumar Dadoria, and Tarun Kumar Gupta. "Comparative analysis of various Domino logic circuits for better performance." In 2014 International Conference on Advances in Electronics, Computers and Communications (ICAECC). IEEE, 2014. http://dx.doi.org/10.1109/icaecc.2014.7002416.

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Sau, Swagata Saha, and Rajat Kumar Pal. "An efficient high performance parallel algorithm to yield reduced wire length VLSI circuits." In 2012 International Conference on Computers and Devices for Communication (CODEC). IEEE, 2012. http://dx.doi.org/10.1109/codec.2012.6509278.

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Ho, Hoang Thien Long, Anh Tien Doan, Duy Tinh Nguyen, and Hoang-Anh Pham. "A LoRaWanbased IoT Testbed for Performance Investigation." In 2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). IEEE, 2022. http://dx.doi.org/10.1109/itc-cscc55581.2022.9894925.

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Bumrungkit, Acharaporn, Watid Phakphisut, and Pornchai Supnithi. "Preliminary results of EPB impact on GBAS performance." In 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). IEEE, 2019. http://dx.doi.org/10.1109/itc-cscc.2019.8793387.

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Han, Sangwoo, Tae Yang Jeong, and Eui-Young Chung. "Multi-node Power/Performance Modeling for HPC System." In 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). IEEE, 2019. http://dx.doi.org/10.1109/itc-cscc.2019.8793388.

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Srisomboon, Kanabadee, and Wilaiporn Lee. "Performance Evaluation of Spectrum Sensing Under PU Random Access." In 2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). IEEE, 2022. http://dx.doi.org/10.1109/itc-cscc55581.2022.9895108.

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Choi, Yuho, Byungguk Kim, and Seon Wook Kim. "Performance Analysis of PointPillars on CPU and GPU Platforms." In 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). IEEE, 2021. http://dx.doi.org/10.1109/itc-cscc52171.2021.9611297.

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Song, W. S., M. M. Vai, and H. T. Nguyen. "High-performance low-power bit-level systolic array signal processor with low-threshold dynamic logic circuits." In Conference Record. Thirty-Fifth Asilomar Conference on Signals, Systems and Computers. IEEE, 2001. http://dx.doi.org/10.1109/acssc.2001.986895.

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