Dissertations / Theses on the topic 'Codesign'
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Dove, G. "CoDesign with data." Thesis, City University London, 2015. http://openaccess.city.ac.uk/14902/.
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Design is a process of changing current situations into preferred ones, through conversations with design materials, and an understanding of the present practice of the designed artefact’s future users. Domain-relevant data, such as those generated by personal and autonomous computing systems, are an increasingly important design material presenting new ways to explore current practice. Examples of these data include that being generated by people using smartphones, health and fitness monitors, smart energy meters and social media; or that from official statistics made publicly available via Open Data initiatives. This thesis details research developing CoDesign With Data, a novel approach to collaborative early-stage design workshops in which working with domain-relevant data is the key distinguishing feature. During a CoDesign With Data workshop participants are given the tools and techniques to help them seek insight from data, gain an understanding of the context these data might come from, and to inspire creative design ideas. These tools and techniques build on an understanding of research into information visualization and applied creativity. The activities in which they are used build on the experiences reported from other approaches to creativity in collaborative requirements gathering and design workshops. The aim of this research is to support design innovation that results in new products or services appropriate to the contexts in which they will be used. To investigate the primary research question, and evaluate the tools and techniques being developed, two design experiments and three case studies were undertaken. In each study, examples of tools, in the form of workshop materials and information visualization interfaces, and techniques, in the form of workshop activities, are presented, and simple takeaways for design practice are offered. Finally, the knowledge and understanding gained during this research is presented as a series of guidelines and recommendations, and a description of the current state-of-the-art CoDesign With Data workshop.
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Soldner, Wolfgang Wilhelm. "HF-ESD-Codesign." Aachen Shaker, 2009. http://d-nb.info/996579168/04.
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Hilton, Adrian J. "High integrity hardware-software codesign." Thesis, Open University, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.402249.
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Cai, Jianming. "An object-based codesign methodology." Thesis, Sheffield Hallam University, 2001. http://shura.shu.ac.uk/19418/.
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The research into Codesign of Hardware and Software stems from the development of embedded systems, on which various systems restrictions are imposed. Typical restrictions can be the overall time (latency) to complete an assigned function and the space/power limits within the system. Although software can be used to undertake most tasks in an embedded system, ASIC (Application Specific Integrated Circuits) hardware components sometimes have to be recruited to meet the system constraints. Designing the restricted embedded system with both software and hardware components in it involves the analysis of not only individual hardware/software components but also their mutual influences. Using co-design principles, the approach is to consider both hardware and software from a coherent viewpoint. This thesis presents the results from our research project in the area of Codesign of Hardware and Software. In this project, we investigated previously published codesign approaches and their methodological supports. The investigation has identified shortcomings and problems with the existing codesign methodologies. A new object-based codesign approach (Co-PARSE) is thus developed in this project, which is supported by successive phases, guidelines, and techniques. This methodology offers a coherent design framework for real-time embedded systems and incorporates the criteria of system performance and hardware cost. Tools have been developed to facilitate the use of the methodology. Within the methodology, a high-level system modeling and specification approach has been developed and formalised in the Co-BSL (Codesign Behavior Specification Language). The means of transforming Co-BSL specifications to C and VHDL implementations is defined, and a library of VHDL components provided. The thesis documents the partitioning approach taken within the methodology and proposes a new multi-layered bus architecture as a basis for more flexible and efficient implementations. A means of simulating the performance characteristics of this architecture under different configurations is provided, and examples of simulation results are presented. A new embedded system (the Radio Data Computing System) is designed and simulated in the Co-PARSE methodology and simulation results analysed. The thesis concludes with an evaluation of the work carried out in the project and proposals for extending the results obtained in future research. The major contributions reported in this thesis can be summarised as follows. First, the unified system specification means has been designed, which is embodied in the Co-BSL. It captures overall dynamic aspects and performance constraints in the system under development. This high-level specification language is independent of implementation and does not bias the designer towards the use of hardware or software components at this early stage. Second, within Co-PARSE, the target architecture of the system under development has been exploited to improve the system performance and at the same time to reduce hardware cost. This novel concept has been realised by the introduction of an asynchronous bus protocol and the multi-layer bus communication structure. Third, in order to evaluate the strength and practicability of the Co-PARSE methodology, an extensive case study has been carried out. The new RDC (Radio Dada Computing) System has been designed in the proposed codesign approach. Codesign phases are subsequently applied and the guidelines and tools that are specially developed in support of the methodology are fully utilized.
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Bambha, Neal Kumar. "Communication-driven codesign for multiprocessor systems." College Park, Md. : University of Maryland, 2004. http://hdl.handle.net/1903/1429.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2004.Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Soldner, Wolfgang W. [Verfasser]. "HF ESD CODESIGN / Wolfgang W Soldner." Aachen : Shaker, 2009. http://d-nb.info/1159834857/34.
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King, Myron Decker. "A methodology for hardware-software codesign." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84891.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 150-156).
Special purpose hardware is vital to embedded systems as it can simultaneously improve performance while reducing power consumption. The integration of special purpose hardware into applications running in software is difficult for a number of reasons. Some of the difficulty is due to the difference between the models used to program hardware and software, but great effort is also required to coordinate the simultaneous execution of the application running on the microprocessor with the accelerated kernel(s) running in hardware. To further compound the problem, current design methodologies for embedded applications require an early determination of the design partitioning which allows hardware and software to be developed simultaneously, each adhering to a rigid interface contract. This approach is problematic because often a good hardware-software decomposition is not known until deep into the design process. Fixed interfaces and the burden of reimplementation prevent the migration of functionality motivated by repartitioning. This thesis presents a two-part solution to the integration of special purpose hardware into applications running in software. The first part addresses the problem of generating infrastructure for hardware-accelerated applications. We present a methodology in which the application is represented as a dataflow graph and the computation at each node is specified for execution either in software or as specialized hardware using the programmer's language of choice. An interface compiler as been implemented which takes as input the FIFO edges of the graph and generates code to connect all the different parts of the program, including those which communicate across the hardware/software boundary. This methodology, which we demonstrate on an FPGA platform, enables programmers to effectively exploit hardware acceleration without ever leaving the application space. The second part of this thesis presents an implementation of the Bluespec Codesign Language (BCL) to address the difficulty of experimenting with hardware/software partitioning alternatives. Based on guarded atomic actions, BCL can be used to specify both hardware and low-level software. Based on Bluespec SystemVerilog (BSV) for which a hardware compiler by Bluespec Inc. is commercially available, BCL has been augmented with extensions to support more efficient software generation. In BCL, the programmer specifies the entire design, including the partitioning, allowing the compiler to synthesize efficient software and hardware, along with transactors for communication between the partitions. The benefit of using a single language to express the entire design is that a programmer can easily experiment with many different hardware/software decompositions without needing to re-write the application code. Used together, the BCL and interface compilers represent a comprehensive solution to the task of integrating specialized hardware into an application.
by Myron King.
Ph.D.
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Dave, Nirav Hemant 1982. "A unified model for hardware/software codesign." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/68171.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student submitted PDF version of thesis.
Includes bibliographical references (p. 179-188).
Embedded systems are almost always built with parts implemented in both hardware and software. Market forces encourage such systems to be developed with dierent hardware-software decompositions to meet dierent points on the price-performance-power curve. Current design methodologies make the exploration of dierent hardware-software decompositions difficult because such exploration is both expensive and introduces signicant delays in time-to-market. This thesis addresses this problem by introducing, Bluespec Codesign Language (BCL), a united language model based on guarded atomic actions for hardware-software codesign. The model provides an easy way of specifying which parts of the design should be implemented in hardware and which in software without obscuring important design decisions. In addition to describing BCL's operational semantics, we formalize the equivalence of BCL programs and use this to mechanically verify design refinements. We describe the partitioning of a BCL program via computational domains and the compilation of dierent computational domains into hardware and software, respectively.
by Nirav Dave.
Ph.D.
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Hauff, Martin Anthony, and marty@extendabilities com au. "Compiler Directed Codesign for FPGA-based Embedded Systems." RMIT University. Electrical and Computer Engineering, 2008. http://adt.lib.rmit.edu.au/adt/public/adt-VIT20081202.141333.
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As embedded systems designers increasingly turn to programmable logic technologies in place of off-the-shelf microprocessors, there is a growing interest in the development of optimised custom processing cores that can be designed on a per-application basis. FPGAs blur the traditional distinction between hardware and software and offer the promise of application specific hardware acceleration. But realizing this in a general sense requires a significant departure from traditional embedded systems development flows. Whereas off-the-shelf processors have a fixed architecture, the same cannot be said of purpose-built FPGA-based processors. With this freedom comes the challenge of empirically determining the optimal boundary point between hardware and software. The fluidity of the hardware/software partition also poses an interesting challenge for compiler developers. This thesis presents a tool and methodology that addresses these codesign challenges in a new way. Described as 'compiler-directed codesign', it makes use of a suitably modified compiler to help direct the development of a custom processor core on a per-application basis. By exposing the compiler's internal representation of a compiled target program, visibility into those instructions, and hardware resources, that are most sought after by the compiler can be gained. This information is then used to inform further processor development and to determine the optimal partition between hardware and software. At each design iteration, the machine model is updated to reflect the available hardware resources, the compiler is rebuilt, and the target application is compiled once again. By including the compiler 'in-the-loop' of custom processor design, developers can accurately quantify the impact on performance caused by the addition or removal of specific hardware resources and iteratively converge on an optimal solution. Compiler Directed Codesign has advantages over existing codesign methodologies because it offers both a concrete point from which to begin the partitioning process as well as providing quantifiable and rapid feedback of the merits of different partitioning choices. When applied to an Adaptive PCM Encoder/Decoder case study, the Compiler Directed Codesign technique yielded a custom processor core that was between 36% and 73% smaller, consumed between 11% to 19% less memory, and performed up to 10X faster than comparable general-purpose FPGA-based processor cores. The conclusion of this work is that a suitably modified compiler can serve a valuable role in directing hardware/software partitioning on a per-application basis.
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Iqbal, Arshad. "VoIP Server HW/SW Codesign for Multicore Computing." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-94203.
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Modern technologies are growing and Voice over Internet Protocol (VoIP) technology is able to function in heterogeneous networks. VoIP gained wide popularity because it offers cheap calling rates compared to traditional telephone system and the number of VoIP subscribers has increased significantly in recent years. End users need reliable and acceptable call quality in real time communication with best Quality of Service (QoS). Server complexity is increasing to handle all client requests simultaneously and needs huge processing power. VoIP Servers will increase processing power but the engineering tradeoff needs to be considered e.g. increasing hardware will increase hardware complexity, energy consumption, network management, space requirement and overall system complexity. Modern System-on-Chip (SoC) uses multiple core technology to resolve the complexity of hardware computation. With enterprises needing to reduce overall costs while simultaneously improving call setup time, the amalgamation of VoIP with SoC can play a major role in the business market. The proposed VoIP Server model with multiple processing capabilities embedded in it is tailored for multicore hardware to achieve the required result. The model uses SystemC-2.2.0 and TLM-2.0 as a platform and consists of three main modules. TLM is built on top of SystemC in an overlay architectural fashion. SystemC provides a bridge between software and hardware co-design and increases HW & SW productivity, driven by fast concurrent programming in real time. The proposed multicore VoIP Server model implements a round robin algorithm to distribute transactions between cores and clients via Load Balancer. Primary focus of the multicore model is the processing of call setup time delays on a VoIP Server. Experiments were performed using OpenSIP Server to measure Session Initiation Protocol (SIP) messages and call setup time processing delays. Simulations were performed at the KTH Ferlin system and based on the theoretical measurements from the OpenSIP Server experiments. Results of the proposed multicore VoIP Server model shows improvement in the processing of call setup time delays.
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Viktorin, Jan. "HW/SW Codesign for the Xilinx Zynq Platform." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2013. http://www.nusl.cz/ntk/nusl-236227.
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This work describes a novel approach of HW/SW codesign on the Xilinx Zynq and similar platforms. It deals with interconnections between the Processing System (ARM Cortex-A9 MPCore) and the Programmable Logic (FPGA) to find an abstract and universal way to develop applications that are partially offloaded into the programmable hardware and that run in the Linux operating system. For that purpose a framework for HW/SW codesign on the Zynq and similar platforms is designed. No such framework is currently available.
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Schulz, Stephan. "Model-based codesign for real-time embedded systems." Diss., The University of Arizona, 2001. http://hdl.handle.net/10150/289712.
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This dissertation presents a model-based codesign framework for real-time embedded systems applications. The presented research provides a theoretical modeling foundation for the construction of design models and their implementation. Whereas most current codesign approaches leverage from a complete specification of an application design at the implementation level, a completely modular, implementation independent system level specification is pursued here. Benefits of the approach presented include: a stepwise refinement of abstract design models for complex applications, a larger design space for possible application implementations, a late design partitioning into hardware and software components, the representation of concurrency inherent to the application, as well as an implementations thereof on a parallel processing platform. A formal abstraction for a general, system level specification of real-time embedded systems is derived which may be used with a variety of executable discrete event modeling specifications. Furthermore, the construction of abstract design models from textual system specifications is discussed based on this abstraction as well as their correct refinement. A set of analysis methods which evaluate system simulation results is introduced to validate and improve abstracted design model performance during each refinement step. A direct transition from the design model to an efficient implementation is addressed though a model compilation algorithm which validates alternative processing platforms for a detailed design model specification against real-time constraints. In addition, a formal mapping of system model component specifications to implementation specifications is given. Separately, this model continuity problem is also addressed through a definition of a multi-level approach to the testing of integrated application implementation prototypes. The presented model-based codesign concepts are illustrated with an embedded systems application example.
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Sananikone, Dang S. "Cosynthesis of embedded systems using coloured interpreted petri nets." Thesis, University of Aberdeen, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.320764.
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The rising complexity in systems design, and the shift in the hardware/software functionality boundary has spurred research into development of EDA (Electronic Design Automation) tools at the systems level. Codesign is a methodology that proposes an integrated approach to systems design unifying both hardware and software approaches. Cosynthesis is a major field of research within codesign; cosynthesis takes a behavioural description and generates a hardware/software partition which satisfies system constraints. Current research is concerned with the automatic partitioning of systems. COSYN was developed to address the cosynthesis of embedded systems. A CIPN (Coloured Interpreted Petri Net) is used to model multiple processes and interprocess communication. The partitioning algorithm, which adopts a fine-grained approach to system partitioning (it considers moving nodes at the basic block level), is based on selecting blocks based on their potential speedup and extra hardware requirements, using hardware and software execution time estimators. The interdependence between interprocess communication primitives is exploited to achieve a better hardware/software partition. Results for an input example pdi are given which illustrate the benefits of the approach presented in this thesis.
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Mendoza, Jose Antonio. "Hardware and Software Codesign of a JPEG2000 Watermarking Encoder." Thesis, University of North Texas, 2008. https://digital.library.unt.edu/ark:/67531/metadc9752/.
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Analog technology has been around for a long time. The use of analog technology is necessary since we live in an analog world. However, the transmission and storage of analog technology is more complicated and in many cases less efficient than digital technology. Digital technology, on the other hand, provides fast means to be transmitted and stored. Digital technology continues to grow and it is more widely used than ever before. However, with the advent of new technology that can reproduce digital documents or images with unprecedented accuracy, it poses a risk to the intellectual rights of many artists and also on personal security. One way to protect intellectual rights of digital works is by embedding watermarks in them. The watermarks can be visible or invisible depending on the application and the final objective of the intellectual work. This thesis deals with watermarking images in the discrete wavelet transform domain. The watermarking process was done using the JPEG2000 compression standard as a platform. The hardware implementation was achieved using the ALTERA DSP Builder and SIMULINK software to program the DE2 ALTERA FPGA board. The JPEG2000 color transform and the wavelet transformation blocks were implemented using the hardware-in-the-loop (HIL) configuration.
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Motiwala, Quaeed. "Optimizations for acyclic dataflow graphs for hardware-software codesign." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06302009-040504/.
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Mendoza, Jose Antonio Kougianos Elias. "Hardware & software codesign of a JPEG200 watermarking encoder." [Denton, Tex.] : University of North Texas, 2008. http://digital.library.unt.edu/permalink/meta-dc-9752.
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Junior, Carlos Alberto Oliveira de Souza. "A hardware/software codesign for the chemical reactivity of BRAMS." Universidade de São Paulo, 2017. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-21092017-170006/.
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Several critical human activities depend on the weather forecasting. Some of them are transportation, health, work, safety, and agriculture. Such activities require computational solutions for weather forecasting through numerical models. These numerical models must be accurate and allow the computers to process them quickly. In this project, we aim at migrating a small part of the software of the weather forecasting model of Brazil, BRAMS Brazilian developments on the Regional Atmospheric Modelling System to a heterogeneous system composed of Xeon (Intel) processors coupled to a reprogrammable circuit (FPGA) via PCIe bus. According to the studies in the literature, the chemical equation from the mass continuity equation is the most computationally demanding part. This term calculates several linear systems Ax = b. Thus, we implemented such equations in hardware and provided a portable and highly parallel design in OpenCL language. The OpenCL framework also allowed us to couple our circuit to BRAMS legacy code in Fortran90. Although the development tools present several problems, the designed solution has shown to be viable with the exploration of parallel techniques. However, the performance was below of what we expected.Várias atividades humanas dependem da previsão do tempo. Algumas delas são transporte, saúde, trabalho, segurança e agricultura. Tais atividades exigem solucões computacionais para previsão do tempo através de modelos numéricos. Estes modelos numéricos devem ser precisos e ágeis para serem processados no computador.Este projeto visa portar uma pequena parte do software do modelo de previsão de tempo do Brasil, o BRAMSBrazilian developments on the Regional Atmospheric Modelling Systempara uma arquitetura heterogênea composta por processadores Xeon (Intel) acoplados a um circuito reprogramável em FPGA via barramento PCIe. De acordo com os estudos, o termo da química da equação de continuidade da massa é o termo mais caro computacionalmente. Este termo calcula várias equações lineares do tipo Ax = b. Deste modo, este trabalho implementou estas equações em hardware, provendo um ´codigo portável e paralelo na linguagem OpenCL. O framework OpenCL também nos permitiu acoplar o código legado do BRAMS em Fortran90 junto com o hardware desenvolvido. Embora as ferramentas de desenvolvimento tenham apresentado vários problemas, a solução implementada mostrou-se viável com a exploração de técnicas de paralelismo. Entretando sua perfomance ficou muito aquém do desejado.
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Braun, Erika L. "Framing Wicked Problems Using CoDesign and a Hybrid Design Toolset." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461202906.
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Bales, Jason M. "Multi-channel hardware/software codesign on a software radio platform." Fairfax, VA : George Mason University, 2008. http://hdl.handle.net/1920/3400.
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Thesis (M.S.)--George Mason University, 2008.Vita: p. 89. Thesis director: David D. Hwang. Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering. Title from PDF t.p. (viewed Mar. 9, 2009). Includes bibliographical references (p. 85-88). Also issued in print.
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Nagaonkar, Yajuvendra. "FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1294.pdf.
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Hardt, Wolfram. "HW-SW-Codesign auf Basis von C-Programmen unter Performanz-Gesichtspunkten /." Aachen : Shaker, 1996. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=007450162&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.
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Oudghiri, Houria. "A hardware/software partitioning framework for the codesign of digital systems." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0020/NQ55368.pdf.
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Lifa, Adrian Alin. "Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms." Doctoral thesis, Linköpings universitet, Programvara och system, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-117637.
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Modern applications running on today's embedded systems have very high requirements. Most often, these requirements have many dimensions: the applications need high performance as well as exibility, energy-eciency as well as real-time properties, fault tolerance as well as low cost. In order to meet these demands, the industry is adopting architectures that are more and more heterogeneous and that have reconguration capabilities. Unfortunately, this adds to the complexity of designing streamlined applications that can leverage the advantages of such architectures. In this context, it is very important to have appropriate tools and design methodologies for the optimization of such systems. This thesis addresses the topic of hardware/software codesign and optimization of adaptive real-time systems implemented on recongurable and heterogeneous platforms. We focus on performance enhancement for dynamically recongurable FPGA-based systems, energy minimization in multi-mode real-time systems implemented on heterogeneous platforms, and codesign techniques for fault-tolerant systems. The solutions proposed in this thesis have been validated by extensive experiments, ranging from computer simulations to proof of concept implementations on real-life platforms. The results have conrmed the importance of the addressed aspects and the applicability of our techniques for design optimization of modern embedded systems.
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McRitchie, I. "Multilanguage generative programming techniques for the codesign of hardware/software subsystems." Thesis, Queen's University Belfast, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.419447.
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Sredojević, Ranko Radovin. "Template-based hardware-software codesign for high-performance embedded numerical accelerators." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84895.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 129-132).
Sophisticated algorithms for control, state estimation and equalization have tremendous potential to improve performance and create new capabilities in embedded and mobile systems. Traditional implementation approaches are not well suited for porting these algorithmic solutions into practical implementations within embedded system constraints. Most of the technical challenges arise from design approach that manipulates only one level in the design stack, thus being forced to conform to constraints imposed by other levels without question. In tightly constrained environments, like embedded and mobile systems, such approaches have a hard time efficiently delivering and delivering efficiency. In this work we offer a solution that cuts through all the design stack layers. We build flexible structures at the hardware, software and algorithm level, and approach the solution through design space exploration. To do this efficiently we use a template-based hardware-software development flow. The main incentive for template use is, as in software development, to relax the generality vs. efficiency/performance type tradeoffs that appear in solutions striving to achieve run-time flexibility. As a form of static polymorphism, templates typically incur very little performance overhead once the design is instantiated, thus offering the possibility to defer many design decisions until later stages when more is known about the overall system design. However, simply including templates into design flow is not sufficient to result in benefits greater than some level of code reuse. In our work we propose using templates as flexible interfaces between various levels in the design stack. As such, template parameters become the common language that designers at different levels of design hierarchy can use to succinctly express their assumptions and ideas. Thus, it is of great benefit if template parameters map directly and intuitively into models at every level. To showcase the approach we implement a numerical accelerator for embedded Model Predictive Control (MPC) algorithm. While most of this work and design flow are quite general, their full power is realized in search for good solutions to a specific problem. This is best understood in direct comparison with recent works on embedded and high-speed MPC implementations. The controllers we generate outperform published works by a handsome margin in both speed and power consumption, while taking very little time to generate.
by Ranko Radovin Sredojević.
Ph.D.
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Wixom, Jacob Hartt. "Logics of Collaboration: An Ethnography of Codesign in the Brazilian Amazon." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8650.
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Engineers working internationally are increasingly concerned with the social impacts of their work. New frontiers in design show promise in helping practitioners address these concerns. One of these is codesign, a practice of making stakeholders co-decision-makers in the design process. Codesign has the potential to greatly improve the social sustainability of engineered products, but some concerns remain surrounding codesign’s practicability in engineering. I explore three such concerns: that conflicting institutional logics may undermine codesign’s collaborative aspirations, that codesign can perpetuate developmental idealism, and that codesign may insufficiently account for the needs and perspectives of marginalized populations. Through more than a year of ethnographic research, including dozens of interviews and hundreds of hours of observation, I examine the realities of codesign as it is carried out by a team of engineers in the Brazilian Amazon. I find that conflicting logics do undermine codesign at times, but that the engineers are still able to explore new tools and practices for socially sustainable engineering, even in times of codesign failure. I also find that the engineers are better equipped to respond to modernizing stakeholders than they are traditional ones. This may lead to the spread of developmental idealism and the further marginalization of disadvantaged groups.
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Dudebout, Nicolas. "Multigigabit multimedia processor for 60GHz WPAN a hardware software codesign implementation /." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26677.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Member: Chang, Gee-Kung; Committee Member: Hasler, Paul; Committee Member: Laskar, Joy. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Wang, Jian. "An FPGA Based Software/Hardware Codesign for Real Time Video Processing : A Video Interface Software and Contrast Enhancement Hardware Codesign Implementation using Xilinx Virtex II Pro FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6173.
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Xilinx Virtex II Pro FPGA with integrated PowerPC core offers an opportunity to implementing a software and hardware codesign. The software application executes on the PowerPC processor while the FPGA implementation of hardware cores coprocess with PowerPC to achieve the goals of acceleration. Another benefit of coprocessing with the hardware acceleration core is the release of processor load. This thesis demonstrates such an FPGA based software and hardware codesign by implementing a real time video processing project on Xilinx ML310 development platform which is featured with a Xilinx Virtex II Pro FPGA. The software part in this project performs video and memory interface task which includes image capture from camera, the store of image into on-board memory, and the display of image on a screen. The hardware coprocessing core does a contrast enhancement function on the input image. To ease the software development and make this project flexible for future extension, an Embedded Operating System MontaVista Linux is installed on the ML310 platform. Thus the software video interface application is developed using Linux programming method, for example the use of Video4Linux API. The last but not the least implementation topic is the software and hardware interface, which is the Linux device driver for the hardware core. This thesis report presents all the above topics of Operating System installation, video interface software development, contrast enhancement hardware implementation, and hardware core’s Linux device driver programming. After this, a measurement result is presented to show the performance of hardware acceleration and processor load reduction, by comparing to the results from a software implementation of the same contrast enhancement function. This is followed by a discussion chapter, including the performance analysis, current design’s limitations and proposals for improvements. This report is ended with an outlook from this master thesis.
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Ruan, Zhuo. "Interface Design and Synthesis for Structural Hybrid Microarchitectural Simulators." BYU ScholarsArchive, 2013. https://scholarsarchive.byu.edu/etd/4369.
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Computer architects have discovered the potential of using FPGAs to accelerate software microarchitectural simulators. One type of FPGA-accelerated microarchitectural simulator, namedthe hybrid structural microarchitectural simulator, is very promising. This is because a hybrid structural microarchitectural simulator combines structural software and hardware, and this particular organization provides both modeling flexibility and fast simulation speed. The performance of a hybrid simulator is significantly affected by how the interface between software and hardware is constructed. The work of this thesis creates an infrastructure, named Simulator Partitioning Research Infrastructure (SPRI), to implement the synthesis of hybrid structural microarchitectural simulators which includes simulator partitioning, simulator-to-hardware synthesis, interface synthesis. With the support of SPRI, this thesis characterizes the design space of interfaces for synthesized hybrid structural microarchitectural simulators and provides the implementations for several such interfaces. The evaluation of this thesis thoroughly studies the important design tradeoffs and performance factors (e.g. hardware capacity, design scalability, and interface latency) involved in choosing an efficient interface. The work of this thesis is essential to the research community of computer architecture. It not only contributes a complete synthesis infrastructure, but also provides guidelines to architects on how to organize software microarchitectural models and choose a proper software/hardware interface so the hybrid microarchitectural simulators synthesized from these software models can achieve desirable speedup
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Egolf, Thomas W. "Virtual prototyping of embedded digital systems : hardware/software codesign, integration, and test." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/15679.
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Chang, Daniel Y. "A systematic software, firmware, and hardware codesign methodology for digital signal processing." Thesis, Monterey, California: Naval Postgraduate School, 2014. http://hdl.handle.net/10945/41358.
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Approved for public release; distribution is unlimited.Creating an embedded system that meets its functional, performance, cost, and schedule goals is a software-and-hardware codesign problem, since the design of the software and hardware components influence each other. The traditional design methodology is sequential, with hardware designed first and then software. The lack of a unified and unbiased approach can lead to suboptimal design and incompatibilities across the software and hardware boundary. To solve these problems, we propose a new software/firmware/hardware codesign methodology to systematically build correct designs efficiently. This codesign methodology includes requirements development, architecture forming, software/ firmware/hardware partitioning, design-pattern mapping, new-design pattern synthesis, integration, and testing. We tested our methods on three application areas. One was a digitizer-filter architecture for ultra-high frequency signals for which we synthesized design patterns in firmware to meet high-frequency requirements. Another was a digitizer-filter architecture for low-frequency signals. A third was a hidden Markov model using dynamic programming. We implemented and tested the first application on a Tektronix/Synopsys embedded system and the second on a Pentek embedded system based on the requirements provided by the stakeholders
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Diehl, Márcia Regina. "Redes de projeto: Análise de Rede Social em uma Experiência de Codesign." Universidade do Vale do Rio dos Sinos, 2014. http://www.repositorio.jesuita.org.br/handle/UNISINOS/4015.
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Submitted by William Justo Figueiro (williamjf) on 2015-06-25T21:44:01Z
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A presente pesquisa analisou a evolução da rede projetual durante o desenvolvimento de um projeto de codesign envolvendo atores de diferentes organizações (interorganizacional), de várias disciplinas de conhecimento (interdisciplinar) e com distintos cargos e tarefas (interfuncional). Utilizou-se do método de análise de que é voltado a entender como se relacionam os atores que constituem uma rede. Os atores que participaram da rede projetual objeto deste estudo são designers, especialistas de outras disciplinas e os futuros usuários de uma plataforma digital para compartilhar conhecimento na comunidade de Taquara/RS. Foram coletados dados sobre as relações sociais entre os participantes e sobre os fluxos de informações durante o desenvolvimento do projeto. Dessa forma, foi possível desenhar os mapas de relações e calcular os índices de centralidade dos atores, ou seja, foi possível visualizar quem forneceu e quem recebeu informações, quais atores engajaram-se no processo servindo com intermediários das informações, os agrupamentos organizacionais, entre outras informações. O resultado do cruzamentos dos dados indicou que: os designers inseriramse na rede tornando-se fonte das informações projetuais; o gestor do projeto desempenhou o papel de gestor das relações provocando o adensamento das relações projetuais; alguns designers e um especialista tornaram-se fontes das informações de aprendizado das ferramentas projetuais. Tais resultados podem servir de insumos estratégicos para o trabalho em redes projetuais, auxiliando os designers no entendimento de suas funções projetuais quando operando projetos colaborativos interorganizacionais, interfuncionais e interdisciplinares.
The present study examined the evolution of design network during the development of a codesign project involving actors from different organizations (interorganizational) from various disciplines of knowledge (interdisciplinary) and with different positions and tasks (interfunctional). We used the method of social network analysis which is addressed to understand the actor’s relationship who constitute a network. The actors who participated of the project’s network, object of this study, are designers, specialists from other disciplines and future users of a digital platform for sharing knowledge in Taquara / RS community. It were collected data about the social relationships between the participants and about the flow of information during the development of the project. Thus, it was possible to draw maps of relationships and calculating the actor’s centrality, ie, it was possible to see who gave and who received information, which actors engaged in the process serving with intermediaries of information, organizational clusters, among other information. The result of the data’s intersections indicated that: the designers were inserted in the network becoming source of project's information; the project manager acted as manager of the relationships causing thickening of project relations; some designers and one expert become information’s source for learning of the project tools. These results may provide strategic inputs to work in project networks, helping designers in understanding its functions when operating interorganizational, interfunctional and interdisciplinary collaborative projects.
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Carvalho, Francisco Rogério de. "O Espaço do Brincar : um estudo sobre o Codesign Pedagógico para Ambientes Virtuais." Universidade Federal do Amazonas, 2016. http://tede.ufam.edu.br/handle/tede/5574.
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The technological revolution, leveraged by globalization, was one of the most farreaching changes in history, and education was not left out of this reality as many researchers, professionals and collaborators began to search for creations involving technology allied to education. Teaching and learning in a dynamic, attractive and efficient way. The diverse actors who work behind the scenes of new information and communication technologies - ICTs with a focus on education, often forget important elements in the process of designing such technological resources, especially with regard to planning, the form of collective work and the Recognition of the cultural differences of the target audience when creating tools to support teaching. In this work, the innovative collaborative work model: Codesign is applied in a case study, in the construction of a virtual toy room called Espaço do Brincar, whose development takes place in the Centro de Formação Continuada, desenvolvimento de Tecnologia e Prestação de Serviços para a Rede Pública de Ensino – CEFORT, Faculty of Education, Universidade Federal do Amazonas - UFAM and presents an innovative strategy for conceptions of projects to create technological mediations. By means of empirical and participative observation without leaving aside the theoretical support, the research results in a pioneering experience of collaborative work applied in the development of technological mediators of the learning for the platform Moodle, articulating with the actor-network theory in which, human actors And non-human actors, to a complex but comprehensive movement of ideas development and decision making that favors the teaching and learning process in a more efficient, clear and humanized way.
A revolução tecnológica, alavancada pela globalização, foi uma das mais abrangentes mudanças ocorridas na história e a educação não ficou de fora dessa realidade pois muitos pesquisadores, profissionais e colaboradores passaram a esmerar-se na busca por criações que envolvam tecnologia aliada à educação com o intuito de promover o ensino e aprendizagem de forma dinâmica, atrativa e eficiente. Os diversos atores que agem nos bastidores das novas tecnologias de informação e comunicação - TICs com foco na educação, muitas vezes olvidam elementos importantes no processo de concepção de tais recursos tecnológicos, especialmente no que se refere ao planejamento, à forma de trabalho coletivo e ao reconhecimento das diferenças culturais do público-alvo, quando da criação de ferramentas de apoio ao ensino. Neste trabalho, o modelo inovador de trabalho colaborativo: Codesign é aplicado em um estudo de caso, na construção de uma brinquedoteca virtual denominada Espaço do Brincar, cujo desenvolvimento se dá no Centro de Formação Continuada, desenvolvimento de Tecnologia e Prestação de Serviços para a Rede Pública de Ensino – CEFORT, da Faculdade de Educação da Universidade Federal do Amazonas - UFAM e apresenta uma estratégia inovadora para as concepções de projetos de criação de mediações tecnológicos. Por meio de observação empírica e participativa sem deixar de lado o apoio teórico, a pesquisa resulta numa experiência pioneira de trabalho colaborativo aplicado no desenvolvimento de mediadores tecnológicos da aprendizagem para a plataforma Moodle, articulando-se coma teoria ator-rede em que, atores humanos e não humanos agem, para um complexo, porém abrangente movimento de desenvolvimento de ideias e tomada de decisões que favoreçam o processo de ensino e aprendizagem de forma mais eficiente, clara e humanizada.
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Gebremariam, Kidane Tadesse. "Effectiveness of SMS text messaging to improve exclusive breastfeeding in Mekelle, Ethiopia." Thesis, Queensland University of Technology, 2020. https://eprints.qut.edu.au/205813/1/Kidane%20Tadesse_Gebremariam_Thesis.pdf.
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This thesis involved the development, delivery and evaluation of an SMS based mHealth intervention targeting fathers and mothers to improve exclusive breastfeeding at three months in Tigray, Ethiopia. Parents and health professionals co-designed the content of the intervention. The four-month trial identified that an SMS based breastfeeding intervention targeting fathers and mothers was more effective in improving exclusive breastfeeding than no intervention or an intervention to mothers only.
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Campagna, Isabelle. "Développement d'une méthodologie de codesign matériel/logiciel pour des applications de communications à haute vitesse." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0021/MQ53563.pdf.
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Cloute, François. "Étude de la conception des systèmes embarqués sur silicium : une approche de codesign matériel / logiciel." Toulouse, INPT, 2001. http://www.theses.fr/2001INPT018H.
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La conception des systèmes embarqués représente un défi majeur d'une importance croissante. Les technologies submicroniques permettent de fabriquer des systèmes toujours plus complexes, gagnant de nouveaux marchés dans les domaines des moyens de transport ou des télécommunications, tels que la téléphonie mobile, la télévision numérique, ou le multimédia. Cependant, cette potentialité est de plus en plus sous utilisée, car l'évolution de la capacité à concevoir de tels systèmes n'augmente pas au même rythme. Cette croissante capacité d'intégration accentue le besoin d'une nouvelle méthodologie de conception. L'objectif de cette thèse est de tentes d'apporter des éléments de réponse au problème de la conception des systèmes embarqués. Nous étudions pour ce faire une approche reposant sur la conception concurrente des parties matérielles câblées et des parties logicielles enfouies, en confrontant cette approche à la conception d'un équipement avionique. Cette thèse propose de passer d'une conception de niveau composant vers une conception qui appréhende le problème à partir d'un point de vue plus global : le niveau système. Les bénéfices issus de cette élévation d'abstraction doivent apporter un gain d'optimisation de la conception aussi bien en terme de qualité qu'en terme de productivité. Les étapes d'une méthodologie de codesign incluent au delà de la spécification de l'application au niveau système, un partitionnement matériel/logiciel, une modélisation des architectures potentielles, une sélection de l'architecture, une synthèse concurrente du matériel et du logiciel, et une covérification.
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Hanauer, Rodrigo. "Codesign: a interação projetual entre organizações e atores externos no processo de desenvolvimento de novos produtos." Universidade do Vale do Rio dos Sinos, 2013. http://www.repositorio.jesuita.org.br/handle/UNISINOS/4341.
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Submitted by William Justo Figueiro (williamjf) on 2015-07-08T20:39:25Z
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O processo de desenvolvimento de novos produtos apresenta-se como uma prática cada vez mais colaborativa. A partir de um modelo de inovação aberta que reconhece o valor das ideias geradas fora dos seus limites, as empresas passam a inserir participantes externos em diversas etapas da cadeia de criação de valor. Nesse sentido, o objetivo deste trabalho é discutir a interação entre atores externos e organizações que ocorre especificamente na etapa de design do desenvolvimento de novos produtos, no processo denominado codesign. Para tanto, é desenvolvida uma pesquisa-ação no âmbito de um projeto de codesign entre uma empresa do setor calçadista, usuários dos seus produtos e outros atores externos, focando na atuação do designer e no seu papel de mediação nas interações projetuais. Os principais resultados obtidos são a discussão da geração coletiva de conhecimento em um processo de codesign realizado em âmbito organizacional, da identificação dos atores e de seus papeis, da função de plataformas on-line, do uso de ferramentas projetuais. Finalmente, a pesquisa aponta para a possibilidade do codesign assumir um valor estratégico para o desenvolvimento organizacional.
The process of new product development is presented as a more collaborative practice. From an open innovation model that recognizes the value of ideas generated outside its limits, companies come to insert external participants in various stages of the value creation chain. From this, our goal is to analyze the interaction between external actors and organizations that occurs specifically in the design stage of new product development, in a process called co-design. For this, is developed an action research that involves a co-design project between company, users of their products and other external participants, focusing into the involvement of the designer and its role in mediating project interactions. The main results are the discussion of the collective generation of knowledge in a co-design process performed in the organizational context, the identification of the actors and their roles, the role of online platforms, the use of projective tools. Finally, the research points to the possibility of co-design assuming a strategic value for organizational development.
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Brunelli, Carmela Vieira. "A inclusão do usuário no processo de codesign como forma de aprimorar o projeto de informação." Universidade do Vale do Rio dos Sinos, 2016. http://www.repositorio.jesuita.org.br/handle/UNISINOS/5706.
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Submitted by Silvana Teresinha Dornelles Studzinski (sstudzinski) on 2016-09-15T15:30:48Z
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Neste estudo investigou-se o processo de projeto de informação através da ferramenta infográfico, a fim de entender de que modo a inclusão e a própria expressão do usuário no processo podem otimizá-lo. Explorou-se a forma com que o designer e o usuário da informação podem, através do codesign, projetar um infográfico que elimine, satisfatoriamente, lacunas na compreensão do usuário sobre um conteúdo técnico. Utilizando-se a metodologia de pesquisa-ação, que envolveu designers, usuários e outros, realizou-se um Workshop e Entrevistas em Profundidade, que serviram de campo para desenvolver um protótipo de infográfico. A partir dos resultados obtidos nesses ambientes, discutiram-se os principais achados em relação à inserção do usuário e ao aprimoramento da metodologia de projeto abordada. Nessa discussão analisou-se: o papel ativo do usuário no processo; o papel do designer, como tradutor de suas impressões sobre o usuário; e o papel do infográfico como ferramenta de projeto de informação. A avaliação dos atores em relação ao processo permitiu identificar pontos positivos agregados pelo codesign ao projeto, entre os quais a capacidade do usuário de criar atalhos e otimizar processos. Também foram abordadas as competências dos designers e os aspectos estruturais do infográfico, com o objetivo de justificar a perspectiva cocriativa para otimizar a informação.
The present study investigates the information design process through infographics, in order to understand how user involvement and expression can optimize the process. We examine how, through codesign, information designers and users can design an infographic that successfully eliminates gaps in user understanding of technical content. Using an action research methodology involving designers, users and authors in a cocreative approach, a workshop and in-depth interviews were conducted to serve as an arena for the development of a prototype infographic. Based on the results obtained in these settings, we discuss the main findings regarding user insertion and improvement of the design methodology by analyzing the active role of users in the infographic design process, the role of designers in conveying their impressions about users, and the role of the infographic as an information design tool. This assessment identifies the positive contribution of codesign to the design as a whole, such as the user’s ability to create shortcuts and optimize processes. We also address the skills of designers and structural aspects of the infographic in order to justify the cocreative approach as a means of optimizing information.
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Arpnikanondt, Chonlameth. "A Platform-Centric UML-/XML-Enhanced HW/SW Codesign Method for the Development of SoC Systems." Diss., Available online, Georgia Institute of Technology, 2004, 2004. http://etd.gatech.edu/theses/available/etd-04112004-153455/unrestricted/arpnikanondt%5Fchonlameth%5F200405%5Fphd.pdf.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004.Madisetti, Vijay, Committee Chair ; Mersereau, Russell, Committee Member ; Yalamanchili, Sudhakar, Committee Member. Includes bibliographical references.
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Nam, HyunSuk, and HyunSuk Nam. "Security-driven Design Optimization of Mixed Cryptographic Implementations in Distributed, Reconfigurable, and Heterogeneous Embedded Systems." Diss., The University of Arizona, 2017. http://hdl.handle.net/10150/624287.
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Distributed heterogeneous embedded systems are increasingly prevalent in numerous applications, including automotive, avionics, smart and connected cities, Internet of Things, etc. With pervasive network access within these systems, security is a critical design concern. This dissertation presents a modeling and optimization framework for distributed, reconfigurable, and heterogeneous embedded systems. Distributed embedded systems consist of numerous interconnected embedded devices, each composed of different computing resources, such single core processors, asymmetric multicore processors, field-programmable gate arrays (FPGAs), and various combinations thereof.
A dataflow-based modeling framework for streaming applications integrates models for computational latency, mixed cryptographic implementations for inter-task and intra task communication, security levels, communication latency, and power consumption. For the security model, we present a level-based modeling of cryptographic algorithms using mixed cryptographic implementations, including both symmetric and asymmetric implementations. We utilize a multi-objective genetic optimization algorithm to optimize security and energy consumption subject to latency and minimum security level constraints. The presented methodology is evaluated using a video-based object detection and tracking application and several synthetic benchmarks representing various application types. Experimental results for these design and optimization frameworks demonstrate the benefits of mixed cryptographic algorithm security model compared to single cryptographic algorithm alternatives. We further consider several distributed heterogeneous embedded systems architectures.
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SMARANDACHE, IRINA MADALINA. "Transformations affines d'horloges : application au codesign de systemes temps-reel en utilisant les langages signal et alpha." Rennes 1, 1998. http://www.theses.fr/1998REN10085.
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Cette these s'inscrit dans le cadre du developpement du langage signal dont les objectifs sont la specification et la mise en uvre d'applications temps-reel critiques. Nos travaux ont concerne l'extension du compilateur de signal qui est un outil formel pour la verification des contraintes de synchronisation d'horloges en signal. De maniere plus generale, notre etude se situe dans un contexte de conception conjointe de systemes mixtes materiel/logiciel (codesign) pour laquelle l'environnement de programmation de signal s'est prouve tres adapte. Dans ce contexte, nous avons constate que les langages signal et alpha possedent des proprietes complementaires concernant la programmation de traitements numeriques importants relies par du controle. Alpha est un langage fonctionnel pour la specification et l'implementation d'algorithmes reguliers, tandis que l'apport de signal se manifeste dans le domaine du controle. L'interfacage des deux langages a releve le probleme du raffinement des specifications mixtes et leur validation. Les transformations de specifications ont induit des transformations affines sur les horloges signal et la necessite de mettre en place un calcul formel sur les synchronisations des horloges transformees. Le nouveau calcul formel mis en place est base sur un ensemble de regles de synchronisabilite deduites a partir des proprietes des transformations affines. Nous avons retrouve des conditions de synchronisabilite basees sur un calcul d'entiers qui nous ont permis d'etendre les capacites de preuve formelle du compilateur de signal. Nous avons valide le calcul de synchronisabilite propose et les concepts lies a la conception conjointe avec signal et alpha a travers une application du domaine de codage d'images video.
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Kim, Jae Hong. "Wide-Band and Scalable Equivalent Circuit Model for Multiple Quantum Well Laser Diodes." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7129.
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This dissertation presents a wide-band lumped element equivalent circuit model and a building block-based scalable circuit model for multiple quantum well laser diodes. The wide-band multiple-resonance model expresses two important laser diode characteristics such as input reflection and electrical-to-optical transmission together. Additionally, it demonstrates good agreements with the measurement results of the selected commercial discrete laser diodes. The proposed building block-based modeling approach proves its validity using a numerically derived scalable rate equation. Since success in a circuit design depends largely on the availability of accurate device models, the practical application of the proposed models provides improved accuracy, simple implementation and a short design time.
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Ehliar, Andreas. "Performance driven FPGA design with an ASIC perspective." Doctoral thesis, Linköpings universitet, Datorteknik, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16372.
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FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient. This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA. Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA. The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated. All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs. Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.
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Yeh, Jinn-Wang, and 葉進旺. "The Study on Hardware/Software CoDesign." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/02143895370729762762.
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碩士國立交通大學
電子工程系
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This thesis investigates an effective approach to the system-level design of multimedia signal processing applications. To design these systems, we use the hardware/software codesign approach, which allows the hardware and software designs to be tightly coupled throughout the design process. Given a specification of system functionality and constraints, we propose a model to describe the system. After the model has been analyzed, partitioning is used to determine the parts of the system functionality that are delegated to application-specific hardware and the software that runs on the processor. Based on the result of hardware/software partitioning, we determine the optimal implementation of a system. We also explore issues concerning system synchronization and the implementation of hardware/software interface to accommodate communications between various parts of the system. This hardware and software codesign approach proposed makes it possible to build a time-constrained signal processing system on a chip using programmable parts and application-specific units. We use a media processor design as an example. The verification method and simulation results are also given in this thesis.
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Lu, Yu-Yin, and 盧昱穎. "Partitioning Strategies of Hardware Software Codesign." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/42449968580705942666.
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碩士大同大學
資訊工程研究所碩士在職專班
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We exploit to design a partitioning tool at hardware software partitioning technology. The thesis describes the partitioning progress and method. There are used the Java programs partitioning tool to specify the partitioning technology and progress. We profile the Java programs to get the program profile information. Then we can use the partitioning tool to partition the program for hardware software co-design. The goal is to enhance the performance of design system. This partitioning tool identifies the critical section in the java programs. It proposed three strategies, execution time, invocation count and saving time cost-effective, and many configurations to setup the tool. It can base the design constrain to partitioning the java program. This can help developer evaluate the partitioning result, and then user can modify the partitioning objects of hardware or software parts to optimization system. The design steps of hardware software partitioning include four steps. First of all, we get the Java programs and define the system requirement. Then create the java bytecode. Second, profiling the program, we specify a tool to get the profile information. This progress needs testing data to realizable to run the program. Third, we specify the method and architecture of partitioning tool. And there are compare the advance and defect by each partitioning strategies. Finally, we specify the conclusion and feature work on hardware software partition.
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Lee, Ren-Jie, and 李仁傑. "Algorithms for Chip-Package-Board Codesign." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/45606062599353937939.
Full textAbstract:
博士國立交通大學
電子研究所
98
Due to the trend of more and more SoC and SiP projects, the complication in chip, package and board designs, and signal interactions thereof is increasing very rapidly. Typical peripheral wire-bond design will be inappropriate for most modern designs; therefore flip-chip package becomes an inevitable choice. However, engineers usually designate the key interfaces including I/Os, bumps and package pin-out (ballplan) by hands in conventional flip-chip designs. The chip-package-board co-planning process is indeed time-consuming and always postpones the time-to-market (TTM) of products. In response to the aforementioned issues, this dissertation proposes methodologies in planning those interfaces with concurrent codesign paradigm, thus speeding up the developing time dramatically. The dissertation contains three parts. First, we propose a novel and very efficient approach to automating pin-out designation in flip-chip BGA packaging for package-board codesign. The manual time-consuming codesign works can be replaced by proposed methodologies. Through considering signal integrity, power delivery, and routability in pin-block design, our frameworks provide trade-offs in signal performance and package cost while achieving the minimum package size. Second, we present a planning algorithm to optimize pin-block locations by using a new representation for pin-block placement, and defining range constraints in stochastic framework. The experimental results show that our algorithm optimizes the system interconnects during package pin-out planning. In addition to the package-board codesign, we develop a concurrent design flow for chip-package codesign in the third part. Comparing with the previous works, the methods in this part preliminarily provide the optimization study of net crossing and length deviation which are very critical requirements in chip-package codesign. By designing specific I/O-bump tiles and proposing an innovative I/O-row based scheme, two heuristic methods and one assignment algorithm are provided for package-aware I/O-bump planning. As a result, a chip-package-board co-planning automation attempt is accomplished for optimizing performance and design cost simultaneously.
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Chan, Wu-Hsiung, and 詹武雄. "HRMS：A Distributed Hardware/Software Codesign Environment." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/14816048968348389747.
Full textAbstract:
碩士逢甲大學
資訊工程學系
89
The three steps of designing program of the traditional Hardware/Software Codesign system are: Profiling Phase, Partitioning Phase, and Cosynthesis Phase. The system also needs a powerful cosynthesis compiler to compile a codesign program. There are advantages for traditional codesign system. There are more options to do the system optimization. The whole design procedure is variable, because of hardware environment could be modified immediately. And it would not impact the total design time. But there are also disadvantages for this system. The design procedure is too complex. Designer should have enough professional knowledge to the design job. This paper describes a simplified Hardware/Software Codesign procedure that designer could easily design a codesign program. It could reduce the difficulty and complexity in designing. And it reserves the basic performance of a codesign system. The Hardware Resources Management System (HRMS) is designed as the bridge between applications and the hardware device. On environment of the simplified codesign system of this paper, a program could employ the pre-user defined function to download and execute the circuits. By the HRMS, the working environment could be the stand-alone or the client-server architecture. The relational system components are designed with Visual Basic 6. The cooperating hardware device is a Reusable PCI Interface (RePCI) with a FPGA chip. It hopes that the design time and compiling time could be reduced with the system performance begin reserved in this simplified codesign system. And it also hopes to support more programming language could work in the codesign environment.
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Tzeng, Guo-Chang, and 曾國昌. "Research on Packages and PCB Codesign." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/47889658226379448098.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
89
ABSTRACT As the number of pins in Ball Grid Array (BGA) and Pin Grid Array (PGA) packages increase, the routing of a Printed-Circuit-Board (PCB) becomes more and more difficult. CAD Tools at present time do not offer a proper integrated developing environment to consider both the PGA/BGA routing and PCB routing problems at the same time. In this Thesis, we propose an algorithm to perform the pin assignment on PGA/BGA packages to achieve the goal of chip-package codesign under the consideration of PCB routing. Given a chip with a number of I/O pads around the boundary of the chip and a number of devices (blocks) distributed on a printed-circuit-board which includes a PGA or BGA chip, our goal is to find a pin assignment solution which eases the routing of a PGA/BGA router and increases the routability of a PCB router. For a randomly initialized pin assignment solution, we use a simulated-annealing algorithm to improve the solution by exchanging the pin assignment for some chosen nets. The routing cost of the PCB router and the PGA/BGA router can be calculated separately for the pin assignment algorithm. The algorithm performs the pin assignment exchange by keeping a cost table which records the cost of different types of exchanges calculated from the other two routers. Some examples are also provided to compare the results of our pin assignment algorithm that considers PCB routing with the results of that without considering PCB routing.
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Zeng, Yu Da, and 曾裕達. "FACE a codesign environment for microprocessor." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/19973363307102096554.
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Rosa, João Manuel de Sousa Nunes da Costa. "Citizens Can: codesign e designing design." Doctoral thesis, 2019. http://hdl.handle.net/10451/40669.
Full textAbstract:
Research selects as main issue the raison d’être of design activity, traditionally associate with the act of projecting —conceiving solutions that contribute to the breeding of the artificial world— and in is extend field: relations that design establish with the biosphere. We argue that design, as an act of project, do not pursuit only material answers, neither is closed nor finish at the moment that proceeds the delivery solution Design is not only a result, neither a visible shape, a configuration or a product, an object or an artefact. Is also a process: reflection, search for relations, making sense and implementation of social networks. Based on codesign, design will be no longer limited to the work of a master designer and moves to the space of action and collective responsibility. This interpretation sees design as a process of languaging or conversation, setting the common ground of meaning and understanding: collective decisions expressed by actions-solutions taken as a set, by shared responsibility and dialogue, or articulation between our needs and the vast reality of the biosphere. According to this point of view, acting in design is primarily a process which seeks promote balances, relationships and interactions (languaging), that come to the forefront or are structured by consensus and actions, which turn into solutions.
In this point of view, consensus is the main goal of design, because through them we conceived answers, not necessarily expressed by objects or material solutions. The idea of openness in design, the invitation to collective participation, is parcel of the contribution to improve relations between parts, as well between parts and the whole, boosting the nature of systemic relations: a web of people and the rest of the world, the remain elements and components of our system of life. In this study we reiterate that design will always be a search for alternatives or better situations, preferred ones, durables, well balanced and more equitable: process of questioning, redesign and improving what we do, how we do and how we live. According to our vision, making together is a fully, democratic and eco-social process to promote change and build improvement, because design cannot run (only) inside one level, the one of our priorities and needs: design also exists in relation, talking or in dialogue with the rest, design only gets sense if exists inside a wide circumstance.