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Journal articles on the topic 'Coarse Grained Reconfigurable arrays'

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Author: Grafiati

Published: 6 September 2023

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1

Dimitroulakos, Grigorios, Stavros Georgiopoulos, Michalis D. Galanis, and Costas E. Goutis. "Resource aware mapping on coarse grained reconfigurable arrays." Microprocessors and Microsystems 33, no. 2 (March 2009): 91–105. http://dx.doi.org/10.1016/j.micpro.2008.07.002.

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2

Theocharis, Panagiotis, and Bjorn De Sutter. "A Bimodal Scheduler for Coarse-Grained Reconfigurable Arrays." ACM Transactions on Architecture and Code Optimization 13, no. 2 (June 27, 2016): 1–26. http://dx.doi.org/10.1145/2893475.

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3

Ansaloni, Giovanni, Kazuyuki Tanimura, Laura Pozzi, and Nikil Dutt. "Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 12 (December 2012): 1803–16. http://dx.doi.org/10.1109/tcad.2012.2209886.

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4

Egger, Bernhard, Eunjin Song, Hochan Lee, and Daeyoung Shin. "Verification of coarse-grained reconfigurable arrays through random test programs." ACM SIGPLAN Notices 53, no. 6 (December 7, 2018): 76–88. http://dx.doi.org/10.1145/3299710.3211342.

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5

Filho, J. O., S. Masekowsky, T. Schweizer, and W. Rosenstiel. "CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 9 (September 2009): 1247–59. http://dx.doi.org/10.1109/tvlsi.2008.2002429.

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6

Dimitroulakos, Grigorios, Nikos Kostaras, Michalis D. Galanis, and Costas E. Goutis. "Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays." Journal of Supercomputing 48, no. 2 (May 16, 2008): 115–51. http://dx.doi.org/10.1007/s11227-008-0208-y.

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7

Qu, Tongzhou, Zibin Dai, Yanjiang Liu, and Lin Chen. "A High Flexible Shift Transformation Unit Design Approach for Coarse-Grained Reconfigurable Cryptographic Arrays." Electronics 11, no. 19 (September 30, 2022): 3144. http://dx.doi.org/10.3390/electronics11193144.

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Shift transformations are the fundamental operation of cryptographic algorithms, and the arithmetic unit implementing different types of shift transformations are utilized in the coarse-grain reconfigurable cryptographic architectures (CGRCA) to meet the different cryptographic algorithms. In this paper, a reconfigurable shift transformation unit (RSTU) is proposed to meet the complicated shift requirement of CGRCA, which achieves high flexibility and a good cost–performance ratio. The mathematical properties of shift transformation are analyzed, and several theorems are introduced to design a reconfigurable shifter. Furthermore, the reconfigurable data path of the proposed unit is presented to implement the random combination of shift operations in different granularity, and configuration word and routing algorithms are proposed to generate control information for RSTU. Moreover, the control information generation module is designed to invert the configuration word into the control information, according to the routing algorithms. As a proof-of-concept, the proposed RSTU is built using the CMOS 65 nm technology. The experimental results show that RSTU supports more shift operations, increases 18.2% speed at most, and reduces 13% area occupation, compared to the existing shifters.

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Lopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto, and José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture." Electronics 10, no. 6 (March 12, 2021): 669. http://dx.doi.org/10.3390/electronics10060669.

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Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.

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9

De Sutter, Bjorn, Paul Coene, Tom Vander Aa, and Bingfeng Mei. "Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays." ACM SIGPLAN Notices 43, no. 7 (June 27, 2008): 151–60. http://dx.doi.org/10.1145/1379023.1375678.

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10

Kissler, Dmitrij, Daniel Gran, Zoran Salcic, Frank Hannig, and Jürgen Teich. "Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays." IEEE Embedded Systems Letters 3, no. 2 (June 2011): 58–61. http://dx.doi.org/10.1109/les.2011.2124438.

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11

Yang, Chen, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, and Shaojun Wei. "Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array." Journal of Circuits, Systems and Computers 24, no. 03 (February 10, 2015): 1550043. http://dx.doi.org/10.1142/s0218126615500437.

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The major bottleneck of coarse-grained reconfigurable arrays (CGRAs) is the excessive configuration overhead; as a result, computing potential cannot be fully utilized. At run-time, the function of CGRAs can be fully and dynamically reconfigured by changing contexts. Therefore, the frequency of context switching on CGRAs is very high. On the other hand, the configuration time of CGRAs is very long. This paper proposes three configuration approaches to reduce interval latency when switching configuration contexts. These proposed approaches include input data relocation (IDR), line-based context switching (LCS), and loop interval minimization (LIM). IDR relocates input data to the first stage of the pipeline; as a result, the delay time for the input data of the next data flow graph (DFG) is reduced. LCS is a LCS mechanism for adjacent independent DFGs to reduce the interval of context switching, thereby expanding the depth of the pipeline. LIM is used to minimize the interval of loops. Simulations on a coarse-grained reconfigurable processor called reconfigurable multimedia system (REMUS) show that 1080 p@30 fps for H.264 high profile video decoding can be achieved under 200 MHz working frequency. As for AVS and MPEG2 decoding algorithms, much higher performance, i.e., 1080 p@39 fps and 1080 p@41 fps, can be achieved respectively.

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12

Choi, Kiyoung. "Coarse-Grained Reconfigurable Array: Architecture and Application Mapping." IPSJ Transactions on System LSI Design Methodology 4 (2011): 31–46. http://dx.doi.org/10.2197/ipsjtsldm.4.31.

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13

Döbrich, Stefan, and Christian Hochberger. "Low-Complexity Online Synthesis for AMIDAR Processors." International Journal of Reconfigurable Computing 2010 (2010): 1–15. http://dx.doi.org/10.1155/2010/953693.

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Future chip technologies will change the way we deal with hardware design. First of all, logic resources will be available in vast amount. Furthermore, engineering specialized designs for particular applications will no longer be the general approach as the nonrecurring expenses will grow tremendously. Reconfigurable logic has often been promoted as a solution to these problems. Today, it can be found in two varieties: field programmable gate arrays or coarse-grained reconfigurable arrays. Using this type of technology typically requires a lot of expert knowledge, which is not sufficiently available. Thus, we believe that online synthesis that takes place during the execution of an application is one way to broaden the applicability of reconfigurable architectures. In this paper, we show that even a relative simplistic synthesis approach with low computational complexity can have a strong impact on the performance of compute intensive applications.

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14

Hartmann, Matthias, Vasileios (Vassilis) Pantazis, Tom Vander Aa, Mladen Berekovic, and Christian Hochberger. "Still Image Processing on Coarse-Grained Reconfigurable Array Architectures." Journal of Signal Processing Systems 60, no. 2 (December 11, 2008): 225–37. http://dx.doi.org/10.1007/s11265-008-0309-0.

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15

Ferreira, Ricardo S., João M. P. Cardoso, Alex Damiany, Julio Vendramini, and Tiago Teixeira. "Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks." Journal of Systems Architecture 57, no. 8 (September 2011): 761–77. http://dx.doi.org/10.1016/j.sysarc.2011.03.006.

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16

Zhou, Li, Dongpei Liu, Jianfeng Zhang, and Hengzhu Liu. "Application-specific coarse-grained reconfigurable array: architecture and design methodology." International Journal of Electronics 102, no. 6 (August 8, 2014): 897–910. http://dx.doi.org/10.1080/00207217.2014.942885.

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17

Bae, Inpyo, Barend Harris, Hyemi Min, and Bernhard Egger. "Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 11 (November 2018): 2301–10. http://dx.doi.org/10.1109/tcad.2018.2857278.

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18

Vranjković, Vuk S., Rastislav J. R. Struharik, and Ladislav A. Novak. "Reconfigurable Hardware for Machine Learning Applications." Journal of Circuits, Systems and Computers 24, no. 05 (April 8, 2015): 1550064. http://dx.doi.org/10.1142/s0218126615500644.

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This paper proposes universal coarse-grained reconfigurable computing architecture for hardware implementation of decision trees (DTs), artificial neural networks (ANNs), and support vector machines (SVMs), suitable for both field programmable gate arrays (FPGA) and application specific integrated circuits (ASICs) implementation. Using this universal architecture, two versions of DTs (functional DT and axis-parallel DT), two versions of SVMs (with polynomial and radial kernel) and two versions of ANNs (multi layer perceptron ANN and radial basis ANN) machine learning classifiers, have been implemented in FPGA. Experimental results, based on 18 benchmark datasets of standard UCI machine learning repository database, show that FPGA implementation provides significant improvement (1–2 orders of magnitude) in the average instance classification time, in comparison with software implementations based on R project.

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19

Munaf, S., Dr A. Bharathi, and Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Electrical and Electronics Research 4, no. 1 (March 31, 2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.

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Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a con- figuration memory unit (configuration cache) for reconfiguration of its PE array. Though this architecture is meant for high performance and flexibility. Power reduction is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. We propose a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) architecture to reduce power-overhead caused by reconfiguration. The power reduction can be achieved by using the characteristics like double pumping the data bus and an I/O buffer between the memory and the data bus of DDR SDRAM. All modules have been designed at behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.

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20

Hannig, Frank, Hritam Dutta, and Jurgen Teich. "Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology." International Journal of Embedded Systems 2, no. 1/2 (2006): 114. http://dx.doi.org/10.1504/ijes.2006.010170.

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21

Kissler, Dmitrij, Frank Hannig, and Jürgen Teich. "Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays." Journal of Low Power Electronics 7, no. 1 (February 1, 2011): 29–40. http://dx.doi.org/10.1166/jolpe.2011.1114.

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22

KIM, YOONJIN. "POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE." Journal of Circuits, Systems and Computers 22, no. 03 (March 2013): 1350001. http://dx.doi.org/10.1142/s0218126613500011.

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Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes — one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves 56.50%/86.84% of the average power in write/read-operation of configuration cache compared to the previous design.

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23

Patel, Kunjan, Séamas McGettrick, and C. J. Bleakley. "Rapid functional modelling and simulation of coarse grained reconfigurable array architectures." Journal of Systems Architecture 57, no. 4 (April 2011): 383–91. http://dx.doi.org/10.1016/j.sysarc.2011.02.006.

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24

Qu, Tongzhou, Zibin Dai, Chen Lin, and Anqi Yin. "Adaptive loop pipeline control mechanism for Coarse-Grained Reconfigurable Block Cipher Array." Journal of Physics: Conference Series 1971, no. 1 (July 1, 2021): 012051. http://dx.doi.org/10.1088/1742-6596/1971/1/012051.

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25

Yang, Chen, LeiBo Liu, ShouYi Yin, and ShaoJun Wei. "Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays." Science China Physics, Mechanics & Astronomy 57, no. 12 (October 21, 2014): 2214–27. http://dx.doi.org/10.1007/s11433-014-5610-2.

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26

Rouson, Damian W. I., and Yi Xiong. "Design Metrics in Quantum Turbulence Simulations: How Physics Influences Software Architecture." Scientific Programming 12, no. 3 (2004): 185–96. http://dx.doi.org/10.1155/2004/910505.

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The information hiding philosophy of object-oriented programming encourages localizing data structures within objects rather than sharing data globally across different classes of objects. This emphasis on local data leads naturally to fine-grained data abstractions, particularly in scientific simulations involving large collections of small, discrete physical or mathematical objects. This paper focuses on a subset of such simulations where dynamically reconfigurable links bind the objects together. It is demonstrated that fine-grained data structures reduce the complexity of local operations on the data at the potential expense of increased global operation complexity. Two metrics are used to describe data structures: granularity is the number of instantiations required to cover the data space, whereas extent is the continuously traversable length of the data along a given direction. These definitions are applied to two abstractions for simulating the turbulent motion of quantum vortices in superfluid liquid helium. Several local and global operations on a fine-grained linked list are compared with those on a coarse-grained array. It is demonstrated that fine-grained data structures recover the simplicity of more coarse-grained structures if maximal extent is maintained as the granularity increases.

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27

Patel, Kunjan, and Chris J. Bleakley. "Coarse Grained Reconfigurable Array Based Architecture for Low Power Real-Time Seizure Detection." Journal of Signal Processing Systems 82, no. 1 (March 7, 2015): 55–68. http://dx.doi.org/10.1007/s11265-015-0981-9.

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28

Liu, Leibo, Chen Yang, Shouyi Yin, and Shaojun Wei. "CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 6 (June 2018): 1171–84. http://dx.doi.org/10.1109/tcad.2017.2748026.

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29

Yang, Chen, Leibo Liu, Kai Luo, Shouyi Yin, and Shaojun Wei. "CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Parallel and Distributed Systems 28, no. 1 (January 1, 2017): 29–43. http://dx.doi.org/10.1109/tpds.2016.2554278.

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30

Weinhardt, Markus, Mohamed Messelka, and Philipp Käsgen. "CHiPReP—A Compiler for the HiPReP High-Performance Reconfigurable Processor." Electronics 10, no. 21 (October 23, 2021): 2590. http://dx.doi.org/10.3390/electronics10212590.

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This article presents CHiPReP, a C compiler for the HiPReP processor, which is a high-performance Coarse-Grained Reconfigurable Array employing Floating-Point Units. CHiPReP is an extension of the LLVM and CCF compiler frameworks. Its main contributions are (i) a Splitting Algorithm for Data Dependence Graphs, which distributes the computations of a C loop to Address-Generator Units and Processing Elements; (ii) a novel instruction clustering and scheduling heuristic; and (iii) an integrated placement, pipeline balancing and routing optimization method based on Simulated Annealing. The compiler was verified and analyzed using a cycle-accurate HiPReP simulation model.

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31

Lu, Yanan, Leibo Liu, Yangdong Deng, Jian Weng, Shouyi Yin, Yiyu Shi, and Shaojun Wei. "Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Parallel and Distributed Systems 29, no. 10 (October 1, 2018): 2360–72. http://dx.doi.org/10.1109/tpds.2018.2822708.

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32

Li, Zeyu, Junjie Wang, Zhao Huang, Nan Luo, and Quan Wang. "Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans based on Evolvable Hardware." Applied Sciences 12, no. 13 (June 29, 2022): 6601. http://dx.doi.org/10.3390/app12136601.

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Hardware Trojans (HTs) are malicious hardware components designed to leak confidential information or cause the chip/circuit on which they are integrated to malfunction during operation. When we deploy such hardware platforms for edge computing, FPGA-based implementations of Coarse-Grained Reconfigurable Array (CGRA) are also currently falling victim to HT insertion. However, for CGRA, an evolvable hardware (EHW) platform, which has the ability to dynamically change its configuration and behavioral characteristics based on inputs from the environment, provides us with a new way to mitigate HT attacks. In this regard, we investigate the feasibility of using EHW to mitigate HTs that disrupt normal functionality in CGRA in this paper. When it is determined that HT is inserted into certain processing elements (PEs), the array autonomously reconfigures the circuit structure based on an evolutionary algorithm (EA) to avoid the use of HT-infected (HT-I) PEs. We show that the proposed approach is applicable to: (1) hardware platforms that support coarse-grained reconfiguration; and (2) pure combinatorial circuits. In a simulation environment built in Python, this paper reports experimental results for two target evolutionary circuits and outlines the effectiveness of the proposed method.

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33

Mehta, Dinesh P., Carl Shetters, and Donald W. Bouldin. "Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs." VLSI Design 2013 (December 25, 2013): 1–13. http://dx.doi.org/10.1155/2013/249592.

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This paper considers the problem of scheduling a chain of n coarse-grained tasks on a linear array of k reconfigurable FPGAs with the objective of primarily minimizing reconfiguration time. A high-level meta-algorithm along with two detailed meta-algorithms (GPRM and SPRM) that support a wide range of problem formulations and cost functions is presented. GPRM, the more general of the two schemes, reduces the problem to computing a shortest path in a DAG; SPRM, the less general scheme, employs dynamic programming. Both meta algorithms are linear in n and compute optimal solutions. GPRM can be exponential in k but is nevertheless practical because k is typically a small constant. The deterministic quality of this meta algorithm and the guarantee of optimal solutions for all of the formulations discussed make this approach a powerful alternative to other metatechniques such as simulated annealing and genetic algorithms.

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34

Liu, LeiBo, YanSheng Wang, ShouYi Yin, Min Zhu, Xing Wang, and ShaoJun Wei. "Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture." Science China Information Sciences 57, no. 10 (September 6, 2014): 1–18. http://dx.doi.org/10.1007/s11432-013-4973-8.

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35

Mudza, Zbigniew, and Rafał Kiełbik. "Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions." Electronics 11, no. 8 (April 16, 2022): 1261. http://dx.doi.org/10.3390/electronics11081261.

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FPGAs can provide application-specific acceleration for computationally demanding tasks. However, they are rarely considered general-purpose platforms due to low productivity of software development and long reconfiguration time. These problems can be mitigated by implementing a coarser overlay atop the FPGA fabric. Combining this approach with partial reconfiguration allows for the modification of individual processing elements (PEs) of the virtual architecture without altering the rest of the system. Module relocation can be used to share implementation details between functionally equivalent PEs that use identical sets of resources, thus eliminating redundant placement and routing runs. Proper floorplanning is crucial for virtual Coarse-Grained Reconfigurable Architectures (CGRAs) with relocatable PEs considering their tendency to use nearest-neighbor connection patterns. It requires solving two problems—finding identical regions in the FPGA fabric and assigning individual partitions to certain locations. This article presents minor improvements of a state-of-the-art solution for the first and proposes a novel technique for solving the other. The proposed automated floorplanner uses modified breadth-first search with direction-based penalties to create initial floorplan consistent with geometry of logical array, then improves the result with 2-opt local optimization. Compared to simulated annealing solutions, the proposed approach allows for the reduction in the floorplanning time by two to three orders of magnitude without compromising the quality of the results.

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36

Ho, H., V. Szwarc, and T. Kwasniewski. "A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications." International Journal of Reconfigurable Computing 2009 (2009): 1–14. http://dx.doi.org/10.1155/2009/529512.

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A reconfigurable systolic array (RSA) architecture that supports the realization of DSP functions for multicarrier wireless and multirate applications is presented. The RSA consists of coarse-grained processing elements that can be configured as complex DSP functions that are the basic building blocks of Polyphase-FIR filters, phase shifters, DFTs, and Polyphase-DFT circuits. The homogeneous characteristic of the RSA architecture, where each reconfigurable processing element (PE) cell is connected to its nearest neighbors via configurable switch (SW) elements, enables array expansion for parallel processing and facilitates time sharing computation of high-throughput data by individual PEs. For DFT circuit configurations, an algorithmic optimization technique has been employed to reduce the overall number of vector-matrix products to be mapped on the RSA. The hardware complexity and throughput of the RSA-based DFT structures have been evaluated and compared against several conventional modular FFT realizations. Designs and circuit implementations of the PE cell and several RSAs configured as DFT and Polyphase filter circuits are also presented. The RSA architecture offers significant flexibility and computational capacity for applications that require real time reconfiguration and high-density computing.

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37

Zhao, Zhongyuan, Weiguang Sheng, Jinchao Li, Pengfei Ye, Qin Wang, and Zhigang Mao. "Similarity-Aware Architecture/Compiler Co-Designed Context-Reduction Framework for Modulo-Scheduled CGRA." Electronics 10, no. 18 (September 9, 2021): 2210. http://dx.doi.org/10.3390/electronics10182210.

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Modulo-scheduled coarse-grained reconfigurable array (CGRA) processors have shown their potential for exploiting loop-level parallelism at high energy efficiency. However, these CGRAs need frequent reconfiguration during their execution, which makes them suffer from large area and power overhead for context memory and context-fetching. To tackle this challenge, this paper uses an architecture/compiler co-designed method for context reduction. From an architecture perspective, we carefully partition the context into several subsections and only fetch the subsections that are different to the former context word whenever fetching the new context. We package each different subsection with an opcode and index value to formulate a context-fetching primitive (CFP) and explore the hardware design space by providing the centralized and distributed CFP-fetching CGRA to support this CFP-based context-fetching scheme. From the software side, we develop a similarity-aware tuning algorithm and integrate it into state-of-the-art modulo scheduling and memory access conflict optimization algorithms. The whole compilation flow can efficiently improve the similarities between contexts in each PE for the purpose of reducing both context-fetching latency and context footprint. Experimental results show that our HW/SW co-designed framework can improve the area efficiency and energy efficiency to at most 34% and 21% higher with only 2% performance overhead.

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38

Tehre, Vaishali, and Ravindra Kshirsagar. "Survey on Coarse Grained Reconfigurable Architectures." International Journal of Computer Applications 48, no. 16 (June 30, 2012): 1–7. http://dx.doi.org/10.5120/7429-0104.

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39

Jong-eun Lee, Kiyoung Choi, and N. D. Dutt. "Compilation approach for coarse-grained reconfigurable architectures." IEEE Design & Test of Computers 20, no. 1 (January 2003): 26–33. http://dx.doi.org/10.1109/mdt.2003.1173050.

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40

Paek, Jong Kyung, Kiyoung Choi, and Jongeun Lee. "Binary acceleration using coarse-grained reconfigurable architecture." ACM SIGARCH Computer Architecture News 38, no. 4 (September 14, 2010): 33–39. http://dx.doi.org/10.1145/1926367.1926374.

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41

Ansaloni, Giovanni, Paolo Bonzini, and Laura Pozzi. "EGRA: A Coarse Grained Reconfigurable Architectural Template." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 6 (June 2011): 1062–74. http://dx.doi.org/10.1109/tvlsi.2010.2044667.

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42

Wang, Xing, Lei Bo Liu, Shou Yi Yin, Min Zhu, and Shao Jun Wei. "H.264/AVC Intra Predictor on a Coarse-Grained Reconfigurable Multi-Media System." Advanced Materials Research 546-547 (July 2012): 469–74. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.469.

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Coarse-Grained Reconfigurable Architectures (CGRA) have proved to be the potential candidates to meet the high performance, low power and flexibility required by embedded systems. In this paper, we implemented a High Profile Intra Predictor for H.264/AVC decoder on a novel coarse-grained reconfigurable processor- Remus (Reconfigurable Multi-media System). We proposed the pipeline and parallel scheduling process for intra prediction algorithm and the simulation results show that 548 clock cycles are consumed for the worst case of intra macro blocks.

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YIN, Shouyi, Chongyong YIN, Leibo LIU, Min ZHU, and Shaojun WEI. "Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture." IEICE Transactions on Information and Systems E95-D, no. 2 (2012): 335–44. http://dx.doi.org/10.1587/transinf.e95.d.335.

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Wang, Chao, Peng Cao, and Jun Yang. "Efficient AES cipher on coarse-grained reconfigurable architecture." IEICE Electronics Express 14, no. 11 (2017): 20170449. http://dx.doi.org/10.1587/elex.14.20170449.

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Hussain, Shaik Rizwan, and Jahangir Badashah Syed. "Design and Applications of Coarse-Grained Reconfigurable Architectures." International Journal of Scientific Research 2, no. 12 (June 1, 2012): 198–201. http://dx.doi.org/10.15373/22778179/dec2013/61.

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Atak, Oguzhan, and Abdullah Atalar. "BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 7 (July 2013): 1285–98. http://dx.doi.org/10.1109/tvlsi.2012.2207748.

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Akbari, Omid, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, and Muhammad Shafique. "Toward Approximate Computing for Coarse-Grained Reconfigurable Architectures." IEEE Micro 38, no. 6 (November 1, 2018): 63–72. http://dx.doi.org/10.1109/mm.2018.2873951.

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Sim, Hyeonuk, Hongsik Lee, Seongseok Seo, and Jongeun Lee. "Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 7 (July 2016): 1092–104. http://dx.doi.org/10.1109/tcad.2015.2504918.

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Seveso, Luigi, Dardo Goyeneche, and Karol Życzkowski. "Coarse-grained entanglement classification through orthogonal arrays." Journal of Mathematical Physics 59, no. 7 (July 2018): 072203. http://dx.doi.org/10.1063/1.5006890.

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KOJIMA, Takuya, and Hideharu AMANO. "A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures." IEICE Transactions on Information and Systems E102.D, no. 7 (July 1, 2019): 1247–56. http://dx.doi.org/10.1587/transinf.2018edp7336.

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