Journal articles: 'CMOS'

1

Deleonibus, S. "Alternative CMOS or alternative to CMOS?" Microelectronics Reliability 41, no. 1 (January 2001): 3–12. http://dx.doi.org/10.1016/s0026-2714(00)00196-7.

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Kawahito, Shoji. "CMOS Image Sensors." IEEJ Transactions on Sensors and Micromachines 134, no. 7 (2014): 199–205. http://dx.doi.org/10.1541/ieejsmas.134.199.

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Lau, K. T., W. Y. Wang, and K. W. Ng. "Adiabatic-CMOS/CMOS-adiabatic logic interface circuit." International Journal of Electronics 87, no. 1 (January 2000): 27–32. http://dx.doi.org/10.1080/002072100132417.

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Banerjee, Sanjay K., Leonard Franklin Register, Emanuel Tutuc, Dipanjan Basu, Seyoung Kim, Dharmendar Reddy, and Allan H. MacDonald. "Graphene for CMOS and Beyond CMOS Applications." Proceedings of the IEEE 98, no. 12 (December 2010): 2032–46. http://dx.doi.org/10.1109/jproc.2010.2064151.

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GABARA, THAD. "PULSED LOW POWER CMOS." International Journal of High Speed Electronics and Systems 05, no. 02 (June 1994): 159–77. http://dx.doi.org/10.1142/s0129156494000097.

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A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS. In addition, several advantages occur in this new circuit technique: (1) low power signal propagation through several gates in series can occur during each evaluation cycle; (2) crowbar current does not occur; (3) additional placed devices, i.e. bipolar, diodes, JFETs are not required to generate this low power capability; (4) the Conventional CMOS process is used to fabricate the circuit; (5) the same physical layout can be used either as a PPS CMOS circuit or as a Conventional CMOS circuit; (6) the device count is the same as that of Conventional CMOS; (7) PPS CMOS uses quasistatic logic levels; (8) capacitive coupling is used to store and restore the contents of a memory cell; (9) the parasitic diodes of the MOS devices are used to improve the noise margin of the circuit; (10) PPS CMOS can easily hold a static state and have the same low power dissipation properties of data inactive Conventional CMOS.

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Ko, Ji Wang, and Woo Young Choi. "Monolithic-3D (M3D) Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical (CMOS-NEM) Hybrid Reconfigurable Logic (RL) Circuits." Journal of Nanoscience and Nanotechnology 20, no. 7 (July 1, 2020): 4176–81. http://dx.doi.org/10.1166/jnn.2020.17790.

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Monolithic-three-dimensional (M3D) CMOS-nanoelectromechanical (CMOS-NEM) hybrid reconfigurable logic (RL) circuits are compared and analyzed with CMOS-only RL ones in the 130-nm CMOS technology node. M3D CMOS-NEM hybrid RL circuits are superior to CMOS-only ones in terms of power consumption and signal transfer speed thanks to the NEM memory switches. As well as in the routing part, it has many advantages in the logic part following the switch.

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Agrawal, Gaurav R., and Leena A. Yelmule. "Linear CMOS LNA." International Journal of Trend in Scientific Research and Development Volume-3, Issue-1 (December 31, 2018): 829–35. http://dx.doi.org/10.31142/ijtsrd19087.

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Wong, H. S. P., D. J. Frank, P. M. Solomon, C. H. J. Wann, and J. J. Welser. "Nanoscale CMOS." Proceedings of the IEEE 87, no. 4 (April 1999): 537–70. http://dx.doi.org/10.1109/5.752515.

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Malhi, S. D. S., K. E. Bean, R. Sunderesan, and L. R. Hite. "Overlaid CMOS." Electronics Letters 22, no. 11 (May 22, 1986): 598–99. http://dx.doi.org/10.1049/el:19860406.

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Brown, G. A., P. M. Zeitzoff, G. Bersuker, and H. R. Huff. "Scaling CMOS." Materials Today 7, no. 1 (January 2004): 20–25. http://dx.doi.org/10.1016/s1369-7021(04)00051-3.

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11

Lee, Charles M., and Ellen W. Szeto. "Zipper CMOS." IEEE Circuits and Devices Magazine 2, no. 3 (May 1986): 10–17. http://dx.doi.org/10.1109/mcd.1986.6311821.

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Sadek, A., and K. Ismail. "CMOS possibilities." Solid-State Electronics 38, no. 9 (September 1995): 1731–34. http://dx.doi.org/10.1016/0038-1101(95)00037-t.

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Ghoshal, U., S. V. Kishore, A. R. Feldman, Luong Huynh, and T. Van Duzer. "CMOS amplifier designs for Josephson-CMOS interface circuits." IEEE Transactions on Appiled Superconductivity 5, no. 2 (June 1995): 2640–43. http://dx.doi.org/10.1109/77.403132.

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Karthikeyan, A., and P. S. Mallick. "Body-Biased Subthreshold Bootstrapped CMOS Driver." Journal of Circuits, Systems and Computers 28, no. 03 (February 24, 2019): 1950051. http://dx.doi.org/10.1142/s0218126619500518.

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This paper proposes a body-biased bootstrapped CMOS driver for subthreshold applications. The proposed driver has been implemented with the same number of transistors as conventional bootstrapped CMOS driver. The performance of the subthreshold bootstrapped CMOS driver has been compared with the conventional bootstrapped CMOS driver. Our results show that the proposed body-biased subthreshold bootstrapped CMOS driver has 37% reduction in delay and 39% reduction in power dissipation compared to conventional bootstrapped CMOS driver. The proposed driver is more suitable to drive large loads compared to the conventional driver and operates better at subthreshold region.

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15

Xu, Haoran, Jianghua Ding, and Jian Dang. "Design and Characteristics of CMOS Inverter based on Multisim and Cadence." Journal of Physics: Conference Series 2108, no. 1 (November 1, 2021): 012034. http://dx.doi.org/10.1088/1742-6596/2108/1/012034.

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Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for various types of communications. Based on multisim 14.0 and cadence, the characteristics and performance of CMOS inverter are studied by simulation.

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Yu, Le, Yaozu Guo, Haoyu Zhu, Mingcheng Luo, Ping Han, and Xiaoli Ji. "Low-Cost Microbolometer Type Infrared Detectors." Micromachines 11, no. 9 (August 24, 2020): 800. http://dx.doi.org/10.3390/mi11090800.

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The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the CMOS-compatible microbolometer IRFPAs in the aspects of the pixel structure, the read-out integrated circuit (ROIC), the focal plane array, and the vacuum packaging.

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O, K. K., S. SANKARAN, C. CAO, E. Y. SEOK, D. SHIM, C. MAO, and R. HAN. "MILLIMETER WAVE TO TERAHERTZ IN CMOS." International Journal of High Speed Electronics and Systems 19, no. 01 (March 2009): 55–67. http://dx.doi.org/10.1142/s0129156409006084.

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The feasibility of CMOS circuits operating at frequencies in the upper millimeter wave and low sub-millimeter frequency regions has been demonstrated. A 140-GHz fundamental mode VCO in 90-nm CMOS, a 410-GHz push-push VCO in 45-nm CMOS, and a 180-GHz detector circuit in 130-nm CMOS have been demonstrated. With the continued scaling of MOS transistors, 1-THz CMOS circuits will be possible. Though these results are significant, output power of signal generators must be increased and acceptable noise performance of detectors must be achieved in order to demonstrate the applicability of CMOS for implementing practical terahertz systems.

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Shi, Chenhao. "Applications of CMOS image sensors: Applications and innovations." Applied and Computational Engineering 11, no. 1 (September 25, 2023): 95–103. http://dx.doi.org/10.54254/2755-2721/11/20230216.

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As semiconductor production processes continue to advance, CMOS image sensors are becoming increasingly popular and are gradually replacing traditional CCD sensors as the mainstream option in the market. Because CMOS image sensors adopt the standard CMOS semiconductor production process, which provides advantages such as low static power consumption, large noise tolerance, strong anti-interference ability, and fast working speed. This article is going to provide an overview of CMOS image sensors and examine their various applications. To achieve this, this article will provide some background information on CMOS image sensors, including a discussion of their structure, components, and working principles. A comprehensive literature review was conducted to explore the characteristics and benefits of CMOS image sensors in applications such as intelligent surveillance systems (ISS), space, and medical. This paper also discusses recent advances in CMOS image sensor technology, namely backside illumination, global shutter, and 3D imaging, and their impact on various industries. Despite the advantages of CMOS image sensors, they still have some limitations and shortcomings. Therefore, further progress in industrial development is necessary to improve the quality of these products.

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Roy, Avisek, Mehdi Azadmehr, Bao Q. Ta, Philipp Häfliger, and Knut E. Aasmundtveit. "Design and Fabrication of CMOS Microstructures to Locally Synthesize Carbon Nanotubes for Gas Sensing." Sensors 19, no. 19 (October 8, 2019): 4340. http://dx.doi.org/10.3390/s19194340.

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Carbon nanotubes (CNTs) can be grown locally on custom-designed CMOS microstructures to use them as a sensing material for manufacturing low-cost gas sensors, where CMOS readout circuits are directly integrated. Such a local CNT synthesis process using thermal chemical vapor deposition (CVD) requires temperatures near 900 °C, which is destructive for CMOS circuits. Therefore, it is necessary to ensure a high thermal gradient around the CNT growth structures to maintain CMOS-compatible temperature (below 300 °C) on the bulk part of the chip, where readout circuits are placed. This paper presents several promising designs of CNT growth microstructures and their thermomechanical analyses (by ANSYS Multiphysics software) to check the feasibility of local CNT synthesis in CMOS. Standard CMOS processes have several conductive interconnecting metal and polysilicon layers, both being suitable to serve as microheaters for local resistive heating to achieve the CNT growth temperature. Most of these microheaters need to be partially or fully suspended to produce the required thermal isolation for CMOS compatibility. Necessary CMOS post-processing steps to realize CNT growth structures are discussed. Layout designs of the microstructures, along with some of the microstructures fabricated in a standard AMS 350 nm CMOS process, are also presented in this paper.

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Nebhen, Jamel, Julien Dubois, Sofiene Mansouri, and Dominique Ginhac. "Low-noise and low power CMOS photoreceptor using split-length MOSFET." Journal of Electrical Engineering 70, no. 6 (December 1, 2019): 480–85. http://dx.doi.org/10.2478/jee-2019-0081.

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Abstract This paper presents the design of a low-power and low-noise CMOS photo-transduction circuit. We propose to use the new technique of composite transistors for noise reduction of photoreceptor in the subthreshold by exploiting the small size effects of CMOS transistors. Several power and noise optimizations, design requirements, and performance limitations relating to the CMOS photoreceptor are presented. This new structure with composite transistors ensures low noise and low power consumption. The CMOS photoreceptor, implemented in a 130 nm standard CMOS technology with a 1.2 V supply voltage, achieves a noise floor of 2μV/⎷Hz within the frequency range from 1 Hz to 10 kHz. The current consumption of the CMOS photoreceptor is 541 nA. This paper shows the need for the design of phototransduction circuit at low voltage, low noise and how these constraints are reflected in the design of CMOS vision sensor.

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21

Huang, Peihao. "Design and optimization of CMOS layout structure for improved semiconductor device performance." Journal of Physics: Conference Series 2649, no. 1 (November 1, 2023): 012040. http://dx.doi.org/10.1088/1742-6596/2649/1/012040.

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Abstract CMOS layout structure plays a very important role in the field of semiconductor. Since the invention of CMOS technology in the 1970s, engineers have developed many other CMOS layout technologies based on it. This paper will also focus on the CMOS transistor layout structure, focusing on the analysis of three more important structures, demonstrating their impact on the performance of semiconductor devices. Before that, this paper will first introduce the basic theory of CMOS, such as the drift and diffusion of charge carriers in PN junctions, and the working principle of PMOS and NMOS, so as to facilitate us to further describe the optimization and improvement of CMOS structure. Then, the performance and characteristics of each structure are introduced in detail, and finally the comparison is made to highlight their advantages in technology and performance compared with traditional structures. In the future, CMOS structure layout will also become a hot spot, constantly creating more reasonable and advanced structures to improve semiconductor performance.

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Moez, K. K., and M. I. Elmasry. "Area-efficient CMOS distributed amplifier using compact CMOS interconnects." Electronics Letters 42, no. 17 (2006): 970. http://dx.doi.org/10.1049/el:20061628.

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Lee, Byoung Hun. "Exploratory NEMS-CMOS Hybrid Devices for Post CMOS Era." ECS Transactions 18, no. 1 (December 18, 2019): 857–62. http://dx.doi.org/10.1149/1.3096546.

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24

Rim, K., R. Anderson, D. Boyd, F. Cardone, K. Chan, H. Chen, S. Christansen, et al. "Strained Si CMOS (SS CMOS) technology: opportunities and challenges." Solid-State Electronics 47, no. 7 (July 2003): 1133–39. http://dx.doi.org/10.1016/s0038-1101(03)00041-8.

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Toriumi, Akira, Choong Hyun Lee, Tomonori Nishimura, Koji Kita, Shengkai Wang, Mahoro Yoshida, and Kosuke Nagashio. "(Invited) Feasibility of Ge CMOS for Beyond Si-CMOS." ECS Transactions 33, no. 6 (December 17, 2019): 33–46. http://dx.doi.org/10.1149/1.3487532.

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Haque, M. Samiul, S. Zeeshan Ali, P. K. Guha, S. P. Oei, J. Park, S. Maeng, K. B. K. Teo, F. Udrea, and W. I. Milne. "Growth of Carbon Nanotubes on Fully Processed Silicon-On-Insulator CMOS Substrates." Journal of Nanoscience and Nanotechnology 8, no. 11 (November 1, 2008): 5667–72. http://dx.doi.org/10.1166/jnn.2008.207.

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This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

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Gao, Changjian, and Dan Hammerstrom. "Cortical Models Onto CMOL and CMOS— Architectures and Performance/Price." IEEE Transactions on Circuits and Systems I: Regular Papers 54, no. 11 (November 2007): 2502–15. http://dx.doi.org/10.1109/tcsi.2007.907830.

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Kang, Min-Jae, Ho-Chan Kim, Wang-Cheol Song, and Sang-Joon Lee. "CMOS neuron activation function." Journal of Korean Institute of Intelligent Systems 16, no. 5 (October 25, 2006): 627–34. http://dx.doi.org/10.5391/jkiis.2006.16.5.627.

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Zhang, C., G. Casse, M. Franks, J. Hammerich, N. Karim, S. Powell, E. Vilella, and J. Vossebeld. "High-performance HV-CMOS sensors for future particle physics experiments — an overview." Journal of Instrumentation 17, no. 09 (September 1, 2022): C09025. http://dx.doi.org/10.1088/1748-0221/17/09/c09025.

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Abstract HV-CMOS (High Voltage-CMOS) sensors are emerging as a prime candidate for future tracking detectors that have extreme requirements on material budget, pixel granularity, time resolution and radiation tolerance. These sensors have the advantages of full monolithic structure, low manufacture cost, fast charge collection and high radiation tolerance. Confirmed and potential tracking applications in physics experiments include the Mu3e experiment, proton EDM searches, future upgrades of LHC (Large Hadron Collider) and CEPC (Circular Electron Positron Collider). The HV-CMOS group at Liverpool is doing generic R&D to push the boundaries of HV-CMOS sensors performance, especially in terms of single point resolution, fast-timing capability and radiation tolerance. This contribution gives an overview of the latest research by the Liverpool HV-CMOS group and presents the HV-CMOS prototypes developed in Liverpool.

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Li, Gongchen, Fangji Zhao, Zicheng Wang, and Zhe Chen. "The development and application of CMOS image sensor." Applied and Computational Engineering 7, no. 1 (July 21, 2023): 767–77. http://dx.doi.org/10.54254/2755-2721/7/20230460.

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This paper focuses on the development of Complementary metal-oxide semiconductor (CMOS) image sensor and its applications in aerospace, medical and automotive fields. Firstly, the representative events in history and the contributions of some companies to CMOS image sensor are described. Subsequently, some characteristics of CMOS image sensor are analyzed in the image field involved. In order to evaluate the performance of CMOS image sensor, single even effect and electronic endoscope structures are analyzed and active and passive range finder experiments are carried out. The results show that the imaging based on CMOS sensor can fully meet the requirements of imaging applications in many fields.

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Kumar, Umesh. "Measurements and Analytical Computer-Based Study of CMOS Inverters and Schmitt Triggers." Active and Passive Electronic Components 19, no. 1 (1996): 41–54. http://dx.doi.org/10.1155/1996/52421.

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Modified CMOS inverters with three and four transistors have been made. Two varieties of CMOS Schmitt Triggers have been considered. CMOS Schmitt Trigger with wide hysteresis has been obtained. Complete detailed theoretical, experimental and computer based results are derived and exhibited.

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Chen, Jiahao. "Integrated circuit design based on CMOS technology principle and its application in GPU." Theoretical and Natural Science 12, no. 1 (November 17, 2023): 141–46. http://dx.doi.org/10.54254/2753-8818/12/20230454.

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In today's society, the application of integrated circuit technology can be seen everywhere, especially in the past two decades. This paper mainly studies the principle and design of CMOS devices in IC technology and discusses the research and analysis of the acceleration algorithm of IC design. This paper adopts the research method of literature review and analysis to summarize the existing research results. This paper first introduces the development background of integrated circuit technology and the importance of CMOS technology. Subsequently, the concept and interconnection principle of CMOS device, and the combined circuit design and sequential logic circuit design principle of dynamic and static CMOS are explained in detail. Then, the application principle of CMOS technology in GPU is analyzed, and its specific application in GPU acceleration algorithm is analyzed. Finally, the application of CMOS technology in integrated circuits and its application and acceleration effect are summarized.

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Kogut, Igor T., Victor I. Holota, Anatoly Druzhinin, and V. V. Dovhij. "The Device-Technological Simulation of Local 3D SOI-Structures." Journal of Nano Research 39 (February 2016): 228–34. http://dx.doi.org/10.4028/www.scientific.net/jnanor.39.228.

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This paper presents the device-technological simulation of local 3D SOI structures. These structures are created by use microcavities under surface of silicon wafer. Is shown that proposed microcavities could be use as a constructive material for CMOS transistor array on the bulk silicon and 3D SOI-CMOS transistor array, as well as the sensitive elements and their combinations. Such structures allow creation and monolithic integration the CMOS, SOI-CMOS circuits and sensitive elements for IC and SoC.

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SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C TOW-THOMAS FILTER USING VOLTAGE OP AMP, CURRENT FEEDBACK OP AMP AND OPERATIONAL TRANSRESISTANCE AMPLIFIER." Journal of Circuits, Systems and Computers 18, no. 01 (February 2009): 151–79. http://dx.doi.org/10.1142/s0218126609004995.

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Several MOS-C realizations of the Tow-Thomas circuit using the commercially available voltage operational amplifier and the current feedback operational amplifier are reviewed in this paper. Additional MOS-C Tow-Thomas realizations using the operational transresistance amplifier and the differential current voltage conveyor are also included. MOS-C realizations of the Tow-Thomas circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS technology model from MOSIS are included together with detailed comparison tables to demonstrate the differences between MOS-C Tow-Thomas circuits using both of the commercially available active building blocks and CMOS integrated building blocks.

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Machowski, Witold, Stanisław Kuta, Jacek Jasielski, and Wojciech Kołodziejski. "Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS Inverters." International Journal of Electronics and Telecommunications 56, no. 4 (November 1, 2010): 381–86. http://dx.doi.org/10.2478/v10177-010-0050-z.

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Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS InvertersThe paper presents quarter-square analog four-quadrant multipliers, based on proprietary architecture using four CMOS inverters. The most important upgrade on already published own circuit implementation is the use of the same inverter "core" of the circuit with completely redesigned auxiliary and steering blocks. Two variants of new driving peripherals are considered: one with differential pair, the second with CMOS inverters. The proposed circuit solutions are suitable for RF applications in communication systems due to simple architecture comprising building blocks with RF CMOS transistors having sufficiently large biasing currents. Postlayout simulation results done on the basis of 180nm CMOS UMC Foundry Design Kit are also presented.

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Mohamed, Khaled Salah. "Work around Moore’s Law: Current and next Generation Technologies." Applied Mechanics and Materials 110-116 (October 2011): 3278–83. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.3278.

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Interconnect dimensions and CMOS transistor feature size approach their physical limits, therefore scaling will no longer play an important role in performance improvement. So, instead of trying to improve the performance of traditional CMOS circuits, integration of multiple technologies and different components in a heterogeneous system that is high performance will be introduced “moore than more” and CMOS replacement”beyond CMOS” will be explored. This paper focuses on Technology level trends where it presents “More Moore”:New Architectures (SOI, FinFET, Twin-Well),”More Moore” :New Materials (High-K, Metal Gate, Strained-Si) ,”More than Moore”:New Interconnects Schemes (3D, NoC, Optical, Wireless), and ”Beyond CMOS” :New Devices (Molecular Computer, Biological computer, Quantum Computer) .

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Rasheed, Israa Mohammed, and Hassan Jasim Motlak. "Performance parameters optimization of CMOS analog signal processing circuits based on smart algorithms." Bulletin of Electrical Engineering and Informatics 12, no. 1 (February 1, 2023): 149–57. http://dx.doi.org/10.11591/eei.v12i1.4128.

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Designing ideal analogue circuits has become difficult due to extremely large-scale integration. The complementary metal oxide semiconductor (CMOS) analog integrated circuits (IC) could use an evolutionary method to figure out the size of each device. The CMOS operational transconductance amplifier (CMOS OTA) and the CMOS current conveyor second generation (CMOS CCII) are designed using advanced nanometer transistor technology (180 nm). Both CMOS OTA and CMOS CCII have high performance, such as a wide frequency, voltage gain, slew rate, and phase margin, to include very wide applications in signal processing, such as active filters and oscillators. The optimization approach is an iterative procedure that uses an optimization algorithm to change design variables until the optimal solution is identified. In this study, different sorts of algorithms the genetic algorithm (GA), particle swarm optimization (PSO), and cuckoo search (CS) are employed to boost and enhance the performance parameters. While decreasing the time required to develop a conventional operation amplifier's settling time. Some studies decrease the value of the power utilized at various frequencies. Others operate at extremely high frequencies, but their power consumption is greater than that of those operating at lower frequencies.

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Siswoko, Siswoko, Hariyadi Singgih, and A. Komarudin. "DISAIN PERANCANGAN ALAT UJI IC TTL / CMOS UNTUK PENUNJANG LABORATORIUM ELEKTRONIKA DIGITAL." JURNAL ELTEK 17, no. 2 (November 11, 2019): 120. http://dx.doi.org/10.33795/eltek.v17i2.186.

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Bentuk IC TTL dan CMOS yang kecil dan memiliki jumlah pin bervariasi membuat orang kesulitan untuk melakukan pengujian kondisi IC TTL dan CMOS secara cepat. Beberapa cara pengujian IC TTL dan CMOS secara manual yakni menggunakan protoboard. Akan tetapi hal tersebut membutuhkan waktu yang cukup lama. Dari permasalahan tersebut, dibutuhkan adanya alat uji yang dapat mempermudah pengguna untuk mengetahui kondisi IC TTL dan CMOS sebelum digunakan. Alat uji IC digital ini dibuat untuk menguji apakah IC yang digunakan dalam keadaan baik atau rusak. Karena jenis IC TTL dan CMOS yang akan diujikan lebih dari satu, maka dalam penelitian ini digunakan keypad sebagai alat untuk menyeleksi IC yang akan diujikan. Keunggulan dari pembuatan alat uji IC ini adalah penyusun dan mengkombinasikan rangkaian dengan menggunakan mikrokontroler AVR Atmega 644 dengan hasil output dapat dilihat pada tampilan di LCD, berupa kondisi dari IC tersebut. Alat uji IC TTL seri 74xxx dan CMOS seri 40xx ini dapat digunakan untuk menguji 100 IC dengan total kesalahan 0%.

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Xiong, Yuanyuan, Erming Rui, Yu Tian, Qiang Jiao, Fuyu Han, and Pei Liu. "Discussion of Mechanical Shock Test Stress for Ultra-large-scale CMOS Image Sensors." Journal of Physics: Conference Series 2694, no. 1 (January 1, 2024): 012028. http://dx.doi.org/10.1088/1742-6596/2694/1/012028.

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Abstract The ultra-large-scale CMOS image sensors are significantly different from the traditional CMOS image sensors in terms of pixel size, chip size and structure. CMOS image sensors generally come with an optical window structure that is sealed to the ceramic housing by means of adhesive. The optical window material is generally sapphire, and the larger the image element size, the larger the required glass optical window area. Ultra-large size CMOS image sensors in the package before the general optical window thickness, parallelism, light window average transmittance assessment. The object of mechanical impact test assessment is the CMOS image sensor optical window structure and capping process. The paper mainly discusses the typical failure cases of ultra-large-scale CMOS image sensors on the basis of the applicability of mechanical shock test standards, and investigates how to define the mechanical shock test stress from simulation, limit test and the requirements by users. This paper provides the qualification assessment basis of mechanical shock for newly developed products.

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MOONEY, P. M. "MATERIALS FOR STRAINED SILICON DEVICES." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 305–14. http://dx.doi.org/10.1142/s0129156402001265.

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Strained Si devices exhibit enhanced carrier mobility compared to that of standard Si CMOS devices of the same dimensions. Recent strained Si CMOS device results are reviewed. Materials issues related to the strained Si/relaxed SiGe heterostructures required for a strained Si CMOS technology are discussed.

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Birla, Shilpi, Sudip Mahanti, and Neha Singh. "Leakage reduction technique for nano-scaled devices." Circuit World 47, no. 1 (May 29, 2020): 97–104. http://dx.doi.org/10.1108/cw-12-2019-0195.

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Purpose The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology. Design/methodology/approach Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices. Findings This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology. Originality/value All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

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SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C KHN FILTER USING VOLTAGE OP AMP, CFOA, OTRA AND DCVC." Journal of Circuits, Systems and Computers 18, no. 04 (June 2009): 733–69. http://dx.doi.org/10.1142/s021812660900523x.

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MOS-C realizations of the Kerwin–Huelsman–Newcomb (KHN) circuit using the commercially available Voltage Operational Amplifier (VOA) and the Current Feedback Operational Amplifier (CFOA) are reviewed in this paper. Additional MOS-C KHN realizations using the Operational Transresistance Amplifier (OTRA) and the Differential Current Voltage Conveyor (DCVC) are also included. MOS-C realizations of the KHN circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS technology model from MOSIS are included together with detailed comparison tables to demonstrate the differences between MOS-C KHN circuits using both of the commercially available active building blocks and CMOS integrated building blocks. A comparison with the Gm-C KHN circuit is also included.

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JOUVET, N., M. A. BOUNOUAR, S. ECOFFEY, C. NAUENHEIM, A. BEAUMONT, S. MONFRAY, A. RUEDIGER, F. CALMON, A. SOUIFI, and D. DROUIN. "RECENT DEVELOPMENTS ON 3D INTEGRATION OF METALLIC SET ONTO CMOS PROCESS FOR MEMORY APPLICATION." International Journal of Nanoscience 11, no. 04 (August 2012): 1240024. http://dx.doi.org/10.1142/s0219581x12400248.

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This work presents a nanodamascene process for a CMOS back-end-of-line fabrication of metallic single electron transistor(SET), together with the use of simulation tools for the development of a SET SRAM memory cell. We show room temperature electrical characterizations of SETs fabricated on CMOS with relaxed dimensions, and simulations of a SET SRAM memory cell. Using their physical characteristics achievable through the use of atomic layer deposition, it will be demonstrated that it has the potential to operate at temperature up to 398 K, and that power consumption is less than that of equivalent circuit in advanced CMOS technologies. In order to take advantage of both low power SETs and high CMOS drive efficiency, a hybrid 3D SET CMOS circuit is proposed.

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M. Surekha, V. HariKrishna, B. MadhuSudhan Reddy, G.Tejaswini, I.Rajasekhar, and K.Divya. "Efficient Approaches to Design Full Adder Using Domino Logic Technique." international journal of engineering technology and management sciences 7, no. 2 (2023): 283–88. http://dx.doi.org/10.46647/ijetms.2023.v07i02.033.

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Static CMOS and Domino CMOS Circuits are significantly used in high performance VLSI system. Designing a circuit with low power, high speed performance is one of the challenging aspects. In modern VLSI systems area efficient devices are utmost popular because most of the devices are becoming portable. This paper proposes One- bit full adder circuit is designed using CMOS based on mirror logic and Domino CMOS also designed based on same logic with LTSPICE at 180nm technology with 1.8V supply. This method provides better power and delay.

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Schlarmann, M. E., and R. L. Geiger. "Simple CMOS transresistor." Electronics Letters 37, no. 23 (2001): 1386. http://dx.doi.org/10.1049/el:20010947.

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Matsunaga, Yoshiyuki. "CMOS Image Sensor." Journal of the Institute of Image Information and Television Engineers 52, no. 8 (1998): 1171–72. http://dx.doi.org/10.3169/itej.52.1171.

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Riza, Nabeel A., Juan Pablo La Torre, and M. Junaid Amin. "CAOS-CMOS camera." Optics Express 24, no. 12 (June 9, 2016): 13444. http://dx.doi.org/10.1364/oe.24.013444.

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Vellacott, O. "CMOS in camera." IEE Review 40, no. 3 (May 1, 1994): 111–14. http://dx.doi.org/10.1049/ir:19940309.

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Moritz, P. S., and L. M. Thorsen. "CMOS circuit testability." IEEE Journal of Solid-State Circuits 21, no. 2 (April 1986): 306–9. http://dx.doi.org/10.1109/jssc.1986.1052520.

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Radamson, Henry H., Xiaobin He, Qingzhu Zhang, Jinbiao Liu, Hushan Cui, Jinjuan Xiang, Zhenzhen Kong, et al. "Miniaturization of CMOS." Micromachines 10, no. 5 (April 30, 2019): 293. http://dx.doi.org/10.3390/mi10050293.

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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Journal articles on the topic 'CMOS'

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