Dissertations / Theses on the topic 'CMOS'
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Covington, James A. "CMOS and SOI CMOS FET-based gas sensors." Thesis, University of Warwick, 2001. http://wrap.warwick.ac.uk/3589/.
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In recent years, there has been considerable interest in the use of gas/vapour monitors and electronic nose instruments by the environmental, automotive and medical industries. These applications require low cost and low power sensors with high yield and high reproducibility, with an annual prospective market of 1 million pounds. Present device and sensor technologies suffer a major limitation, their incompatibility with a standard silicon CMOS process. These technologies have either operating/annealing temperatures unsuited for MOSFET operation or an inappropriate sensing mechanism. The aim of this research is the development of CMOS compatible gas/vapour sensors, with a low cost of fabrication, high device repeatability and, in the future, transducer sensor amalgamation. Two novel approaches have been applied, utilising bulk CMOS and SOI BiCMOS. The bulk CMOS designs use a MOSFET sensing structure, with an active polymeric gate material, operating at low temperatures (<100°C), based on an array device of four elements, with channel lengths of 10 μm or 5 μm. The SOI designs exploit a MOSFET heater with a chemoresistive or chemFET sensing structure, on a thin membrane formed by the epi-taxial layer. By applying SOI technology, the first use in gas sensor applications, operating temperatures of up to 300 °C can be achieved at a power cost of only 35 mW (simulated). Full characterisation of the bulk CMOS chemFET sensors has been performed using electrochemically deposited (e.g. poly(pyrrole)/BSA)) and composite polymers (e.g. poly(9-vinylcarbazole)) to ethanol and toluene vapour in air. In addition, environmental factors (humidity and temperature) on the response and baseline were investigated. This was carried out using a newly developed flow injection analysis test station, which conditions the test vapour to precise analyte (<15 PPM of toluene) and water concentrations at a fixed temperature (RT to 105°C +- 0.1), with the sensor characterised by either I-V or constant current instrumentation. N-channel chemFET sensors operated at constant current (10 μA) with electrochemically deposited and composite polymers showed sensitivities of up to 1.1 μV/PPM and 4.0 μV/PPM to toluene vapour and to 1.1 μV/PPM and 0.4 μV/PPM for ethanol vapour, respectively, with detection limits of <20 PPM and <100 PPM to toluene and <20 PPM and 10+ PPM to ethanol vapour (limited by baseline noise), respectively. These responses followed either a power law (composite polymers) or a modified Langmuir isotherm model (electrochemically deposited polymers) with analyte concentration. It is proposed that this reaction-rate limited response is due to an alteration in polymers work function by either a partial charge transfer from the analyte or a swelling effect (polymer expansion). Increasing humidity caused, in nearly all cases a reduction in relative baseline, possible by dipole formation at the gate oxide surface. For the response, increasing humidity had no effect on sensors with composite polymers and an increase for sensors with electrochemically-deposited polymers. Higher temperatures caused a reduction in baseline signal, by a thermal expansion of the polymer, and a reduction in response explained by the analyte boiling point model describing a reduction in the bulk solubility of the polymer. Electrical and thermal characterisation of the SOI heaters, fabricated by the MATRA process, has been performed. I-V measurements show a reduction in drain current for a MOSFET after back-etching, by a degradation of the carrier mobility. Dynamic measurement showed a two stage thermal response (dual exponential), as the membrane reaching equilibrium (100-200 ms) followed by the bulk (1-2 s). A temperature coefficient of 8 mW/°C was measured, this was significantly higher than expected from simulations, explained by the membrane being only partially formed. Diode and resistive temperature sensors showed detection limits under 0.1°C and shown to measure a modulated heater output of less than 1°C at frequencies higher than 10Hz. The principal research objectives have been achieved, although further work on the SOI device is required. The results and theories presented in this study should provide a useful contribution to this research area.
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Meng, Huaiyu. "CMOS nanofluidics." Thesis, Massachusetts Institute of Technology, 2018. http://hdl.handle.net/1721.1/120374.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 217-226).
Diagnostic tests are essential to medical practice. In vitro diagnostics is a market worth US$ 40-45 billion. Diagnostic tests are usually conducted in centralized laboratories, equipped with expensive instrumentation and staffed with trained personnel. An important part of clinical diagnosis involves protein and DNA sensing. Significant effort is made to make protein and DNA sensing more accessible and affordable, through micro and nano-technologies. However, typical commercial and academic devices for molecular sensing suffered needs for external equipment, high cost and large form factors. In this work, we propose a self-contained point-of-care platform based on complementary metal oxide semiconductor (CMOS). CMOS platform has the capability of pattern features at the scale of nanometers. Important electronic functions in bio-sensing, such as amplifiers, counters and drivers are routinely implemented in CMOS. With the introduction of photonic and nanofluidic functionalities in this thesis, a CMOS chip can potentially perform biomolecular sensing without the aid of external equipment, hence becoming true lab-on-chip devices. This thesis presents the methods developed to introduce nanofluidic and photonic devices in commercial CMOS chips. We first introduce a method to fabricate nanofluidic channels in CMOS by using the transistor gate polysilicon as a sacrificial layer. A nanochannel with critical dimension of 100nm and length of 200 [mu]m is fabricated. Actuation and separation of bio-molecules in the nanochannel with electrophoresis is demonstrated. We then incorporate avalanche photodiodes (APD) in CMOS. Additionally, a packaging method is introduced to work with CMOS chips with size of a few square millimeters. With components mentioned above, clinical applications, such as gene mapping for virus identification and protein separation for cancer diagnosis and monitoring, could potentially run on a chip without external equipment.
by Huaiyu Meng.
Ph. D.
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Kerber, Andreas. "Methodology for electrical characterization of MOS devices with alternative gate dielectrics." Phd thesis, [S.l. : s.n.], 2004. http://elib.tu-darmstadt.de/diss/000404.
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Carletti, Luca. "Photonique intégrée nonlinéaire sur plate-formes CMOS compatibles pour applications du proche au moyen infrarouge." Thesis, Ecully, Ecole centrale de Lyon, 2015. http://www.theses.fr/2015ECDL0013/document.
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La photonique intégrée offre la possibilité d’exploiter un vaste bouquet de phénomènes optique nonlinéaires pour la génération et le traitement de signaux optiques sur des puces très compactes et à des débits potentiels extrêmement rapides. De nouvelles solutions et technologies de composants pourraient être ainsi réalisées, avec un impact considérable pour les applications télécom et datacom. L’utilisation de phénomènes optiques nonlinéaires (e.g. effet Kerr optique, effet Raman) permet même d’envisager la réalisation de composants actifs (e.g. amplificateurs, modulateurs, lasers, régénérateurs de signaux et convertisseurs en longueur d’onde).Pendant cette dernière décennie, les efforts ont principalement porté sur la plateforme Silicium sur isolant (SOI), profitant du fort confinement optique dans ce matériau, qui permet la miniaturisation et intégration de composants optiques clés (e.g. filtres passifs, jonctions coupleurs et multiplexeurs). Cependant, la présence de fortes pertes nonlinéaires dans ce matériau aux longueurs d’onde d’intérêt (i.e. autour de 1.55 µm dans les télécommunications) limite certaines applications pour lesquelles une forte réponse nonlinéaire est nécessaire et motive la recherche de nouvelles plates-formes, mieux adaptées. L’objectif premier de cette thèse était ainsi l’étude de matériaux alternatifs au Si cristallin, par exemple le silicium amorphe hydrogéné, alliant de très faibles pertes nonlinéaires et une compatibilité CMOS, pour la réalisation de dispositifs photoniques intégrés qui exploitent les phénomènes nonlinéaires. Alternativement, l’utilisation de longueurs d’onde plus élevées (dans le moyen-IR) permet de relaxer la contrainte sur le choix de la filière matériau, en bénéficiant de pertes nonlinéaires réduites, par exemple dans la filière SiGe, également explorée dans cette thèse. Ce travail est organisé de la façon suivante. Le premier chapitre donne un iii panorama des phénomènes nonlinéaires qui permettent de réaliser du traitement tout-optique de l’information, en mettant en évidence les paramètres clés à maitriser (confinement optique, ingénierie de dispersion) pour les composants d’optique intégrée, et en présentant le cadre de modélisation de ces phénomènes utilisé dans le travail de thèse. Il inclut également une revue des démonstrations marquantes publiées sur Silicium cristallin, donnant ainsi des points de référence pour la suite du travail. Le chapitre 2 introduit les cristaux photoniques comme structures d’optique intégrée permettant d’exalter les phénomènes nonlinéaires. On s’intéresse ici aux cavités, avec une démonstration de génération de deuxième et troisième harmoniques qui exploite un design original. Ce chapitre décrit également les enjeux associés à l’utilisation de guides à cristaux photoniques en régime de lumière lente, qui serviront de fondements pour le chapitre 4. Le chapitre 3 présente les résultats de caractérisation de la réponse nonlinéaire associée à des guides réalisés dans deux matériaux alternatifs au silicium cristallin : le silicium amorphe hydrogéné testé dans le proche infrarouge et le silicium germanium testé dans le moyen infrarouge. Le modèle présenté au chapitre 1 est exploité pour déduire la réponse de ces deux matériaux, et il est même étendu pour rendre compte d’effets nonlinéaires d’ordre plus élevé dans le cas du silicium germanium à haute longueur d’onde. Ce chapitre inclut également une discussion sur la comparaison des propriétés nonlinéaires de ces deux matériaux avec le SOI standard. Le chapitre 4 combine l’utilisation d’une plate-forme plus prometteuse que le SOI, avec des structures photoniques plus avancées que les simples guides réfractifs utilisés au chapitre 3 : il décrit l’ingénierie de modes (lents) dans des guides à cristaux photoniques en silicium amorphe hydrogéné et enterrés dans la silice. [...]Integrated photonics offers a vast choice of nonlinear optical phenomena that could potentially be used for realizing chip-based and cost-effective all-optical signal processing devices that can handle, in principle, optical data signals at very high bit rates. The new components and technological solutions arising from this approach could have a considerable impact for telecom and datacom applications. Nonlinear optical effects (such as the optical Kerr effect or the Raman effect) can be potentially used for realizing active devices (e.g. optical amplifiers, modulators, lasers, signal regenerators and wavelength converters). During the last decade, the silicon on insulator (SOI) platform has known a significant development by exploiting the strong optical confinement, offered by this material platform, which is key for the miniaturization and realization of integrated optical devices (such as passive filters, splitters, junctions and multiplexers). However, the presence of strong nonlinear losses in the standard telecom band (around 1.55 µm) prevents some applications where a strong nonlinear optical response is needed and has motivated the research of more suitable material platforms. The primary goal of this thesis was the study of material alternatives to crystalline silicon (for instance hydrogenated amorphous silicon) with very low nonlinear losses and compatible with the CMOS process in order to realize integrated photonics devices based on nonlinear optical phenomena. Alternatively, the use of longer wavelengths (in the mid-IR) relaxes the constraints on the choice of the material platform, through taking advantage of lower nonlinear losses, for instance on the SiGe platform, which is also explored in this thesis. This work is organized as follows. In the first chapter we provide an overview of the nonlinear optical effects used to realize all optical signal processing functions, focusing on the key parameters that are essential (optical confinement and dispersion engineering) for integrated optical components, and presenting the main models used in this thesis. This chapter also includes a review of the main demonstrations reported on crystalline silicon, to give some benchmarks. Chapter 2 introduces the use of photonic crystals as integrated optical structures that can significantly enhance nonlinear optical phenomena. First we present photonic crystal cavities, with a demonstration of second and third harmonic generation that makes use of an original design. In the second part of the chapter, we describe the main features and challenges associated with photonic crystal waveguides in the slow light regime, which will be used later in chapter 4. In chapter 3, we report the experimental results related to the characterization of the optical nonlinear response of integrated waveguides made of two materials that are alternative to crystalline silicon : the hydrogenated amorphous silicon, probed in the near infrared, and the silicon germanium, probed in the mid-infrared. The model presented in chapter 1 is extensively used here for extracting the nonlinear parameters of these materials and it is also extended to account for higher order nonlinearities in the case of silicon germanium tested at longer wavelengths. This chapter also includes a comparison of the nonlinear properties of these two material platforms with respect to the standard SOI. In chapter 4, we combine the use of a material platform that is better suited than SOI for nonlinear applications with integrated photonics structures that are more advanced that those used in chapter 3. Here we describe the design of (slow) modes in photonic crystal waveguides made in hydrogenated amorphous silicon fully embedded in silica. [...]
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Chen, Tingsu. "Spin Torque Oscillator Modeling, CMOS Design and STO-CMOS Integration." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-176890.
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Spin torque oscillators (STOs) are microwave oscillators with an attractive blend of features, including a more-than-octave tunability, GHz operating frequencies, nanoscale size, nanosecond switching speed and full compatibility with CMOS technology. Over the past decade, STOs' physical phenomena have been explored to a greater extent, their performance has been further improved, and STOs have already shown great potential for a wide range of applications, from microwave sources and detectors to neuromorphic computing. This thesis is devoted to promoting the STO technology towards its applications, by means of implementing the STO's electrical model, dedicated CMOS integrated circuits (ICs), and STO-CMOS IC integration. An electrical model, which can capture magnetic tunnel junction (MTJ) STO's characteristics, while enabling system- and circuit-level designs and performance evaluations, is of great importance for the development of MTJ STO-based applications. A comprehensive and compact analytical model, which is based on macrospin approximations and can fulfill the aforementioned requirements, is proposed. This model is fully implemented in Verilog-A, and can be used for efficient simulations of various MTJ STOs. Moreover, an accurate phase noise generation approach, which ensures a reliable model, is proposed and successfully used in the Verilog-A model implementation. The model is experimentally validated by three different MTJ STOs under different bias conditions. CMOS circuits, which can enhance the limited output power of MTJ STOs to levels that are required in different applications, are proposed, implemented and tested. A novel balun-low noise amplifier (LNA), which can offer sufficient gain, bandwidth and linearity for MTJ STO-based magnetic field sensing applications, is proposed. Additionally, a wideband amplifier, which can be connected to an MTJ STO to form a highly-tunable microwave oscillator in a phase-locked loop (PLL), is also proposed. The measurement results demonstrate that the proposed circuits can be used to develop MTJ STO-based magnetic field sensing and microwave source applications. The investigation of possible STO-CMOS IC integration approaches demonstrates that the wire-bonding-based integration is the most suitable approach. Therefore, a giant magnetoresistance (GMR) STO is integrated with its dedicated CMOS IC, which provides the necessary functions, using the wire-bonding-based approach. The RF characterization of the integrated GMR STO-CMOS IC system under different magnetic fields and DC currents shows that such an integration can eliminate wave reflections. These findings open the possibility of using GMR STOs in magnetic field sensing and microwave source applications.QC 20151112
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Boltshauser, Thomas. "CMOS humidity sensors /." [S.l.] : [s.n.], 1993. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=10320.
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Maul, Thomas. "CMOS-integrierte Feldemissionsspitzen /." Göttingen : Cuvillier, 2009. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=018923495&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.
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Zhou, Tiansheng. "CMOS cantilever microresonator." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0010/MQ60201.pdf.
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Scholvin, Jörg 1976. "RF power CMOS." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86742.
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Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references (p. 103-105).
by Jörg Scholvin.
M.Eng.and S.B.
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Buttar, Alistair George. "CMOS process simulation." Thesis, University of Edinburgh, 1986. http://hdl.handle.net/1842/13282.
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Moss, Benjamin (Benjamin Roy). "High-speed modulation of resonant CMOS photonic modulators in deep-submicron CMOS." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/93823.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 161-164).
Processor manufacturers have turned to parallelism to continue to improve processor performance, and the bandwidth demands of manycore systems are rising. Silicon photonics can lower the energy-per-bit of core-to-core and core-to-memory interconnects while simultaneously alleviating bandwidth bottlenecks. In this work, methods of controlling the amount of charge entering the diode structure of a photonic modulator are investigated to achieve high energy efficiency in a constrained monolithic process. Two digital modulator topologies are simulated, fabricated and tested. One circuit topology, intended to drive a carrier-injection-based ring modulator, uses a digital push-pull topology with preemphasis to reduce the energy-per-bit and to prevent the ring's optical passband from shifting to the next optical channel. The second circuit topology drives a depletion-mode modulator device for high energy efficiency and speed. High-level system modeling is addressed, as well as practical considerations such as packaging. This work marks the first monolithic transceiver in a zero-change CMOS process, and the most energy-efficient monolithically-integrated modulator in a sub-100 nm CMOS process.
by Benjamin Moss.
Ph. D.
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Lenggenhager, René. "CMOS thermoelectric infrared sensors /." [S.l.] : [s.n.], 1994. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=10744.
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Mende, Ole. "Laserumschalterstruktur in CMOS-Technologie." [S.l. : s.n.], 2003. http://deposit.ddb.de/cgi-bin/dokserv?idn=969347189.
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Chen, Yonggang Suhling J. C. Jaeger Richard C. "CMOS stress sensor circuits." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Fall/Dissertations/CHEN_YONGGANG_42.pdf.
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Dmochowski, Przemyslaw. "CMOS modulated light camera." Thesis, University of Nottingham, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.438301.
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Šťastná, Hilda. "Simulace CMOS VLSI obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-363732.
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This diploma thesis deals with processes of electrical circuits calculations in the last years' worldwide standards like Dymola, MATLAB, Maple or SPICE applications. Circuits calculations are linked with methods for solving linear differential equations, used in this work also by verification of functionality of designed models for CMOS inverter, CMOS NAND, CMOS NOR. Numerical integration method in combination with Taylor series is a suitable method also for parallel calculations of CMOS VLSI circuits. CMOS circuits simulation was implemented with this method in applications in MATLAB language, solving circuits, represented by differential equations. Functionality of the applications was verified by some real examples. Significant acceleration of calculations using Taylor series compared to other methods is an important factor in choosing methods used in circuit simulations.
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Lefebvre, Martin C. (Martin Claude) Carleton University Dissertation Engineering Electrical. "CMOS leaf cell synthesis." Ottawa, 1989.
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Dandache, Abbas. "Conception de PLA CMOS." Phd thesis, Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37596962j.
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Navrátil, Jakub. "Návrh operačního zesilovače CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217898.
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The present work deals with issues of a design of operational transconductance amplifier in technology CMOS AMIS 0,7 um. The aim of the work is to design a accurate operational amplifier with a low input differential voltage.
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Sundaresan, Krishnakumar. "Temperature Compensated CMOS and MEMS-CMOS Oscillators for Clock Generators and Frequency References." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/13977.
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Silicon alternatives to quartz crystal based oscillators to electronic system clocking are explored. A study of clocking requirements reveals widely different specifications for different applications. Traditional CMOS oscillator-based solutions are optimized for low-cost fully integrated micro-controller clock applications. The frequency variability of these clock generators is studied and techniques to compensate for this variability are proposed. The efficacy of these techniques in reducing variability is proven theoretically and experimentally. MEMS-resonator based oscillators, due to their exceptional quality factors, are identified as suitable integrated replacements to quartz based oscillators for higher accuracy applications such as data converter clocks. The frequency variation in these oscillators is identified and techniques to minimize the same are proposed and demonstrated. The sources of short-term variation (phase noise) in these oscillators are discussed and an inclusive theory of phase noise is developed. Techniques to improve phase noise are proposed. Findings from this research indicate that MEMS resonator based oscillators, may in future, outperform quartz based solutions in certain applications such as voltage controlled oscillators. The implications of these findings and potential directions for future research are identified.
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Moss, Benjamin (Benjamin Roy). "High-speed modulation of resonant CMOS photonic modulators in deep-submicron bulk-CMOS." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/55122.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 71-72).
Processor manufacturers have turned to parallelism to continue to improve processor performance, and the bandwidth demands of these systems have risen. Silicon photonics can lower the energy-per-bit of core-to-core and core-to-memory interconnects to help alleviate bandwidth bottlenecks. In this thesis, methods of controlling the amount of charge entering the PiN-diode structure of a photonic ring modulator are investigated to achieve high energy-efficiency in a constrained monolithic process. A digital modulator driver circuit is designed, simulated, fabricated and partially tested. This circuit uses a push-pull topology with pre emphasis to reduce the energy per bit and to prevent the ring's optical passband from shifting to the next optical channel. A flexible driver test circuit for in-situ device characterization has been developed with a device-to-circuit modeling framework. There are many tradeoffs that must be analyzed from the system, circuit, and device levels.
by Benjamin Moss.
S.M.
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Schrey, Olaf. "Methoden zur Dynamikerweiterung in der zweidimensionalen CMOS-Bildsensorik - Dynamic range expansion in CMOS imaging." Gerhard-Mercator-Universitaet Duisburg, 2001. http://www.ub.uni-duisburg.de/ETD-db/theses/available/duett-05252001-090540/.
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Nearly 80% of the worldwide semiconductor market volume is covered by standard-CMOS-technology products. Due to the increasing demand on highly flexible, reliable and robust image sensors from many different industry parts, CMOS-technology has become more and more attractive, since it offers several features in contrast to the CCD-technology. The focus of this work lies on the development of high dynamic range CMOS image sensors suitable for industrial, automotive and consumer applications. The developed sensors should yield more powerful and cost-saving system solutions compared with CCD-sensor systems that are available from the market. The work concentrates on mainly linear CMOS-sensors offering a linear dependency between illumination and electronic signal representation. The developed sensors achieve a dynamic range of more than 90dB, which is much more than CCD´s have with 50-60dB. Two sensors are presented with the first one using a mixed logarithmic/linear characteristic and the second sensor working with a multi-illumination scheme using different exposure/integration times, resp. The work finishes with a discussion of the presented sensors and their underlying signal processing algorithms and a short outlook on future developments.
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Rabe, Dirk. "Accurate power analysis of integrated CMOS circuits on gate level." [S.l.] : [s.n.], 2001. http://deposit.ddb.de/cgi-bin/dokserv?idn=962733520.
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Machul, Olaf. "Nichtlineare Approximationsmethoden zur Reduzierung nichtidealer Sensoreigenschaften in integrierten CMOS-Sensorsystemen." [S.l. : s.n.], 1999. http://www.ub.uni-duisburg.de/diss/diss9913/.
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Loeliger, Teddy. "Large-area photosensing in CMOS /." Zürich, 2001. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=14038.
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Enz, Christian C. Enz Christian Charles Enz Christian Charles Enz Christian Charles. "High precision CMOS micropower amplifiers /." [S.l.] : [s.n.], 1989. http://library.epfl.ch/theses/?nr=802.
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Kerness, Nicole. "CMOS-based calorimetric chemical microsensors /." [S.l.] : [s.n.], 2002. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=14839.
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Banerjee, Gaurab. "Desensitized CMOS low noise amplifiers /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6014.
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Ahmed, Jamil. "Asynchronous design in dynamic CMOS." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0011/MQ34126.pdf.
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Bengtson, Håkan. "High speed CMOS optical receiver /." Linköping : Univ, 2004. http://www.bibl.liu.se/liupubl/disp/disp2004/tek904s.pdf.
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Blanksby, Andrew J. "Colour cameras in standard CMOS /." Title page, contents and abstract only, 1998. http://web4.library.adelaide.edu.au/theses/09PH/09phb6419.pdf.
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Sasse, Guido Theodor. "Reliability engineering in RF CMOS." Enschede : University of Twente [Host], 2008. http://doc.utwente.nl/59032.
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Wodnicki, Robert. "A CMOS foveated image sensor." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=23759.
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The foveated or log-polar mapping is a biologically motivated image transformation with the potential for realizing efficient real-time vision sensors. By using space-variant sampling, the foveation process compresses the data in the perceived scene, thereby producing a significant reduction in subsequent image processing computations. These savings make foveated image sensors attractive for use on autonomous mobile robots with limited available computing power. When fabricated in standard Complimentary Metal Oxide Semiconductor (CMOS) technology, foveated sensors benefit from the integration of image sensing and processing functions on one substrate, yielding a further reduction in power consumption and system mass. In this thesis, the design, implementation and test of a CMOS foveated image sensor are examined in detail. A new representation of the foveated mapping, called the hybrid model, is introduced to facilitate design of the sensor using a standard CMOS process. The imager is based on the archetypal CMOS Passive Pixel Sensor (PPS). A study of this technology is undertaken, including an investigation of some non-ideal effects. A detailed explanation of the design of the prototype CMOS foveated sensor is presented. Issues related to the use of a standard CMOS process are examined, and the development of a software tool for automatic layout generation explained. The theoretical discussion is followed by a presentation of a comprehensive analysis of the fabricated prototype. With the help of experimental results, including sample images, noise performance, maximum frame rate and power consumption, the merits of the fabricated prototype are demonstrated, and its potential for use as a mobile robot vision sensor investigated.
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Li, Y. "CMOS compatible EWOD microfluidic systems." Thesis, University of Edinburgh, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.653865.
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This thesis reports a CMOS compatible fabrication procedure that enables ElecroWetting On Dielectric (EWOD) technology to be post-processed on foundry technology. With driving voltages less than 15V it is believed to be the lowest reported driving voltage for any material system compatible with post-processing on integrated circuits. The process architecture uses anodically grown tantalum pentoxide as the pinhole free high dielectric constant insulator with the overlying 16nm layer of Teflon-AF, which provides the hydrophobic surface upon which droplets can be manipulated. This stack provides a very robust dielectric, which maintains a sufficiently high capacitance per unit area for effective operation at the lower voltage favoured by more standard CMOS technology. The thesis demonstrates that the sputtered tantalum layer can be integrated with the aluminium (or copper) interconnect of foundry CMOS processes by standard microfabrication techniques. Different EWOD systems and applications fabricated in this CMOS compatible way are developed and discussed in this thesis.
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Chen, Andrew R. (Andrew Raymond). "A CMOS-compatible compact display." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/33934.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 119-127).
Portable information devices demand displays with high resolution and high image quality that are increasingly compact and energy-efficient. Microdisplays consisting of a silicon CMOS backplane integrated with light generating or modifying devices, are being developed for direct-view and projection applications. A microdisplay architecture using silicon light emitters and image intensification suitable for a micro-projector application is developed. A standard low-voltage CMOS IC incorporating display drivers and an array of avalanche diodes produces a faint optical image, and an image intensifier efficiently amplifies the image to useful brightness. This architecture has high efficiency and the potential to achieve adequate luminance for projection applications. A proof-of-concept system with 16x32 arrays is implemented and evaluated. A high-performance silicon backplane for the above system is designed, implemented, and evaluated. The backplane is a standard CMOS die including a 360x200 pixel array with silicon light emitters, and 10b precision current-mode driver circuits. The driver circuits can support a number of emissive display technologies including silicon light emitters and organic light emitting diode (OLED).
(cont.) They employ a self-calibration technique based on the current copier circuit to minimize variation and fixed-pattern noise while reducing circuit area by a factor of five to seven compared to a conventional solution. A circuit technique to improve the retention time of dynamic analog memories is also presented. This technique allows a dynamic analog memory to retain 10b precision for 500ms at room temperature.
by Andrew Chen.
Ph.D.
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Lauer, Isaac 1976. "Double-sided CMOS fabrication technology." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86778.
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Chong, Johanna S. "Hybrid laser with CMOS photonics." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91446.
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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.26
Title as it appears in MIT degrees awarded booklet, February 19, 2014: Multiwavelength integrated ring laser. Cataloged from PDF version of thesis.
Includes bibliographical references (pages 151-153).
In this thesis, an interesting approach for a photonic laser source is presented. By using integrated photonic resonators with an external gain medium, we are able to build a laser that offers a number of advantages including reducing the electrical and thermal load on the integrated chip socket, eliminating the challenges of integrating gain mediums into CMOS processes, allowing for lasing at virtually arbitrary wavelengths, the possibility of multiwavelength operation with a shared gain medium, elimination of closed-loop control of wavelength tuning, ability to control laser output and wavelength on-chip, and the potential for wavelength modulation using novel resonator tuning designs. Several iterations of the laser were built and characterized culminating in a final integrated laser that showed a wall-plug efficiency of 1.10% at a maximum output power of 6 mW. We demonstrate even higher wall-plug efficiencies using commercial filters. We also demonstrate wavelength modulation and open eye diagrams for data rates up to 5 Gb/s using the laser in a communications link. Simulations of birefringent filters are performed to model wavelength dependence on polarization which when manipulated can give rise to single or multiwavelength lasing. Finally, the power spectral density is simulated by assuming uncorrelated phase between lasing modes.
by Johanna S. Chong.
M. Eng.
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Haneef, Ibraheem. "SOI CMOS MEMS flow sensors." Thesis, University of Cambridge, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.611843.
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Duncan, Martin Russell. "CMOS-compatible high-voltage transistors." Thesis, University of Edinburgh, 1994. http://hdl.handle.net/1842/12182.
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Bipolar transistors are known to be the most suitable for high-voltage and power applications, due to their inherently greater current handling capability. In contrast, MOS technology is preferable for logic applications, due to its superior packing density. Therefore the 'ideal' solution to the smart power problem of integrating control elements on the same die as power switches is a marriage of the two different technologies. This results in a complex process that can only be cost effective in high volume applications. For ASIC applications and low volume product runs a less expensive compromise solution is needed. By analyzing both bipolar and MOS, low and high voltage devices, it was found that if more than one power transistor is needed on the circuit, and a single technology is to be used, then MOS power transistors are inherently easier to integrate into a low voltage process. In particular the lateral double-diffused transistor (LDMOS) with all terminal contacts on the surface is to be preferred. Analyzing a CMOS process, common processing steps were found for both the low and high-voltage devices, leading to a smart power solution that doesn't need many masking levels. By making small changes to an established n-well CMOS process, and developing a novel power transistor structure with a field oxidation separating the channel and drain, a 120 Volt n-channel power transistor could be realised within a conventional process with no additional processing steps. By adding one further masking layer, a complementary p-channel power transistor that supported -55 Volts could be fabricated. If these transistors were fabricated on a p- epitaxial layer on an n- substrate then by changing the p-channel power device structure, a breakdown voltage of -95 Volt could be achieved using only nine masking layers.
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Wang, Guoyu. "CMOS VLSI circuits for imaging." Thesis, University of Edinburgh, 1993. http://hdl.handle.net/1842/13190.
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MOS technology is very attractive for achieving low-cost miniature cameras. It also permits the inclusion of the sensor with other control and processing functions on the same chip. However, this technique has never been developed to the point at which MOS sensor performance matches that of CCD cameras. The objective of this project has been to develop design techniques to achieve single chip video cameras, in unmodified CMOS processes, with improved performance (aimed to match the performance of CCD cameras) and enhanced functionality. In this thesis, following an overview of solid state image sensors, the fundamentals and basic sensor array structure suitable for CMOS implementation is presented. The pixel structure and sensor array, the sense amplifier, scan circuitry, and the output amplifier and buffer are described. Noise analysis is also presented with the main noise sources highlighted and compensation schemes proposed. Other useful on-chip techniques including auto-exposure control, gain control, and data conversion are then discussed. A successfully designed device, named ASIS-1011 which incorporates all these circuit techniques, is finally reported. This design shows that the aim of achieving good picture quality and incorporating sensors and control logic on one chip can be achieved.
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Kittler, Mario Doll Theodor. "Nonclassical CMOS /." 2005. http://www.gbv.de/dms/ilmenau/abs/48516373Xkittl.txt.
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Man, Cintia. "CMOS biosensors /." 2007. http://proquest.umi.com/pqdweb?did=1568799571&sid=11&Fmt=2&clientId=12520&RQT=309&VName=PQD.
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Anghel, L. "Conception Robuste dans les Technologies CMOS et post-CMOS." Habilitation à diriger des recherches, 2007. http://tel.archives-ouvertes.fr/tel-00185993.
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Les technologies de silicium s'approchent de leurs limites physiques en termes de réduction des tailles des transistors, et de la tension d'alimentation, d'augmentation de la vitesse de fonctionnement et du nombre de dispositifs intégrés dans une puce. En s'approchant de ces limites, les circuits deviennent de plus en plus sensibles aux phénomènes parasites diverses, d'origine interne ou externe au circuit, provoquant une augmentation très importante du taux d'erreurs du fonctionnement. Le manuscrit présente un résumé de mes travaux de recherche, menés en collaboration avec les doctorants que jái co-encadrés ou que j'encadre en ce moment et avec les nombreux stagiaires qui se sont succédés au laboratoire TIMA, et dans un premier temps concerne les techniques de tolérance aux fautes permanentes et transitoires destinées aux nouvelles technologies de silicium (ciblant les technologies en dessous des 32nm) ainsi qu'aux futures technologies de remplacement du silicium, les nanotechnologies. Une partie de travaux de recherche s'articule autour de la prédiction des taux de défaillances des systèmes intégrés complexes. Des méthodologies de simulation de fautes concernant tous les niveaux d'abstraction sont présentées, tant pour les circuits numériques que pour les circuits analogiques, ainsi que la mise en place d'outils de simulation automatique. In fine, une dernière partie du manuscrit présente des activités de recherche beaucoup plus récentes, articulées autour de la modélisation et de la simulation des structures simples et complexes à base de nanotubes de carbone en vue d'une analyse prédictive de fonctionnement sans défaillances. Au passage des systèmes complexes et les outils de CAO pour les nanotechnologies sont aussi présentés.
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Hung, Kei-Kang, and 洪根剛. "ESD ROBUSTNESS OF CMOS DEVICES IN SOI SALICIDE CMOS TECHNOLOGY." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/22766714966573020828.
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碩士國立交通大學
電子工程系
89
There are two parts included in this thesis, which are related to the MOSFET devices and diode devices in the silicon-on-insulator (SOI) CMOS technology. In the first part, electrostatic discharge (ESD) robustness of CMOS MOSFETs with four different layout structures of H-gate, T-gate, floating-body, and sided-body, fabricated in a 0.15-µm partially-depleted SOI salicide CMOS process are studied and compared. Both of the positive polarity and the negative polarity ESD robustness of these fabricated MOSFETs are verified by ESD tester, and the second breakdown current (It2) of these MOSFETs are also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of these CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process. The ESD robustness raised by gate-driven technique performs more efficient than by substrate-triggered technique. In the second part, novel gated and non-gated diode structures for ESD protection are disclosed. The I-V characteristics of these new diodes under forward-biased and reverse-biased conditions are measured and compared to that of the lateral unidirectional bipolar type insulated gate transistor (Lubistor) diode. The experimental results show that the proposed new diode structures have an improved ESD robustness. A novel design on the power-rail ESD clamp circuit with the gate-triggered diodes in stacked configuration has shown a higher ESD robustness.
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Hung, Chin-Chung, and 洪志忠. "A CMOS Multiplier Circuit using a 1.5V CMOS Logic Circuit." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/66188657075161112912.
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碩士國立臺灣大學
電機工程學系
85
This thesis reports a 1.5V high-speed 8X8 multiplier circuit usingthe Wallace tree reduction architecture and true-single- phase bootstrappeddyanmic and static circuit techniques. Based on a 0.8um CMOS technology, the CLA circuit speed performance of this 8X8 dynamic multiplier circuit is improved by 39% as compared to the CMOS Manchester carry look-aheadcircuit without using the bootstrapped technique. In the whole dynamicmultiplier circuit, it is improved by 15.5%. The proposed Modified- Manchester CLA circuit speed performance of this 8X8 static multiplier circuit is improved by 60.8% as compared to thhe conventional static CLA circuit whithout using bootstrapped technique. The whole static multiplier circuit is improvedby 35.5%.
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Wei, Liao Jieh, and 廖介偉. "CMOS Limiting Amplifiers." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/90065034680663127279.
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碩士國立臺灣大學
電子工程學研究所
91
The exponential growth of data in telecommunication networks has rekindled interest in high-speed optical and electric device and systems. The majority of the backbone optical communication systems are based on the SONET standard. In this system, optical data can be transmitted via differential lengths of fiber. At the receiving end, these differential transmission paths result in a large attenuation range of optical signal. How to maintain a constant magnitude for the succeeding electrical interfaces, namely, timing recovery and data regeneration, is the key requirement for analog frond-end of the receiver. Limiting and automatic gain control (AGC) amplifiers are the two commonly employed measures to keep the signal magnitude constant against the receiving power variation. However, AGC amplifiers require longer settling time and more complicated analog components, and larger chip size than an open-loop type limiter. For this reason, this work will focus on the design and implementation of limiting amplifiers.
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Fernandes, Miguel Duarte Madeira. "Wideband CMOS receiver." Master's thesis, 2014. http://hdl.handle.net/10362/13337.
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Li, Mingyu. "Architecting SkyBridge-CMOS." 2015. https://scholarworks.umass.edu/masters_theses_2/157.
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As the scaling of CMOS approaches fundamental limits, revolutionary technology beyond the end of CMOS roadmap is essential to continue the progress and miniaturization of integrated circuits. Recent research efforts in 3-D circuit integration explore pathways of continuing the scaling by co-designing for device, circuit, connectivity, heat and manufacturing challenges in a 3-D fabric-centric manner. SkyBridge fabric is one such approach that addresses fine-grained integration in 3-D, achieves orders of magnitude benefits over projected scaled 2-D CMOS, and provides a pathway for continuing scaling beyond 2-D CMOS.
However, SkyBridge fabric utilizes only single type transistors in order to reduce manufacture complexity, which limits its circuit implementation to dynamic logic. This design choice introduces multiple challenges for SkyBridge such as high switching power consumption, susceptibility to noise, and increased complexity for clocking. In this thesis we propose a new 3-D fabric, similar in mindset to SkyBridge, but with static logic circuit implementation in order to mitigate the afore-mentioned challenges. We present an integrated framework to realize static circuits with vertical nanowires, and co-design it across all layers spanning fundamental fabric structures to large circuits. The new fabric, named as SkyBridge-CMOS, introduces new technology, structures and circuit designs to meet the additional requirements for implementing static circuits. One of the critical challenges addressed here is integrating both n-type and p-type nanowires. Molecular bonding process allows precise control between different doping regions, and novel fabric components are proposed to achieve 3-D routing between various doping regions.
Core fabric components are designed, optimized and modeled with their physical level information taken into account. Based on these basic structures we design and evaluate various logic gates, arithmetic circuits and SRAM in terms of power, area footprint and delay. A comprehensive evaluation methodology spanning material/device level to circuit level is followed. Benchmarking against 16nm 2-D CMOS shows significant improvement of up to 50X in area footprint and 9.3X in total power efficiency for low power applications, and 3X in throughput for high performance applications. Also, better noise resilience and better power efficiency can be guaranteed when compared with original SkyBridge fabrics.
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ZHENG, LIN YI, and 林宜政. "5GHz CMOS Radio Transceiver Front-End Circuit5GHz CMOS Radio Transceiver Front-End Circuit5GHz CMOS Radio Transceiver Front-End Circuit." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/25734903180546882382.
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碩士聖約翰科技大學
自動化及機電整合研究所
94
This thesis presents the development of 5GHz wireless transceiver front-end circuits for the IEEE802.11a WLAN applications in TSMC 0.18um 1P6M CMOS technology. By using a 5.24GHz VCO, the 10MHz baseband signal is mixed and modulated up to the 5.25GHz RF signal. The system design considers the high linearity, low phase noise, and high isolation. The wireless transceiver front-end circuits of this thesis include a quadrature up-conversion mixer（QMixer） and a quadrature voltage- controlled oscillator（QVCO）. The circuit operating voltages are 1V and 1.5V, respectively. The simulation results of QMixer show conversion gain of 6.3dB, noise figure of 11.47dB, of -16dBm, IIP3 of -6dBm, and under -40~-50dB for isolation. The magnitude difference of the 5.25GHz RF signal and the 5.23GHz image sideband signal can be up to 38 dB. The QVCO has output frequency range of 5.13GHz~5.45GHz, and the phase noise of -97.554dBc/Hz@100KHz and -119.47dBc/Hz@1MHz。
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Patel, Vishal. "CMOS negative resistance circuits." Thesis, 2008. http://spectrum.library.concordia.ca/975640/1/MR40893.pdf.
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Active resistors in VLSI technology have grown in stature as they enable the design of large resistive loads without using excessively bulky resistors, or a high voltage supply. Active resistors designed in CMOS technology have the property of being voltage controlled, which permits the design of negative resistance circuits. A negative resistance circuit has the property in which the current is a decreasing function of the input voltage, and has an I-V curve with a negative slope. They have the potential of being a key building block for larger electronic systems in VLSI technology, with applications in various fundamental circuits such as amplifiers and oscillators. A detailed characterization of negative resistance circuits is presented in this thesis. Important large and small signal characteristics, including noise, linearity and power consumption are investigated. A strategy for designing wide bandwidth active resistors is proposed with supporting analysis. Key stability issues that have not previously been reported are brought forward and the stability of larger circuits that accommodate a negative resistor are investigated. To conclude the thesis, design applications in which negative resistors have been used to improve the performance of larger electronic systems are demonstrated. These include the design of a low phase noise current mode oscillator and a high bandwidth inverting feedback amplifie