Journal articles: 'CMOS weak inversion'

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Dokic, Branko, Tatjana Pesic-Brdjanin, and Rados Dabic. "Analytic models of CMOS logic in various regimes." Serbian Journal of Electrical Engineering 11, no. 2 (2014): 269–90. http://dx.doi.org/10.2298/sjee140106022d.

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In this paper, comparative analytic models of static and dynamic characteristics of CMOS digital circuits in strong, weak and mixed inversion regime have been described. Term mixed inversion is defined for the first time. The paper shows that there is an analogy in behavior and functional dependencies of parameters in all three CMOS regimes. Comparative characteristics of power consumption and speed in static regimes are given. Dependency of threshold voltage and logic delay time on temperature has been analyzed. Dynamic model with constant current is proposed. It is shown that digital circuits with dynamic threshold voltage of MOS transistor (DT-CMOS) have better logic delay characteristics. The analysis is based on simplified current-voltage MOS transistor models in strong and weak inversion regimes, as well as PSPICE software using 180 nm technology parameters.

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De Jesus-Peregrina, Rogelio, Alejandro Diaz-Sanchez, Esteban Tlelo-Cuautle, and Jose Miguel Rocha-Pérez. "A novel CMOS exponential transconductor operating in weak inversion." International Journal of Electronics 95, no. 12 (December 2008): 1221–28. http://dx.doi.org/10.1080/00207210802354965.

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BOZOMITU, R. G., and V. CEHAN. "New ELIN Systems Using CMOS Transistors in Weak Inversion Operation." Advances in Electrical and Computer Engineering 13, no. 4 (2013): 99–102. http://dx.doi.org/10.4316/aece.2013.04017.

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Akbari, Meysam, Omid Hashemipour, and Farshad Moradi. "Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 9 (September 2018): 1812–16. http://dx.doi.org/10.1109/tvlsi.2018.2830749.

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WANG, KEPING, XUEMEI LEI, KAIXUE MA, KIAT SENG YEO, XIANG CAO, and ZHIGONG WANG. "A CMOS LOW-POWER TEMPERATURE-ROBUST RSSI USING WEAK-INVERSION LIMITING AMPLIFIERS." Journal of Circuits, Systems and Computers 22, no. 10 (December 2013): 1340034. http://dx.doi.org/10.1142/s0218126613400343.

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This paper presents a low-power CMOS receiving signal strength indicator (RSSI). The main architecture of the circuit adopts a six-stage limiting amplifier (LA) in a logarithmic-linear form, which shows a good performance in weak signal detection. The RSSI achieves high tolerance to process, voltage, and temperature (PVT) variations by utilizing the unique nature of branch currents in a transconductance amplifier. The power consumption is decreased by using the weak-inversion LAs. Full-waveform current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low power consumption. Measured results show that in the 1 kHz–50 MHz frequency range, the input dynamic range is wider than 70 dB within ±2 dB linearity error. The chip occupies an area of 0.7 mm2 × 0.3 mm2 using a 0.18-μm CMOS. It draws 1.3 mA from a 1.8 V supply.

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Georgiou, Pantelis, and Christofer Toumazou. "ISFET characteristics in CMOS and their application to weak inversion operation." Sensors and Actuators B: Chemical 143, no. 1 (December 4, 2009): 211–17. http://dx.doi.org/10.1016/j.snb.2009.09.018.

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Papadimitriou, Konstantinos I., and Emmanuel M. Drakakis. "CMOS weak-inversion log-domain glycolytic oscillator: a cytomimetic circuit example." International Journal of Circuit Theory and Applications 42, no. 2 (September 17, 2012): 173–94. http://dx.doi.org/10.1002/cta.1847.

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Malits, Maria, Dan Corcos, Alexander Svetlitza, Danny Elad, and Yael Nemirovsky. "Thermal performance of CMOS-SOI transistors from weak to strong inversion." IEEE Instrumentation & Measurement Magazine 15, no. 5 (October 2012): 28–34. http://dx.doi.org/10.1109/mim.2012.6314512.

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Prodanov, V. I., and M. M. Green. "Bipolar/CMOS (weak inversion) rail-to-rail constant-gm input stage." Electronics Letters 33, no. 5 (1997): 386. http://dx.doi.org/10.1049/el:19970263.

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Ma, Bill, and Feng Qi Yu. "A 1.2-V 1.76-Ppm/°C Low Voltage CMOS Band-Gap Reference." Applied Mechanics and Materials 303-306 (February 2013): 1798–802. http://dx.doi.org/10.4028/www.scientific.net/amm.303-306.1798.

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This paper proposes an innovative CMOS band-gap reference (BGR) topology with a curvature-compensation by using MOS transistors operating in weak inversion region. The mechanism is analyzed thoroughly and the corresponding BGR circuit has been implemented in standard CMOS 0.18u technology. The proposed BGR achieves 1.76 ppm/°C in the range of -40°C to 120°C at 1.2V supply voltage. In addition, it consumes only 30uA current.

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Toledo, Pedro, Hamilton Klimach, David Cordova, Sergio Bampi, and Eric Fabris. "Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition." Journal of Integrated Circuits and Systems 11, no. 1 (December 28, 2016): 27–37. http://dx.doi.org/10.29292/jics.v11i1.427.

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Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/oC.

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Mitrea, O., C. Popa, A. M. Manolescu, and M. Glesner. "A curvature-corrected CMOS bandgap reference." Advances in Radio Science 1 (May 5, 2005): 181–84. http://dx.doi.org/10.5194/ars-1-181-2003.

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Abstract. This paper presents a CMOS bandgap reference that employs a curvature correction technique for compensating the nonlinear voltage temperature dependence of a diode connected BJT. The proposed circuit cancels the first and the second order terms in the VBE(T ) expansion by using the current of an autopolarizedWidlar source and a small correction current generated by a MOSFET biased in weak inversion. The voltage reference has been fabricated in a 0.35µm 3Metal/2Poly CMOS technology and the chip area is approximately 70µm × 110µm. The measured temperature coefficient is about 10.5 ppm/K over a temperature range of 10– 90°C while the power consumption is less than 1.4mW.

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ROY, KAUSHIK, SAIBAL MUKHOPADHYAY, and HAMID MAHMOODI-MEIMAND. "LEAKAGE CURRENT IN DEEP-SUBMICRON CMOS CIRCUITS." Journal of Circuits, Systems and Computers 11, no. 06 (December 2002): 575–600. http://dx.doi.org/10.1142/s021812660200063x.

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The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power applications. This paper explores the various transistor intrinsic leakage mechanisms including the weak inversion, the drain-induced barrier lowering, the gate-induced drain leakage, and the gate oxide tunneling.

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Jaeger, Richard C., and Jeffrey C. Suhling. "First- and Second-Order Piezoresistive Coefficients of CMOS FETs From Strong Into Weak Inversion." IEEE Sensors Journal 19, no. 23 (December 1, 2019): 11309–17. http://dx.doi.org/10.1109/jsen.2019.2935993.

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Comer, D. J., and D. T. Comer. "Using the weak inversion region to optimize input stage design of CMOS op amps." IEEE Transactions on Circuits and Systems II: Express Briefs 51, no. 1 (January 2004): 8–14. http://dx.doi.org/10.1109/tcsii.2003.821517.

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Botma, J. H., R. F. Wassenaar, and R. J. Wiegerink. "Simple rail-to-rail low-voltage constant-transconductance CMOS input stage in weak inversion." Electronics Letters 29, no. 12 (1993): 1145. http://dx.doi.org/10.1049/el:19930764.

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Kalra, Shruti, and Amalendu B. Bhattacharyya. "Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold." International Journal of Electronics and Telecommunications 63, no. 4 (November 27, 2017): 369–74. http://dx.doi.org/10.1515/eletel-2017-0050.

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Abstract Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The value of α is obtained through interpolation following EKV model. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as the application of the proposed model. The abstract goes here.

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Toledo, Pedro, Hamilton Klimach, David Cordova, Sergio Bampi, and Eric Fabris. "MOSFET ZTC Condition Analysis for a Self-biased Current Reference Design." Journal of Integrated Circuits and Systems 10, no. 2 (December 28, 2015): 103–12. http://dx.doi.org/10.29292/jics.v10i2.411.

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In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be implemented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and provides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, showing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/oC from -40 to +85oC, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V.

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Srivastava, Richa, Maneesha Gupta, and Urvashi Singh. "Fully Programmable Gaussian Function Generator Using Floating Gate MOS Transistor." ISRN Electronics 2012 (November 20, 2012): 1–5. http://dx.doi.org/10.5402/2012/148492.

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Floating gate MOS (FGMOS) based fully programmable Gaussian function generator is presented. The circuit combines the tunable property of FGMOS transistor, exponential characteristics of MOS transistor in weak inversion, and its square law characteristic in strong inversion region to implement the function. Two-quadrant current mode squarer is the core subcircuit of Gaussian function generator that helps to implement full Gaussian function for positive as well as negative input current. FGMOS implementation of the circuit reduces the current mismatching error and increases the tunability of the circuit. The performance of circuit is verified at 1.8 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.

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Kompitaya, Pantre, and Khanittha Kaewdang. "An Ultra-Low-Voltage Low-Power Current-Mode True RMS-to-DC Converter." Journal of Circuits, Systems and Computers 25, no. 06 (March 31, 2016): 1650066. http://dx.doi.org/10.1142/s0218126616500663.

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A current-mode CMOS true RMS-to-DC (RMS: root-mean-square) converter with very low voltage and low power is proposed in this paper. The design techniques are based on the implicit computation and translinear principle by using CMOS transistors that operate in the weak inversion region. The circuit can operate for two-quadrant input current with wide input dynamic range (0.4–500[Formula: see text]nA) with an error of less than 1%. Furthermore, its features are very low supply voltage (0.8[Formula: see text]V), very low power consumption ([Formula: see text]0.2[Formula: see text]nW) and low circuit complexity that is suitable for integrated circuits (ICs). The proposed circuit is designed using standard 0.18[Formula: see text][Formula: see text]m CMOS technology and the HSPICE simulation results show the high performance of the circuit and confirm the validity of the proposed design technique.

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Rakús, Matej, Viera Stopjaková, and Daniel Arbet. "Design techniques for low-voltage analog integrated circuits." Journal of Electrical Engineering 68, no. 4 (August 28, 2017): 245–55. http://dx.doi.org/10.1515/jee-2017-0036.

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AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

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Fiorelli, Rafaella, Fernando Silveira, and Eduardo Peralias. "MOST Moderate–Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs." IEEE Transactions on Microwave Theory and Techniques 62, no. 3 (March 2014): 556–66. http://dx.doi.org/10.1109/tmtt.2014.2303476.

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Lin, Yu-Hsuan, and Huei Wang. "A 35.7–64.2 GHz low power Miller Divider with Weak Inversion Mixer in 65 nm CMOS." IEEE Microwave and Wireless Components Letters 26, no. 11 (November 2016): 948–50. http://dx.doi.org/10.1109/lmwc.2016.2615013.

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Tedja, S., H. H. Williams, J. Van der Spiegel, F. M. Newcomer, and R. Van Berg. "Noise spectral density measurements of a radiation hardened CMOS process in the weak and moderate inversion." IEEE Transactions on Nuclear Science 39, no. 4 (1992): 804–8. http://dx.doi.org/10.1109/23.159711.

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Guo, Benqing, Jun Chen, Hongpeng Chen, and Xuebing Wang. "A 0.1–1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS." Modern Physics Letters B 32, no. 02 (January 20, 2018): 1850009. http://dx.doi.org/10.1142/s0217984918500094.

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An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 [Formula: see text]m CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8–3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13–18.9 and 24–40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

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Martin, Lucy Claire, Hua Khee Chan, David T. Clark, Ewan P. Ramsay, A. E. Murphy, Dave A. Smith, Robin F. Thompson, et al. "Low Frequency Noise Analysis of Monolithically Fabricated 4H-SiC CMOS Field Effect Transistors." Materials Science Forum 778-780 (February 2014): 428–31. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.428.

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Low frequency noise in 4H-SiC lateral p-channel metal oxide semiconductor field effect transistors (PMOSFETs) in the frequency range from 1 Hz to 100 kHz has been used to investigate the relationship between gate dielectric fabrication techniques and the resulting density of interface traps at the semiconductor-dielectric interface in order to examine the impact on device performance. The results show that the low frequency noise characteristics in p-channel 4H-SiC MOSFETs in weak inversion are in agreement with the McWhorter model and are dominated by the interaction of channel carriers with interface traps at the gate dielectric/semiconductor interface.

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Girardi, Alessandro, and Sergio Bampi. "Power Constrained Design Optimization of Analog Circuits Based on Physical gm/ID Characteristics." Journal of Integrated Circuits and Systems 2, no. 1 (September 9, 2007): 22–28. http://dx.doi.org/10.29292/jics.v2i1.232.

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This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimization guide. Our custom layout tool LIT implements and uses the ACM MOS compact model in the optimization loop. The methodology is implemented for automation within LIT and exploits all design space through the simulated annealing optimization process, providing solutions close to optimum with a single technology-dependent curve and accurate expressions for transconductance and current valid in all operation regions. The compact model itself contributes to convergence and to optimized implementations, since it has analytic expressions which are continuous in all current regimes, including weak and moderate inversion. The advantage of constraining the optimization within a power budget is of great importance for low-power CMOS. As examples we show the optimization results obtained with LIT, resulting in significant power savings, for the design of a folded-cascode and a two-stage Miller operational amplifier.

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Köymen, Itır, Konstantinos N. Glaros, and Emmanuel M. Drakakis. "Class A and Class AB CMOS-Only Nanopower Memristive Dynamics Emulators." International Journal of Bifurcation and Chaos 26, no. 08 (July 2016): 1650127. http://dx.doi.org/10.1142/s0218127416501273.

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Memristive dynamics are generated utilizing active, weak-inversion, CMOS circuits. Class A and Class AB approaches to the generation of these dynamics are presented. The Class A circuit is composed of a grounded capacitor and two exponential transconductors (E-cells). It consumes a few nanowatts of power from a 1V power supply. The Class AB circuit also consists of a similar architecture with an added geometric mean splitter. Simulation results confirm the realization of pinched hysteresis loops exhibiting the zero crossing property of the memristor. The effects of varying input amplitude and frequency as well as the capacitor value are investigated. With the use of MOS capacitors in the place of monolithic capacitors, the area requirements of these emulators can be significantly diminished. Simulation results of circuits with both types of capacitors are presented. The simple emulators presented here offer the possibility of realizing nanoscale memristor dynamics when high yield memristor processes are not accessible.

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Dokic, B. L. "A Review on Energy Efficient CMOS Digital Logic." Engineering, Technology & Applied Science Research 3, no. 6 (December 18, 2013): 552–61. http://dx.doi.org/10.48084/etasr.389.

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Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt) and power supply voltage (Vdd) on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed) depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL), complementary pass logic (CPL), push-pull pass logic (PPL) and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.

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Setiabudi, Agung, Hiroki Tamura, and Koichi Tanno. "CMOS Temperature Sensor with Programmable Temperature Range for Biomedical Applications." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 2 (April 1, 2018): 946. http://dx.doi.org/10.11591/ijece.v8i2.pp946-953.

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<div class="page" title="Page 1"><div class="layoutArea"><div class="column"><p class="p1"><span class="s1">A CMOS temperature sensor circuit with programmable temperature range is proposed for biomedical applications. The proposed circuit consists of temperature sensor core circuit and programmable temperature range digital interface circuit. Both circuits are able to be operated at 1.0 V. The proposed temperature sensor circuit is operated in weak inversion region of MOSFETs. The proposed digital interface circuit converts current into time using Current-to-Time Converter (ITC) and converts time to digital data using counter. Temperature range can be programmed by adjusting pulse width of the trigger and clock frequency of counter. The proposed circuit was simulated using HSPICE with 1P, 5M, 3-wells, 0.18-μm CMOS process (BSIM3v3.2, LEVEL53). From the simulation of proposed circuit, temperature range is programmed to be 0 °C to 100 °C, it is obtained that resolution of the proposed circuit is 0.392 °C with -0.89/+0.29 °C inaccuracy and the total power consumption is 22.3 μW in 25 °C.<span class="Apple-converted-space"> </span></span></p></div></div></div>

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Akhamal, Hicham, Mostafa Chakir, Hatim Ameziane, Mohammed Akhamal, Kamal Zared, and Hassan Qjidaa. "Nano-Power Low-Dropout Voltage Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications." WSEAS TRANSACTIONS ON POWER SYSTEMS 15 (January 4, 2021): 240–48. http://dx.doi.org/10.37394/232016.2020.15.28.

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This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for Radio-Frequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transientresponse degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any onchip and off-chip compensation capacitors. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 µm2 . The regulator operates with supply voltages from 1.2V to 2V.

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POPA, COSMIN. "LOGARITHMICAL CURVATURE-CORRECTED VOLTAGE REFERENCES WITH IMPROVED TEMPERATURE BEHAVIOR." Journal of Circuits, Systems and Computers 18, no. 03 (May 2009): 519–34. http://dx.doi.org/10.1142/s0218126609005253.

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Two voltage reference circuits will be presented. For the first circuit, the linear compensation of V GS (T) for an MOS transistor in subthreshold region will be realized using an original offset voltage follower block as PTAT voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. A new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier for compensating the logarithmic temperature dependent term from V GS (T). Because of the operation in weak inversion of all MOS transistors, the circuit will have a very small current consumption, making it compatible with low-power low-voltage designs. The simulated temperature coefficient of the reference voltage for V DD = 2.5 V and a temperature range 0 < t < 30° C is 36.5 ppm/K, confirming the theoretical estimations. The variation of the reference voltage with respect to the supply voltage is 1.5 mV/V for 2–4 V. The circuit current consumption is about 1 μA and the minimal supply voltage is 2 V. The main goal of the second proposed voltage reference is to improve the temperature behavior of a previous reported bipolar voltage reference, by replacing the bipolar transistors with MOS transistors working in weak inversion, with the advantage of obtaining the compatibility with CMOS technology. The new proposed curvature-correction technique will be based on the compensation of the nonlinear temperature dependence of the gate-source voltage for a subthreshold operated MOS transistor by a correction current obtained by taking the difference between two gate-source voltages for MOS transistors biased at drain currents with different temperature dependencies. The circuit is implemented in 0.35 μm CMOS technology. The SPICE simulation confirms the theoretical estimated results, reporting a temperature coefficient of 4.23 ppm/K for the commercial temperature range, 0 < t < 70° C and a small supply voltage, V DD = 2.5 V . The variation of the reference voltage with respect to the supply voltage is 0.9 mV/V for 2–4 V.

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Dong, Zigang, Xiaolin Zhou, and Yuanting Zhang. "A Novel Differential Log-Companding Amplifier for Biosignal Sensing." Journal of Sensors 2016 (2016): 1–7. http://dx.doi.org/10.1155/2016/5358963.

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We proposed a new method for designing the CMOS differential log-companding amplifier which achieves significant improvements in linearity, common-mode rejection ratio (CMRR), and output range. With the new nonlinear function used in the log-companding technology, this proposed amplifier has a very small total harmonic distortion (THD) and simultaneously a wide output current range. Furthermore, a differential structure with conventionally symmetrical configuration has been adopted in this novel method in order to obtain a high CMRR. Because all transistors in this amplifier operate in the weak inversion, the supply voltage and the total power consumption are significantly reduced. The novel log-companding amplifier was designed using a 0.18 μm CMOS technology. Improvements in THD, output current range, noise, and CMRR are verified using simulation data. The proposed amplifier operates from a 0.8 V supply voltage, shows a 6.3 μA maximum output current range, and has a 6 μW power consumption. The THD is less than 0.03%, the CMRR of this circuit is 74 dB, and the input referred current noise density is166.1 fA/Hz. This new method is suitable for biomedical applications such as electrocardiogram (ECG) signal acquisition.

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Kaskouta, Elpida, Stavroula Kapoulea, Costas Psychalinos, and Ahmed S. Elwakil. "Implementation of a Fractional-Order Electronically Reconfigurable Lung Impedance Emulator of the Human Respiratory Tree." Journal of Low Power Electronics and Applications 10, no. 2 (May 16, 2020): 18. http://dx.doi.org/10.3390/jlpea10020018.

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The fractional-order lung impedance model of the human respiratory tree is implemented in this paper, using Operational Transconductance Amplifiers. The employment of such active element offers electronic adjustment of the impedance characteristics in terms of both elements values and orders. As the MOS transistors in OTAs are biased in the weak inversion region, the power dissipation and the dc bias voltage of operation are also minimized. In addition, the partial fraction expansion tool has been utilized, in order to achieve reduction of the spread of the required time-constants and scaling factors. The performance of the proposed scheme has been evaluated, at post-layout level, using MOS transistors models provided by the 0.35 μ m Austria Mikro Systeme technology CMOS process, and the Cadence IC design suite.

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Akhamal, Hicham, Mostafa Chakir, Hatim Ameziane, Mohammed, Akhamal, Kamal Zared, and Hassan Qjidaa. "A 916 nW Power LDO Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 19 (February 26, 2021): 311–19. http://dx.doi.org/10.37394/23201.2020.19.34.

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This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for RadioFrequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any on-chip and off-chip compensation capacitors. The power is 916 nW. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 μm2. The regulator operates with supply voltages from 1.2V to 2V

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Hosseinipouya, Seid Jafar, and Farhad Dastadast. "Design of a New Low Power Fully Differential Amplifier with Settling Time Enhancement Characteristics." Journal of Circuits, Systems and Computers 24, no. 06 (May 26, 2015): 1550078. http://dx.doi.org/10.1142/s0218126615500784.

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High performance of fully differential operational transconductance amplifier is designed and implemented using a 0.18-μm CMOS process. The implemented op-amp uses common mode feedback (CMFB) circuit operating in weak inversion region which does not affect other electrical characteristics due to eliminating common mode (CM) levels automatically leading to improve CM rejection ratio (CMRR) of the amplifier significantly. Moreover, the output stage has class-AB operation so that its current can be made larger due to increasing the output current dynamically using adaptive biasing circuit. Additionally, the AC currents of the active loads have been significantly reduced using negative impedances to increase the gain of the amplifier. The results show the GBW 2.3 MHz, slew rate 2.6 V/μs and 1% settling time 150 ns with a capacitive load of 15 pF. This amplifier dissipates only 6.2 μW from a 1.2 V power supply.

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Olmos, Alfredo, Fabricio Ferreira, Fernando Paixão Cortes, Fernando Chavez, and Marcelo Soares Lubaszewski. "A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference: Design and Application." Journal of Integrated Circuits and Systems 10, no. 2 (December 28, 2015): 74–80. http://dx.doi.org/10.29292/jics.v10i2.408.

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This paper presents the design and application of a CMOS sub-1V voltage reference using a 2-transistor Self-Cascode MOSFET (SCM) structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. The two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a > 0.18mm standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of ±0.18% from -20°C to 75°C (or less than 15ppm/°C), operates from 3.6V down to 800mV while biased with a 5nA resistor-less PTAT current source that varies ±30% over PVT, and consumes less than 20nA with an area of 0.01mm2. The same concept was used to create a temperature compensated voltage drop with regard to a monitored power supply voltage but using a 2-PMOS SCM structure with transistors of different threshold voltages. These two circuits were adopted as part of a Power Management (PM) system for RFID tag applications. The PM includes a LDO voltage regulator and a low voltage detector that require both the voltage reference and the low voltage monitor. The LDO regulated output voltage and the trip-point of the voltage detector vary +/-5.5% and +/-3.3%, respectively, over temperature, without trimming.

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Ericson, M. N., C. L. Britton, J. M. Rochelle, B. J. Blalock, D. M. Binkley, A. L. Wintenberg, and B. D. Williamson. "Flicker noise behavior of MOFSETs fabricated in 0.5 μm fully depleted (FD) silicon-on-sapphire (SOS) CMOS in weak, moderate, and strong inversion." IEEE Transactions on Nuclear Science 50, no. 4 (August 2003): 963–68. http://dx.doi.org/10.1109/tns.2003.815146.

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LANG, WEI, PEIYUAN WAN, and PINGFEN LIN. "A 0.8 V 48 μW 82 dB SNDR 10-kHz BANDWIDTH ΣΔ MODULATOR IN 0.13-μM CMOS." Journal of Circuits, Systems and Computers 22, no. 04 (April 2013): 1350027. http://dx.doi.org/10.1142/s0218126613500278.

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This paper presents a low-power low-voltage chopper stabilized discrete-time second-order feed-forward ΣΔ modulator with an asynchronous 4-bit successive-approximation-register (SAR) quantizer. The feed-forward topology will reduce the internal signal swing, relaxing the linearity and slew rate requirements for an operational amplifier (op-amp). The analog weighted summation of feed-forward paths is merged with the sampling capacitor array of a SAR quantizer to minimize the distortion and associated hardware overhead. To achieve low power consumption, a partially switched op-amp bias in weak inversion is used for the first integrator. The energy efficiency is further improved by the asynchronous SAR 4-bit quantizer. Moreover, the asynchronous scheme will reduce loop delay caused by the summation block, the quantizer and the data weighted averaging (DWA) circuit, improving circuit stability and lowering power consumption. A 0.13-μm CMOS experimental prototype achieves 84 dB dynamic range, 84 dB peak SNR and 82 dB peak SNDR over an input signal bandwidth of 10-kHz. The total power consumption of the modulator is 48 μW from a 0.8 V supply at an 800-kHz sampling rate.

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Bellando, Francesco, Leandro Julian Mele, Pierpaolo Palestri, Junrui Zhang, Adrian Mihai Ionescu, and Luca Selmi. "Sensitivity, Noise and Resolution in a BEOL-Modified Foundry-Made ISFET with Miniaturized Reference Electrode for Wearable Point-of-Care Applications." Sensors 21, no. 5 (March 4, 2021): 1779. http://dx.doi.org/10.3390/s21051779.

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Ion-sensitive field-effect transistors (ISFETs) form a high sensitivity and scalable class of sensors, compatible with advanced complementary metal-oxide semiconductor (CMOS) processes. Despite many previous demonstrations about their merits as low-power integrated sensors, very little is known about their noise characterization when being operated in a liquid gate configuration. The noise characteristics in various regimes of their operation are important to select the most suitable conditions for signal-to-noise ratio (SNR) and power consumption. This work reports systematic DC, transient, and noise characterizations and models of a back-end of line (BEOL)-modified foundry-made ISFET used as pH sensor. The aim is to determine the sensor sensitivity and resolution to pH changes and to calibrate numerical and lumped element models, capable of supporting the interpretation of the experimental findings. The experimental sensitivity is approximately 40 mV/pH with a normalized resolution of 5 mpH per µm2, in agreement with the literature state of the art. Differences in the drain current noise spectra between the ISFET and MOSFET configurations of the same device at low currents (weak inversion) suggest that the chemical noise produced by the random binding/unbinding of the H+ ions on the sensor surface is likely the dominant noise contribution in this regime. In contrast, at high currents (strong inversion), the two configurations provide similar drain noise levels suggesting that the noise originates in the underlying FET rather than in the sensing region.

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Blakiewicz, Grzegorz, Jacek Jakusz, and Waldemar Jendernalik. "Starter for Voltage Boost Converter to Harvest Thermoelectric Energy for Body-Worn Sensors." Energies 14, no. 14 (July 6, 2021): 4092. http://dx.doi.org/10.3390/en14144092.

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This paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscillators as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip implementation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability of n-channel native MOS transistors with negative or near-zero threshold voltage in ULV oscillators is analyzed. The results demonstrate that a near-zero threshold voltage transistor operating in the weak inversion region is most advantageous for the considered application. The obtained results were used as a reference for design of a boost converter starter intended for integration in 180-nm CMOS X-FAB technology. In the selected technology, the most suitable transistor available with a negative threshold voltage was used. Despite using a transistor with a negative threshold voltage, a low startup voltage of 29 mV, a power consumption of 70 µW, and power conversion efficiency of about 1.5% were achieved. A great advantage of the proposed starter is that it eliminates a multistage charge pump necessary to obtain a voltage of sufficient value to supply the boost converter control circuit.

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Sharan, Tripurari, and Vijaya Bhadauria. "Fully Differential, Bulk-Driven, Class AB, Sub-Threshold OTA With Enhanced Slew Rates and Gain." Journal of Circuits, Systems and Computers 26, no. 01 (October 4, 2016): 1750001. http://dx.doi.org/10.1142/s0218126617500013.

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This paper presents a single-stage ultra-low-power fully differential operational transconductance amplifier (FD-OTA) with rail-to-rail linear input range operating in weak inversion region. The input core of the OTA is comprised of source degenerated, flipped voltage follower (FVF)-based bulk-driven class AB input pair, into which a regenerative feedback loop has been inserted to boost its bulk transconductance ([Formula: see text]). The proposed FD-OTA has utilized self-cascode current mirror (SC-CM) loads, which increase its open loop gain from nominal intrinsic value of 42[Formula: see text]dB to 70.4[Formula: see text]dB. It has provided 9.24[Formula: see text]kHz gain bandwidth (GBW), consuming 64[Formula: see text]nW of quiescent power from a 0.51[Formula: see text]V single power supply at 15[Formula: see text]pF load. The proposed OTA in unity gain configuration has ensured reduced total harmonic distortion (THD) of [Formula: see text][Formula: see text]dB at 200[Formula: see text]Hz frequency and 1[Formula: see text]V[Formula: see text] signal swing. Its fully differential class AB input and output structures have ensured increased gain, GBW, slew rates and output swings with reduced nonlinearity and common mode substrate noise. The Cadence Virtuoso environment using GPDK 180[Formula: see text]nm standard [Formula: see text]-well CMOS process technology has been used to simulate the proposed circuit.

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Ameziane, Hatim, Kamal Zared, and Hassan Qjidaa. "A New CMOS OP-AMP Design with an Improved Adaptive Biasing Circuitry." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 19 (January 4, 2021). http://dx.doi.org/10.37394/23201.2020.19.27.

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This paper sets out a new technique for designing an operational amplifier (OP-AMP) using tanner EDA 1um FDSOI CMOS Technology. Fully Depleted Silicon on Insulator used for building integrated circuits to support the temperature changes, the proposed OP-AMP operates at 3.75V power supply and 70uA bias current using the proposed Adaptive Biasing Circuitry (ABC), which its devices operate at the weak inversion to allow low power dissipation of 0.62mW. The 0.064us settling time and 37.016V/μs slew rate parameters improved by the ABC technique, reducing the power dissipation by operating the ABC devices in weak inversion. The phase margin is more than 100 degrees for the DC gain of 13.97dB, which is a reasonable margin when temperature range increases.

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Fekih-Ahmed, Lazhar. "A Constructive Methodology of Analog Synthesis of Nonlinear Functions in Subthreshold CMOS." Journal of Circuits, Systems and Computers, March 31, 2021, 2150221. http://dx.doi.org/10.1142/s0218126621502212.

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We introduce a clear constructive methodology of approximation and synthesis of analog functions using the transfer characteristics of the basic differential pair. The new methodology provides circuit designers with an easy-to-understand solution of the function approximation problem employing MOSFETs in weak inversion. It further provides compact formulas for the optimal coefficients involved in the approximation. We confirm the design methodology using SPICE through two examples involving the exponential function.

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Zarei, Reza, and Moora Maali. "Analog Multiplier Based on Squarer Cells." International Journal of Scientific Research in Science, Engineering and Technology, March 8, 2019, 350–54. http://dx.doi.org/10.32628/ijsrset1841078.

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In this paper, a current-mode analog multiplier circuit is proposed that utilizes MOS translinear principle. The parameters of TSMC 0.18µm technology are used to design the proposed multiplier that employs CMOS transistors operating in weak inversion region. Simulations are performed by HSPICE for the circuit to prove its great merits of; low power consumption (100µW), low supply voltage (1.6V), body effect immunity, wide input range (±100nA), bandwidth of 1 MHz, and THD of 4%.

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"High Performance Bulk Driven Operational Trans Conductance Amplifier and Applications." International Journal of Innovative Technology and Exploring Engineering 8, no. 12S (December 26, 2019): 344–47. http://dx.doi.org/10.35940/ijitee.l1089.10812s19.

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In this paper a bulk driven Fully cascoded operational transconductance amplifier(FCOTA) is designed. OTA applications are designed for voltage controlled current amplifier, filters and analog subtractor. With the current sizing method, all transistors in FCOTA work under weak inversion field. The total current in the proposed amplifier in terms of nano amperes only. As part of low power the circuit operated with the power supply of 0.8V. The main important features of the design are good linearity and accuracy. Full input and output voltage swings. This circuit has been constructed using CMOS technology with UMC90 nm. The circuit’s total power consumption is 620nW

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DANESH, MOHAMMAD HADI, SASAN NIKSERESHT, and MAHYAR DEHDAST. "A CURRENT-MODE RMS-TO-DC CONVERTER BASED ON TRANSLINEAR PRINCIPLE." International Journal of Electronics and Electical Engineering, January 2015, 171–74. http://dx.doi.org/10.47893/ijeee.2015.1149.

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In this paper a low-power current-mode RMS-to-DC converter is proposed. The proposed converter includes absolute value circuit, squarer/divider circuit, low-pass filter and square root circuit which employ CMOS transistors operating in weak inversion region. The RMS-to-DC converter has low power consumption (<1μW), low supply voltage (0.9V), wide input range (from 50 nA to 500 nA), low relative error (<3 %), and low circuit complexity. Comparing the proposed circuit with two other current-mode circuits shows that the former outperforms the latters in terms of power dissipation, supply voltage, and complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

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DANESH, MOHAMMAD HADI, SASAN NIKSERESHT, and MAHYAR DEHDAST. "A CURRENT-MODE RMS-TO-DC CONVERTER BASED ON TRANSLINEAR PRINCIPLE." International Journal of Electronics and Electical Engineering, January 2015, 171–74. http://dx.doi.org/10.47893/ijeee.2015.1149.

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In this paper a low-power current-mode RMS-to-DC converter is proposed. The proposed converter includes absolute value circuit, squarer/divider circuit, low-pass filter and square root circuit which employ CMOS transistors operating in weak inversion region. The RMS-to-DC converter has low power consumption (<1μW), low supply voltage (0.9V), wide input range (from 50 nA to 500 nA), low relative error (<3 %), and low circuit complexity. Comparing the proposed circuit with two other current-mode circuits shows that the former outperforms the latters in terms of power dissipation, supply voltage, and complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

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"Subthreshold Region based Linear Feedback Shift Register." International Journal of Engineering and Advanced Technology 8, no. 6S2 (October 10, 2019): 817–21. http://dx.doi.org/10.35940/ijeat.f1205.0886s219.

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Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

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Journal articles on the topic 'CMOS weak inversion'

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