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Journal articles on the topic 'CMOS VOLTAGE'

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Author: Grafiati

Published: 11 September 2023

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1

Dai, Y., D. T. Comer, D. J. Comer, and C. S. Petrie. "Threshold voltage based CMOS voltage reference." IEE Proceedings - Circuits, Devices and Systems 151, no. 1 (2004): 58. http://dx.doi.org/10.1049/ip-cds:20040217.

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2

Fouad, Hafez, Hesham Kamel, and Adel Youssef. "High Precision Low Input Voltage of 65nm CMOS Rectifier for Energy Harvesting using Threshold Voltage Minimization in Telemedicine Embedded System." International Journal of Circuits, Systems and Signal Processing 16 (October 7, 2022): 1135–47. http://dx.doi.org/10.46300/9106.2022.16.137.

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Telemedicine applications run at very low input voltages, necessitating the use of Great Precision Rectifier with high sensitivity to function at low input voltages. In this study, we used a 65 nm CMOS rectifier to achieve a 0.2V input voltage for Energy Harvesting Telemedicine application. The suggested rectifier, which has two-stage structure and operates at frequency of 2.4GHz, has been found to perform better in cases where the minimum operating voltage is lower than previously published papers, and the rectifier can operate over a wide range of low input voltage amplitudes. Full-Wave Fully gate cross-coupled Rectifiers (FWFR) CMOS Rectifier Efficiency at Freq of 2.4 GHz: With an input voltage amplitude of 2V, the minimum and maximum output voltages are 0.49V and 1.997V, respectively, with a peak VCE of 99.85 percent and a peak PCE of 46.86 percent. This enables the suggested rectifier to be used in a variety of vibration energy collecting systems, including electrostatic, electromagnetic, and piezoelectric energy harvesters. The proposed rectifier, which is built at 2.4GHz and has a two-stage structure, performs better in the event of low input voltage amplitude and has lower minimum operation voltage than previously published papers. Full-wave fully gate cross-coupled rectifiers (FWFR) CMOS Rectifier Performance Summary at Freq of 2.4 GHz: With a 2V input voltage amplitude, the minimum and maximum output voltages are 0.49V and 1.997V, respectively, with a maximum VCE of 99.85% and a maximum PCE of 46.86%.

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3

Fouad, Hafez, and Hesham Kamel. "Threshold Voltage Cancellation For Low Input Voltage of 65nm CMOS Rectifier of Energy Harvesting For Implantable Medical Devices in Telemedicine Embedded System." International Journal of Mathematics and Computers in Simulation 16 (October 27, 2022): 103–14. http://dx.doi.org/10.46300/9102.2022.16.16.

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Telemedicine applications run at very low voltages, necessitating the use of a Great Precision Rectifier with high sensitivity to function at low input voltages. In this study, we used a 65 nm CMOS rectifier to achieve a 0.2V input voltage for Energy Harvesting Telemedicine application. The suggested rectifier, which has two-stage structure and operates at frequency of 2.4GHz, has been found to perform better in cases where the minimum operating voltage is lower than previously published papers, and the rectifier can operate over a wide range of low input voltage amplitudes. Full-Wave Fully gate cross-coupled Rectifiers (FWFR) CMOS Rectifier Efficiency at Freq of 2.4 GHz: With an input voltage amplitude of 2V, the minimum and maximum output voltages are 0.49V and 1.997V, respectively, with a peak VCE of 99.85 percent and a peak PCE of 46.86 percent. This enables the suggested rectifier to be used in a variety of vibration energy collecting systems, including electrostatic, electromagnetic, and piezoelectric energy harvesters. The proposed rectifier, which is built at 2.4GHz and has a two-stage structure, performs better in the event of low input voltage amplitude and has a lower minimum operation voltage than previously published papers. Full-wave fully gate cross-coupled rectifiers (FWFR) CMOS Rectifier Performance Summary at Freq of 2.4 GHz: With a 2V input voltage amplitude, the minimum and maximum output voltages are 0.49V and 1.997V, respectively, with a maximum VCE of 99.85% and a maximum PCE of 46.86%.

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4

Ehrler, F., R. Blanco, R. Leys, and I. Perić. "High-voltage CMOS detectors." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 824 (July 2016): 400–401. http://dx.doi.org/10.1016/j.nima.2015.09.004.

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5

Marzaki, Abderrezak, V. Bidal, R. Laffont, W. Rahajandraibe, J.-M. Portal, and R. Bouchakour. "New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)." International Journal of Reconfigurable and Embedded Systems (IJRES) 2, no. 1 (March 1, 2013): 49. http://dx.doi.org/10.11591/ijres.v2.i1.pp49-54.

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This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages <em>V<sub>TH- </sub></em>(low switching voltage) and <em>V<sub>TH+ </sub></em>(high switching voltage).

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6

BISDOUNIS, LABROS. "ANALYTICAL MODELING OF OVERSHOOTING EFFECT IN SUB-100 nm CMOS INVERTERS." Journal of Circuits, Systems and Computers 20, no. 07 (November 2011): 1303–21. http://dx.doi.org/10.1142/s0218126611007967.

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Modeling of CMOS inverters and consequently, CMOS gates, is a critical task for improving accuracy and speed of simulation in modern sub-100 nm digital circuits. One of the key factors that determine the operation of a CMOS structure is the influence of the input-to-output coupling capacitance, also called overshooting effect. In this paper, an analytical model for this effect is presented, that computes the time period which is necessary to eliminate the extra output charge transferred through the input-to-output capacitance at the beginning of the switching process in a CMOS inverter. In addition, the maximum or minimum output voltage (depending on the considered edge) is analytically computed. The derived model is based on analytical expressions of the CMOS inverter output voltage waveform, which include the influences of both transistor currents and the input-to-output (gate-to-drain) coupling and load capacitances. An accurate version of the alpha-power law MOSFET model is used to relate the terminal voltages to the drain current in sub-100 nm devices, with an extension for varying transistor widths. The resulting model also accounts for the influences of input voltage transition time, transistors' sizes, as well as device carrier velocity saturation and narrow-width effects. The results produced by the presented model for three sub-100 nm CMOS technologies, several input voltage transition times, capacitive loads and device sizes, show very good agreement with BSIM4 HSPICE simulations.

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7

Hu, Jian Ping, and Jia Guo Zhu. "Voltage Scaling for SRAM in 45nm CMOS Process." Applied Mechanics and Materials 39 (November 2010): 253–59. http://dx.doi.org/10.4028/www.scientific.net/amm.39.253.

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Scaling supply voltage is an efficient approach to achieve low energy. Scaling supply voltage to sub-threshold region can reach minimum energy consumption but only suits for ultra-low operation frequencies. In order to attain more extensive application, scaling supply voltage to medium-voltage region is an attractive approach especially suiting for mid performances. This paper investigates performances of conventional SRAMs in near-threshold and super-threshold regions in terms of energy dissipation and max operating frequency. All circuits are simulated with HSPICE at PTM 45nm CMOS technology by varying supply voltages from 0.4V to 1.1V with 0.1V steps. The simulation results demonstrate that the conventional SRAMs operate on medium-voltage region can not only keep reasonable speed but also reduce greatly energy consumptions.

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8

AL-Qaysi, Hayder Khaleel, Musaab Mohammed Jasim, and Siraj Manhal Hameed. "Design of very low-voltages and high-performance CMOS gate-driven operational amplifier." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 2 (November 1, 2020): 670. http://dx.doi.org/10.11591/ijeecs.v20.i2.pp670-679.

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This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

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9

Meyer, Joseph, Reza Moghimi, and Noah Sturcken. "Package Voltage Regulators: The Answer for Power Management Challenges." International Symposium on Microelectronics 2019, no. 1 (October 1, 2019): 000438–43. http://dx.doi.org/10.4071/2380-4505-2019.1.000438.

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Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

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10

Wang, San-Fu. "A 5 V-to-3.3 V CMOS Linear Regulator with Three-Output Temperature-Independent Reference Voltages." Journal of Sensors 2016 (2016): 1–7. http://dx.doi.org/10.1155/2016/1436371.

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This paper presents a 5 V-to-3.3 V linear regulator circuit, which uses 3.3 V CMOS transistors to replace the 5 V CMOS transistors. Thus, the complexity of the manufacturing semiconductor process can be improved. The proposed linear regulator is implemented by cascode architecture, which requires three different reference voltages as the bias voltages of its circuit. Thus, the three-output temperature-independent reference voltage circuit is proposed, which provides three accurate reference voltages simultaneously. The three-output temperature-independent reference voltages also can be used in other circuits of the chip. By using the proposed temperature-independent reference voltages, the proposed linear regulator can provide an accurate output voltage, and it is suitable for low cost, small size, and highly integrated system-on-chip (SoC) applications. Moreover, the proposed linear regulator uses the cascode technique, which improves both the gain performance and the isolation performance. Therefore, the proposed linear regulator has a good performance in reference voltage to output voltage isolation. The voltage variation of the linear regulator is less than 2.153% in the temperature range of −40°C–120°C, and the power supply rejection ratio (PSRR) is less than −42.8 dB at 60 Hz. The regulator can support 0~200 mA output current. The core area is less than 0.16 mm2.

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11

Shawkat, Mst Shamim Ara, Mohammad Habib Ullah Habib, Md Sakib Hasan, Mohammad Aminul Haque, and Nicole McFarlane. "Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes." International Journal of High Speed Electronics and Systems 27, no. 03n04 (September 2018): 1840018. http://dx.doi.org/10.1142/s0129156418400189.

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A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.

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12

Lo, Tien-Yu, Chung-Chih Hung, and Mohammed Ismail. "CMOS voltage reference based on threshold voltage and thermal voltage." Analog Integrated Circuits and Signal Processing 62, no. 1 (June 11, 2009): 9–15. http://dx.doi.org/10.1007/s10470-009-9321-y.

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13

Kursun, Volkan, Vivek K. De, Eby G. Friedman, and Siva G. Narendra. "Monolithic voltage conversion in low-voltage CMOS technologies." Microelectronics Journal 36, no. 9 (September 2005): 863–67. http://dx.doi.org/10.1016/j.mejo.2005.03.008.

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14

Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty, and Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (November 1, 2022): 716. http://dx.doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when compared with Fin Field-Effect Transistor (FinFET) device. The leakage current is more in CMOS devices while in FinFET device due to the control of multi-Gates on the channel, the leakage current is reduced. This will improve the power consumption in the FinFET device when compared to CMOS devices. The comparator results shows that CMOS device is inferior when compared with FinFET device comparator. For the implementation of the comparator Spice model were used in this work. The software used in the project is synopsis Hspice.

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15

Torrance, R., T. Viswanathan, and J. Hanson. "CMOS voltage to current transducers." IEEE Transactions on Circuits and Systems 32, no. 11 (November 1985): 1097–104. http://dx.doi.org/10.1109/tcs.1985.1085644.

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16

Vlassis, S., and C. Psychalinos. "Low-voltage CMOS VT extractor." Electronics Letters 43, no. 17 (2007): 921. http://dx.doi.org/10.1049/el:20070917.

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17

Hosticka, B. J., W. Brockherde, D. Hammerschmidt, and R. Kokozinski. "Low-voltage CMOS analog circuits." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 42, no. 11 (1995): 864–72. http://dx.doi.org/10.1109/81.477197.

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18

Seevinck, E., M. du Plessis, T.-H. Joubert, and A. E. Theron. "Low-voltage CMOS bias circuit." Electronics Letters 32, no. 20 (1996): 1879. http://dx.doi.org/10.1049/el:19961252.

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19

Hanson, S., B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak, and D. M. Sylvester. "Ultralow-voltage, minimum-energy CMOS." IBM Journal of Research and Development 50, no. 4.5 (July 2006): 469–90. http://dx.doi.org/10.1147/rd.504.0469.

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20

ELWAN, HASSAN O., SOLIMAN A. MAHMOUD, and AHMED M. SOLIMAN. "CMOS voltage controlled floating resistor." International Journal of Electronics 81, no. 5 (November 1996): 571–76. http://dx.doi.org/10.1080/002072196136472.

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21

Jendernalik, W., J. Grzyb, and S. Szczepański. "Easily compensated CMOS voltage buffer." Electronics Letters 35, no. 22 (1999): 1947. http://dx.doi.org/10.1049/el:19991326.

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22

Pashmineh, S., and D. Killat. "High-voltage circuits for power management on 65 nm CMOS." Advances in Radio Science 13 (November 3, 2015): 109–20. http://dx.doi.org/10.5194/ars-13-109-2015.

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Abstract. This paper presents two high-voltage circuits used in power management, a switching driver for buck converter with optimized on-resistance and a low dropout (LDO) voltage regulator with 2-stacked pMOS pass devices. The circuit design is based on stacked MOSFETs, thus the circuits are technology independent. High-voltage drivers with stacked devices suffer from slow switching characteristics. In this paper, a new concept to adjust gate voltages of stacked transistors is introduced for reduction of on-resistance. According to the theory, a circuit is proposed that drives 2 stacked transistors of a driver. Simulation results show a reduction of the on-resistance between 27 and 86 % and a reduction of rise and fall times between 16 and 83 % with a load capacitance of 150 pF at various supply voltages, compared to previous work. The concept can be applied to each high-voltage driver that is based on a number (N) of stacked transistors. The high voltage compatibility of the low drop-out voltage regulator (LDO) is established by a 2-stacked pMOS transistors as pass device controlled by two regulators: an error amplifier and a 2nd amplifier adjusting the division of the voltages between the two pass transistors. A high GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. To improve stability, two feedback loops are utilized. In this paper, the 2.5 V I/O transistors of the TSMC 65 nm CMOS technology are used for the circuit design.

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23

Nejati, Ali, Yasin Bastan, Parviz Amiri, and Mohammad Hossein Maghami. "A Low-Voltage Bulk-Driven Differential CMOS Schmitt Trigger with Tunable Hysteresis." Journal of Circuits, Systems and Computers 28, no. 07 (June 27, 2019): 1920004. http://dx.doi.org/10.1142/s0218126619200044.

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This paper describes a low-voltage bulk-driven differential CMOS Schmitt trigger with tunable hysteresis for use in noise removal applications. The hysteresis of the proposed Schmitt trigger is designed based on a regenerative current feedback and its width is adjustable by two control voltages. The center of the hysteresis can also be adjusted by either the control voltages or input common-mode voltage. The principle operation of the proposed circuit is discussed, its main formulas are derived and its performance is verified by Cadence post-layout simulations. Designed in the TSMC 0.18[Formula: see text][Formula: see text]m standard CMOS process, the circuit consumes [Formula: see text]m2 of silicon area. Post-layout simulation results indicate that the hysteresis width of the Schmitt trigger can be adjusted from 170 to 270[Formula: see text]mV and the ratio of the hysteresis width variation to supply voltage is 11.11%. Operated with 0.8[Formula: see text]V supply voltage, the power consumption of the circuit ranges from 0.48 to 1.12[Formula: see text]mW.

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24

Boni, Andrea, Michele Caselli, Alessandro Magnanini, and Matteo Tonelli. "CMOS Interface Circuits for High-Voltage Automotive Signals." Electronics 11, no. 6 (March 21, 2022): 971. http://dx.doi.org/10.3390/electronics11060971.

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The acquisition of high-voltage signals from sensors and actuators in an internal-combustion engine is often required for diagnostic purposes or in the case of conversion to alternative fuels, such as hydrogen, natural gas, or biogas. The integration of electronic interfaces and acquisition circuits in a single device provides benefits in terms of component-count reduction and performance. Nonetheless, the high voltage level of the involved signals makes on-chip design challenging. Additionally, the circuits should be compatible with the CMOS technology, with limited use of high-voltage options and a minimum number of off-chip components. This paper describes the design and the implementation in 350 nm CMOS technology of electronic interfaces and acquisition circuits for typical high-voltage signals of automotive context. In particular, a novel co-design of dedicated voltage clamps with electro-static discharge (ESD) protections is described. The proposed circuits require only a single off-chip resistor, and they are suitable for the acquisition of signals with peak voltages up to 400 V. The measured performance of the silicon prototypes, in the [−40 °C, +125 °C] temperature range, make the proposed electronic interfaces suitable for the automotive domain.

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25

Ria, Andrea, Alessandro Catania, Paolo Bruschi, and Massimo Piotto. "A Low-Power CMOS Bandgap Voltage Reference for Supply Voltages Down to 0.5 V." Electronics 10, no. 16 (August 8, 2021): 1901. http://dx.doi.org/10.3390/electronics10161901.

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A voltage reference is strictly required for sensor interfaces that need to perform nonratiometric data acquisition. In this work, a voltage reference capable of working with supply voltages down to 0.5 V is presented. The voltage reference was based on a classic CMOS bandgap core, properly modified to be compatible with low-threshold or zero-threshold MOSFETs. The advantages of the proposed circuit are illustrated with theoretical analysis and supported by numerical simulations. The core was combined with a recently proposed switched capacitor, inverter-like integrator implementing offset cancellation and low-frequency noise reduction techniques. Experimental results performed on a prototype designed and fabricated using a commercial 0.18 μm CMOS process are presented. The prototype produces a reference voltage of 220 mV with a temperature sensitivity of 45 ppm/°C across a 10–50 °C temperature range. The proposed voltage reference can be used to source currents up to 100 μA with a quiescent current consumption of only 630 nA.

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26

Olmos, Alfredo, Fabricio Ferreira, Fernando Paixão Cortes, Fernando Chavez, and Marcelo Soares Lubaszewski. "A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference: Design and Application." Journal of Integrated Circuits and Systems 10, no. 2 (December 28, 2015): 74–80. http://dx.doi.org/10.29292/jics.v10i2.408.

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This paper presents the design and application of a CMOS sub-1V voltage reference using a 2-transistor Self-Cascode MOSFET (SCM) structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. The two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a > 0.18mm standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of ±0.18% from -20°C to 75°C (or less than 15ppm/°C), operates from 3.6V down to 800mV while biased with a 5nA resistor-less PTAT current source that varies ±30% over PVT, and consumes less than 20nA with an area of 0.01mm2. The same concept was used to create a temperature compensated voltage drop with regard to a monitored power supply voltage but using a 2-PMOS SCM structure with transistors of different threshold voltages. These two circuits were adopted as part of a Power Management (PM) system for RFID tag applications. The PM includes a LDO voltage regulator and a low voltage detector that require both the voltage reference and the low voltage monitor. The LDO regulated output voltage and the trip-point of the voltage detector vary +/-5.5% and +/-3.3%, respectively, over temperature, without trimming.

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27

Miresan, Paul, Marius Neag, Marina Topa, Istvan Kovacs, and Laurentiu Varzaru. "Multipurpose Drivers for MEMS Devices Based on a Single ASIC Implemented in a Low-Cost HV CMOS Process without a Triple Well." Journal of Sensors 2021 (March 30, 2021): 1–22. http://dx.doi.org/10.1155/2021/8818917.

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This paper presents a novel topology for multipurpose drivers for MEMS sensors and actuators, suitable for integration in low-cost high-voltage (HV) CMOS processes, without a triple well. The driver output voltage, V MEMS , can be programmed over a wide, symmetrical range of positive and negative values, with the maximum output voltage being limited only by the maximum drain-source voltage that the HV transistors can handle. The driver is also able to short its output to the ground line and to leave it floating. It comprises generators for large positive and negative voltages followed by an LDO for each polarity that ensures that V MEMS has a well-controlled level and a very low ripple. The LDOs also help implement the grounded- and floating-output operating modes. Most of the required circuitry is integrated within a HV CMOS ASIC: the drivers for the large voltage generators, the error amplifiers of the LDOs, the DAC used to program the V MEMS level, and their support circuits. Thus, only the power stages of the large voltage generators, the pass transistors of the LDOs and two resistors for the LDO feedback network are discrete. A suitable configuration was devised for the latter that allows for the external resistor network to be shared by the two LDOs and prevents negative voltages from developing at the ASIC pins. Two circuit implementations of the proposed topology, designed in a low-cost 0.18 μm HV CMOS process, are presented in some detail. Simulation results demonstrate that they realize the required operating modes and provide V MEMS voltages programmable with steps of 100 mV or 200 mV, between -20 V and +20 V or between −45 V and +45 V, respectively. The output voltage ripple is relatively small, just 3.4 mVpkpk for the first implementation and 17 mVpkpk for the second. Therefore, both circuits are suitable for biasing and controlling a wide range of MEMS devices, including MEMS mirrors used in applications such as endoscopic optical coherence tomography.

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28

YUCE, ERKAN, SHAHRAM MINAEI, and HALIL ALPASLAN. "NOVEL CMOS TECHNOLOGY-BASED LINEAR GROUNDED VOLTAGE CONTROLLED RESISTOR." Journal of Circuits, Systems and Computers 20, no. 03 (May 2011): 447–55. http://dx.doi.org/10.1142/s0218126611007384.

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In this paper, a grounded voltage controlled resistor (GVCR) employing eight CMOS transistors, all of which are operating in saturation region, is proposed. The developed GVCR has two identical control voltages in opposite sign for electronically changing the resistance value. The linearity of the current-voltage (I - V) characteristic of the proposed GVCR is not affected by the body effect of the transistors. Computer simulation results with SPICE program are given to exhibit the performance and effectiveness of the introduced GVCR.

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29

Kempf, P., R. Hadaway, and J. Kolk. "Complementary metal oxide semiconductor compatible high-voltage transistors." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 1003–8. http://dx.doi.org/10.1139/p87-161.

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The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.

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30

Li, Xiang, Rui Li, Chunge Ju, Bo Hou, Qi Wei, Bin Zhou, Zhiyong Chen, and Rong Zhang. "A Regulated Temperature-Insensitive High-Voltage Charge Pump in Standard CMOS Process for Micromachined Gyroscopes." Sensors 19, no. 19 (September 25, 2019): 4149. http://dx.doi.org/10.3390/s19194149.

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Micromachined gyroscopes require high voltage (HV) for actuation and detection to improve its precision, but the deviation of the HV caused by temperature fluctuations will degrade the sensor’s performance. In this paper, a high-voltage temperature-insensitive charge pump is proposed. Without adopting BCD (bipolar-CMOS-DMOS) technology, the output voltage can be boosted over the breakdown voltage of n-well/substrate diode using triple-well NMOS (n-type metal-oxide-semiconductor) transistors. By controlling the pumping clock’s amplitude continuously, closed-loop regulation is realized to reduce the output voltage’s sensitivity to temperature changes. Besides, the output level is programmable linearly in a large range by changing the reference voltage. The whole circuit has been fabricated in a 0.18- μ m standard CMOS (complementary metal-oxide-semiconductor) process with a total area of 2.53 mm 2 . Measurements indicate that its output voltage has a linear adjustable range from around 13 V to 16.95 V, and temperature tests show that the maximum variations of the output voltage at − 40 ∼ 80 ∘ C are less than 1.1%.

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Li, Lin An, Ming Tang, Wen Ou, and Yang Hong. "An All CMOS Current Reference." Applied Mechanics and Materials 135-136 (October 2011): 192–97. http://dx.doi.org/10.4028/www.scientific.net/amm.135-136.192.

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In this paper, an all CMOS current reference circuit which generates a reference current independent of PVT (Process, supply Voltage, and Temperature) variations is presented. The circuit consists of a self-biased current source (SBCS) and two nested connected transistors which supply a voltage with positive temperature coefficient and the resulting reference circuit has low temperature coefficient. It is based on CSMC 0.5um mixed-signal process with the supply voltage of 5V. The precision of reference current is about ±3.05% when considering the process, supply voltage and temperature variation at the same time.

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Schmitz, A., and R. Tielert. "A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies." Advances in Radio Science 3 (May 13, 2005): 355–58. http://dx.doi.org/10.5194/ars-3-355-2005.

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Abstract. Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

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Ishida, Yosuke, and Toru Tanzawa. "A Fully Integrated AC-DC Converter in 1 V CMOS for Electrostatic Vibration Energy Transducer with an Open Circuit Voltage of 10 V." Electronics 10, no. 10 (May 15, 2021): 1185. http://dx.doi.org/10.3390/electronics10101185.

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This paper proposes an AC-DC converter for electrostatic vibration energy harvesting. The converter is composed of a CMOS full bridge rectifier and a CMOS shunt regulator. Even with 1 V CMOS, the open circuit voltage of the energy transducer can be as high as 10 V and beyond. Bandgap reference (BGR) inputs a regulated voltage, which is controlled by the output voltage of the BGR. Built-in power-on reset is introduced, which can minimize the silicon area and power to function normally found upon start-up. The AC-DC converter was fabricated with a 65 nm low-Vt 1 V CMOS with 0.081 mm2. 1 V regulation was measured successfully at 20–70 °C with a power conversion efficiency of 43%.

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Kim, Jae-Bung, and Seong-Ik Cho. "Modified Low-Votlage CMOS Bandgap Voltage Reference with CTAT Compensation." Transactions of The Korean Institute of Electrical Engineers 61, no. 5 (May 1, 2012): 753–56. http://dx.doi.org/10.5370/kiee.2012.61.5.753.

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Barteselli, Edoardo, Luca Sant, Richard Gaggl, and Andrea Baschirotto. "Design Techniques for Low-Power and Low-Voltage Bandgaps." Electricity 2, no. 3 (July 26, 2021): 271–84. http://dx.doi.org/10.3390/electricity2030016.

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Reverse bandgaps generate PVT-independent reference voltages by means of the sums of pairs of currents over individual matched resistors: one (CTAT) current is proportional to VEB; the other one (PTAT) is proportional to VT (Thermal voltage). Design guidelines and techniques for a CMOS low-power reverse bandgap reference are presented and discussed in this paper. The paper explains firstly how to design the components of the bandgap branches to minimize circuit current. Secondly, error amplifier topologies are studied in order to reveal the best one, depending on the operation conditions. Finally, a low-voltage bandgap in 65 nm CMOS with 5 ppm/°C, with a DC PSR of −91 dB, with power consumption of 5.2 μW and with an area of 0.0352 mm2 developed with these techniques is presented.

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Singhal, Sonal, Rohit Singh, and Amit Kumar Singh. "Design of a Sub-0.4 V Reference Circuit in 0.18μm CMOS Technology." Advanced Materials Research 816-817 (September 2013): 882–86. http://dx.doi.org/10.4028/www.scientific.net/amr.816-817.882.

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This paper proposes a low power voltage reference generator in 0.18μm CMOS technology.The circuit presented here includes MOSFETs in sub threshold mode and uses the temperature dependence of threshold voltages and sub-threshold current of MOSFET to form a temperature-insensitive reference. An input supply voltage of 1.8 Volt is used for the circuit generating a total current of 1.33μA. By varying the device temperature over the range of-20°C to 100°C corresponding variation over the output voltage was found to lie in the range 397.8 to 400.2 mV. Thus a 0.6% variation in voltage over the considered range of temperature is obtained.

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Campos, Fernando de Souza, Bruno Albuquerque de Castro, and Jacobus W. Swart. "A Tunable CMOS Image Sensor with High Fill-Factor for High Dynamic Range Applications." Engineering Proceedings 2, no. 1 (November 14, 2020): 79. http://dx.doi.org/10.3390/ecsa-7-08235.

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Several CMOS imager sensors were proposed to obtain high dynamic range imager (>100 dB). However, as drawback these imagers implement a large number of transistors per pixel resulting in a low fill factor, high power consumption and high complexity CMOS image sensors. In this work, a new operation mode for 3 T CMOS image sensors is presented for high dynamic range (HDR) applications. The operation mode consists of biasing the conventional reset transistor as active load to photodiode generating a reference current. The output voltage achieves a steady state when the photocurrent becomes equal to the reference current, similar to the inverter operation in the transition region. At a specific bias voltage, the output swings from o to Vdd in a small light intensity range; however, high dynamic range is achieve using multiple readout at different bias voltage. For high dynamic range operation different values of bias voltage can be applied from each one, and the signal can be captured to compose a high dynamic range image. Compared to other high dynamic range architectures this proposed CMOS image pixel show as advantage high fill-factor (3 T) and lower complexity. Moreover, as the CMOS pixel does not operate in integration mode, de readout can be performed at higher speed. A prototype was fabricated at 3.3 V 0.35 µm CMOS technology. Experimental results are shown by applying five different control voltage from 0.65 to 1.2 V is possible to obtain a dynamic range of about 100 dB.

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SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C TOW-THOMAS FILTER USING VOLTAGE OP AMP, CURRENT FEEDBACK OP AMP AND OPERATIONAL TRANSRESISTANCE AMPLIFIER." Journal of Circuits, Systems and Computers 18, no. 01 (February 2009): 151–79. http://dx.doi.org/10.1142/s0218126609004995.

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Several MOS-C realizations of the Tow-Thomas circuit using the commercially available voltage operational amplifier and the current feedback operational amplifier are reviewed in this paper. Additional MOS-C Tow-Thomas realizations using the operational transresistance amplifier and the differential current voltage conveyor are also included. MOS-C realizations of the Tow-Thomas circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS technology model from MOSIS are included together with detailed comparison tables to demonstrate the differences between MOS-C Tow-Thomas circuits using both of the commercially available active building blocks and CMOS integrated building blocks.

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Kocanda, Piotr, and Andrzej Kos. "Energy losses and DVFS effectiveness vs technology scaling." Microelectronics International 32, no. 3 (August 3, 2015): 158–63. http://dx.doi.org/10.1108/mi-01-2015-0008.

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Purpose – This article aims to present complete analysis of energy losses in complementary metal-oxide semiconductor (CMOS) circuits and the effectiveness of dynamic voltage and frequency scaling (DVFS) as a method of energy conservation in CMOS circuits in variety of technologies. Energy efficiency in CMOS devices is an issue of highest importance with still continuing technology scaling. There are powerful tools for energy conservation in form of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS). Design/methodology/approach – Using analytical equations and Spice models of various technologies, energy losses are calculated and effectiveness of DVS and DFS is evaluated for every technology. Findings – Test showed that new dedicated technology for low static energy consumption can be as economical as older technologies. The dynamic voltage and frequency scaling are most effective when there is a dominance of dynamic energy losses in circuit. In case when static energy losses are comparable to dynamic energy losses, use of dynamic voltage frequency scaling can even lead to increased energy consumption. Originality/value – This paper presents complete analysis of energy losses in CMOS circuits and effectiveness of mentioned methods of energy conservation in CMOS circuits in six different technologies.

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40

Machowski, Witold, Stanisław Kuta, Jacek Jasielski, and Wojciech Kołodziejski. "Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS Inverters." International Journal of Electronics and Telecommunications 56, no. 4 (November 1, 2010): 381–86. http://dx.doi.org/10.2478/v10177-010-0050-z.

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Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS InvertersThe paper presents quarter-square analog four-quadrant multipliers, based on proprietary architecture using four CMOS inverters. The most important upgrade on already published own circuit implementation is the use of the same inverter "core" of the circuit with completely redesigned auxiliary and steering blocks. Two variants of new driving peripherals are considered: one with differential pair, the second with CMOS inverters. The proposed circuit solutions are suitable for RF applications in communication systems due to simple architecture comprising building blocks with RF CMOS transistors having sufficiently large biasing currents. Postlayout simulation results done on the basis of 180nm CMOS UMC Foundry Design Kit are also presented.

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41

Shubin, V. V. "High-Speed CMOS Voltage Level Converter." Nano- i Mikrosistemnaya Tehnika 20, no. 11 (November 20, 2018): 695–703. http://dx.doi.org/10.17587/nmst.20.695-703.

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Peric, Ivan, Attilio Andreazza, Heiko Augustin, Marlon Barbero, Mathieu Benoit, Raimon Casanova, Felix Ehrler, et al. "High-Voltage CMOS Active Pixel Sensor." IEEE Journal of Solid-State Circuits 56, no. 8 (August 2021): 2488–502. http://dx.doi.org/10.1109/jssc.2021.3061760.

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Fujimoto, R., R. Tachibana, H. Yoshida, K. Kojima, and S. Otaka. "4.6 GHz CMOS voltage-controlled oscillator." Electronics Letters 38, no. 13 (2002): 632. http://dx.doi.org/10.1049/el:20020444.

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Meyer, W. G. "High Voltage CMOS: Devices and Application." ECS Proceedings Volumes 1987-13, no. 1 (January 1987): 60–67. http://dx.doi.org/10.1149/198713.0060pv.

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Siniscalchi, Mariana, Fernando Silveira, and Carlos Galup-Montoro. "Ultra-Low-Voltage CMOS Crystal Oscillators." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 6 (June 2020): 1846–56. http://dx.doi.org/10.1109/tcsi.2020.2971110.

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Lu, Liang-Hung, and Huan-Sheng Chen. "Lower the Voltage for CMOS RFIC." IEEE Microwave Magazine 11, no. 1 (February 2010): 70–77. http://dx.doi.org/10.1109/mmm.2009.935204.

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Olivera, Fabian, and Antonio Petraglia. "Adjustable Output CMOS Voltage Reference Design." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 10 (October 2020): 1690–94. http://dx.doi.org/10.1109/tcsii.2019.2943303.

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48

Nagaraj, K. "New CMOS floating voltage-controlled resistor." Electronics Letters 22, no. 12 (1986): 667. http://dx.doi.org/10.1049/el:19860456.

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Zhang, C., A. Srivastava, and P. K. Ajmera. "Low voltage CMOS Schmitt trigger circuits." Electronics Letters 39, no. 24 (2003): 1696. http://dx.doi.org/10.1049/el:20031131.

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Ferreira, J. V. T., and C. Galup‐Montoro. "Ultra‐low‐voltage CMOS ring oscillators." Electronics Letters 55, no. 9 (May 2019): 523–25. http://dx.doi.org/10.1049/el.2019.0281.

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