Dissertations / Theses on the topic 'CMOS VOLTAGE'
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Duncan, Martin Russell. "CMOS-compatible high-voltage transistors." Thesis, University of Edinburgh, 1994. http://hdl.handle.net/1842/12182.
Full textNg, Wing Lun. "Low-voltage high-frequency CMOS transformer-feedback voltage-controlled oscillators /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20NG.
Full textHolman, William Timothy. "A low noise CMOS voltage reference." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/14968.
Full textShabra, Ayman U. (Ayman Umar). "Ultra-low voltage CMOS operational amplifiers." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/29876.
Full textColombo, Dalton Martini. "Bandgap voltage references in submicrometer CMOS technology." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/16136.
Full textA Voltage Reference is a pivotal block in several mixed-signal and radio-frequency applications, for instance, data converters, PLL's and power converters. The most used CMOS implementation for voltage references is the Bandgap circuit due to its highpredictability, and low dependence of the supply voltage and temperature of operation. This work studies the Bandgap Voltage References (BGR). The most relevant and the traditional topologies usually employed to implement Bandgap Voltage References are investigated, and the limitations of these architectures are discussed. A survey is also presented, discussing the most relevant issues and performance metrics for BGR, including, high-accuracy, low-voltage and low-power operation, as well as the output noise of Bandgap References fabricated in submicrometer technologies. Moreover, a comprehensive investigation on the impact of fabrication process effects and noise on the reference voltage is presented. It is shown that output noise can limit the accuracy of the BGR and trim circuits. To support and develop our work, three BGR´s were designed using the IBM 0.18 Micron 7RF process with a supply voltage of 1.8 V. The layouts of these circuits were also designed to provide post-extracted layout information and electrical simulation results. This work provides a comprehensive discussion on the structure and design practices for Bandgap References.
Kim, Hyung-Seuk 1976. "Low voltage CMOS frequency synthesizers for RF applications." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=82607.
Full textNaude, Neil. "Differential current sensor linearisation in low-voltage CMOS." Diss., University of Pretoria, 2017. http://hdl.handle.net/2263/62785.
Full textDissertation (MEng)--University of Pretoria, 2017.
Electrical, Electronic and Computer Engineering
MEng
Unrestricted
Layton, Kent D. "Low-voltage analog CMOS architectures and design methods /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd2141.pdf.
Full textLayton, Kent Downing. "Low-Voltage Analog CMOS Architectures and Design Methods." BYU ScholarsArchive, 2007. https://scholarsarchive.byu.edu/etd/1218.
Full textBallan, Hussein Declercq Michel Declercq Michel Declercq Michel. "High voltage devices and circuits in standard CMOS technologies /." Dordrecht : Kluwer Academic Publishers, 1999. http://opac.nebis.ch/cgi-bin/showAbstract.pl?u20=079238234X.
Full textEken, Yalcin Alper. "High frequency voltage controlled ring oscillators in standard CMOS." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/8064.
Full textParker, Kevin. "An on-chip trimming technique for CMOS voltage references." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp04/mq20686.pdf.
Full textPark, Byeong-Ha. "A low-voltage, low-power, CMOS 900MHZ frequency synthesizer." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/16686.
Full textCaicedo, Jhon Alexander Gomez. "CMOS low-power threshold voltage monitors circuits and applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.
Full textA threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.
Eken, Yalçin Alper. "High frequency voltage controlled ring oscillators in standard CMOS." Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-06072004-131133/unrestricted/eken%5Fyalcin%5Fa%5F200405%5Fphd.pdf.
Full textMattia, Neto Oscar Elisio. "NanoWatt resistorless CMOS voltage references for Sub-1 V applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/107131.
Full textIntegrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.
Beck, Riley D. "High Voltage Analog Design in a Standard Digital CMOS Process." Diss., CLICK HERE for online access, 2005. http://contentdm.lib.byu.edu/ETD/image/etd1092.pdf.
Full textChunda, Jaime P. "Low voltage operational amplifier using parasitic bipolar transistors in CMOS." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA303882.
Full textWang, Yanbin. "Threshold voltage control by backgating in fully depleted SOI CMOS." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0007/MQ43350.pdf.
Full textHu, Yamu. "CMOS low-voltage preamplifier based on i/f noise cancellation." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ60898.pdf.
Full textBhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.
Full textNohra, George. "Low voltage CMOS LNA design." Thesis, 2005. http://spectrum.library.concordia.ca/8913/1/MR14276.pdf.
Full textXu, Deng-Tai, and 許登泰. "CMOS-compatible high-voltage MOSFETs." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/26534510776214840699.
Full textWang, Ru-Jie, and 王銣傑. "CMOS Voltage References without Resistors." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/77139533456387300631.
Full text輔仁大學
電子工程學系
95
This work presents two CMOS voltage references without resistors. The first one is a curvature-compensated bandgap reference without resistors in 0.18-μm CMOS technology. The circuit uses a new current generator circuit for higher order temperature terms curvature compensation and a PMOS voltage divider for scaling down the reference voltage. A 605.6mV output voltage is generated with a temperature coefficient of 1 ppm/°C from –40 to 125 °C. It dissipates 77μW at a supply voltage of 1.8-V. The second one is a low-voltage low-power bandgap voltage reference without using passive components. A reference voltage of 646.4 mV is generated with a temperature coefficient of 1.7 ppm/°C in the range [−40, +125] °C at 1.8-V supply voltage. A line sensitivity of 0.18 mV/V in the supply voltage range [+1, +1.8] V are achieved. It dissipates a maximum power of 4.9 μW at a 1.8-V supply voltage and 125 °C. The silicon area is as small as 100 × 50 μm2 in 0.18um CMOS process.
Cheng, Yu-Sung, and 鄭育松. "CMOS Integrated Buck Voltage Converter." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/85998319352058519420.
Full text龍華科技大學
電子工程研究所
98
In this thesis, a series of DC voltage regulators, such as Bandgap reference (BGR), Low dropout regulator (LDO) and DC-DC Buck Converter are developed. The BGR circuit is a low sensitivity to temperature and supply voltage. To increase the performances, an nMOS arrangement folded operational transconductance amplifier is developed for the BGR circuit. In addition, a small size, low cost and low ripple output voltage LDO regulator is introduced. Finally, in order to increase operating time of the battery powered devices, a high efficiency, high noise rejection Buck DC-DC Converter is also introduced. The LDO circuit consists of an error amplifier, buffer and feedback circuit, while the DC-DC Buck Converter circuit is composed of a frequency compensation circuit, PWM control circuit, non-overlapping circuit and pMOS power transistor. In the power converter, the PWM circuit included a ramp generator, a clock generator, a comparator, a clock generator and a flip-flop circuit. The clock generator provided a fixed frequency for the PWM controlled circuit. This PWM circuit generates a fixed-frequency and has a wide range controlled duty. In this thesis, the proposed circuit, had simulated with TSMC 0.35μm 2P4M models, and had implemented with TSMC 0.35μm 2P4M process. The measurement results show that the output voltage of the LDO and DC-DC Buck Converter Operating voltage are ranging 2V to 5V and the output voltage is 1.8V. The maximum efficiency of DC converter is over 90 %.
KRISHNA, KUMMARAPALLI KOMALA. "ADAPTIVELY BIASED CMOS VOLTAGE FOLLOWER." Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/15208.
Full textChen, Shih-Lun, and 陳世倫. "High-Voltage Circuit Design in Low-Voltage CMOS Processes." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/70309962398742844556.
Full text國立交通大學
電子工程系所
94
The scaling trend of the CMOS technology is toward the nanometer region to increase the speed and density of the transistors in integrated circuits. Due to the reliability issue, the power supply voltage is also decreased with the advanced technologies. However, in an electronic system, some circuits could be still operated at high voltage levels. If the circuits realized with low-voltage devices are operated at high voltage levels, the gate-oxide breakdown, hot-carrier degradation, leakage issues, and so on will occur. Therefore, designing the high-voltage circuits in low-voltage CMOS processes is an important topic in today and future VLSI (very large scale integration) design. In this dissertation, several circuits designed in low-voltage CMOS processes but operated in high-voltage environments are presented. There are seven chapters included in this dissertation. Two new mixed-voltage I/O buffers realized with low-voltage devices are presented in Chapter 2 to prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the conventional CMOS I/O buffer. These two new mixed-voltage I/O buffer have novel gate-tracking circuits and dynamic n-well bias circuits. Compared with the prior designs of mixed-voltage I/O buffers, these two new mixed-voltage I/O buffers occupy smaller silicon area. Besides, the new proposed mixed-voltage I/O buffer 2 can be applied for high-speed applications without the gate-oxide reliability problem and the circuit leakage issue. The new proposed mixed-voltage I/O buffers realized with 1×VDD devices can be easily applied in 1×VDD/2×VDD mixed-voltage interface. Due to the high-integration trend of SOC (system-on-a-chip), an electronic system may be integrated into a single chip. Hence, there are digital circuits and analog circuits integrated in a single chip. For example, the digital part of the SOC is designed with 1-V devices to decrease its power consumption, the analog part is designed with 2.5-V devices to improve the circuit performance, and the chip-to-chip interface is 3.3-V PCI-X in a 0.13-µm 1/2.5-V CMOS process. Thus, the traditional I/O circuits are not suitable for this application. An input buffer with the proposed Schmitt trigger circuit and an output buffer with the proposed level converter in a 0.13-µm 1/2.5-V CMOS process are presented in Chapter 3 for 3.3-V applications. An NMOS-blocking technique for mixed-voltage I/O buffer design is presented in Chapter 4. Unlike the traditional mixed-voltage I/O buffer design, the mixed-voltage I/O buffer realized with only 1×VDD devices by using the NMOS-blocking technique can receive 2×VDD, 3×VDD, and even 4×VDD input signals without the gate-oxide reliability issue. In this dissertation, the 2×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been verified in a 0.25-μm 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been verified in a 0.13-μm 1-V CMOS process to serve 1/3-V mixed-voltage interface. The NMOS-blocking technique can be extended to design the 4×VDD, 5×VDD, and even 6×VDD input tolerant mixed-voltage I/O buffers. The limitation of the NMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process. A new charge pump circuit without the gate-oxide overstress is presented in Chapter 5. Because the charge transfer switches of the new proposed charge pump circuit can be fully turned on and turned off, as well as the output stage doesn’t have the threshold drop problem, its pumping efficiency is higher than that of the prior designs. The gate-drain and the gate-source voltages of all devices in the new charge pump circuit don’t exceed VDD, so the new charge pump circuit doesn’t suffer the gate-oxide reliability problem. Besides, the proposed charge pump circuit has two pumping branches pumping the output node alternately so the output voltage ripple is small. The proposed circuit is suitable in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices. In general, the output voltage of the charge pump circuit will be limited by the breakdown voltage of the parasitic pn-junction in the given CMOS process. Chapter 6 presents an on-chip ultra-high-voltage charge pump circuit designed with the polysilicon diodes in low-voltage standard CMOS processes. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of parasitic pn-junction. The polysilicon diodes can be implemented in the standard (bulk) CMOS processes without extra process steps. The proposed charge pump circuit designed with the polysilicon diodes has been fabricated and verified in a 2.5-V 0.25-µm bulk CMOS process. In summary, several circuits designed in low-voltage CMOS processes but operated in high-voltage environments are presented in this dissertation. The proposed circuits have been implemented and verified in silicon chips. The proposed circuits are very useful and cost-efficient for the advanced SOC applications.
Ren, Jie. "Design of Low-Voltage Wide Tuning Range CMOS Multipass Voltage-Controlled Ring Oscillator." 2011. http://hdl.handle.net/10222/13341.
Full textChien, Mao-Chuan, and 簡茂全. "A CMOS High-speed Voltage Comparator." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/ub99h5.
Full text逢甲大學
電機工程所
90
This thesis presents a design of an innovational high-speed CMOS voltage comparator. The comparator proposed in this thesis uses a p-type differential pair as input stage to provide more gains which differs from using an n-type differential pair. Furthermore, the comparator makes use of a self-biasing circuit to provide a stable 3.5 V output voltage. This output voltage is not affected by the variations of temperature or supplies. By utilizing the designed circuit, high-speed can be achieved. The designed comparator is fabricated by UMC 0.5mm double-poly, triple-metal, N-well CMOS process. The comparator can achieve less propagation delay time (36 ns), fast response time (41 ns), hysteresis voltage between 5 mV and 11 mV, and low power dissipation (4 mW).
Cheng, Chih-Yen, and 鄭志彥. "2.4GHz, Low Voltage CMOS Downconversion Mixer." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/90289325598420371077.
Full text逢甲大學
電子工程所
92
The purpose of the thesis is to design a 2.4GHz low voltage CMOS downconversion mixer. The circuit is designed based on traditional Gilbert Cell structure, such that it can be operated in 0.7V. In low voltage circuit design, conversion gain is often very low, so how to get high gain in low voltage is key point in this work. There are three parts in circuit topology:V-I Converter, Core Gilbert Cell circuit and Negative circuit. The purpose of V-I Converter is to get high Iout/Vin value. We use PMOS common drain amplifier as V-I Converter to replace previous literature’s circuit structure. Core Gilbert Cell circuit use an inductor to replace a current source, so the number of cascade is only one, and it can be operated in 0.7V. In order to improve the conversion gain, we use negative resistor to parallel the load resistor in Core Gilbert Cell circuit. From the simulation results, the proposed circuit has good performance, as compared to that of recent literatures (work in 0.9V~1.2V). Not only the operation frequency is increased but also the supply voltage can be operated in 0.7V. Other performance are described as the following: P1dB 6.987dBm, Conversion gain -10.537dBm, IIP3 24dBm and power consumption is 2.94mW.
"Giga-hertz CMOS voltage controlled oscillators." 2001. http://library.cuhk.edu.hk/record=b5890786.
Full textThesis (M.Phil.)--Chinese University of Hong Kong, 2001.
Includes bibliographical references (leaves 131-154).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iii
Table of Contents --- p.iv
List of Figures --- p.ix
List of Tables --- p.xv
Chapter Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Overview --- p.1
Chapter 1.2 --- Objectives --- p.2
Chapter 1.3 --- Thesis Organization --- p.4
Chapter Chapter 2 --- Fundamentals of Voltage Controlled Oscillators --- p.6
Chapter 2.1 --- Definition of Commonly Used Figures of Merit --- p.6
Chapter 2.1.1 --- Cutoff frequency --- p.6
Chapter 2.1.2 --- Center Frequency --- p.8
Chapter 2.1.3 --- Tuning Range --- p.8
Chapter 2.1.4 --- Tuning Sensitivity --- p.8
Chapter 2.1.5 --- Output Power --- p.8
Chapter 2.1.6 --- Power Consumption --- p.9
Chapter 2.1.7 --- Supply Pulling --- p.9
Chapter 2.2 --- Phase Noise --- p.9
Chapter 2.2.1 --- Definition of Phase Noise --- p.9
Chapter 2.2.2 --- Phase Noise Specification --- p.11
Chapter 2.2.3 --- Leeson's formula --- p.12
Chapter 2.2.4 --- Models developed by J. Cranincks and M. Steyaert10 --- p.13
Chapter 2.2.5 --- Linear Time-Variant Phase Noise Model --- p.13
Chapter 2.3 --- Building Blocks of Voltage Controlled Oscillators --- p.17
Chapter 2.3.1 --- FETs --- p.17
Chapter 2.3.2 --- Varactor --- p.18
Chapter 2.3.3 --- Spiral Inductor --- p.21
Chapter 2.3.4 --- Modeling of the Spiral Inductor --- p.24
Chapter 2.3.5 --- Analysis and Simulation --- p.26
Chapter Chapter 3 --- Digital Controlled Oscillator --- p.28
Chapter 3.1 --- Introduction --- p.28
Chapter 3.2 --- General Principle of Oscillation --- p.28
Chapter 3.3 --- Different Oscillator Architectures --- p.30
Chapter 3.3.1 --- Single-ended Ring Oscillator --- p.30
Chapter 3.3.2 --- Differential Ring Oscillator --- p.32
Chapter 3.3.3 --- CMOS Injection-locked Oscillator --- p.33
Chapter 3.4 --- Basic Principle of the Injection-locked Oscillator --- p.34
Chapter 3.5 --- Digital Controlled Oscillator --- p.36
Chapter 3.5.1 --- R-2R Digital-to-Analog Converter --- p.37
Chapter 3.6 --- Injection Locking --- p.42
Chapter 3.6.1 --- Synchronization Model of the Injection Locked Oscillator --- p.42
Chapter 3.7 --- Simulation Results --- p.44
Chapter 3.7.1 --- Frequency Tuning Characteristics --- p.44
Chapter 3.7.2 --- Phase Noise Performance --- p.47
Chapter 3.7.3 --- Locking Characteristics --- p.48
Chapter 3.7.4 --- Sensitivity to Supply Voltage and Temperature --- p.48
Chapter 3.8 --- Conclusion --- p.49
Chapter Chapter 4 --- CMOS LC Voltage Controlled Oscillator --- p.51
Chapter 4.1 --- Introduction --- p.51
Chapter 4.2 --- LC Oscillator --- p.52
Chapter 4.3 --- Circuit Design --- p.54
Chapter 4.3.1 --- Oscillation Frequency --- p.55
Chapter 4.3.2 --- Oscillation Amplitude --- p.58
Chapter 4.3.3 --- Transistor Sizing --- p.59
Chapter 4.3.4 --- Power Consumption --- p.62
Chapter 4.3.5 --- Tuning Range --- p.62
Chapter 4.3.6 --- Phase Noise Analysis --- p.63
Chapter 4.4 --- Conclusion --- p.70
Chapter Chapter 5 --- LC Quadrature Voltage Controlled Oscillator --- p.71
Chapter 5.1 --- Introduction --- p.71
Chapter 5.2 --- Conventional CMOS Quadrature LC Voltage Controlled Oscillator --- p.73
Chapter 5.3 --- Operational Principle of the CMOS Quadrature LC Voltage Controlled Oscillator --- p.74
Chapter 5.3.1 --- General Explanation --- p.74
Chapter 5.3.2 --- Mathematical Analysis --- p.75
Chapter 5.3.3 --- Drawback of the Conventional CMOS LC Quadrature VCO --- p.77
Chapter 5.4 --- Novel CMOS Low Noise Quadrature Voltage Controlled Oscillator --- p.78
Chapter 5.4.1 --- Equivalent Output Noise due to the Coupling Transistor --- p.80
Chapter 5.4.2 --- Linear Time Varying Model for the Analysis of Total Phase Noise --- p.83
Chapter 5.4.3 --- Tuning Range --- p.94
Chapter 5.4.4 --- Start-up Condition --- p.95
Chapter 5.4.5 --- Power Consumption --- p.97
Chapter 5.5 --- New Tuning Mechanism of the Proposed LC Quadrature VCO --- p.98
Chapter 5.6 --- Modified Version of the Proposed LC Quadrature Voltage Controlled Oscillator --- p.105
Chapter 5.7 --- Conclusion --- p.108
Chapter Chapter 6 --- Layout Consideration --- p.109
Chapter 6.1 --- Substrate Contacts --- p.109
Chapter 6.2 --- Guard Rings --- p.110
Chapter 6.3 --- Thermal Noise of the Gate Interconnect --- p.111
Chapter 6.4 --- Use of Different Layers of Metal for Interconnection --- p.112
Chapter 6.5 --- Slicing of Transistors --- p.113
Chapter 6.6 --- Width of Interconnecting Wires and Numbers of Vias --- p.114
Chapter 6.7 --- Matching of Devices --- p.114
Chapter 6.8 --- Die Micrographs of the Prototypes of the Oscillators --- p.115
Chapter Chapter 7 --- Experimental Results --- p.118
Chapter 7.1 --- Methodology --- p.118
Chapter 7.2 --- Evaluation Board --- p.119
Chapter 7.3 --- Measurement Setup --- p.123
Chapter 7.4 --- Experimental Results --- p.125
Chapter 7.4.1 --- CMOS Injection Locked Oscillator --- p.125
Chapter 7.4.2 --- LC Differential Voltage Controlled Oscillator --- p.128
Chapter 7.4.3 --- LC Quadrature Voltage Controlled Oscillator --- p.132
Chapter 7.5 --- Summary of Performance --- p.139
Chapter Chapter 8 --- Conclusion --- p.142
Chapter 8.1 --- Contribution --- p.142
Chapter 8.2 --- Further Development --- p.143
Chapter Chapter 9 --- Appendix --- p.145
Chapter 9.1 --- Circuit Transformation --- p.145
Chapter 9.2 --- Derivation of the Inductor Model with PGS --- p.146
Chapter 9.2.1 --- "Inductance," --- p.146
Chapter 9.2.2 --- "Series Resistance, Rs" --- p.146
Chapter 9.2.3 --- Series Capacitance --- p.147
Chapter 9.2.4 --- Shunt Oxide Capacitance --- p.147
Chapter 9.3 --- Calculation of Phase Noise Using the Linear Time Variant Model --- p.148
Chapter Chapter 10 --- Bibliography --- p.151
Sun, Fu-Tsun, and 孫福村. "CMOS Low-Voltage Dual-Band Mixer." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/56173793573324828410.
Full text國立成功大學
電機工程學系
89
Abstract Mixer has been widely used in many communication systems, especially in superheterodyne architecture. In modern communication systems, however, dual-band systems are popular, because mobile telephones are highly available and the consumers require good communication quality. The purpose of this thesis is to investigate a mixer working at dual-band frequency. The concept is to improve original Gilbert mixer for low-voltage supply. By using dual-band frequency resonators, both bands can be mixed, and just use one mixer circuit. The proposed mixer is fabricated with TSMC 0.35 um sp/4m process. The Chip die size is about 3*3 mm2. When testing, RF signal is swept from 0.5 GHz to 2.2 GHz in 100 MHz step. The LO frequency is varied with RF frequency so the IF is fired at 100 MHz.
Chiang, Tzung-Yin, and 江宗殷. "Temperature-compensated CMOS voltage reference circuit." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/07003708814603618036.
Full text國立清華大學
工程與系統科學系
93
Reference circuits have been studying for many years. Following the vigorous development of portable electronic products, integrated circuits with low voltage and small area have become the core part of the recent research. Parasitic vertical bipolar junction transistors are commonly used in CMOS voltage reference circuits for a better stability. Recently, MOS reference circuits have been used to replace BJT ones in order to reduce the chip area and supply voltage. Whether BJT or MOS is utilized, the problem that resistances parallelizing on either side of BJT or MOS generally occupy quite large ratio of chip area under the consideration of power consumption and loading parasitic capacitances of op-amp still exists. Another problem worthy of our concern is that spurious signals coming from the supply voltage cannot be adequately rejected and may couple into the circuit to degrade output signal in high frequency applications. This thesis aims to improve the above problems and proposes a novel voltage reference circuit. A current mirror is designed for temperature compensation and large resistors are defeasible for reduction chip area. Besides, it has been implemented by a 0.18 μm CMOS process with a chip area of 0.023 mm2. Simulation shows that the variation of temperature coefficient is from 59.5 to 63.8 ppm/℃ under the temperature range from -40 to 100 ℃ and a supply voltage variation from 1.2 to 1.98 V. The power noise rejection ratio is -70 dB at 10 kHz with 1.2V supply voltage. In summary, the thesis adopts a current mirror to achieve low-temperature-drift reference voltage and abandons large resistances on design consideration. With this approach, power noise rejection ration is reduced.
Liu, Zhiyu. "Multi-voltage nanoscale CMOS circuit techniques." 2008. http://www.library.wisc.edu/databases/connect/dissertations.html.
Full textLiao, Jia-Zheng, and 廖家正. "Design of A CMOS Reference Voltage." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/3h6nk8.
Full text國立虎尾科技大學
電子工程系碩士班
101
In this thesis, a CMOS differential-mode reference voltage circuit has been proposed. By properly using the positive and negative temperature coefficient parameters, a zero temperature-coefficient can be achieved. The proposed circuits are based on the traditional bandgap voltage reference circuit architecture with an additional current mirror and a proportional-to-absolute-temperature current source which is composed of current mirrors. As compared with the existed differential-mode reference voltage circuit, the proposed circuit does not need an operational amplifier, therefore it benefits from simpler circuit architecture, less chip area, and less power consumption. Besides the detailed design principle, the HSPICE and LAKER simulation program with 0.35-um and 0.18-um process parameters have been used to perform the pre-layout and post-layout simulation. According to the post-layout simulation results, as the supply voltages is 3.3V, the differential-mode output voltage reference circuit shows that, as the temperature varies from -20oC to 120oC, the corresponding output voltage changes only 1.3mV(0.225%), the corresponding power dissipation is 2.354mW and the temperature-coefficient is 16.11 ppm/˚C. In addition, if a transistor and a resistor are removed from the proposed differential-mode output voltage reference circuit, a single-ended mode reference voltage with zero temperature coefficient can be obtained. According to the post-layout simulation results, when the supply voltages is 2.8V, and as the temperature varies from -20oC to 120oC, the corresponding output voltage changes only 2.01mV(0.387%), the corresponding power dissipation is 1.412mW and the temperature-coefficient is 27.79 ppm/˚C. All the simulation results are consistent with the theoretic analysis. The proposed circuits can be applied to different analog circuits.
Lee, Chia-Yu, and 李佳祐. "A Low-Voltage Low-Temperature-Coefficient CMOS Bandgap Voltage Reference Generator." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/60462464118919911604.
Full text國立臺灣大學
電子工程學研究所
94
Voltage references play an important role in modern integrated circuits systems. They are widely apdopted in many integrated circuits, such as A/D or D/A converters, power-management system, operational amplifiers, and linear regulators. They are used for defining input/output voltage range, baising current source of differential pairs, and providing a comparison reference for comparators. A precision voltage reference must be, inherently, well-defined and insensitive to temperature, power supply and load variations. The objective of this thesis is to design a bandgap voltage reference with input voltage 1.8V to 3.3V and output voltage around 1.2V. The bandgap voltage reference is intended for using in low dropout linear regulators (LDO). In order to reduce the supply voltage, the voltage reference is using low voltage operational amplifers in place of using conservative cascade current mirror. In addition, this thesis designs a 1-V bandgap voltage reference with temperature compensation to suit the current of low supply voltage. During design and analysis stages, the HSPICE is used for the simulation, modification and verification of the circuit.
Chang, Wei-Jen, and 張瑋仁. "High-Voltage-Tolerant ESD Protection Design in Low-Voltage CMOS Processes." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/70232955293959803259.
Full text國立交通大學
電子工程系所
96
The scaling trend of the CMOS technology is toward the nanometer region to increase the speed and density of the transistors in integrated circuits. Due to the reliability issue, the power supply voltage is also decreased with the advanced technologies. However, in an electronic system, some circuits could be still operated at high voltage levels. If the circuits realized with low-voltage devices are operated at high voltage levels, the gate-oxide breakdown and leakage issues will occur. Therefore, for the CMOS integrated circuits (ICs) with the mixed-voltage I/O interfaces, the on-chip electrostatic discharge (ESD) protection circuits will meet more design constraints and difficulties. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths during normal circuit operating operation. During ESD stress condition, the on-chip ESD protection circuit should provide effective ESD protection for the internal circuits. In high-voltage CMOS technology, high-voltage transistors have been widely used for display driver ICs, power supplies, power management, and automotive electronics. The high-voltage MOSFET was often used as the ESD protection device in the high-voltage CMOS ICs, because it can work as both of output driver and ESD protection device simultaneously. With an ultra-high operating voltage, the ESD robustness of high-voltage MOSFET is quite weaker than that of low-voltage MOSFET. Hence, how to improve the ESD robustness of HV NMOS with a reasonable silicon area is indeed an important reliability issue in HV CMOS technology. In this thesis, some new ESD protection structures are proposed to improve ESD robustness of the high-voltage IC products fabricated in CMOS technology. To protect the mixed-voltage I/O interfaces for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS), ESD protection design with the low-voltage-triggered PNP (LVTPNP) device in CMOS technology is proposed. The LVTPNP is realized by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the PNP device. The LVTPNP devices with different structures have been investigated and compared in CMOS processes. The experimental results in a 0.35-um CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device. Furthermore, layout on LVTPNP device for ESD protection in mixed-voltage I/O interfaces is also optimized in this work. The experimental results verified in both 0.35-um and 0.25-um CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the single finger layout style. Moreover, one of the LVTPNP devices drawn with the multi-finger layout style has been used to successfully protect the input stage of an ADSL IC in a 0.25-um salicided CMOS process. To increase the system-on-chip ESD immunity of micro-electronic products against system-level ESD stress, the chip-level ESD/EMC protection design should be enhanced. Considering gate-oxide reliability, a new ESD protection scheme with ESD_BUS and high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed in this chapter. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage NMOS/PMOS devices which can be safely operated under the 2.5 V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (PS, NS, PD, and ND) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13 um CMOS process have confirmed that the proposed new ESD protection scheme has high human-body-model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low-voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces. To greatly improve ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications, a new electrostatic discharge protection structure of high-voltage P-type silicon controlled rectifier (HVPSCR) embedded into the high-voltage PMOS device is proposed. By only adding the additional N+ diffusion into the drain region of high-voltage PMOS, the TLP-measured secondary breakdown current (It2) of output driver has been greatly improved greater than 6A in a 0.5-µm high-voltage CMOS process. Such ESD-enhanced VFD driver IC, which can sustain HBM ESD stress of up to 8kV, has been in mass production for automotive applications in car without latchup problem. Moreover, with device widths of 500um, 600um, and 800um, the MM ESD levels of the HVPSCR are as high as 1100V, 1300V, and 1900V, respectively. The dependences of drift implant and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the HV MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased. It was also demonstrated that a specific test structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the excellent TLP-measured It2 and ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the dependences of the TLP-measured It2 and HBM ESD levels on the spacing from the drain diffusion to polygate are different. In this thesis, the novel ESD protection circuits have been developed for mixed-voltage I/O interfaces and high-voltage CMOS process with high ESD robustness. Each of the ESD protection circuits has been successfully verified in the testchips.
吳榮田. "Standard CMOS Low Operating Voltage Linear Type Bandgap Reference Voltage Generator." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/35770322350884476361.
Full text國立臺灣大學
電機工程學研究所
90
For many modern analog circuits, it is very important to generate a power supply voltage and temperature independent reference voltage to improve the performance of circuits such as accuracy, reliability, yield rate and so on. In the past the linear type CMOS bandgap reference voltage generator was chosen as a reliable reference voltage source for many years because of its working very well. But the traditional linear type CMOS bandgap reference voltage generator cannot work properly when the power supply voltage is lower than 2V. Due to the progress of CMOS process and the application of ICs, the power supply voltage of many ICs has to be reduced less than 2V in the future. A novel architecture of current summation type linear CMOS bandgap reference voltage generator is proposed here to afford a reliable bandgap reference voltage generating circuit that can operate at 1.3V power supply perfectly.
Wu, Ming-Shian, and 吳明憲. "A Linear CMOS Voltage to Current Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/42037852180078379348.
Full text國立雲林科技大學
電子與資訊工程研究所
93
An improved CMOS voltage-to-current converter is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting of the proposed converter to avoid the body effect. To accurately annihilate the non-linear voltage terms, a better modeling of the drain-to-source current of the MOS transistor operating in the linear region is essential and is adopted. Specifically the substrate-bias effect of the MOS transistor is treated more thoroughly in our design. Consequently, the non-linearity of the large-signal transresistance of the converter, caused mainly by the body effect of a NMOS transistor in a previously published converter, is greatly minimized. In order to compensate the resultant voltage inversion created by the switching from NMOS transistors to PMOS transistors in the resistor-replacement and voltage-level shifting in the proposed circuit, a voltage-inversion sub-circuit is devised and employed in our converter. The voltage-to-current converter is designed and fabricated in a 0.35μm CMOS technology. The fabricated circuit occupies an area of 267μm×197μm(~0.053mm2) and dissipates less than 3.92mW from a 3.3 V supply. The measured and simulated data are in good agreement. For a 1 input voltage, the total harmonic distortion (THD) of the output current is less than 1.5%.
"A low voltage 900 MHz CMOS mixer." 2001. http://library.cuhk.edu.hk/record=b5890834.
Full textThesis (M.Phil.)--Chinese University of Hong Kong, 2001.
Includes bibliographical references (leaves 108-111).
Abstracts in English and Chinese.
Abstract --- p.i
摘要 --- p.iii
Acknowledgments --- p.v
Contents --- p.vii
List of Tables --- p.xiii
List of Figures --- p.xiv
Chapter Chapter1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Technical Challenges of CMOS RF Design --- p.2
Chapter 1.3 --- General Background --- p.2
Chapter 1.3.1 --- Bipolar and CMOS Mixers --- p.4
Chapter 1.4 --- Research Goal --- p.4
Chapter 1.5 --- Thesis Outline --- p.5
Chapter Chapter2 --- RF Fundamentals --- p.6
Chapter 2.1 --- Introduction --- p.6
Chapter 2.2 --- Frequency Translation --- p.6
Chapter 2.3 --- Conversion Gain --- p.8
Chapter 2.4 --- Linearity --- p.8
Chapter 2.4.1 --- 1-dB Compression Point --- p.11
Chapter 2.4.2 --- Third Intercept Point (IP3) --- p.11
Chapter 2.5 --- Dynamic Range (DR) --- p.13
Chapter 2.5.1 --- Spurious-Free Dynamic Range (SFDR) --- p.13
Chapter 2.5.2 --- Blocking Dynamic Range (BDR) --- p.14
Chapter 2.6 --- Blocking and Desensitization --- p.15
Chapter 2.7 --- Port-to-Port Isolation --- p.15
Chapter 2.8 --- Single-Balanced and Double-Balanced Mixers --- p.16
Chapter 2.9 --- Noise --- p.16
Chapter 2.9.1 --- Noise in the Local Oscillator --- p.17
Chapter 2.9.2 --- Noise Figure --- p.18
Chapter Chapter3 --- Downconversion Mixer --- p.19
Chapter 3.1 --- Introduction --- p.19
Chapter 3.2 --- Review of Mixer Topology --- p.19
Chapter 3.2.1 --- Square-Law Mixer --- p.20
Chapter 3.2.2 --- CMOS Gilbert Cell --- p.21
Chapter 3.2.3 --- Potentiometric Mixer --- p.22
Chapter 3.2.4 --- Subsampling Mixer --- p.23
Chapter Chapter4 --- Proposed Downconversion Mixer --- p.24
Chapter 4.1 --- Analysis of Proposal Mixer --- p.24
Chapter 4.2 --- Current Folded Mirror Mixer --- p.24
Chapter 4.2.1 --- Operating Principle --- p.25
Chapter 4.2.2 --- Large Signal Analysis --- p.26
Chapter 4.2.3 --- Small Signal Analysis --- p.29
Chapter 4.3 --- Current Mode Mixer --- p.32
Chapter 4.3.1 --- Operating Principle --- p.33
Chapter 4.3.2 --- Large Signal Analysis --- p.33
Chapter 4.3.3 --- Small Signal Analysis --- p.34
Chapter 4.3.4 --- V-I Converter --- p.36
Chapter 4.3.4.1 --- Equation Analysis --- p.37
Chapter 4.4 --- Second Order Effects --- p.38
Chapter 4.4.1 --- Device Mismatch --- p.38
Chapter 4.4.2 --- Body Effect --- p.39
Chapter 4.5 --- Single-ended to Differential-ended converter --- p.39
Chapter 4.6 --- Output Buffer Stage --- p.40
Chapter 4.7 --- Noise Theory --- p.41
Chapter 4.7.1 --- SSB and DSB Noise Figure --- p.42
Chapter 4.7.2 --- Noise Figure --- p.43
Chapter Chapter5 --- Simulation Results --- p.44
Chapter 5.1 --- Introduction --- p.44
Chapter 5.2 --- Current Folded Mirror Mixer --- p.44
Chapter 5.2.1 --- Conversion Gain --- p.45
Chapter 5.2.2 --- Linearity --- p.46
Chapter 5.2.2.1 --- 1dB Compression Point and IIP3 --- p.49
Chapter 5.2.3 --- Output Buffer Stage --- p.49
Chapter 5.3 --- Current Mode Mixer --- p.51
Chapter 5.3.1 --- Conversion Gain --- p.51
Chapter 5.3.2 --- Linearity --- p.52
Chapter 5.3.2.1 --- 1-dB Compression Point and IIP3 --- p.52
Chapter 5.3.3 --- Output Buffer Stage --- p.53
Chapter 5.3.4 --- V-I Converter --- p.54
Chapter 5.4 --- Single-ended to Differential-ended Converter --- p.55
Chapter Chapter6 --- Layout Consideration --- p.57
Chapter 6.1 --- Introduction --- p.57
Chapter 6.2 --- CMOS transistor Layout --- p.57
Chapter 6.3 --- Resistor Layout --- p.59
Chapter 6.4 --- Capacitor Layout --- p.60
Chapter 6.5 --- Substrate Tap --- p.62
Chapter 6.6 --- Pad Layout --- p.63
Chapter 6.7 --- Analog Cell Layout --- p.64
Chapter Chapter7 --- Measurements --- p.65
Chapter 7.1 --- Introduction --- p.65
Chapter 7.2 --- Downconversion mixer --- p.66
Chapter 7.3 --- PCB Layout --- p.66
Chapter 7.4 --- Test Setups --- p.68
Chapter 7.4.1 --- Measurement Setup for S-Parameter --- p.68
Chapter 7.4.2 --- Measurement Setup for 1-dB Compression Point and IIP3 --- p.70
Chapter 7.5 --- Measurement Result of the Current Folded Mirror Mixer --- p.72
Chapter 7.5.1 --- S-Parameter Measurement --- p.75
Chapter 7.5.2 --- Conversion Gain and the Effect of the IF Variation --- p.77
Chapter 7.5.3 --- 1-dB Compression Point --- p.78
Chapter 7.5.4 --- IIP3 --- p.79
Chapter 7.5.5 --- LO Power Effect to the Mixer --- p.81
Chapter 7.5.6 --- Performance Summaries of the Current Folded Mirror Mixer --- p.82
Chapter 7.5.7 --- Discussion --- p.83
Chapter 7.6 --- Measurement Result of the Current Mode Mixer --- p.84
Chapter 7.6.1 --- S-Parameter Measurement --- p.87
Chapter 7.6.2 --- Conversion Gain and the Effect of the IF Variation --- p.89
Chapter 7.6.3 --- 1-dB Compression Point --- p.90
Chapter 7.6.4 --- IIP3 --- p.91
Chapter 7.6.5 --- LO Power Effect to the Mixer --- p.93
Chapter 7.6.6 --- Performance Summaries of the Current Mode Mixer --- p.94
Chapter 7.6.7 --- Discussion --- p.95
Chapter 7.7 --- Measurement Result of the Single-ended to Differential-ended converter --- p.96
Chapter 7.7.1 --- Measurement Setup for the Phase Difference --- p.97
Chapter 7.7.2 --- Phase Difference Measurement --- p.98
Chapter 7.7.3 --- Discussion --- p.99
Chapter Chapter8 --- Conclusion --- p.100
Chapter Appendix A --- Characteristics of the Gilbert Quad Pair --- p.102
Chapter A.1 --- Large-Signal Analysis --- p.102
Chapter Appendix B --- Characteristics of the V-I Converter --- p.105
Chapter B.1 --- Large-Signal Analysis --- p.105
Bibliography --- p.108
Yang, Julian, and 楊宙穎. "CMOS Temperature Sensor and Bandgap Voltage Reference." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/64563h.
Full text國立交通大學
電子物理系所
92
A temperature sensing system with digital output consists of a front part and a rear part. The front part includes temperature sensor and bandgap voltage reference. The rear part is an analog to digital converter (ADC). In CMOS technology, the BJT device is used as the basic temperature sensor. The base-emitter voltage (VEB) can be approximated as a linear function of temperature. By using it, temperature sensor and bandgap voltage reference can be accomplished. The simulation of the front part using a standard TSMC 0.25um 1P5M CMOS process is presented in the thesis. The designed PTAT (Proportional To Absolute Temperature) circuit has an output voltage in proportion to absolute temperature with 3.6mV / ℃. The reference voltage (Vref) is 1.21V with an effective temperature coefficient of 8.3 ppm/℃ from -25℃~125℃. Further more, A new type of bandgap voltage reference, in the form of , is proposed. We expand VEB(T) into Taylor series. After second-order compensation with one scaling factor a1=1 and a2 =-0.79, we will get a third-order temperature dependency of bandgap voltage reference. With current mode topology, the circuits design achieves a second-order compensation of VEB. It is simulated with the models of standard TSMC 0.18um 1P6M process. From simulation, the output voltage is 255mV with an effective temperature coefficient of 7.8 ppm/℃ for the temperature range -40℃~125℃. Total current consumption is about 408uA and power consumption is about 0.73mW at 25℃ for this proposed circuit.
Chang, Ting-Wei, and 張庭瑋. "CMOS current reference and voltage reference design." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/53278481139150247466.
Full text北台科學技術學院
機電整合研究所
94
This paper presents some new circuits including CMOS circuit reference and voltage reference. The architecture of the current references is produced not only by adding a positive supply voltage coefficient current reference and a negative supply voltage coefficient current reference to cancel out the supply voltage variations but also by adding a positive temperature coefficient current reference and a negative temperature coefficient current reference to cancel out the temperature variation. About the negative supply voltage coefficient current reference, we can product it by subtracting two current references with different positive supply voltage coefficient. This paper also presents a sub-1v voltage reference, which is different from the traditional bandgap reference. The main architecture of the voltage reference is composed of a positive temperature coefficient voltage reference and a negative temperature coefficient voltage reference. At first, by putting two different bias voltage of the bipolar junction transistors into the differential pair and adjusting the transistor size, we can obtain a voltage reference with a positive temperature coefficient; Secondly, by putting a ground voltage and a bias voltage of the bipolar junction transistors into the differential pair and adjusting the transistor size, we can obtain a voltage reference with a negative temperature coefficient. Finally, by putting the positive coefficient voltage reference and the negative temperature coefficient voltage reference into the differential pair and adjusting the transistor size, we can obtain a voltage reference with less sensitive to temperature variation.
Tseng, Po-Ying, and 曾柏穎. "A 1.9 GHz CMOS LOW VOLTAGE MIXER." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/37565549430170601692.
Full text大同大學
電機工程研究所
88
In recent years, personal communications system (PCS) is a hot topic. With the channel length of CMOS transistor scaling down year by year, CMOS RF-ICs are practical today. In this paper we report an integrated RF circuit topology that can be used to realize low voltage RF integrated circuits. The scheme uses on-chip capacitively coupled resonating elements to dc isolate circuit elements that under the present art are connected in series and share a common dc current. We use classical Gilbert cell mixer with 0.35μm CMOS process to realize this topology. Finally a comparison is made between a low-voltage version of the Gilbert cell mixer and the classical Gilbert cell mixer.
Wang, Li Yueh, and 王麗月. "A low voltage 900MHz CMOS RF receiver." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/70929662516083788096.
Full text國立中正大學
電機工程研究所
87
In this thesis, the design methodology and implementation techniques of CMOS RF receiver front-end circuits are presented, and this receiver is applied in the 902MHz~928MHz ISM band. The RF front-end receiver consists of a low-noise amplifier(LNA), a down-conversion mixer and a local oscillator(LO). The LNA was implemented by using single-ended and two-stage amplifying circuitry. The measured forward gain(S21) of the LNA is around 12dB at 900MHz, and its noise figure is around 10dB. The 1dB compression point and output 3dB intercept point (OIP3) are -11.1dBm and -4.6dB, respectively. In order to reduce the off-chip RF baluns, the down-conversion mixer was implemented by using a single-ended RF input. This mixer has -7 dB conversion gain at a frequency of 900MHz with an input LO power of 0dBm. The 1dB compression point is -7dBm. In the local oscillator design, we realized a voltage-controlled oscillator(VCO). It was implemented by cascading delay elements which was designed by differential-pair circuitry. It can generate an output signal of 1.7GHz. It has a phase noise of -84.27dBc/Hz at 100KHz from the 900MHz carrier. The proposed RF receiver was fabricated by using the TSMC 0.6um single-poly-triple-metal CMOS technology. The power consumption of our receiver chip is 70mW at a supply voltage of 2.2V.
Chang, Ching-Che, and 張景喆. "Low Actuation Voltage Lateral CMOS MEMS Switch." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/57897696373615005962.
Full text國立交通大學
電子研究所
100
Because CMOS switch has low efficiencies in high frequency system, the application of MEMS switch in high frequency system is the trend in the recent years. CIC offers a new CMOS MEMS technology now, the MEMS structure can be combined with the electronic circuit by this process. The thesis presents the MEMS switch is the design of the new process and application for the high frequency system. The electronic circuit is combined with the chip, and then discussed the etching of substrate how to affect the electronic circuit. The circuit is fabricated by TSMC 0.18μm CMOS process with the MEMS post - process. The chip has an extra RLS mask compare to the traditional CMOS process. The CMOS MEMS is imperfect now. The etching can only hollow out the substrate and let the metal and the SiO2 structure to float. And the material of metal has only Aluminum and Gold. The choice of design in CMOS MEMS is less than traditional MEMS process. The aim is trying to design a CMOS MEMS switch that is limited by the etching and application for RF system.
Louh, Shieng-Tai, and 陸湘台. "Fabrication and Simulation of High-Voltage CMOS." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/03150063439793335229.
Full text國立交通大學
電子工程系
87
This thesis focuses on fabrication and simulation of high-voltage CMOS devices. Based on Standard low-voltage CMOS fabrication process recipes, and with specific additive process steps onto high-voltage CMOS without affecting any low-voltage CMOS characteristics. This makes combining both low-voltage devices and high-voltage devices on a chip possible. This combination is not only increasing the range of its applications but also meet the requirement of the circuit designer uptodate. Mask counting and layout decision is the first step to high-voltage device design. After its layout and its masks, we use process simulator to have recipes on it. Finally go to device simulator to get reasonable electrical characteristics that can be operate in circuits.
Chi, Hong-Sian, and 紀宏憲. "Design of CMOS Quadrature Voltage Controlled Oscillator." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/90871257096219940335.
Full text國立勤益科技大學
電子工程系
102
A rapid oscillator design approach is proposed in this thesis. By using the rapid oscillator design approach, three CMOS Quadrature Voltage Controlled Oscillator (QVCO) are proposed, and to compare with five previous works. Based on TSMC CMOS 1P6M 0.18um standard process technology with supply voltage 1.8V, Spectre-RF and HSPICE are used to perform simulation on five previous QVCOs and three proposed QVCOs. Proposed Type-Ⅰ, Type-Ⅱ and Type-Ⅲ QVCO schemes have significantly decreased phase noise (Pnoise), which are -167.05 dBc/Hz, -172.84 dBc/Hz and 177.94 dBc/Hz at 1 MHz offset frequency, respectively. Type-Ⅲ has the best FoM (Figure of Merit) to be -227.46 dBc/Hz. The oscillation frequency of QVCO schemes has ranging from 750MHz to 1.15GHz as the control voltage adjusted from 0V to 1.8V.
Cai, Bo-Rong, and 蔡柏戎. "Design And application Of CMOS Reference Voltage." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/4r55n9.
Full text國立虎尾科技大學
電子工程系碩士班
102
In this thesis, a differential-mode reference voltage circuit with cascode architecture has been proposed. The design principle is using both the positive and the negative temperature coefficient parameters in BJT to compensate each other, and then a zero temperature coefficient output reference voltage can be achieved. Circuit simulations has used two different circuit architectures to realize the reference voltage, and both the advantages and disadvantages have been discussed. As compared with the existed differential mode reference voltage circuits, the proposed circuits benefits from simpler circuit architecture, less chip area, and also they don''t need any operational amplifier . Detailed design principle has been disclosed in this thesis, also the HSPICE and LAKER simulation programs with 0.35-μm process parameters have been used to perform the pre-layout and post-layout simulation. The supply voltages of the proposed circuits are 3.3V and 5V, respectively. The test temperature ranges from -20°C to 120°C. According to the simulation results, the double-cascode architecture can enhance the PSRR. When the supply voltage is 3.3V and the temperature is 25°C, the output voltage of the proposed cascode architecture reference voltage circuit is 426.2mv, the maximum output voltage variation is 1.37mv, the power dissipation is 0.5149mW, and the corresponding PSRR is -27.52dB. As the supply voltage is 5V and the temperature is 25°C, the output voltage of the proposed double-cascode architecture reference voltage circuit is 500.27mv, the maximum output voltage variation is only 1.0236mv, the power dissipation is 0.96502mW, and the corresponding PSRR is -45dB. All the simulation results are consistent with the theoretic analysis. The proposed circuits can be applied to vehicle electronic devices design and other digital and analog circuits.
Wang, Bo-Lun, and 王柏倫. "Design of CMOS Low-Power Reference Voltage." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/zwuwk7.
Full text國立虎尾科技大學
電子工程系碩士班
105
In this thesis, three Low-Power CMOS Reference Voltage circuits have been presented. The first circuit is with single-ended output voltage, and the second and third circuit provides multiple output voltages. In the proposed circuits, MOS transistors are biased to operate in the weak inversion region to achieve the low-power consumption characteristics. Appropriate combination of the positive and the negative temperature coefficients of the voltages, the zero-temperature coefficient reference voltage can be achieved. As compared with the existed circuits, the proposed circuits benefits from its low power consumption, simple structure, and less wafer area. In this thesis, both the pre/post layout simulation and measurement results with 0.18m and 0.35m process parameters are given to show the validity of the proposed circuits. The proposed circuits can be applied to embedded medical instruments and portable electronic devices.
Liao, Ying-Hsiang, and 廖英翔. "Design of Low Voltage Voltage-Controlled Oscillators in CMOS 0.18 μm Process." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/06418843147748077846.
Full text國立臺灣科技大學
電子工程系
98
In wireless communication system, frequency synthesizers are used to implement the frequency up/down converting of signal. In a frequency synthesizer, voltage-controlled oscillator (VCO) and frequency divider are the key blocks. For VCOs, low phase-noise output is required to avoid corrupting the mixer-converted signal by close interfering tones. The frequency of output signal of VCO is divided down to the level of reference signal, and is compared with reference signal by a phase frequency detector (PFD) to adjust the output of VCO. Therefore the dividers must have the ability of high frequency operation. Because of wireless application, both of them should operate at low power consumption. This thesis proposes two VCOs. The first VCO is a self-injection-locked Armstrong oscillator. The second is a Hartley type dual resonance oscillator. The above circuits are fabricated in the TSMC 0.18 μm CMOS process. Firstly, we propose an Armstrong voltage controlled oscillator using self-injection-locked technique. The oscillating frequency of the VCO can be tuned from 6.42 GHz to 7.58 GHz while the tuning voltage varies from 0 V to 2 V. The phase noise of the oscillation frequency at 7.45 GHz is -110.9 dBc/Hz at 1 MHz frequency offset. Secondly, we present an n-type Hartley oscillator with dual resonance. The high band tuning voltage varies from 0V to 0.8V, the oscillation frequency tuning range can be tuned from 6.36GHz to 7.09GHz; the low band tuning voltage is from 0.9V to 1.8V, and the tuning frequency ranges from 2.12GHz to 2.32GHz. The high band and low band each has a phase noise respectively of -116.74 dBc/Hz and -124.71 dBc/Hz at 1 MHz frequency offset.