Journal articles: 'CMOS readout'

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Yoon, Eun-Jung, Jong-Tae Park, and Chong-Gun Yu. "CMOS ROIC for MEMS Acceleration Sensor." Journal of IKEEE 18, no. 1 (March 31, 2014): 119–27. http://dx.doi.org/10.7471/ikeee.2014.18.1.119.

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Morgenshtein, Arkadiy, Liby Sudakov-Boreysha, Uri Dinnar, Claudio G. Jakobson, and Yael Nemirovsky. "CMOS readout circuitry for ISFET microsystems." Sensors and Actuators B: Chemical 97, no. 1 (January 2004): 122–31. http://dx.doi.org/10.1016/j.snb.2003.08.007.

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GAO, ZHIYUAN, SUYING YAO, JIANGTAO XU, and CHAO XU. "DYNAMIC RANGE EXTENSION OF CMOS IMAGE SENSORS USING MULTI-INTEGRATION TECHNIQUE WITH COMPACT READOUT." Journal of Circuits, Systems and Computers 22, no. 06 (July 2013): 1350042. http://dx.doi.org/10.1142/s0218126613500424.

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A multi-integration technology with compact readout method to extend CMOS image sensor's dynamic range is presented. Compared with the timing of rolling readout, compact readout extends the available pixel readout time by adjusting the time-domain offset between two adjacent rows and each integration time in one frame. Thus the column readout bus is working continuously rather than intermittently, which makes good use of the whole integration time and the available readout time can be extended. This dynamic range extension technology was implemented on a prototype chip with a 128 × 128 pixel array. The pixel readout time with compact readout method is almost as 3 times long as the one with rolling readout method while 39 dB dynamic range extension is achieved at 120 fps.

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Biswas, Subrata, Poly Kundu, Md Hasnat Kabir, Sagir Ahmed, and Md Moidul Islam. "Design and Analysis of High Frame Rate Capable Active Pixel Sensor by Using CNTFET Devices for Nanoelectronics." International Journal of Recent Contributions from Engineering, Science & IT (iJES) 3, no. 4 (December 14, 2015): 20. http://dx.doi.org/10.3991/ijes.v3i4.5185.

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This paper presents a high frame rate capable Active Pixel Sensor (APS) using Carbon Nanotube Field Effect Transistor (CNTFET) instead of Complementary Metal Oxide Semiconductor (CMOS). Conventionally, the design of a single APS circuit is based on three transistors (3T) model. In order to achieve higher frame rate, one extra transistor with a column sensor circuit has been introduced in the proposed design to reduce the readout time. This study also concerns about the effect of transistor sizing, bias current, and moreover, the chiral vector of CNTFET. The power consumption and power delay product (PDP) are also investigated for specific sets of reset and row selector signal. Data for these studies were collected with the help of HSPICE software which were further plotted in OriginPro to analyze the optimal operation point of APS circuit. The bias current was also recorded for the readout transistor which is uniquely introduced in the proposed model for achieving better readout time. Hence, the main focus of this paper is to improve the frame rate by reducing the readout time. Results of the proposed CNTFET APS circuit are compared with the conventional CMOS APS circuit. The performance benchmarking shows that CNTFET APS cell significantly reduces readout time, PDP, and thus can achieve much higher frame rate than that of conventional CMOS APS cell.

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Roy, Avisek, Mehdi Azadmehr, Bao Q. Ta, Philipp Häfliger, and Knut E. Aasmundtveit. "Design and Fabrication of CMOS Microstructures to Locally Synthesize Carbon Nanotubes for Gas Sensing." Sensors 19, no. 19 (October 8, 2019): 4340. http://dx.doi.org/10.3390/s19194340.

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Carbon nanotubes (CNTs) can be grown locally on custom-designed CMOS microstructures to use them as a sensing material for manufacturing low-cost gas sensors, where CMOS readout circuits are directly integrated. Such a local CNT synthesis process using thermal chemical vapor deposition (CVD) requires temperatures near 900 °C, which is destructive for CMOS circuits. Therefore, it is necessary to ensure a high thermal gradient around the CNT growth structures to maintain CMOS-compatible temperature (below 300 °C) on the bulk part of the chip, where readout circuits are placed. This paper presents several promising designs of CNT growth microstructures and their thermomechanical analyses (by ANSYS Multiphysics software) to check the feasibility of local CNT synthesis in CMOS. Standard CMOS processes have several conductive interconnecting metal and polysilicon layers, both being suitable to serve as microheaters for local resistive heating to achieve the CNT growth temperature. Most of these microheaters need to be partially or fully suspended to produce the required thermal isolation for CMOS compatibility. Necessary CMOS post-processing steps to realize CNT growth structures are discussed. Layout designs of the microstructures, along with some of the microstructures fabricated in a standard AMS 350 nm CMOS process, are also presented in this paper.

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ZHAO, HONGLIANG, YIQIANG ZHAO, YIWEI SONG, JUN LIAO, and JUNFENG GENG. "A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA." Journal of Circuits, Systems and Computers 22, no. 10 (December 2013): 1340033. http://dx.doi.org/10.1142/s0218126613400331.

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A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

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Habibi, Mehdi, Yunus Dawji, Ebrahim Ghafar-Zadeh, and Sebastian Magierowski. "Nanopore-based DNA sequencing sensors and CMOS readout approaches." Sensor Review 41, no. 3 (July 15, 2021): 292–310. http://dx.doi.org/10.1108/sr-05-2020-0121.

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Purpose Nanopore-based molecular sensing and measurement, specifically DNA sequencing, is advancing at a fast pace. Some embodiments have matured from coarse particle counters to enabling full human genome assembly. This evolution has been powered not only by improvements in the sensors themselves, but also in the assisting microelectronic CMOS readout circuitry closely interfaced to them. In this light, this paper aims to review established and emerging nanopore-based sensing modalities considered for DNA sequencing and CMOS microelectronic methods currently being used. Design/methodology/approach Readout and amplifier circuits, which are potentially appropriate for conditioning and conversion of nanopore signals for downstream processing, are studied. Furthermore, arrayed CMOS readout implementations are focused on and the relevant status of the nanopore sensor technology is reviewed as well. Findings Ion channel nanopore devices have unique properties compared with other electrochemical cells. Currently biological nanopores are the only variants reported which can be used for actual DNA sequencing. The translocation rate of DNA through such pores, the current range at which these cells operate on and the cell capacitance effect, all impose the necessity of using low-noise circuits in the process of signal detection. The requirement of using in-pixel low-noise circuits in turn tends to impose challenges in the implementation of large size arrays. Originality/value The study presents an overview on the readout circuits used for signal acquisition in electrochemical cell arrays and investigates the specific requirements necessary for implementation of nanopore-type electrochemical cell amplifiers and their associated readout electronics.

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Szymański, Andrzej, Dariusz Obrębski, Jacek Marczewski, Daniel Tomaszewski, Mirosław Grodner, and Janusz Pieczyński. "CMOS Readout Circuit Integrated with Ionizing Radiation Detectors." International Journal of Electronics and Telecommunications 60, no. 1 (March 1, 2014): 105–12. http://dx.doi.org/10.2478/eletel-2014-0014.

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Abstract This paper describes the work performed in ITE on integration in one CMOS chip the ionizing radiation detectors with dedicated readout electronics. At the beginning, some realizations of silicon detectors of ionizing radiation are presented together with most important issues related to these devices. Next, two developed test structures for readout electronics are discussed in detail together with main features of non-typical silicon process deployed.

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Kavadias, S., P. De Moor, and C. Van Hoof. "CMOS circuit for readout of microbolometer arrays." Electronics Letters 37, no. 8 (2001): 481. http://dx.doi.org/10.1049/el:20010330.

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Nasri, B., and C. Fiorini. "A CMOS readout circuit for microstrip detectors." Journal of Instrumentation 10, no. 03 (March 24, 2015): C03038. http://dx.doi.org/10.1088/1748-0221/10/03/c03038.

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Schoeneberg, U., B. J. Hosticka, and F. V. Schnatz. "A CMOS readout amplifier for instrumentation applications." IEEE Journal of Solid-State Circuits 26, no. 7 (July 1991): 1077–80. http://dx.doi.org/10.1109/4.92029.

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Shakoor, Abdul, Boon Chong Cheah, Mohammed A. Al-Rawhani, Marco Grande, James Grant, Luiz Carlos Paiva Gouveia, and David R. S. Cumming. "CMOS Nanophotonic Sensor With Integrated Readout System." IEEE Sensors Journal 18, no. 22 (November 15, 2018): 9188–94. http://dx.doi.org/10.1109/jsen.2018.2870255.

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Ren, Mingyuan, and Chunxiang Zhang. "CMOS readout circuit for piezo-resistive accelerometer." International Journal of Simulation and Process Modelling 7, no. 1/2 (2012): 115. http://dx.doi.org/10.1504/ijspm.2012.047869.

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Sieberer, P., T. Bergauer, K. Flöckner, C. Irmler, and H. Steininger. "Readout system and testbeam results of the RD50-MPW2 HV-CMOS pixel chip." Journal of Physics: Conference Series 2374, no. 1 (November 1, 2022): 012096. http://dx.doi.org/10.1088/1742-6596/2374/1/012096.

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The RD50-CMOS group aims to design and study High Voltage CMOS (HV-CMOS) chips for use in a high radiation environment. Currently, measurements are performed on RD50-MPW2 chip, the second prototype developed by this group. The active matrix of the prototype consists of 8x8 pixels with analog front end. Details of the analog front end and simulations have been already published earlier. This contribution focuses on the Caribou based readout system of the active matrix. Each pixel of the active matrix can be readout one after the other. Relevant aspects of hardware, firmware and software are introduced. As a first stage, firmware for a standalone setup is introduced and details on data flow are given. Afterwards, a second stage of the firmware capable of synchronizing with other detectors and accepting triggers is presented, focusing on operation of the chip in combination with a tracking telescope to measure efficiency and residuals.

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Kwon, Yu-Mi, Hee-Sung Kang, Jung-Hee Lee, and Yong Soo Lee. "Si PIN Radiation Sensor with CMOS Readout Circuit." Journal of Sensor Science and Technology 23, no. 2 (March 31, 2014): 73–81. http://dx.doi.org/10.5369/jsst.2014.23.2.73.

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Kwok, T., J. J. Zhong, T. Wilkinson, and W. A. Crossland. "Readout circuit for CMOS active pixel image sensor." Electronics Letters 38, no. 7 (2002): 317. http://dx.doi.org/10.1049/el:20020248.

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De Geronimo, G., P. O'Connor, and J. Grosholz. "A CMOS baseline holder (BLH) for readout ASICs." IEEE Transactions on Nuclear Science 47, no. 3 (June 2000): 818–22. http://dx.doi.org/10.1109/23.856523.

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Schoeneberg, U., B. J. Hosticka, J. Fent, H. Oberlack, and G. Zimmer. "CMOS readout electronics for operation at cryogenic temperatures." IEEE Journal of Solid-State Circuits 24, no. 3 (June 1989): 718–22. http://dx.doi.org/10.1109/4.32031.

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Jakobson, C. G., G. Asa, S. Bar Lev, and Y. Nemirovsky. "Low noise CMOS readout for CdZnTe detector arrays." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 428, no. 1 (June 1999): 113–17. http://dx.doi.org/10.1016/s0168-9002(98)01587-3.

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Qisong, Wu, Yang Haigang, Yin Tao, and Zhang Chong. "A high precision CMOS weak current readout circuit." Journal of Semiconductors 30, no. 7 (July 2009): 075011. http://dx.doi.org/10.1088/1674-4926/30/7/075011.

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Hartsough, Neal E., Jan S. Iwanczyk, Einar Nygard, Nail Malakhov, William C. Barber, and Thulasidharan Gandhi. "Polycrystalline Mercuric Iodide Films on CMOS Readout Arrays." IEEE Transactions on Nuclear Science 56, no. 4 (August 2009): 1810–16. http://dx.doi.org/10.1109/tns.2009.2023478.

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Arbet, Daniel, Viera Stopjaková, Martin Kovác, Lukás Nagy, and Gabriel Nagy. "Design of CMOS readout frontend circuit for MEMS capacitive microphones." Facta universitatis - series: Electronics and Energetics 28, no. 2 (2015): 263–74. http://dx.doi.org/10.2298/fuee1502263a.

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This paper deals with a frontend part of the readout circuit developed as an integrated circuit that after bonding together with a MEMS capacitive microphone (MCM) chip will be used in a noise dosimeter applicable in very noisy and harsh environment, e.g. mine. Therefore, the main attention has been paid to the high dynamic range, low offset and low noise of the developed readout interface as well as its low-power consumption feature. For conversion of the MCM?s capacitance variation into voltage, an approach based on the buffered input conversion stage biased by a voltage divider was used. The advantage of this approach is that the voltage divider formed by MOS transistors can be connected to the high-impedance node (i.e. the output of the MCM, in this case). The whole frontend part of the readout interface was designed in a standard 0.35mm CMOS technology. Finally, the achieved results are discussed and compared to other works.

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Mokso, Rajmund, Christian M. Schlepütz, Gerd Theidel, Heiner Billich, Elmar Schmid, Tine Celcer, Gordan Mikuljan, et al. "GigaFRoST: the gigabit fast readout system for tomography." Journal of Synchrotron Radiation 24, no. 6 (October 17, 2017): 1250–59. http://dx.doi.org/10.1107/s1600577517013522.

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Owing to recent developments in CMOS technology, it is now possible to exploit tomographic microscopy at third-generation synchrotron facilities with unprecedented speeds. Despite this rapid technical progress, one crucial limitation for the investigation of realistic dynamic systems has remained: a generally short total acquisition time at high frame rates due to the limited internal memory of available detectors. To address and solve this shortcoming, a new detection and readout system, coined GigaFRoST, has been developed based on a commercial CMOS sensor, acquiring and streaming data continuously at 7.7 GB s−1directly to a dedicated backend server. This architecture allows for dynamic data pre-processing as well as data reduction, an increasingly indispensable step considering the vast amounts of data acquired in typical fast tomographic experiments at synchrotron beamlines (up to several tens of TByte per day of raw data).

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SUPON, TAREQ MUHAMMAD, KRISHNAMOHAN THANGARAJAH, RASHID RASHIDZADEH, and MAJID AHMADI. "A READOUT SOLUTION FOR MEMS SENSORS." Journal of Circuits, Systems and Computers 21, no. 06 (October 2012): 1240014. http://dx.doi.org/10.1142/s0218126612400142.

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A new readout circuit for MEMS devices is presented in this paper. A Phase Locked Loop (PLL) has been utilized to convert variations of MEM capacitance to time domain signals. The proposed scheme presents a robust performance against process, power supply and temperature variations due to inherent feedback of PLL systems. Simulation results in Cadence environment using TSMC CMOS 65-nm technology indicate that a measurement resolution of 73 aF can be achieved.

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Campos, Fernando de Souza, Bruno Albuquerque de Castro, and Jacobus W. Swart. "A Tunable CMOS Image Sensor with High Fill-Factor for High Dynamic Range Applications." Engineering Proceedings 2, no. 1 (November 14, 2020): 79. http://dx.doi.org/10.3390/ecsa-7-08235.

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Several CMOS imager sensors were proposed to obtain high dynamic range imager (>100 dB). However, as drawback these imagers implement a large number of transistors per pixel resulting in a low fill factor, high power consumption and high complexity CMOS image sensors. In this work, a new operation mode for 3 T CMOS image sensors is presented for high dynamic range (HDR) applications. The operation mode consists of biasing the conventional reset transistor as active load to photodiode generating a reference current. The output voltage achieves a steady state when the photocurrent becomes equal to the reference current, similar to the inverter operation in the transition region. At a specific bias voltage, the output swings from o to Vdd in a small light intensity range; however, high dynamic range is achieve using multiple readout at different bias voltage. For high dynamic range operation different values of bias voltage can be applied from each one, and the signal can be captured to compose a high dynamic range image. Compared to other high dynamic range architectures this proposed CMOS image pixel show as advantage high fill-factor (3 T) and lower complexity. Moreover, as the CMOS pixel does not operate in integration mode, de readout can be performed at higher speed. A prototype was fabricated at 3.3 V 0.35 µm CMOS technology. Experimental results are shown by applying five different control voltage from 0.65 to 1.2 V is possible to obtain a dynamic range of about 100 dB.

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Kim, Hyuntae, and Bertan Bakkaloglu. "CMOS Analog Front-End IC for Gas Sensors." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 001761–96. http://dx.doi.org/10.4071/2011dpc-wp25.

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An electrochemical sensor readout analog front-end (AFE) IC for recording long term chemical and gas exposure is presented. The AFE readout circuit enables the detection of exhaust fumes in hazardous diesel and gasoline equipment, which helps correlate atmospheric pollutants with severe illnesses. The AFE reads out the output of eight conductometric sensor arrays and eight amperometric sensor arrays. The IC consists of a low noise potentiostat and associated 9 bits current-steering DAC for sensor stimulus, followed by the first order nested chopped ΣΔ ADC. The conductometric sensor uses a current driven approach for extracting resistance change of the sensor depending on gas concentration. The amperometric sensor uses a potentiostat to apply constant voltage for measuring current out of the sensor after a chemical reaction. The core area for the AFE is 2.65x0.95 mm2. The IC is fabricated in 0.18μm CMOS process and achieves 91dB SNR with 1.32mW power consumption per channel from a 1.8 V supply. With digital offset storage and nested chopping, the readout IC achieves 500 μV input referred offset. In order to use the system with AFE as part of a compact badge with battery, the entire gas detection system has been designed in 3D layers with a bio sensor mounted layer, an AFE layer, power management layer, a micro controller layer, and battery.

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Crescentini, Marco, Cinzia Tamburini, Luca Belsito, Aldo Romani, Alberto Roncaglia, and Marco Tartagni. "Ultra-Low Power CMOS Readout for Resonant MEMS Strain Sensors." Proceedings 2, no. 13 (December 11, 2018): 973. http://dx.doi.org/10.3390/proceedings2130973.

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This paper presents an ultra-low power, silicon-integrated readout for resonant MEMS strain sensors. The analogue readout implements a negative-resistance amplifier based on first-generation current conveyors (CCI) that, thanks to the reduced number of active elements, targets both low-power and low-noise. A prototype of the circuit was implemented in a 0.18-µm technology occupying less than 0.4 mm2 and consuming only 9 µA from the 1.8-V power supply. The prototype was earliest tested by connecting it to a resonant MEMS strain resonator.

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Maity, N. P., Reshmi Maity, and Srimanta Baishya. "Design of a Low Noise Active Pixel Sensor using Complementary Metal-Oxide-Semiconductor Technology." Science & Technology Journal 4, no. 2 (July 1, 2016): 130–36. http://dx.doi.org/10.22232/stj.2016.04.02.07.

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In this paper, our focus is on designing of complementary metal-oxide-semiconductor (CMOS) photodiode based active pixel sensor (APS) and performance analysis and achievements for CMOS image sensor. Different important design parameters like photocurrent, conversion gain, conversion factor, dynamic range, readout speed, and quantum efficiency have been calculated. Noise is also considered for the design at different phase of operations of CMOS APS. Various design parameters of our design are computed and compared with simulated results. Noise calculation shows that the pixel noise is dominated by reset noise.

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Quintero, Andres, Fernando Cardes, Carlos Perez, Cesare Buffa, Andreas Wiesbauer, and Luis Hernandez. "A VCO-Based CMOS Readout Circuit for Capacitive MEMS Microphones." Sensors 19, no. 19 (September 24, 2019): 4126. http://dx.doi.org/10.3390/s19194126.

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Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered “always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta ( Σ Δ ) analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by 1 / f and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 μ A at 1.8 V and the effective area is 0.12 mm 2 . This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.

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Raciti, B., Y. Gao, R. Schimassek, A. Andreazza, Z. Feng, H. Fox, Y. Han, et al. "Characterisation of HV-MAPS ATLASPix3 and its applications for future lepton colliders." Journal of Instrumentation 17, no. 09 (September 1, 2022): C09031. http://dx.doi.org/10.1088/1748-0221/17/09/c09031.

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Abstract HV-MAPS are a novel type of CMOS depleted active pixel sensors for ionizing particles, implemented in standard CMOS processes, that have been proposed in several future particle physics experiments for particle tracking. In depleted monolithic sensors, the sensor element is the n-well/p-substrate diode. The sensor matrix and the readout are integrated in one single piece of silicon and the electronics is embedded in shallow wells inside deep n-wells, isolated from the substrate. High voltage biasing increases the depth of the depletion region, improving sensor properties as signal amplitude, charge collection speed and radiation tolerance. ATLASPix3 is the first full reticle size high voltage Monolithic Active Pixel CMOS sensor, designed to meet the specifications of the outer layers of the ATLAS inner tracker (ITk). Its thin design, the excellent position resolution, high readout rate and high radiation tolerance make ATLASPix3 an ideal candidate for large-area tracking detector R&D of future collider experiments such as the Circular Electron Positron Collider (CEPC) silicon tracker.

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Bechen, B., A. Kemna, M. Gnade, T. v. d. Boom, and B. Hosticka. "Noise Considerations of Integrators for Current Readout Circuits." Advances in Radio Science 3 (May 13, 2005): 331–36. http://dx.doi.org/10.5194/ars-3-331-2005.

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Abstract. In this paper the noise analysis of a current integrator is carried out and measures to reduce the overall noise are presented. The effects of various noise sources are investigated and their dependence on the input capacitance and on the gate area of the input transistors of the OTA used for the readout is shown. Both, input capacitance and gate area, should be kept as small as possible. Moreover, the linearity of the integrator is examined. In addition to that, the available application of such sensor readout circuit, which is a CMOS photodetector readout, is introduced. It uses an automatic gain switching, so that the dynamic range is extended.

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Lu, Fei Bao, Guo Lin Lu, You Shu Huang, and Xiang Hui Yuan. "Readout Circuit for Uncooled Pyroelectric IRFPA." Applied Mechanics and Materials 84-85 (August 2011): 284–88. http://dx.doi.org/10.4028/www.scientific.net/amm.84-85.284.

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A 320×240 readout circuit (ROIC) for the uncooled pyroelectric infrared detector was fabricated in the double-poly-double-metal (DPDM) N-well CMOS technology. Composed of X- and Y-shift register, column amplifier and correlated double sampling (CDS) circuit, the readout circuit integrated signal from the detector for frame time. It has the pitch of 50um and power dissipation of less than 50 mW. The circuit configuration, operation and testing result are described. Testing result indicates that the designed circuit meets with the requirement. Thermal images were obtained by the hybrid-integrated sensing array.

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Chavarria, A. E. "The Selena Neutrino Experiment." Journal of Physics: Conference Series 2156, no. 1 (December 1, 2021): 012155. http://dx.doi.org/10.1088/1742-6596/2156/1/012155.

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Abstract Imaging sensors made from an ionization target layer of amorphous selenium (aSe) coupled to a silicon complementary metal-oxide-semiconductor (CMOS) active pixel array for charge readout are a promising technology for neutrino physics. The high spatial resolution in a solid-state target provides unparalleled rejection of backgrounds from natural radioactivity in the search for neutrinoless ββ decay and for solar neutrino spectroscopy with 82Se. We present results on the ionization response of aSe measured from the photoabsorption of 122 keV γ rays in a single-pixel device. We report on the progress in the fabrication and testing of the first prototype imaging sensors based on the Topmetal II − pixelated CMOS charge readout chip. We explore the scientific reach of a large neutrino detector with the proposed technology based on our experimental understanding of the sensor performance.

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Wang, Wei, and Sameer Sonkusale. "An Approach for a Wide Dynamic Range Low-Noise Current Readout Circuit." Journal of Low Power Electronics and Applications 10, no. 3 (July 29, 2020): 23. http://dx.doi.org/10.3390/jlpea10030023.

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Designing low-noise current readout circuits at high speed is challenging. There is a need for preamplification stages to amplify weak input currents before being processed by conventional integrator based readout. However, the high current gain preamplification stage usually limits the dynamic range. This article presents a 140 dB input dynamic range low-noise current readout circuit with a noise floor of 10 fArms/sq(Hz). The architecture uses a programmable bidirectional input current gain stage followed by an integrator-based analog-to-pulse conversion stage. The programmable current gains setting enables one to achieve higher overall input dynamic range. The readout circuit is designed and in 0.18 μm CMOS and consumes 10.3 mW power from a 1.8 V supply. The circuit has been verified using post-layout simulations.

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Liu, Yu-Sian, and Kuei-Ann Wen. "Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme." Micromachines 9, no. 12 (November 30, 2018): 637. http://dx.doi.org/10.3390/mi9120637.

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A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/√Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.

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Zhou, Tong, Tao Dong, Yan Su, and Yong He. "A High Uniformity Readout Integrated Circuit for Infrared Focal Plane Array Applications." Applied Mechanics and Materials 602-605 (August 2014): 2632–36. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.2632.

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Infrared focal plane arrays (IRFPA) suffer from inherent low frequency and fixed patter noise (FPN). To achieve high quality infrared image by mitigating the FPN of IRFPAs, a novel low-noise and high uniformity readout integrated circuit (ROIC) has been proposed. A correlated double sampling (CDS) with single capacitor method has been adopted in the ROIC design which can effectively reduce the FPN, KTC and 1/f noise. A 4×4 experimental readout chip has been designed and fabricated using the SMIC 0.18 μm CMOS process. Both the function and performance of the proposed readout circuit have been verified by experimental results. The test results show that the proposed ROIC has a good performance in practical applications.

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Siu Fan, Vinny Lam, and Yusmeeraz Binti Yusof. "Design of Fully Integrated Impedimetric CMOS Biosensor for DNA Detection." Advanced Materials Research 925 (April 2014): 524–28. http://dx.doi.org/10.4028/www.scientific.net/amr.925.524.

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This paper described a label-free and fully integrated impedimetric biosensor using standard Complementary Metal Oxide Semiconductor (CMOS) technology to measure both capacitance and resistance of the electrode-electrolyte interface. Conventional impedance biosensors usually use bulky and expensive instruments to monitor the impedance change. This paper demonstrates a low power, high gain and low cost impedance readout circuit design for detecting the biomolecular interactions of deoxyribonucleic acid (DNA) strands at the electrode surface. The proposed biosensor circuit is composed of a transimpedance amplifier (TIA) with two quadrature phase mixers and finally integrated with 5μm x 5μm microelectrode based on 0.18μm Silterra CMOS technology process with 1.8V supply. The output value of the readout circuit is used to estimate the amplitude and phase of the measured admittance. The developed TIA can achieve a gain of 88.6dB up to a frequency of 50MHz. It also has very good linearity up to 2.7mA and the overall dynamic range is approximately 90dB.

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Teo, T. H., K. L. Oung, X. T. Chen, Z. Q. Gao, Y. Fan, and W. G. Yeoh. "Time-constant-based CMOS readout circuit for DNA detection." Electronics Letters 44, no. 6 (2008): 400. http://dx.doi.org/10.1049/el:20082875.

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De Geronimo, G., P. O'Connor, and J. Grosholz. "A generation of CMOS readout ASICs for CZT detectors." IEEE Transactions on Nuclear Science 47, no. 6 (2000): 1857–67. http://dx.doi.org/10.1109/23.914460.

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Visschers, J. L., V. Blanco Carballo, M. Chefdeville, P. Colas, H. van der Graaf, J. Schmitz, S. Smits, and J. Timmermans. "Direct readout of gaseous detectors with tiled CMOS circuits." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 572, no. 1 (March 2007): 203–4. http://dx.doi.org/10.1016/j.nima.2006.10.287.

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Schoeneberg, U., B. J. Hosticka, J. Fent, H. Oberlack, and G. Zimmer. "A CMOS readout system for very large detector capacitances." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 288, no. 1 (March 1990): 191–96. http://dx.doi.org/10.1016/0168-9002(90)90485-o.

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Kavadias, S. "Offset-free column readout circuit for CMOS image sensors." Electronics Letters 35, no. 24 (1999): 2112. http://dx.doi.org/10.1049/el:19991453.

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Miyatake, S., M. Miyamoto, K. Ishida, T. Morimoto, Y. Masaki, and H. Tanabe. "Transversal-readout architecture for CMOS active pixel image sensors." IEEE Transactions on Electron Devices 50, no. 1 (January 2003): 121–29. http://dx.doi.org/10.1109/ted.2002.806960.

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López-Portilla, Bárbaro M., Wladimir Valenzuela, Payman Zarkesh-Ha, and Miguel Figueroa. "A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction." Sensors 23, no. 2 (January 13, 2023): 934. http://dx.doi.org/10.3390/s23020934.

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Images produced by CMOS sensors may contain defective pixels due to noise, manufacturing errors, or device malfunction, which must be detected and corrected at early processing stages in order to produce images that are useful to human users and image-processing or machine-vision algorithms. This paper proposes a defective pixel detection and correction algorithm and its implementation using CMOS analog circuits, which are integrated with the image sensor at the pixel and column levels. During photocurrent integration, the circuit detects defective values in parallel at each pixel using simple arithmetic operations within a neighborhood. At the image-column level, the circuit replaces the defective pixels with the median value of their neighborhood. To validate our approach, we designed a 128×128-pixel imager in a 0.35μm CMOS process, which integrates our defective-pixel detection/correction circuits and processes images at 694 frames per second, according to post-layout simulations. Operating at that frame rate, our proposed algorithm and its CMOS implementation produce better results than current state-of-the-art algorithms: it achieves a Peak Signal to Noise Ratio (PSNR) and Image Enhancement Factor (IEF) of 45 dB and 198.4, respectively, in images with 0.5% random defective pixels, and a PSNR of 44.4 dB and IEF of 194.2, respectively, in images with 1.0% random defective pixels.

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Yang, Ping, Xiangming Sun, Guangming Huang, Le Xiao, Chaosong Gao, Xing Huang, Wei Zhou, et al. "An asynchronous data-driven readout prototype for CEPC vertex detector." International Journal of Modern Physics A 32, no. 34 (December 10, 2017): 1746012. http://dx.doi.org/10.1142/s0217751x17460125.

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The Circular Electron Positron Collider (CEPC) is proposed as a Higgs boson and/or Z boson factory for high-precision measurements on the Higgs boson. The precision of secondary vertex impact parameter plays an important role in such measurements which typically rely on flavor-tagging. Thus silicon CMOS Pixel Sensors (CPS) are the most promising technology candidate for a CEPC vertex detector, which can most likely feature a high position resolution, a low power consumption and a fast readout simultaneously. For the R&D of the CEPC vertex detector, we have developed a prototype MIC4 in the Towerjazz 180 nm CMOS Image Sensor (CIS) process. We have proposed and implemented a new architecture of asynchronous zero-suppression data-driven readout inside the matrix combined with a binary front-end inside the pixel. The matrix contains 128 rows and 64 columns with a small pixel pitch of 25 [Formula: see text]m. The readout architecture has implemented the traditional OR-gate chain inside a super pixel combined with a priority arbiter tree between the super pixels, only reading out relevant pixels. The MIC4 architecture will be introduced in more detail in this paper. It will be taped out in May and will be characterized when the chip comes back.

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Jeong, Kyungsoo, Duckhoon Ro, Gwanho Lee, Myounggon Kang, and Hyung-Min Lee. "A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications." Electronics 7, no. 12 (December 12, 2018): 429. http://dx.doi.org/10.3390/electronics7120429.

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A nuclear fusion reactor requires a radiation-hardened sensor readout integrated circuit (IC), whose operation should be tolerant against harsh radiation effects up to MGy or higher. This paper proposes radiation-hardening circuit design techniques for an instrumentation amplifier (IA), which is one of the most sensitive circuits in the sensor readout IC. The paper studied design considerations for choosing the IA topology for radiation environments and proposes a radiation-hardened IA structure with total-ionizing-dose (TID) effect monitoring and adaptive reference control functions. The radiation-hardened performance of the proposed IA was verified through model-based circuit simulations by using compact transistor models that reflected the TID effects into complementary metal–oxide–semiconductor (CMOS) parameters. The proposed IA was designed with the 65 nm standard CMOS process and provides adjustable voltage gain between 3 and 15, bandwidth up to 400 kHz, and power consumption of 34.6 μW, while maintaining a stable performance over TID effects up to 1 MGy.

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Shen, Chao, Caiwen Ma, and Wei Gao. "Design of a Ultra-Stable Low-Noise Space Camera Based on a Large Target CMOS Detector and Image Data Analysis." Sensors 22, no. 24 (December 18, 2022): 9991. http://dx.doi.org/10.3390/s22249991.

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To detect faint target stars of 22nd magnitude and above, an astronomical exploration project requires its space camera’s readout noise to be less than 5e− with long-time working stability. Due to the limitation of satellite, the traditional CCD detector-based camera does not meet the requirements, including volume, weight, and power consumption. Thereby, a low-noise ultra-stable camera based on 9 K × 9 K large target surface CMOS is designed to meet the needs. For the first time, the low-noise ultra-stable camera based on CMOS detector will be applied to space astronomy projects, remote sensing imaging, resource survey, atmospheric and oceanic observation and other fields. In this paper, the design of the camera is introduced in detail, and the camera is tested for several rounds at −40 °C; it also undergoes further testing and data analysis. Tests proved super stability and that the readout noise is lower than 4.5e−. Dark current, nonlinearity and PTC indicators meet the requirements of the astronomical exploration project.

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Menssouri, Aicha, Karim El Khadiri, and Ahmed Tahiri. "In-Pixel CTIA & Readout Circuitry for an Active CMOS Image Sensor." WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL 16 (December 2, 2021): 626–32. http://dx.doi.org/10.37394/23203.2021.16.58.

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This work aims to design and simulate an in-pixel Capacitive Transimpedance Amplifier (CTIA) and peripheral circuitry that ensures pixel reading. Each pixel circuit is composed of four transistors using 90nm CMOS technology with a supply voltage of 1.8 V and is part of an array of pixels that make up a CMOS image sensor with peripheral circuitry. Pixel output is sent to a delta difference sampling (DDS) circuit to filter reset voltages. The Gain Margin achieved for the in-pixel CTIA is 44dB and 91dB for the Phase Margin. We also present measured pixel parameters and give a comparison with prior work. The timing and readout circuitry is also described.

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Jirsa, J., J. Gecnuk, M. Havranek, Z. Janoska, M. Jansky, V. Kafka, O. Korchak, et al. "Characterization of 3.2 Gbps readout in 65 nm CMOS technology." Journal of Instrumentation 18, no. 01 (January 1, 2023): C01055. http://dx.doi.org/10.1088/1748-0221/18/01/c01055.

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Abstract A new class of photon-counting pixel detectors allows for capturing of an image in several photon energy bins in one shot. A decreased pixel pitch and an increased number of energy bins are needed to enhance the spatial and spectral resolution of the detector. This led to new requirements for the readout systems and their bandwidths, as more data is generated for the same detection area. Fast differential serial communication enables high-speed data rates, thus providing an ideal solution to transfer large amounts of data generated by the detector’s front-end electronics. However, its implementation provides extra challenges. This work introduces a novel high-speed serial readout designed in a 65 nm CMOS technology that will be used in the future photon-counting X-ray imaging detectors. The design of the serial transmitter is presented together with the characterization of jitter and channel performance.

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Perelló-Roig, Rafel, Jaume Verd, Sebastià Bota, and Jaume Segura. "Thermomechanical Noise Characterization in Fully Monolithic CMOS-MEMS Resonators." Sensors 18, no. 9 (September 16, 2018): 3124. http://dx.doi.org/10.3390/s18093124.

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We analyzed experimentally the noise characteristics of fully integrated CMOS-MEMS resonators to determine the overall thermomechanical noise and its impact on the limit of detection at the system level. Measurements from four MEMS resonator geometries designed for ultrasensitive detection operating between 2-MHz and 8-MHz monolithically integrated with a low-noise CMOS capacitive readout circuit were analyzed and used to determine the resolution achieved in terms of displacement and capacitance variation. The CMOS-MEMS system provides unprecedented detection resolution of 11 yF·Hz−1/2 equivalent to a minimum detectable displacement (MDD) of 13 fm·Hz−1/2, enabling noise characterization that is experimentally demonstrated by thermomechanical noise detection and compared to theoretical model values.

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Journal articles on the topic 'CMOS readout'

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