Dissertations / Theses: 'CMOS readout'

1

Guo, Xiaochuan. "A time-base asynchronous readout cmos image sensor." [Gainesville, Fla.] : University of Florida, 2002. http://purl.fcla.edu/fcla/etd/UFE0000540.

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2

Kepenek, Reha. "Capacitive Cmos Readout Circuits For High Performance Mems Accelerometers." Master's thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/12609310/index.pdf.

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This thesis presents the development of high resolution, wide dynamic range sigma-delta type readout circuits for capacitive MEMS accelerometers. Designed readout circuit employs fully differential closed loop structure with digital output, achieving high oversampling ratio and high resolution. The simulations of the readout circuit together with the accelerometer sensor are performed using the models constructed in Cadence and Matlab Simulink environments. The simulations verified the stability and proper operation of the accelerometer system. The sigma-delta readout circuit is implemented using XFab 0.6 µ
m CMOS process. Readout circuit is combined with Silicon-On-Glass (SOG) and Dissolved Wafer Process (DWP) accelerometers. Both open loop and closed loop tests of the accelerometer system are performed. Open loop test results showed high sensitivity up to 8.1 V/g and low noise level of 4.8 µ
g/&
#61654
Hz. Closed loop circuit is implemented on a PCB together with the external filtering and decimation electronics, providing 16-bit digital output at 800 Hz sampling rate. High acceleration tests showed ±
18.5 g of linear acceleration range with high linearity, using DWP accelerometers. The noise tests in closed loop mode are performed using Allan variance technique, by acquiring the digital data. Allan variance tests provided 86 µ
g/&
#61654
Hz of noise level and 74 µ
g of bias drift. Temperature sensitivity tests of the readout circuit in closed loop mode is also performed, which resulted in 44 mg/º
C of temperature dependency. Two different types of new adaptive sigma-delta readout circuits are designed in order to improve the resolution of the systems by higher frequency operation. The two circuits both change the acceleration range of operation of the system, according to the level of acceleration. One of the adaptive circuits uses variation of feedback time, while the other circuit uses multi-bit feedback method. The simulation results showed micro-g level noise in closed loop mode without the addition of the mechanical noise of the sensor.

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3

Toprak, Alperen. "Cmos Readout Electronics For Microbolometer Type Infrared Detector Arrays." Master's thesis, METU, 2009. http://etd.lib.metu.edu.tr/upload/3/12610390/index.pdf.

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This thesis presents the development of CMOS readout electronics for microbolometer type infrared detector arrays. A low power output buffering architecture and a new bias correction digital-to-analog converter (DAC) structure for resistive microbolometer readouts is developed
and a 384x288 resistive microbolometer FPA readout for 35 µ
m pixel pitch is designed and fabricated in a standard 0.6 µ
m CMOS process. A 4-layer PCB is also prepared in order to form an imaging system together with the FPA after detector fabrication. The low power output buffering architecture employs a new buffering scheme that reduces the capacitive load and hence, the power dissipation of the readout channels. Furthermore, a special type operational amplifier with digitally controllable output current capability is designed in order to use the power more efficiently. With the combination of these two methods, the power dissipation of the output buffering structure of a 384x288 microbolometer FPA with 35 µ
m pixel pitch operating at 50 fps with two output channels can be decreased to 8.96% of its initial value. The new bias correction DAC structure is designed to overcome the power dissipation and noise problems of the previous designs at METU. The structure is composed of two resistive ladder DAC stages, which are capable of providing multiple outputs. This feature of the resistive ladders reduces the overall area and power dissipation of the structure and enables the implementation of a dedicated DAC for each readout channel. As a result, the need for the sampling operation required in the previous designs is eliminated. Elimination of sampling prevents the concentration of the noise into the baseband, and therefore, allows most of the noise to be filtered out by integration. A 384x288 resistive microbolometer FPA readout with 35 &
#956
m pixel pitch is designed and fabricated in a standard 0.6 &
#956
m CMOS process. The fabricated chip occupies an area of 17.84 mm x 16.23 mm, and needs 32 pads for normal operation. The readout employs the low power output buffering architecture and the new bias correction DAC structure
therefore, it has significantly low power dissipation when compared to the previous designs at METU. A 4-layer imaging PCB is also designed for the FPA, and initial tests are performed with the same PCB. Results of the performed tests verify the proper operation of the readout. The rms output noise of the imaging system and the power dissipation of the readout when operating at a speed of 50 fps is measured as 1.76 mV and 236.9 mW, respectively.

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4

Musayev, Javid. "Cmos Integrated Sensor Readout Circuitry For Dna Detection Applications." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12613645/index.pdf.

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This study presents a CMOS integrated sensor chip suitable for sensing biological samples like DNA. The sensing part of the chip consists of a 32 X 32 pixel array with a 15 µ
m pixel pitch. Pixels have 5 µ
m X 5 µ
m detector electrodes implemented with the top metal of the CMOS process, and they are capable of detecting charge transferred or induced on those electrodes with a very high sensitivity. This study also includes development of an external electronics containing ADC for analog to digital data conversion. This external circuitry is implemented on a PCB compatible with the Opal Kelly XM3010 FPGA that provides data storage and transfer to PC. The measured noise of the overall system is 6.7 e- (electrons), which can be shrunk down to even 5.1 e- with an over sampling rate. This kind of sensitivity performance is very suitable for DNA detection, as a single nucleotide of a DNA contains 1 or 2 e- and as 10 to 20 base pair long DNA&rsquo
s are usually used in microarray applications. The measured dynamic range of the system is 71 dB, in other words, at most 24603 e- per frame (20 ms) can be detected. The measured leakage is 31 e-/frame, but this does not have a dramatic effect on the sensitivity of the system, noting that the leakage is a predictable quantity. DNA detection tests are performed with the chip in addition to electronic performance measurements. The surface of the chip is covered with a nitride passivation layer to prevent the pixel crosstalk and is modified with an APTES polymer for suitable DNA immobilization. DNA immobilization and hybridization tests are performed with 5&rsquo
-TCTCACCTTC-3&rsquo
probe and its complementary 3&rsquo
-AGAGTGGAAG-5&rsquo
target sequences. Hybridization performed in 1 pM solution is shown to have a larger steady state leakage than the immobilization in a 13 µ
M solution, implying the ability to differentiate between the full match and full mismatch sequences. To best of our knowledge, the measured pM sensitivity has not yet been reported with any label free CMOS DNA microarrays in literature, and it is comparable with the sensitivity of techniques like QCM or the fluorescence imaging. The 1 pM sensitivity is not a theoretical limit of the sensor, since theoretically the sensitivity level of 6.7 e- can offer much better results, down to the aM level, as far as the noise of electronics is considered, nevertheless the sensitivity is expected to be limited by DNA immobilization and hybridization probabilities which are determined by the surface modification technique and applied protocol. Improving those can lead to much smaller detection limits, such as aM level as stated above.

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5

CICIOTTI, FULVIO. "Oscillator-Based CMOS Readout Interfaces for Gas Sensing Applications." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2019. http://hdl.handle.net/10281/241089.

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Il rilevamento di gas tossici e pericolosi è sempre stato necessario per motivi di sicurezza. Negli ultimi anni, in particolare, l’attenzione per lo sviluppo di sistemi portatili e a basso costo per il rilevamento dei gas è aumentata notevolmente. Questa tesi presenta circuiti CMOS versatili, veloci, ad alta precisione e basso consumo per applicazioni portatili di rilevamento di gas. I sensori target sono i Metal Oxide Semiconductor (MOX). Questi sensori sono ampiamente utilizzati per la loro intrinseca compatibilità con le tecnologie MEMS integrate. Le tipologie di lettura scelte sono basate su un oscillatore controllato dalla resistenza del sensore stessa, in modo da ottenere una conversione resistenza-tempo. Ciò garantisce un ampio range dinamico, una buona precisione e la capacità di far fronte alle grandi variazioni di resistenza del sensore MOX. Quattro diversi prototipi sono stati sviluppati e testati con successo. Sono state anche eseguite misurazioni chimiche con un vero sensore SnO2 MOX, validando i risultati ottenuti. Le misure hanno mostrato come il sensore e l’interfaccia sia in grado di rilevare fino a 5ppm di CO in aria. Gli ASIC sono in grado di coprire 128 dB di DR a 4Hz di output data rate digitale, o 148 dB a 0.4Hz, garantendo un errore relativo percentuale sempre migliore dello 0,4% (SNDR> 48 dB). Le prestazioni target sono state raggiunte con aggressive strategie di progettazione e ottimizzazione a livello di sistema. È stata utilizzata una tecnologia CMOS a 130nm fornita da Infineon Technologies AG. La scelta di un nodo tecnologico così scalato (rispetto alle tipiche implementazioni in questo settore) ha consentito di ridurre ulteriormente i consumi fino a circa 450 μA. Inoltre, questo lavoro introduce la possibilità di utilizzare la stessa architettura basata su oscillatore per eseguire la lettura di sensori capacitivi. I risultati delle misurazioni con sensori capacitivi MEMS hanno mostrato 116 dB di DR, con un SNR di 74 dB a 10Hz di velocità di trasmissione dati digitale. Le architetture sviluppate in questa tesi sono compatibili con gli standard moderni nel settore del rilevamento del gas per dispositivi portatili.
Detection of toxic and dangerous gases has always been a need for safety purpose and, in recent years, portable and low-cost gas sensing systems are becoming of main interest. This thesis presents fast, high precision, low-power, versatile CMOS interface circuits for portable gas sensing applications. The target sensors are Metal Oxide Semiconductor (MOX) sensors which are widely used due to their inherent compatibility with integrated MEMS technologies. The chosen readout typologies are based on the time-domain Resistor-Controlled Oscillator. This guarantees wide dynamic range, good precision and the ability to cope with the large MOX sensor resistance variations. Four different prototypes have been successfully developed and tested. Chemical measurements with a real SnO2 MOX sensor have also been performed to validate the results, showing a minimum CO detection capability in ambient air of 5 ppm. The ASICs are able to cover 128 dB of DR at 4 Hz of digital output data rate, or 148 dB at 0.4 Hz, while providing a relative error always better than 0.4% (SNDR >48 dB). Target performances have been achieved with aggressive design strategies and system-level optimization, and using a scaled (compared to typical implementations in this field) 130nm CMOS technology provided by Infineon Technologies AG. Power consumption is about 450 μA. Moreover, this work introduces the possibility to use the same oscillator-based architecture to perform capacitive sensors readout. Measurement results with capacitive MEMS sensors have shown 116 dB of DR in CSENS mode, with an SNR of 74 dB at 10 Hz of digital output data rate. The architectures developed in this thesis are compatible with the modern standards in the portable gas sensing industry.

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6

RESTA, FEDERICA. "Integrated Read-out Front-end for High-Energy Physics Experiments." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2017. http://hdl.handle.net/10281/158121.

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Le ricerche e le scoperte fatte nell'ambito della fisica sono fortemente dipendenti dall'efficienza e dall'affidabilità degli esperimenti ad alta energia. L'obiettivo principale è lo studio delle particelle che costituiscono la materia in termini di cariche elementari, loro interazioni e prodotti secondari che ne possono derivare. L'LHC (Large Hadron Collider) lavora al CERN ogni giorno con l’obiettivo di scoprire nuovi dettagli su particelle cariche come neutroni e Bosoni di Higgs. Queste sono generate e accelerate all’interno dell’LHC e vengono rilevate da opportuni detector organizzati in una struttura a shell. In questo modo, è possibile avere una caratterizzazione in termini di momento, carica elettrica, energia, tempo di volo e distanza associati alla particella rilevata. La progettazione dei rilevatori è importante come anche quella dell’elettronica vicina. Un grande esperimento richiede un duro lavoro di scienziati e ingegneri. Negli ultimi anni, l’elettronica è sempre più efficiente e compatta grazie alla sostituzione dei componenti discreti con circuiti integrati CMOS. La progettazione deve essere però fatta considerando sia le reti di interfacciamento con i sensori sia l’ambiente radiattivo circostante. Le radiazioni, infatti, possono modificare parzialmente o totalmente le performance e la scelta della tecnologia scalata può però essere di grande aiuto. In questo scenario, sono stati progettati, integrati e misurati 3 circuiti di lettura per esperimenti di fisica delle alte energie. 2 prototipi sono stati realizzati in tecnologia 130nm per l'esperimento ATLAS in collaborazione dell’Istituto Max-Plank di Monaco. Questi prototipi sono pensati per rilevare cariche fino a 100fC e convertirle in un segnale di tensione di ampiezza variabile che sarà processato in digitale per avere informazioni sull’istante di arrivo della carica e sulla sua intensità. A tal fine, gli integrati hanno uno stadio di discriminazione ed un Wilkinson ADC in grado di convertire in un tempo il segnale in tensione ricevuto. Il secondo prototipo è molto simile al primo. Esso è stato migliorato principalmente per poter essere più immune ai disturbi provenienti da masse e alimentazioni. Il terzo circuito presentato in questa tesi è un sistema di lettura progettato per Pixel detectors in tecnologia CMOS 28nm. Il canale integrato include un preamplificatore di carica con un comparatore in cascata. L'utilizzo della tecnologia 28nm con la sua ridotta alimentazione comporta una serie di difficoltà nella progettazione ma anche una maggiore resistenza alle radiazioni, consumi ridotti e una minor area occupata. I circuiti sono stati progettati per due differenti scenari in termini di capacità parassita del rilevatore, cariche di ingresso rilevabili, alimentazioni, soglie, consumi di potenza e rumore. In tutti i casi, però, i sistemi sono in grado di fornire le informazioni sulla carica rilevata in tempi relativamente rapidi (entro 25ns). Questo aspetto è molto importante e permette di evitare errori. Collisioni successive potrebbe causare segnali spuri e si potrebbe rilevare come unico evento due eventi distinti e consecutivi. Questo lavoro è organizzato come segue. La Parte I include una breve introduzione sull'intera attività svolta nei tre anni di attività di ricerca. La Parte II è dedicata alla descrizione semplificata del campo di applicazione ed ai target previsti per i prossimi esperimenti di fisica. In particolare, sono forniti alcuni dettagli su come l'elettronica può essere influenzata dalla presenza delle radiazioni. Le parti III e IV rappresentano il core della tesi perché mirano all'analisi dettagliata dei circuiti progettati e descritti precedentemente in maniera generica. L'analisi prevede una caratterizzazione completa degli integrati con simulazioni e misure. Infine, prima di concludere, la Parte V è dedicata alla pubblicazioni correlate all'attività di ricerca.
Physic researches and discoveries depend heavily from efficient and reliability of the High-Energy Physics (HEP) experiments. The main goal is to study the fundamental constituents of the matter in terms of elementary charge particles, their interactions and their secondary products. The Large Hadron Collider (LHC) at the CERN works every day to discover details on new charged particles as neutrinos and Higgs Bosons. Charges are generated and accelerated from beam collisions inside the LHC. Different detectors are organized in shell structures and are designed to detect few particles topology. Typically, the parameters useful to identify a charged particle are momentum, electrical charge, energy, time of flight and distance. Detectors design is important but it is enhanced from proper electronic readout systems. In the last years, electronics parts are more and more efficient and compact. CMOS integrated solution are preferred to discrete one allowing major reliability, cost reduction and performance improvement. The design is not trivial but not impossible. Some characteristics depend on the electronic designer and his capability to manage the external parasitic effects, as the parasitic capacitance of the connected detector. Unfortunately, phenomena as radiation effects on electronics must be taken in account but they are not completely eliminated. CMOS technology influences strongly the integrated circuit performance and radiation hardness. In this scenario, 3 readout frontend circuits for HEP experiments have been designed, integrated and measured. 2 of them represent 2 different prototypes realized in IBM 130nm technology for ATLAS experiment at CERN laboratory with Max-Plank Institute for Physics collaboration. They include an analog chain in cascade with a digital one. Input charges (up to 100fC) are detected and converted into voltage signals. Their amplitude are proportional to the input and are sent to the following digital part. The digital part provides information about arrival time and amount of the input charge. When the discriminator switches, an event is detected and the Wilkinson ADC starts the voltage-to-time conversion. The full chips have a JTAG section to manage all programmable parameters (i.e. thresholds, hysteresis, deadtime, etc.) The second prototype is designed improving the previous version in terms of supply rejection noise, deadtime range and hysteresis management. The third circuit presented in this thesis is the first readout frontend for Pixel detectors in 28nm technology. The channel includes a charge sensitive preamplifier with an inverter switched based comparator. Reduced supply voltage and 28nm technology imply some difficult in the design with a major tolerance to the radiations, a lower area occupancy and a lower power consumption. The circuits are been designed for 2 different scenarios in terms of detector parasitic capacitance, detectable input charges, supply voltage, threshold voltage, power consumption and noise. In overall cases, the integrated systems provide information about amount of detected input charge and arrival time within 25ns. This aspect is very important and allows avoiding mistakes. Successive collisions lead to spurious signals presence and a single detection could have information about two different events. Maintaining the processing time within 25ns, consecutive collisions are detected as different events. This work is organized as follows. Part I includes a brief summary of the entire work in order to fix the goals of my activities. Then, the Part II is dedicated on a simplified description of the application field and the next target of the future experiments. In particular, some details on the effects induced by the radiation to integrated electronic component are provided. Part III and Part IV represent the core, including 3 readout frontend circuits design and measurements. Finally, there are correlated publications and conclusions.

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7

Kramnik, Danielius. "Scaling trapped-ion quantum computers with CMOS-integrated state readout." Thesis, Massachusetts Institute of Technology, 2020. https://hdl.handle.net/1721.1/129912.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2020
Cataloged from student-submitted PDF of thesis.
Includes bibliographical references (pages 155-164).
Quantum information processing (QIP) has emerged as a powerful new computing paradigm as traditional Moore's law scaling slows due to skyrocketing costs of shrinking feature sizes, interconnects becoming the dominant source of energy consumption and delay as transistor critical dimensions fall below 10 nm, and power density limiting the activity factor in digital systems on a chip. Quantum computers use quantum states ("qubits") to store and manipulate information, giving them fundamental performance advantages over classical digital computers in certain applications. Although the feasibility of QIP has been proven for decades using smallscale (. 50 physical qubit) demonstration systems, the main problem is achieving scalability using existing designs.
Individual atomic ions trapped by electromagnetic fields in a vacuum and manipulated using lasers have been a leading candidate for a physical substrate for QIP since the beginning, but scaling has been limited by the bulky free-space optics that are traditionally used for state manipulation and readout. CMOS chips with integrated photonics, on the other hand, can solve the scalability issue by tightly packing photodetectors for state readout, classical computing resources for timing and control, and optical waveguides and modulators for state manipulation onto the same chip. In recent years researchers have fabricated a planar ion trap in a CMOS foundry and addressed individual ions using photonic components built on a custom-fabricated ion trap, but the problem of CMOS-integrated state readout remains unaddressed. Current approaches to state readout use a large external lens and photomultiplier tube to detect state-dependent ion fluorescence.
Instead, fabricating silicon photodetectors directly below the trap location would eliminate large light collection optics and enable scaling of readout to greater numbers of ions by closing the sensing-to-manipulation loop on-chip. This thesis addresses this issue by developing hardware and methodology to perform detailed characterization of single-photon avalanche diodes (SPADs) integrated on a CMOS ion trap at cryogenic temperatures, showing that state readout with speed and fidelity comparable to the bulk optics approach is possible. Based on our results, state readout experiments using a CMOS ion trap with integrated SPADs are presently underway at the MIT Lincoln Laboratory.
by Danielius Kramnik.
M. Eng.
M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science

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8

Shiah, Jack Chih-Chieh. "Design techniques for low-power low-noise CMOS capacitive-sensor readout circuits." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/54529.

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In recent years, the demand for low-cost, high performance, and miniature sized MEMS capacitive inertial sensors (accelerometer/gyroscope) has been steadily increasing. Use MEMS capacitive accelerometer as an example, for high precision applications, the resolution needs to be in the μg range at the frequency of interest. These high performance sensors are now been used in numerous applications that require more demanding specifications. For instance, they found their use in active suspension, adaptive brakes, alarm systems, tilt control, vibration, shock measurements, platform stabilization, inertial measurement units, inertial navigation/guidance, machine control, microgravity measurements, seismology, geophysical sensing, oil-field applications, earthquake detection, tactical missiles, robotics and minimally invasive surgery. The precision in a micro-sensory system is limited by the CMOS electronic interfaces, due to the often higher electrical noise associated with the circuits. Additionally, with the growing popularity for portable devices such as cellular phones and tablets, power consumption also becomes an important factor. Therefore, the dissertation discusses and presents several circuit design techniques that improve important system parameters such as noise and power. Moreover, a design flow is provided at the end of the thesis to demonstrate a systematic approach to design the sensor interface circuits. Three major readout circuit blocks have been designed, built, and tested. The first interface uses a circuit technique such that the overall system is insensitive to parasitic capacitances from the sensing nodes. Moreover, a calibration scheme is used to remove DC offset caused by sensor capacitance mismatch. The second interface uses two circuit design techniques called correlated level shifting (CLS) and chopper stabilization (CS) to reduce the noise and the finite gain error from the operational amplifier (op amp), thereby improving both the noise and power performance of the system. The final interface utilizes a modified CLS technique such that it also serves as a noise and power improving mechanism. The first two readout circuits have been tested and measured experimentally, while the third readout circuit is verified via post-layout simulation.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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9

Herrera, Hugo Daniel Hernández. "Noise and PSRR improvement technique for TPC readout front-end in CMOS. technology." Universidade de São Paulo, 2015. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-05072016-151016/.

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ALICE is one of four major experiments of particle accelerator LHC installed in the European laboratory CERN. The management committee of the LHC accelerator has just approved a program update for this experiment. Among the upgrades planned for the coming years of the ALICE experiment is to improve the resolution and tracking efficiency maintaining the excellent particles identification ability, and to increase the read-out event rate to 100 KHz. In order to achieve this, it is necessary to update the Time Projection Chamber detector (TPC) and Muon tracking (MCH) detector modifying the read-out electronics, which is not suitable for this migration. To overcome this limitation the design, fabrication and experimental test of new ASIC named SAMPA has been proposed . This ASIC will support both positive and negative polarities, with 32 channels per chip and continuous data readout with smaller power consumption than the previous versions. This work aims to design, fabrication and experimental test of a readout front-end in 130nm CMOS technology with configurable polarity (positive/negative), peaking time and sensitivity. The new SAMPA ASIC can be used in both chambers (TPC and MCH). The proposed front-end is composed of a Charge Sensitive Amplifier (CSA) and a Semi-Gaussian shaper. In order to obtain an ASIC integrating 32 channels per chip, the design of the proposed front-end requires small area and low power consumption, but at the same time requires low noise. In this sense, a new Noise and PSRR (Power Supply Rejection Ratio) improvement technique for the CSA design without power and area impact is proposed in this work. The analysis and equations of the proposed circuit are presented which were verified by electrical simulations and experimental test of a produced chip with 5 channels of the designed front-end. The measured equivalent noise charge was <550e for 30mV/fC of sensitivity at a input capacitance of 18.5pF. The total core area of the front-end was 2300?m × 150?m, and the measured total power consumption was 9.1mW per channel.
ALICE é um dos quatro grandes experimentos do acelerador de partículas LHC (Large Hadron Collider) instalado no laboratório europeu CERN. Um programa de atualizações desse experimento acaba de ser aprovado pelo comitê gestor do acelerador LHC. Dentro das atualizações planejadas para os próximos anos do experimento ALICE, está melhorar a resolução e eficiência de rastreamento de partículas produzidas em colisões entre íons pesados, mantendo a excelente capacidade de identificação de partículas para uma taxa de leitura de eventos significativamente maior da atual. Para se alcançar esse objetivo, entre outras ações, é preciso atualizar os detectores Time Projection Chamber (TPC), modificando a eletrônica de leitura de eventos, a qual não é adequada para esta migração. Para superar esta limitação tem sido proposto o projeto, simulação, fabricação, teste experimental e validação de um ASIC protótipo de aquisição de sinais e de processamento digital chamado SAMPA, que possa ser usado na eletrônica de detecção dos sinais no cátodo do TPC, que suporte polaridades negativas de tensão de entrada e leitura continua de dados, com 32 canais por chip, com menor consumo de potência comparado com a versão anterior do chip. Este trabalho tem como objetivo o projeto, fabricação, e teste experimental de um readout front-end em tecnologia CMOS 130nm, com polaridade configurable (positiva/ negativa), peaking time e sensibilidade, de forma que o novo SAMPA ASIC possa ser usada em ambos detectores. Para obter um ASIC integrando 32 canais por chip, o projeto do front-end proposto precisa ter baixa área e baixo consumo de potência, mas ao mesmo tempo requer baixo ruido. Neste sentido, uma nova técnica para melhorar a especificação de ruido e o PSRR (Power Supply Rejection Ratio) sem impacto no consumo de área e potência é proposta neste trabalho. A análise e as equações do circuito proposto são apresentadas as quais foram validadas por simulação e teste experimental de um circuito integrado com 5 canais do front-end projetado. O Equivalent Noise Charge medido foi <550e para uma capacitance do detector de 18.5pF. A área total do front-end foi de 2300?m × 150?m, e o consumo total de potencia medido foi de 9.1mW por canal.

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10

Trunk, Ulrich. "Development and characterisation of the radiation tolerant HELIX 128-2 readout chip for the HERA-B microstrip detectors." [S.l. : s.n.], 2001. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB9142825.

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11

Sonmez, Ugur. "Capacitive Cmos Readouts For High Performance Mems Accelerometers." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12613068/index.pdf.

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MEMS accelerometers are quickly approaching navigation grade performance and navigation market for MEMS accelerometer systems are expected to grow in the recent years. Compared to conventional accelerometers, these micromachined sensors are smaller and more durable but are generally worse in terms of noise and dynamic range performance. Since MEMS accelerometers are already dominant in the tactical and consumer electronics market, as they are in all modern smart phones today, there is significant demand for MEMS accelerometers that can reach navigation grade performance without significantly altering the developed process technologies. This research aims to improve the performance of previously fabricated and well-known MEMS capacitive closed loop &Sigma
&Delta
accelerometer systems to navigation grade performance levels. This goal will be achieved by reducing accelerometer noise level through significant changes in the system architecture and implementation of a new electronic interface readout ASIC. A flexible fourth order &Sigma
&Delta
modulator was chosen as the implementation of the electro-mechanical closed loop system, and the burden of noise shaping in the modulator was shifted from the mechanical sensor to the programmable electronic readout. A novel operational transconductance amplifier (OTA) was also designed for circuit implementation of the electronic interface readout. Design and fabrication of the readout was done in a standard 0.35 µ
m CMOS technology. With the newly designed and fabricated readout, single-axis accelerometers were implemented and tested for performance levels in 1g range. The implemented system achieves 5.95 µ
g/sqrt Hz, 6.4 µ
g bias drift, 131.7 dB dynamic range and up to 37.2 g full scale range with previously fabricated dissolved epitaxial wafer process (DEWP) accelerometers in METU MEMS facilities. Compared to a previous implementation with the same accelerometer element reporting 153 µ
g/sqrtHz, 50 µ
g bias drift, 106.8 dB dynamic range and 33.5 g full scale range
this research reports a 25 fold improvement in noise, 24 dB improvement in dynamic range and removal of the deadzone region.

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12

Sánchez, Chiva Josep Maria. "High performance readout circuits and devices for Lorentz force resonant CMOS-MEMS magnetic sensors." Doctoral thesis, Universitat Politècnica de Catalunya, 2020. http://hdl.handle.net/10803/671068.

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In the last decades, sensing capabilities of martphones have greatly improved since the early mobile phones of the 90’s. Moreover, wearables and the automotive industry require increasing electronics and sensing sophistication. In such echnological advance, Micro Electro Mechanical Systems (MEMS) have played an important role as accelerometers and gyroscopes were the first sensors based on MEMS technology massively introduced in the market. In contrast, it still does not exist a commercial MEMS-based compass, even though Lorentz force MEMS magnetometers were first proposed in the late 90’s. Currently, Lorentz force MEMS magnetometers have been under the spotlight as they can offer an integrated solution to nowadays sensing power. As a consequence, great advances have been achieved, but various bottlenecks limit the introduction of Lorentz force MEMS compasses in the market. First, current MEMS magnetometers require high current consumption and high biasing voltages to achieve good sensitivities. Moreover, even though devices with excellent performance and sophistication are found in the literature, there is still a lack of research on the readout electronic circuits, specially in the digital signal processing, and closed loop control. Second, most research outcomes rely on custom MEMS fabrication rocesses to manufacture the devices. This is the same approach followed in current commercial MEMS, but it requires different fabrication processes for the electronics and the MEMS. As a consequence, manufacturing cost is high and sensor performance is affected by the MEMS-electronics interface parasitics. This dissertation presents potential solutions to these issues in order to pave the road to the commercialization of Lorentz force MEMS compasses. First, a complete closed loop, digitally controlled readout system is proposed. The readout circuitry, implemented with off-the-shelf commercial components, and the digital control, on an FPGA, are proposed as a proof of concept of the feasibility, and potential benefits, of such architecture. The proposed system has a measured noise of 550 nT / vHz while the MEMS is biased with 300 µA rms and V = 1 V . Second, various CMOS-MEMS magnetometers have been designed using the BEOL part of the TSMC and SMIC 180 nm standard CMOS processes, and wet and vapor etched. The devices measurement and characterisation is used to analyse the benefits and drawbacks of each design as well as releasing process. Doing so, a high volume manufacturing viability can be performed. Yield values as high as 86% have been obtained for one device manufactured in a SMIC 180 nm full wafer run, having a sensitivity of 2.82 fA/µT · mA and quality factor Q = 7.29 at ambient pressure. While a device manufactured in TSMC 180 nm has Q = 634.5 and a sensitivity of 20.26 fA/µT ·mA at 1 mbar and V = 1 V. Finally, an integrated circuit has been designed that contains all the critical blocks to perform the MEMS signal readout. The MEMS and the electronics have been manufactured using the same die area and standard TSMC 180 nm process in order to reduce parasitics and improve noise and current consumption. Simulations show that a resolution of 8.23 µT /mA for V = 1 V and BW = 10 Hz can be achieved with the designed device.
En les últimes dècades, tenint en compte els primers telèfons mòbils dels anys 90, les capacitats de sensat dels telèfons intel·ligents han millorat notablement. A més, la indústria automobilística i de wearables necessiten cada cop més sofisticació en el sensat. Els Micro Electro Mechanical Systems (MEMS) han tingut un paper molt important en aquest avenç tecnològic, ja que acceleròmetres i giroscopis varen ser els primers sensors basats en la tecnologia MEMS en ser introduïts massivament al mercat. En canvi, encara no existeix en la indústria una brúixola electrònica basada en la tecnologia MEMS, tot i que els magnetòmetres MEMS varen ser proposats per primera vegada a finals dels anys 90. Actualment, els magnetòmetres MEMS basats en la força de Lorentz són el centre d'atenció donat que poden oferir una solució integrada a les capacitats de sensat actuals. Com a conseqüència, s'han aconseguit grans avenços encara que existeixen diversos colls d'ampolla que encara limiten la introducció al mercat de brúixoles electròniques MEMS basades en la força de Lorentz. Per una banda, els agnetòmetres MEMS actuals necessiten un consum de corrent i un voltatge de polarització elevats per aconseguir una bona sensibilitat. A més, tot i que a la literatura hi podem trobar dispositius amb rendiments i sofisticació excel·lents, encara existeix una manca de recerca en el circuit de condicionament, especialment de processat digital i control del llaç. Per altra banda, moltes publicacions depenen de processos de fabricació de MEMS fets a mida per fabricar els dispositius. Aquesta és la mateixa aproximació que s'utilitza actualment en la indústria dels MEMS, però té l'inconvenient que requereix processos de fabricació diferents pels MEMS i l’electrònica. Per tant, el cost de fabricació és alt i el rendiment del sensor queda afectat pels paràsits en la interfície entre els MEMS i l'electrònica. Aquesta tesi presenta solucions potencials a aquests problemes amb l'objectiu d'aplanar el camí a la comercialització de brúixoles electròniques MEMS basades en la força de Lorentz. En primer lloc, es proposa un circuit de condicionament complet en llaç tancat controlat digitalment. Aquest s'ha implementat amb components comercials, mentre que el control digital del llaç s'ha implementat en una FPGA, tot com una prova de concepte de la viabilitat i beneficis potencials que representa l'arquitectura proposada. El sistema presenta un soroll de 550 nT / vHz quan el MEMS està polaritzat amb 300 µArms i V = 1 V . En segon lloc, s'han dissenyat varis magnetòmetres CMOS-MEMS utilitzant la part BEOL dels processos CMOS estàndard de TSMC i SMIC 180 nm, que després s'han alliberat amb líquid i gas. La mesura i caracterització dels dispositius s’ha utilitzat per analitzar els beneficis i inconvenients de cada disseny i procés d’alliberament. D'aquesta manera, s'ha pogut realitzar un anàlisi de la viabilitat de la seva fabricació en massa. S'han obtingut valors de yield de fins al 86% per un dispositiu fabricat amb SMIC 180 nm en una oblia completa, amb una sensibilitat de 2.82 fA/µT · mA i un factor de qualitat Q = 7.29 a pressió ambient. Per altra banda, el dispositiu fabricat amb TSMC 180 nm presenta una Q = 634.5 i una sensibilitat de 20.26 fA/µT · mA a 1 mbar amb V = 1 V. Finalment, s'ha dissenyat un circuit integrat que conté tots els blocs per a realitzar el condicionament de senyal del MEMS. El MEMS i l'electrònica s'han fabricat en el mateix dau amb el procés estàndard de TSMC 180 nm per tal de reduir paràsits i millorar el soroll i el consum de corrent. Les simulacions mostren una resolució de 8.23 µT /mA amb V = 1 V i BW = 10 Hz pel dispositiu dissenyat.

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13

PEZZOTTA, ALESSANDRO. "Design and Development of an Integrated Readout System for the Triple-GEM Detector." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2015. http://hdl.handle.net/10281/95360.

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One of the most active research branches in GEM detectors is frontend performance improvement, employing dedicated CMOS integrated solutions, suitable to sustain overall count rate while reducing power consumption, and at the same time increasing system portability. In fact, the development of an ASIC can afford several advantages with respect to other common solutions, i.e. PCBs. For instance, the inclusion of a digital-based data elaboration can greatly increase performance reducing the overall readout system complexity, limiting the necessity of off-chip devices like FPGAs or standard microcontrollers. Then, silicon implementation allows dedicated circuital/system-level choices, optimizing the system to cope with detector performance. Improvements in portability are also crucial, since the detector pixelated output includes hundreds of pads, manufactured in different size factors. These represent a primary issue in readout design, in terms of noise and efficiency. In this scenario, two prototypes with different targets have been developed. The aim of GEMMA (GEM Mixed-signal Asic) is to measure the arrival time and the amount of charge from the Triple-GEM detector. It composes of 8 detecting channels including a Charge Sensitive Preamplifier (CSP) and a Charge-Time Converter (CTC). It is able to manage up to 15pF of pixel parasitic capacitance. The embedded calibration system tunes all channels’ CSP feedback capacitances, to match the target sensitivity of 0.5mV/fC within a 5% tolerance. The CTC converts the CSP output voltage signal into digital domain. In detail, the CTC gets the CSP output and generates two logic output signals. The first, named Charge-Time Signal (CTS), includes information into its time duration, directly proportional to the input charge. The second, named Event Detection Signal (EDS) gives information about the arrival time of the incident particle. In channel 6, for prototyping concern, the CTS is also converted into a 7-bit digital word by a 250MHz clocked counter (the clock is off-chip). In order to control and stabilize comparators performance, an effective circuital block named Auto-Zero acts as an adjustable level shifter for the CSP output signal, adapting it separately for the two comparators. The shifting is set by a 4-bit logarithmic DAC, representing the actual channel threshold for measurements. The device is able to sustain a count rate up to 4Mcps consuming 3.8mW/ch. On the other hand, GEMINI (GEM INtegrated Interface) target application includes time-of-flight and counting measurements, with the option to make spectroscopic analysis externally via the analog preamplifier output. The GEMINI has a mixed signal capability, with analog and digital outputs available in parallel for each one of the 16 channels included, also with automatic on chip calibration acting on channel capacitors, keeping performance constant against CMOS process, supply voltage and environmental variations. This allows managing a count rate up to 5Mcps and an input pad capacitance up to 40pF, while consuming 2.7mW/ch. As a whole, GEMINI channels include a charge-sensitive preamplifier (CSP) with a sensitivity of 1mV/fC. Then, a discriminator (DISC) with a channel-specific threshold set by a 9 bit R-2R Resistive DAC, generates the Event Detection Signal (EDS), then converted to LVDS. The CSP composes of a Class-A Miller Opamp with a capacitor and a switch in parallel connected in feedback. The reset generation is event triggered, without the inclusion of a clock signal.

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Vatte, Madhu Latha Reddy. "Readout Circuitry for a Logarithmic CMOS Active Pixel Sensor That Facilities High Speed Image Processing." University of Akron / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=akron1278549382.

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15

Eminoglu, Selim. "Uncooled Infrared Focal Plane Arrays With Integrated Readout Circuitry Using Mems And Standard Cmos Technologies." Phd thesis, METU, 2003. http://etd.lib.metu.edu.tr/upload/4/698597/index.pdf.

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This thesis reports the development of low-cost uncooled microbolometer focal plane arrays (FPAs) together with their integrated readout circuitry for infrared night vision applications. Infrared microbolometer detectors are based on suspended and thermally isolated p+-active/n-well diodes fabricated using a standard 0.35 µ
m CMOS process followed by a simple post-CMOS bulk-micromachining process. The post-CMOS process does not require any critical lithography or complicated deposition steps
and therefore, the FPA cost is reduced considerably. The integrated readout circuitry is developed specially for the p+-active/n-well diode microbolometers that provides lower input referred noise voltage than the previously developed microbolometer readout circuits suitable for the diode type microbolometers. Two FPAs with 64 ×
64 and 128 ×
128 array formats have been implemented together with their low-noise integrated readout circuitry. These FPAs are first of their kinds where such large format uncooled infrared FPAs are designed and fabricated using a standard CMOS process. The fabricated detectors have a temperature coefficient of -2 mV/K, a thermal conductance value of 1.55 ×
10-7 W/K, and a thermal time constant value of 36 ms, providing a measured DC responsivity (&
#8476
) of 4970 V/W under continuous bias. The measured detector noise is 0.69 µ
V in 8 kHz bandwidth, resulting a measured detectivity (D*) of 9.7 ×
108 cm&
#8730
Hz/W. The 64 ×
64 FPA chip has 4096 pixels scanned by an integrated 16-channel parallel readout circuit composed of low-noise differential transconductance amplifiers, switched capacitor integrators, and sample-and-hold circuits. It measures 4.1 mm ×
5.4 mm, dissipates 25 mW power, and provides an estimated NETD value of 0.8 K at 30 frames/sec (fps) for an f/1 optics. The measured uncorrected voltage non-uniformity for the 64 ×
64 array after the CMOS fabrication is 0.8 %, which is reduced further down to 0.2 % for the 128 ×
128 array using an improved FPA structure that can compensate for the fixed pattern noise due to the FPA routing. The 128 ×
128 FPA chip has 16384 microbolometer pixels scanned by a 32-channel parallel readout circuitry. The 128 ×
128 FPA measures 6.6 mm ×
7.9 mm, includes a PTAT temperature sensor and a vacuum sensor, dissipates 25 mW power, and provides an estimated NETD value of 1 K at 30 fps for an f/1 optics. These NETD values can be decreased below 350 mK with further optimization of the readout circuit and post-CMOS etching steps. Hence, the proposed method is very cost-effective to fabricate large format focal plane arrays for very low-cost infrared imaging applications.

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16

Zhang, Jianbo. "Readout Circuits for a Z-axis Hall Sensor with Sensitivity Drift Calibration." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175785.

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Hall effect magnetic sensors have gradually gained dominance in the market of magnetic sensors during the past decades. The compatibility of Hall sensors with conventional CMOS technologies makes monolithic Hall sensor microsystem possible and economic. An attractive application is the contactless current sensor by using Hall sensors to measure the magnetic field generated by the electrical current. However, Hall sensors exhibit several non-idealities, i.e., offset, noise and sensitivity drift, which limit their precision. Therefore, effective techniques to reduce these imperfections are desired. This thesis presents the design of a new readout scheme for Hall magnetic sensor with low offset, low noise and low sensitivity drift. The Hall sensor is realized in N-well as Hall plate and modeled in Verilog-A for the purpose of co-simulation with interface circuits. The self-calibrated system is composed of two identical Hall plates, preamplifiers and a first-order ΣΔ modulator, which can be fully integrated monolithically. Four-phase spinning current technique and chopper stabilization technique have been employed to reduce the offset and 1/fnoise of Hall platesand OTA, respectively. Integrated coils are used to generate the reference magnetic field for calibration. The preamplifiers amplify the signal and separate the Hall voltage and reference voltage. The ΣΔ modulator reduces the thermal drift by using Hall voltage as the modulator input and reference voltage as the DAC output. This new calibration technique also compensates the thermal drifts of the biasing current and readout circuits. The overall system is implemented in NXP140nm CMOS process with 1.8V supply. The Virtuoso/Spectre simulation results show residual drifts lower than 10ppm/ ̊C, which are 3-5 times lower than the state of the art. The input magnetic field and temperature range are ±100mT and -40 ̊C to 120 ̊C, respectively.

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17

Abdalla, Munir. "Pixel Detectors and Electronics for High Energy Radiation Imaging." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3206.

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Hausmann, Joachim. "Development of a low noise integrated readout electronic for pixel detectors in CMOS technology for a Compton camera." [S.l.] : [s.n.], 2002. http://deposit.ddb.de/cgi-bin/dokserv?idn=964928701.

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Chesler, Troy Alexander. "Design of pixel level CMOS readout circuitry for continuous bias uncooled bolometric long wave infrared focal plane arrays." College Park, Md. : University of Maryland, 2004. http://hdl.handle.net/1903/2126.

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Thesis (M.S.) -- University of Maryland, College Park, 2004.
Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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Michal, Vratislav. "Design of CMOS analog integrated circuits as readout electronics for High-TC superconductor and semiconductor terahertz bolometric sensors." Phd thesis, Université Pierre et Marie Curie - Paris VI, 2006. http://tel.archives-ouvertes.fr/tel-00417838.

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Cette thèse porte sur la conception d'un circuit intégré CMOS pour l'électronique de lecture de capteurs bolométriques à base de semiconducteurs ou supraconducteurs haute-température. Dans ce manuscrit, une chaîne de traitement du signal est étudiée. Elle est composée d'un amplificateur différentiel à gain fixé pour des températures de 40 à 400K, ainsi que d'un filtre de fréquence passe-bas actif à haute dynamique. Une architecture optimale d'amplificateur est définie sans contre-réaction, permettant d'atteindre une large bande passante (17MHz pour un gain de 40dB), une consommation réduite (Iq = 2mA) et une haute impédance d'entrée. Afin de fixer le gain avec précision dans la structure CMOS, deux méthodes différentes sont présentées et vérifiées sur un circuit intégré. Par la suite, le comportement des filtres dans la bande d'atténuation est étudié afin d'augmenter la fréquence de coupure maximale. Deux structures avec une faible influence des éléments actifs « réels » sont conçues: le filtre Sallen-Key amélioré et la structure basée sur un convoyeur du courant CCII-. Enfin, nous présentons un CCII- intégré en CMOS ayant une très faible impédance de sortie.

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21

Fang, Xiaochao. "Design and integration of a low-noise readout chain in CMOS technology for APD-based sall-animal PET imaging." Strasbourg, 2011. http://www.theses.fr/2011STRA6021.

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Cette thèse présente mon travail de recherche sur la conception d'une chaîne de lecture dédiée à la TEP (Tomographie à Emission de Positons) fondée sur l'APD (Avalanche Photo Diode) pour les petits animaux. Le laboratoire IPHC (Institut Pluridisciplinaire Hubert Curien, UMR 7178) est en train de développer un système d'imagerie multimodale dénommé AMISSA (A Multimodality Imaging System for Small Animal) dédié au petit animal. L'AMISSA est composé par un micro imageur TDMX (micro TomoDensitoMétrie X), un micro imageur TEMP (Tomographie d'Emission Mono Photonique) et un micro imageur TEP. Le TDMX et le TEMP ont été réalisés. L'imagerie TEP permettra d'ajouter la modalité manquante au banc d'imagerie. Deux prototypes ont été développés afin de réaliser la chaîne de lecture complète dédiée à l'APD. Le premier prototype APD Chip est un circuit bas bruit de dix voies. Chaque voie est constituée d'un CSA (Charge Sensitive Amplifier), d'un CR-(RC)2 « shaper » et d'un « buffer » analogique. Le test montre que l'ENC (Equivalent Noise Charge) à l'entrée est égal à 275 ± 2 e- + 10 e-/pF pour un « shaping time » de 136 ns. Le deuxième prototype PETROC est un microcircuit mixte qui comprend un PDH (Peak Detect and Hold) d'huit voies et un TDC (Time-to-Digital Converter) de cinq voies. L'erreur sur le pic détecté est inférieure à 0. 7%. Une interpolation multi-niveaux est incluse dan la conception du TDC afin d'obtenir une plage de mesure de 10 µs et un pas de 20 ps. Dans ce texte, des analyses théoriques et des prototypes sont présentés, ainsi que la conception des circuits. Les résultats des tests du premier prototype sont également exposés
This thesis presents my research work on the conception of a readout chain dedicated to the APD (Avalanche Photo Diodes)-based PET (Positron Emission Tomography) imaging for small animal. The PET imaging allows the conjunction of its modality with the micro CT (X-ray Computerized Tomography) and micro SPECT (Single Photon Emission Computed Tomography) imaging which have been developed at IPHC (Institut Pluridisciplinaire Hubert Curien, UMR 7178). These three imaging compose a multi-modality imaging system for small animal (AMISSA). Two prototypes have been designed in order to finally realize the complete readout chain. The first one (called APD Chip) is a ten-channel low noise front-end circuit. Every channel consists of a Charge Sensible Amplifier (CSA), a CR-(RC)2 shaper, and an analogue buffer. The Equivalent Noise Charge (ENC) in input from test is equal to 275 ± 2 e- + 10 e- /pF for a shaping time of 136 ns. The second prototype PETROC is a mixed circuit. It comprises an eight-channel Peak Detect and Hold (PDH) circuit and a five-channel Time-to-Digital Converter (TDC). The simulation shows that the error is less than 0. 7% over the whole dynamic range. A multi-level interpolation was implemented in the TDC design to obtain a measurement range up to 10 µs and a bin size of 20 ps. In this thesis, the prototypes are presented for both their theoretical analyses and their circuit designs. The test results of the first prototype are also presented

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22

Karagounis, Michael Athanassios [Verfasser]. "Analog Integrated CMOS Circuits for the Readout and Powering of Highly Segmented Detectors in Particle Physics Applications / Michael Athanassios Karagounis." Hagen : Fernuniversität Hagen, 2010. http://d-nb.info/1009326414/34.

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23

Gao, Wu. "Design of a monolithic front-end readout chip with a high-precision TDC and a time-based ADC in CMOS technology for PET imaging." Strasbourg, 2011. http://www.theses.fr/2011STRA6002.

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La technique de tomographie à émission de positrons (TEP) se présente comme une imagerie non invasive moléculaire mesurant la biodistribution in vivo d'agents etiquettes pour l'imagerie avec des radioisotopes. Le principe se base sur la détection des radiations gamma est la désintégration de positrons émis par le radiotraceur. Cette thèse porte sur la conception d'un ASIC de lecture dédié au photodétecteur multi-canaux (MCP, Photonis Corp. ) munis de cristaux LYSO. Dans cette étude, les cristaux sont orientés dans la direction axiale mesurés des deux côtés par des canaux individuels de photo détecteurs permettant d'obtenir une résolution spatiale et une efficacité de détection indépendantes les unes des autres. Depuis 2007, trois prototypes ont été conçus et fabriqués en technologies CMOS 0,35 m. Il s'agit d'un circuit analogique "front-end" de traitement du signal, d'un CTN basé sur des techniques de compteur et de matrice des DLLs, et enn d'un CAN multi-canaux basé sur le temps à haute résolution. Pour les futures conceptions, l'intégration des circuits de lecture en mode courant et de convertisseur de données basé sur le temps sera effectuée en fonction des applications spécifiques. Parce que la technologie CMOS a développé à l'ordre de nanomètres, les considérations de conception pour les dés en raison de l'échelle de la technologie seront prises en compte
Positron Emission Tomography (PET) is a noninvasive molecular imaging that measures in vivo biodistribution of imaging agents labeled with positron-emitting radionuclides. The physical principle is based on the detection of gamma radiations resulting from the disintegration of positrons emitted by the radiotracer. This thesis focuses on the design of a full-custom front-end readout ASIC dedicated to the Photonics Corp. Multi-channel plate photodetector (MCP) with LYSO crystals. In this study, the crystals are oriented in the axial direction and read out on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both the energy quantity and the time information should be measured. Three prototype chips are designed in AMS 0. 35 μm CMOS technology. They include front-end analog signal processing circuits, a high-precision multi-channel time-to-digital converter, and a high-resolution multi-channel time-based ADC. For the future developments, the performance evaluation of a monolithic front-end readout ASIC including front-end analog processing circuits, multi-channel TDC circuits and proposed time-based ADC circuits will be carried out. Moreover, since CMOS technology scaling has moved the process node to nanometers, design considerations for the challenges due to technology scaling will be taken into account

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24

Egel, Eugen [Verfasser], Markus [Akademischer Betreuer] Becherer, György [Gutachter] Csaba, and Markus [Gutachter] Becherer. "Design of a 9-50 GHz CMOS Integrated Readout Circuitry for Spin Wave Characterization / Eugen Egel ; Gutachter: György Csaba, Markus Becherer ; Betreuer: Markus Becherer." München : Universitätsbibliothek der TU München, 2020. http://d-nb.info/1217783784/34.

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25

Amhaz, Hawraa. "Traitement d'images bas niveau intégré dans un capteur de vision CMOS." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00838399.

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Le traitement d'images classique est basé sur l'évaluation des données délivrées par un système à basede capteur de vision sous forme d'images. L'information lumineuse captée est extraiteséquentiellement de chaque élément photosensible (pixel) de la matrice avec un certain cadencementet à fréquence fixe. Ces données, une fois mémorisées, forment une matrice de données qui estréactualisée de manière exhaustive à l'arrivée de chaque nouvelle image. De fait, Pour des capteurs àforte résolution, le volume de données à gérer est extrêmement important. De plus, le système neprend pas en compte le fait que l'information stockée ai changé ou non par rapport à l'imageprécédente. Cette probabilité est, en effet, assez importante. Ceci nous mène donc, selon " l'activité "de la scène filmée à un haut niveau de redondances temporelles. De même, la méthode de lectureusuelle ne prend pas en compte le fait que le pixel en phase de lecture a la même valeur ou non que lepixel voisin lu juste avant. Cela rajoute aux redondances temporelles un taux de redondances spatialesplus ou moins élevé selon le spectre de fréquences spatiales de la scène filmée. Dans cette thèse, nousavons développé plusieurs solutions qui visent contrôler le flot de données en sortie de l'imageur enessayant de réduire les redondances spatiales et temporelles des pixels. Les contraintes de simplicité etd'" intelligence " des techniques de lecture développées font la différence entre ce que nousprésentons et ce qui a été publié dans la littérature. En effet, les travaux présentés dans l'état de l'artproposent des solutions à cette problématique, qui en général, exigent de gros sacrifices en terme desurface du pixel, vu qu'elles implémentent des fonctions électroniques complexes in situ.Les principes de fonctionnement, les émulations sous MATLAB, la conception et les simulationsélectriques ainsi que les résultats expérimentaux des techniques proposées sont présentés en détailsdans ce manuscrit.

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26

Krylov, Vladyslav. "Versatile low-energy electron source at the PHIL accelerator to characterise Micromegas with integrated Timepix CMOS readout and study dE/dx for low energy electrons." Thesis, Université Paris-Saclay (ComUE), 2018. http://www.theses.fr/2018SACLS169/document.

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Dans le cadre de cette thèse, la conception, la construction et la mise en service de la plateforme de test LEETECH ont été réalisées. La performance de LEETECH, y compris le mode de fonctionnement à faible multiplicité a été démontrée. En fournissant des paquets d’électrons avec une énergie ajustable jusqu’à 3.5 MeV, une multiplicité ajustable à partir d’électrons simples et une durée des paquets jusqu’à 20ps, LEETECH prend sa place entre les faisceaux tests de hautes énergies et de coûts élevés d’un part et l’utilisation de sources radioactifs d’autre part. Dans la région, qui correspond à la particule d’ionisation minimale, la plateforme offre aux détecteurs de traces les conditions similaires aux celles de faisceaux des hautes énergies. Le mode de fonctionnement à faible multiplicité a été étudié en utilisant un détecteur diamant de grande surface. En plus une capacité d’un capteur diamant de résoudre des paquets à faible nombre des particules a été démontrée. Dans le cadre du développement de la chambre à projection temporelle (TPC) pour le projet ILC, une session de test a été dédiée à un détecteur Micromegas/InGrid de large surface. Pour la première fois les pertes d’énergie par un électron dans un mélange de gaz basée sur Helium ont été mesurées pour une énergie de quelques MeV. La résolution en dE/dx et un algorithme pour la reconstruction de traces ont été développés. Une caractérisation préliminaire du quartz barre lu par MCPPMT – un candidat pour le détecteur temps-de- vol (TOF) avec la mission de l’identification des hadrons chargés dans le futur usine tau-charm HIEPA – a été accomplie. La résolution temporelle de 50 ps obtenue pour le détecteur étudié met cette technologie prometteuse pour les études plus approfondies
Within the present thesis the design, construction and commissioning of a new test beam facility LEETECH have been performed. Performance of the new facility, including low-multiplicity operation mode has been demonstrated. A number of interesting detector tests, including large-area diamond, Micromegas/InGrid and quartz bar detectors have been performed. Development of new detector technologies for future high-energy physics collider experiments calls for selection of versatile test beam facilities, permitting to choose or adjust beam parameters such as particles type, energy and beam intensity, are irreplaceable in characterization and tests of developed instruments. Major applications comprise generic detector R&D, conceptual design and choice of detector technologies, technical design, prototypes and full-scale detector construction and tests, detector calibration and commissioning. A new test beam facility LEETECH (Low Energy Electron TECHnique) was designed, constructed and commissioned in LAL (Orsay) as an extension of existing PHIL accelerator. Providing electron bunches of adjustable energy (up to 3.5 MeV), intensity (starting from a few particles per bunch) and bunch time duration (down to 20 ps), LEETECH fills the gap between high-cost high-energy test beam facilities and use of radioactive sources. Covering a minimum-ionization particles region (electrons of energy above 1.6 MeV), LEETECH provides for tracking detectors similar conditions as high-energy facilities. Using LEETECH as an electron source, several types of detectors were investigated in order to study their performance or applications, also providing a characterization of the LEETECH performance. First studies of the LEETECH facility were performed with a plastic scintillator coupled to the Micro-channel plate photomultiplier. A low-multiplicity mode was investigated using the diamond sensor, at the same time demonstrating its ability to resolve bunches consisting of a few particles. In framework of Time Projection Chamber development for the ILC project, a session dedicated to a large-area Micromegas/InGrid module was performed. For the first time the electron energy losses in Helium-based gas mixtures were measured for the energies of few MeV. The dE/dx resolution was obtained and track reconstruction algorithm was developed. Being a candidate for the time-of- flight detector of the BESIII upgrade and future HIEPA tau-charm factories, a preliminary characterization of the quartz bar performed. The time resolution of the detector module of 50 ps was obtained, giving a promising results for the further detector studies

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Fu, Yunan. "Développement de capteurs à pixels CMOS pour un détecteur de vertex adapté au collisionneur ILC." Phd thesis, Université de Strasbourg, 2012. http://tel.archives-ouvertes.fr/tel-00869940.

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Le travail de thèse a consisté, en priorité, à s'approprier les technologies d'intégration verticale en usage dans l'industrie pour réaliser des mémoires à plusieurs étages, et à en évaluer l'apport pour les capteurs à pixel CMOS (CPS). Cette approche s'appuie sur la capacité de l'industrie à interconnecter des puces amincies empilées les unes sur les autres. Elle ouvre la perspective d'associer plusieurs microcircuits superposés à un même pixel, en dépits de sa taille réduite. L'interconnexion est donc réalisée au niveau du pixel. Ce saut technologique permet de lever la majorité des obstacles à l'obtention de performances optimales des CPS. On peut en particulier combiner des puces réalisées dans des technologies CMOS très différentes, chacune optimale pour une fonctionnalité précise. La collection des charges du signal peut ainsi être réalisée dans une couche dédiée, les microcircuits de conditionnement analogique des signaux peuvent être concentrés dans une autre couche, une troisième couche pouvant héberger les parties numériques assurant la compression puis la transmission des signaux, etc. Ce progrès se traduit notamment par la possibilité de combiner haute résolution spatiale et lecture rapide, avec une amélioration probable de la tolérance aux rayonnements intenses.On s'affranchit de cette manière des limitations provenant des paramètres de fabrication des fondeurs, qui ne permettent pas à l'heure actuelle, de pleinement exploiter le potentiel des CPS à l'aide d'une technologie CMOS unique.

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Amin, Farooq ul. "On the Design of an Analog Front-End for an X-Ray Detector." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-21395.

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Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible.

A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector.

The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.

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29

Corrin, Emlyn Peter. "Development of digital readout electronics for the CMS tracker." Thesis, Imperial College London, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.401285.

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Sachdeva, Rajiv. "Signal processing algorithms and radiation hard electronics for the CMS tracking detector." Thesis, Imperial College London, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.318228.

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Marefat, Fatemeh. "Toward Cuffless Blood Pressure Monitoring: Integrated Microsystems for Implantable Recording of Photoplethysmogram." Case Western Reserve University School of Graduate Studies / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=case1595441087168539.

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32

Bainbridge, Robert John. "Influence of highly ionising events on the CMS APV25 readout chip." Thesis, Imperial College London, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.409640.

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Noah, Messomo Etam Albert. "Radiation and temperature effects on the APV25 readout chip forthe CMS tracker." Thesis, Imperial College London, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.401673.

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34

Leaver, James David George. "Testing and development of the CMS silicon tracker front end readout electronics." Thesis, Imperial College London, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.429876.

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Troska, Jan Kevin. "Radiation-hard optoelectronic data transfer for the CMS tracker." Thesis, Imperial College London, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313621.

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36

Braga, Davide. "Development of the readout electronics for the high luminosity upgrade of the CMS outer strip tracker." Thesis, Imperial College London, 2016. http://hdl.handle.net/10044/1/33725.

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The High-luminosity upgrade of the LHC will deliver the dramatic increase in luminosity required for precision measurements and to probe Beyond the Standard Model theories. At the same time, it will present unprecedented challenges in terms of pileup and radiation degradation. The CMS experiment is set for an extensive upgrade campaign, which includes the replacement of the current Tracker with another all-silicon detector with improved performance and reduced mass. One of the most ambitious aspects of the future Tracker will be the ability to identify high transverse momentum track candidates at every bunch crossing and with very low latency, in order to include tracking information at the L1 hardware trigger stage, a critical and effective step to achieve triggers with high purity and low threshold. This thesis presents the development and the testing of the CMS Binary Chip 2 (CBC2), a prototype Application Specific Integrated Circuit (ASIC) for the binary front-end readout of silicon strip detectors modules in the Outer Tracker, which also integrates the logic necessary to identify high transverse momentum candidates by correlating hits from two silicon strip detectors, separated by a few millimetres. The design exploits the relation between the transverse momentum and the curvature in the trajectory of charged particles subject to the large magnetic field of CMS. The logic which follows the analogue amplification and binary conversion rejects clusters wider than a programmable maximum number of adjacent strips, compensates for the geometrical offset in the alignment of the module, and correlates the hits between the two sensor layers. Data are stored in a memory buffer before being transferred to an additional buffer stage and being serially read-out upon receipt of a Level 1 trigger. The CBC2 has been subject to extensive testing since its production in January 2013: this work reports the results of electrical characterization, of the total ionizing dose irradiation tests, and the performance of a prototype module instrumented with CBC2 in realistic conditions in a beam test. The latter is the first experimental demonstration of the Pt-selection principle central to the future of CMS. Several total-ionizing-dose tests highlighted no functional issue, but observed significant excess static current for doses < 1 Mrad. The source of the excess was traced to static leakage current in the memory pipeline, and is believed to be a consequence of the high instantaneous dose delivered by the x-ray setup. Nevertheless, a new SRAM layout aimed at removing the leakage path was proposed for the CBC3. The results of single event upset testing of the chip are also reported, two of the three distinct memory circuits used in the chip were proven to meet the expected robustness, while the third will be replaced in the next iteration of the chip. Finally, the next version of the ASIC is presented, highlighting the additional features of the final prototype, such as half-strip resolution, additional trigger logic functionality, longer trigger latency and higher rate, and fully synchronous stub readout.

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Starling, Elizabeth Rose. "Detection and Mitigation of Propagating Electrical Discharges Within the Gas Electron Multiplier Detectors of the CMS Muon System for the CERN HL-LHC." Doctoral thesis, Universite Libre de Bruxelles, 2020. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/315833.

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In preparation for the High-Luminosity Large Hadron Collider (HL-LHC) at CERN, the Compact Muon Solenoid (CMS) Detector is undergoing a series of upgrades to its existing infrastructure, and is adding in several completely new subdetector systems. The first of these new systems, called GE1/1, is a series of 144 gas electron multiplier (GEM) detectors, arranged as 36 two-detector "superchambers" in each of the muon endcaps of CMS. These detectors are a subtype of micropattern gas detectors, and consist of three layers of "GEM foils", thin sheets of polyimide coated with 5 um of copper on each side and chemically etched with holes of 50 - 70 um diameter at a pitch of 140 um. These layers are stacked on top of a printed circuit board (PCB) readout and sealed within a gastight volume that is filled with Ar:CO2 70:30, and a high voltage is applied to the foils to create electric fields within the GEM detectors. When a muon enters the detector and ionizes the gas within, the ionized electrons encounter these fields and multiply in Townsend avalanches at each successive foil layer, until they are read out at the readout PCB at a gain of ~10^4. In early 2017, a demonstrator system known as the "slice test" was installed into the negative endcap. Consisting of 10 GEM detectors, the two-year-long slice test served as both a proof of concept for the GE1/1 system and an invaluable learning experience that would permanently impact not only the GE1/1 project, but future GEM systems GE2/1 and ME0 as well. During the slice test, it was observed that readout channels were being lost in the course of operation to such a degree that the operational lifetime of the system was in serious jeopardy. These losses were attributed to damage to the front-end readout ASIC (VFAT) inputs, caused propagating electrical discharges within the detectors, and a dedicated campaign to study the discharges was launched. The results of this study will be presented in this dissertation. A campaign to mitigate these discharges and their resulting damage was launched. In order to protect the sensitive VFAT from damage, several external protection circuits were proposed and thoroughly tested. The results of these tests, which are presented herein, determined that a series of resistors totaling 470 Ohms would be installed on the VFAT hybrid. When coupled with an additional 200 kOhm resistor on the HV filter, this reduced the probability of damage following a discharge from 93% to 3% As GE2/1 and ME0 are not due to be installed for another few years, more complex discharge-prevention measures can be put into place. As such, the following measures have been examined, and results will be discussed herein: A new, larger VFAT hybrid is being manufactured, whose larger surface area can accommodate more robust protection circuits than those considered and used for GE1/1. As well, double-segmented GEM foils, in which both the top and bottom of each foil is segmented into < 100 cm^2 sectors that are separated by resistors, were examined for use in the detectors. These double-segmented foils were found to introduce a cross-talk signal in the detectors that results in false signals being treated as true signals, which causes a saturation of the GEM bandwidth and results in unwanted dead time. These cross-talk signals, as well as the compromises made to reduce the cross-talk while maintaining robust discharge prevention, will be discussed.
Doctorat en Sciences
info:eu-repo/semantics/nonPublished

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38

Fu, Chien-Cheng, and 傅建程. "CMOS BIOSENSOR READOUT CIRCUIT WITH TEMPERATURE SENSOR." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/61626205578424005036.

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碩士
國立高雄師範大學
電子工程學系
101
The ion-sensitive field effect transistor (ISFET), introduced first by Bergveld in 1970, combined the chemical-sensitive membrane with the metal-oxide-semiconductor field effect transistor. For the past many years, various sensing membrane, readout circuits and calibration methods have been presented. In this thesis, a novel temperature sensor, ISFET structures with built-in gold (Au) reference electrode, and several readout circuits with multiple inputs and an offset sub-circuit are presented. Our laboratory has confirmed previously that the native aluminum oxide applies to the pH-value sensing and brings about the good linearity and sensitivity. In addition, the related read-out circuits have also been presented and the good experimental measurement results have also been exhibited. But the improvement of the read-out circuit, such as the reduction of output signal level for the better resolution by less bit number, is still needed. At first, we utilize a common-source amplifier with a source-degeneration poly-crystalline silicon resistor, which gate is biased by a voltage with a positive temperature coefficient, to implement a temperature sensor with a highly linear output current. By using a current controlled oscillator, the pulse output, which frequency increases highly linearly with increasing temperature, is generated. For the temperature range from 0℃ to 125℃, the measured linearity is up to 99.99% at least and the related nonlinear temperature error range is from 0.47℃ to −0.45℃. Then, we purpose to novel multi-sensor readout circuits and a current offset mechanism, which can adjust the output signal level. Compared with the readout circuit previously presented by our laboratory, the novel readout circuit architecture has a less power consumption and a smaller chip area, and can reduce the output error resulting from process variation, which causes difference between each output characteristics of the multi-sensor readout circuit. The offset mechanism can make these output characteristics nearly the same. The output of the readout circuit is digital pulses, which frequencies exhibit good linearity with environmental temperature and pH value. In addition, the ISFET device structures with built-in gold reference were designed and the sensitivity and linearity of transfer characteristics of output pulse frequency against pH value under the bias by an external silver/silver chloride (Ag/AgCl) reference electrode and a built-in Au reference electrode were studied. The measurement results show that under the chosen biasing conditions for the approximate output frequencies with Ag/AgCl and Au reference electrodes, the sensitivities are -2.24 and -2.91 KHz/pH with linearity of 99.18% and 99.88%, respectively. The sensitivity of the sensor by using the built-in Au reference electrode is larger than by using an external Ag/AgCl electrode.

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39

Hung, Jiun-Yuan, and 洪俊淵. "Design of CMOS Readout Circuit for Condenser Microphone." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/46788907774109861389.

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碩士
國立暨南國際大學
電機工程學系
101
This thesis presents a CMOS readout circuit which for MEMS microphones﹒The readout circuit consists of a charge pump, an impedance transducer and a preamplifier . The charge pump can provide a high voltage for operating microphone through a low power supply voltage﹒The impedance transducer transfers the weak signal from microphone to the input of preamplifier﹒And the preamplifier amplifies the input signal to drive the output load﹒Referring to some related product specifications, a microphone readout circuit chip without the use of external component and additional power supply has been designed and implemented by using TSMC 0.18μm 1P6M CMOS process﹒The chip area is 696×596 μm2 ﹒This circuit operates with 1.8V power supply and the charge pump can provides 12.9V voltage power consumption is 148.87μW﹒

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40

Liu, Yu-Sian, and 劉昱賢. "CMOS/MEMS Accelerometer Readout with Zero-g Calibration." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/42039168850004371575.

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碩士
國立交通大學
電子工程學系電子研究所
101
A monolithic accelerometer design with zero-g calibration in standard 0.18 μm CMOS mixed signal ASIC process is presented. The low noise chopper architecture and telescopic topology are adopted to achieve low noise. The output noise is 26.85 μg/√Hz at 1KHz. On-chip digital offset calibration enables compensation of random offset in the sensor interface. The maximum 21 fF capacitance mismatch can be calibrated. The simulation results show that the whole system have 452.1 mV/g sensitivity. The power consumption is about 1.16 mW.

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Yu, Shin-Yi, and 游士儀. "CMOS Capacitive Pressure Sensor and Readout Circuit Design." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/64616325781417776370.

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碩士
中原大學
電子工程研究所
93
The aim of this thesis is to fabricate CMOS-compatible capacitive pressure sensors and design its readout circuit. The capacitor to frequency converter and readout circuit is tested and it is linear. The sensors use surface micromachining to form an airtight cavity. The sensing capacitor of the capacitive pressure sensors is composed wtih the fourth metal and second metal layer. The third metal layer serves as the sacrificial layer. The whole structure consisted of a sensor capacitor, a reference capacitor, two capacitor to frequency converters and a 12 bit up╱down counter. In the first half cycle, the capacitance of the reference capacitor was converted into frequency and counted its frequency upwardly. In the latter half cycle, counting downwardly for the frequency of stressed sensor capacitor. The readout circuit converted capacitor difference into the product of frequency difference and the time of counting upwardly（be the same as the time counting downwardly）. The output of counter represents the pressure on the capacitive pressure sensor. The readout system has been implemented with 0.18μm 1P6M CMOS technology. With 3V power supply, the power consumption is 6mW. The sensitivity of frequency to capacitor curve is 1.796 [ μs / pF ] and the linearity of the curve is 99.94%. The sensitivity is 275 [ code / pF ], resolution is 3.6fF and linearity is 99.95% for 12 bit digital output to capacitor curve under the conditions of 0.1s converting time and 0pF∼2pF capacitance increase of the capacitive pressure sensor.

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42

WENG, YING-JUN, and 翁穎鈞. "Analog CMOS readout circuit design for low temperature operation." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/98073431278660899514.

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Hsin, Chin-Te, and 辛親德. "Design of CMOS MEMS Pressure Sensor and Readout Circuits." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/m552qw.

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碩士
淡江大學
電機工程學系碩士班
107
A CMOS MEMS pressure sensor for blood pulse and pressure measurement applications is proposed. A capacitive pressure sensor implemented in UMC 0.18 μm CMOS MEMS process is adopted to sense blood pulses and pressure. A readout circuit is designed and integrated with the MEMS sensor. The MEMS sensor has a simulated sensitivity of 6.53 fF/kPa with a sensing range of 4-40 kPa (30-300 mmHg). The overall system has a measured conversion gain of 4.72 mV/kPa. The power dissipation of the whole circuit is only 6.46 μW. Finally, a SAR-ADC is designed to convert the output analog signal of the previous sensing circuit into a digital signal .The sampling rate is 5KHz.The maximum concumed power is 48.114uW under 1.8V power supply.

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44

Po-ChangWu and 吳伯昌. "Design of Multi-Sensor Readout Circuit by Using CMOS MEMS Process." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/59273957360057987911.

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博士
國立成功大學
電機工程學系
103
This dissertation presents the design of low-power low-noise monolithic CMOS MEMS accelerometers using area-efficient digital offset trimming techniques to compensate for process variations caused by sensor capacitance mismatches. The consistent distributions of resonant frequency and sensitivity indicates that the wafer-level 0.18-μm CMOS MEMS process is suitable for integrated inertial sensors. The simulation and measurement results for the designed and fabricated chips show good linearity and noise performance, which are comparable to those seen with commercial products. A 0.6-V monolithic CMOS MEMS accelerometer design with automatic offset trimming capability is also demonstrated in this dissertation, in order to achieve further reductions in the power consumption of the sensor readout circuits. With only 0.2-mW power consumption, the readout circuit can detect smaller than 0.01 g acceleration with the digital output provided by a low-voltage 14-bit ΣΔ ADC. Finally, a multiplexed multi-sensor generic interface circuit which can support the voltage-to-voltage, currentto-voltage, resistance-to-voltage, and capacitance-to-voltage conversion requirements of different sensors is proposed. This feature makes multi-sensor SoC possible when integrating an embedded microprocessor and memory in the CMOS MEMS process. A test chip, which includes a three-axis CMOS MEMS accelerometer, the generic interface circuit, an incremental ΣΔ ADC, and an ARM M0 microprocessor, was fabricated. When combined with a three-axis magnetic sensor which needs some post processing after finishing all CMOS MEMS processes, this test chip can provide a low-power and low-cost three-axis virtual gyroscope with commercial applications.

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Chen, Wei-Yu, and 陳威宇. "The Design of High Performance CMOS Image Sensors and Readout Circuits." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/70768239251003767795.

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碩士
國立交通大學
電子工程系所
97
Image has been played an important role in daily lives recently, like the camera, the video camera, the artificial satellite and so on. The requirement of the high quality image is getting increasing with the advancement of the technology. Due to the usage of the standard CMOS process technology, the CMOS image sensor system can be integrated on a single chip, it can achieve small area and low cost. In my thesis research for high performance image sensor, the main parts of this thesis include: (1) voltage mode CMOS image sensor; (2) new current mode CMOS image sensor. In the voltage mode CMOS image sensor, we analysis, design and optimize the architecture. The implemented voltage mode sensor features high linearity and low fixed pattern noise. The voltage mode sensor is implemented with TSMC 0.18 um process. In the current modes CMOS image sensor, we propose a new linear current mode image sensor. The proposed circuit features high linearity, low power consumption, programmable multiple gain stages, wide input swing and correlated double sampling (CDS) technology. The signal swing of the linear current mode sensor is enhanced by the proposed multiple gain readout structure. A simple and accurate front-end programmable gain structure is proposed to improve the signal-to-noise ratio (SNR) with low power consumption. The current mode sensor is implemented with TSMC 0.18um process.

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Chang, Po-Wei, and 張伯維. "A Wide Dynamic Range CMOS Image Sensor with Dual Exposure Readout." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/71989025977510814402.

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碩士
國立清華大學
電機工程學系
101
This thesis describes a wide dynamic range dual exposure CMOS image sensor with illumination detection scheme to extend the dynamic range, and synthesize the images into a wide dynamic range scene without post signal processing. There are some innovations in this thesis. First, a novel operation for conventional 4T active pixel sensor is proposed so that it can proceed long exposure time and short time in a frame time, and does not require any external image processing to synthesize the wide dynamic range image. Second, an illumination detection scheme is used to reduce the fixed pattern noise (FPN) by process variation in above operation. By detecting the partial signal in the integration time, it can determine the illumination condition of the sensor. It provides a tunable transition point by using different exposure ratios and Vmid, making the sensor to obtain the best image quality in different environment. The prototype wide dynamic range dual exposure readout CMOS image sensor chip is composed of a 128×128 4T-pixel array, and the pixel pitch is 6×6 um2 with 32%fill factor. It was fabricated in TSMC 0.18um 1P6M CMOS image sensor process. A prototype 128×128 imager employed these schemes experimentally achieves 98.9 dB dynamic range with the exposure time ratio of 144. Compared with conventional 4T-APS without these schemes, it increased 37 dB of dynamic range. The column FPN is 1.07mV (0.097%), and the pixel FPN is reduced from 97.4mV (8.85%) to 18.2mV (1.65%) under high illumination condition.

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47

Ke, Wan-Ting, and 柯婉婷. "Visible Light Suppressing CMOS Ultraviolet Phototransistors Integrated with the Readout Circuits." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/kc6gxs.

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Chi, Wen-kuan, and 齊文寬. "DESIGN OF A CMOS-MEMS ACCELEROMETER READOUT WITH DIFFERENTIAL LC OSCILLATORS." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/e7sft3.

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碩士
大同大學
電機工程學系(所)
106
In this thesis, an acceleration sensor and readout circuit for wearable devices have been designed and implemented with UMC 0.18μm CMOS-MEMS 1P7M process, which can integrate the sensor and readout circuits in a single chip. Two LC tanks are used to sense the capacitance variation via the oscillation frequencies, and the frequency difference is extracted by a Gilbert mixer. Finally, a 17-bit counter is used to convert the frequency to a digital signal for easy reading. MEMS simulation software ConventorWare is used to predict the capacitance change caused by acceleration. The sensing capacitors and the suspended inductors are integrated into the mass to reduce the area. According to the simulation result, the initial frequencies of the two oscillators are 1.49GHz and 1.53GHz. The Brown noise from the sensor is 7.64μg/√Hz. The overall system sensitivity is 1.37MHz/g. The overall chip area is 1430um x 1110um.

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49

Ho, Yung-Kuo, and 何勇國. "The Analysis and Design of Split-Path Readout CMOS Active Pixel Sensor Circuits." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/99973386116265923832.

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碩士
長庚大學
半導體研究所
89
In recent years, CMOS image sensors have been extensively noticed and applied. The major reason is that customers popularly and continuously notice the demand for low-power, low-cost and light-thin-short-small feature of products. In additions, there is another advantage for CMOS image sensors that they can integrate distinct systems of VLSI electronics on a single chip and reduce packaging costs, and as being operated with single and standard supply voltage, the power consumption of this kind of camera-on-a-chip system may be measured in the tens of milli watts. In this thesis, we propose an improved CMOS image sensor structure. On the active pixel design, we use the manner of pixel-shared split-path readout to reduce the complexity of each pixel to only two transistors. Due to the reduction of the transistor count, the size of each pixel is 8×8μm2 and the fill factor can be increased to 49% to enhance the quantum efficiency. By the N-well/P-sub structure taken as the photodiode, the sensor will get both smoother photon-electron current and wider sensing range of different wavelengths. To reduce the fixed pattern noise (FPN), the delta-differential sampling circuit is used for the photo signal readout. A 128×128 CMOS image sensor including pixel sensor array, decoder, and readout amplifier circuit are designed based on TSMC 0.35μm 1P4M CMOS technology. Judging from the simulation results, the power consumption is 52mW for a single 128 pixel-array at 3.3V power supply, and the frame readout rate reaches 300 frames per second.

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Huang, Ren-Feng, and 黃仁鋒. "A Mismatch Study on Readout Circuit Designs for Fine-Pitched CMOS Image Sensors." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/84326676922869213193.

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Abstract:

碩士
國立成功大學
電機工程學系碩博士班
94
CMOS image sensors have drawn much attention in these days. The market is booming in different product sectors for the recent 3-4 years and is expected to continue growing in the future. The market share has successfully penetrated into areas such as web cameras, security cameras, digital still cameras and video camcorders. Compared with its technical competing products, CCD (charge-coupled devices), the highly circuit integration capability of the CMOS image sensors makes it superior in certain new imaging applications which requires system compactness and lower power consumption. Column circuit matching issue is critical for integrated CMOS image sensors due to sensitive edge detection capability of human vision. At low illumination conditions, the column-to-column fixed pattern noise is further critical due to signal amplification. Therefore, the contents of this study are itemized as: (a) The design issues of the integrated CMOS imagers, which include column readout circuit architecture and mismatch of the readout circuits, are investigated. (b) The major sources of mismatch are identified and design solutions are proposed to minimize the effect under the constraint of pixel-size pitch match and chip area consumption. (c) The test chip with different design parameters related to circuit matching are implemented and fabricated to verify the analysis results. (d) An imager characterization system is constructed to measure the test chip. The test chip is fabricated in TSMC 0.18μm 1P6M 3.3V mixed-mode process and occupies the area of 1.163×1.163 mm2. The pixel arrays adopt three-transistor (3-T) active pixel sensor (APS) and NW/Psub photodiode. Three types of readout circuit are implemented, and each one contains two mismatch factors to be analyzed.

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