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Journal articles on the topic 'CMOS interface'

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Author: Grafiati

Published: 14 March 2023

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1

Lau, K. T., W. Y. Wang, and K. W. Ng. "Adiabatic-CMOS/CMOS-adiabatic logic interface circuit." International Journal of Electronics 87, no. 1 (January 2000): 27–32. http://dx.doi.org/10.1080/002072100132417.

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2

Ghoshal, U., S. V. Kishore, A. R. Feldman, Luong Huynh, and T. Van Duzer. "CMOS amplifier designs for Josephson-CMOS interface circuits." IEEE Transactions on Appiled Superconductivity 5, no. 2 (June 1995): 2640–43. http://dx.doi.org/10.1109/77.403132.

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3

Wei, Daniel, Stephen R. Whiteley, Lizhen Zheng, Heejoung Park, Hoki Kim, and Theodore Van Duzer. "New Josephson-CMOS Interface Amplifier." IEEE Transactions on Applied Superconductivity 21, no. 3 (June 2011): 805–8. http://dx.doi.org/10.1109/tasc.2010.2088358.

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4

Takagi, Shinichi, Sanjeewa Dissanayake, and Mitsuru Takenaka. "High Mobility Ge-Based CMOS Device Technologies." Key Engineering Materials 470 (February 2011): 1–7. http://dx.doi.org/10.4028/www.scientific.net/kem.470.1.

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In this paper, we report on critical issues and possible solutions for realizing Ge MOSFETs on the Si platform. The main critical objectives in regard to Ge MOSFETs are (1) formation of high quality Ge channel layers on Si substrates (2) MIS gate stacks with much smaller EOT and interface defects (3) superior source/drain junction technology (4) combination of mobility booster technologies such as surface orientation and strain. We demonstrate that GeO2/Ge MOS interfaces can provide superior interface properties, leading to high hole and electron mobility. It is also shown that a gas phase doping technique is promising for forming superior n+/p junctions, which is critical for obtaining Ge nMOSFETs. Also, the importance of surface orientation engineering on the further mobility enhancement of Ge CMOS is addressed.

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5

Wu, Xiang, and Fang Ming Deng. "A Capacitive Humidity Sensor for Low-Cost Low-Power Application." Applied Mechanics and Materials 556-562 (May 2014): 1847–51. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1847.

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This paper presents a capacitive humidity sensor in CMOS technology. The humidity sensor element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication cost. The sensor interface employs a fully-digital architecture based on phase locked loop, which results in low pow dissipation. The proposed humidity sensor is fabricated in TSMC 0.18μm CMOS process and the chip occupies an area of 0.05mm2. The measurement result shows that the sensor value exhibits good linearity within the range of 10-90%RH and the interface circuit consumes only 1.05μW at 0.5V supply voltage.

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6

Chen, Wei Ping, Chang Chun Dong, Xiao Wei Liu, and Zhi Ping Zhou. "A Miniature Fluxgate Sensor with CMOS Interface Circuitry." Key Engineering Materials 483 (June 2011): 164–68. http://dx.doi.org/10.4028/www.scientific.net/kem.483.164.

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In this paper, the writers reported on a fluxgate sensor and a CMOS-ASIC for sensor supply. The design method and principle of the interface circuit of the fluxgate sensor was also presented, which was based on second-harmonic detection of the output voltage. This circuit has been simulated and realized through 0.5μm DPDM P-sub CMOS Process. The size of this circuit is 2mm×2mm. The circuit exhibited a sensitivity of 16.5mV/μT and a linear range of ±90μT. With 5V of voltage supply, the total power consumption of the circuit was as low as 35 mW.

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7

Civardi, L., U. Gatti, F. Maloberti, and G. Torelli. "An integrated CMOS interface for lambda sensor." IEEE Transactions on Vehicular Technology 43, no. 1 (1994): 40–46. http://dx.doi.org/10.1109/25.282264.

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8

Schubert, M. "70V-to-5V differential CMOS input interface." Electronics Letters 30, no. 4 (February 17, 1994): 296–97. http://dx.doi.org/10.1049/el:19940235.

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9

Obaid, Abdulmalik, Mina-Elraheb Hanna, Yu-Wei Wu, Mihaly Kollo, Romeo Racz, Matthew R. Angle, Jan Müller, et al. "Massively parallel microwire arrays integrated with CMOS chips for neural recording." Science Advances 6, no. 12 (March 2020): eaay2789. http://dx.doi.org/10.1126/sciadv.aay2789.

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Multi-channel electrical recordings of neural activity in the brain is an increasingly powerful method revealing new aspects of neural communication, computation, and prosthetics. However, while planar silicon-based CMOS devices in conventional electronics scale rapidly, neural interface devices have not kept pace. Here, we present a new strategy to interface silicon-based chips with three-dimensional microwire arrays, providing the link between rapidly-developing electronics and high density neural interfaces. The system consists of a bundle of microwires mated to large-scale microelectrode arrays, such as camera chips. This system has excellent recording performance, demonstrated via single unit and local-field potential recordings in isolated retina and in the motor cortex or striatum of awake moving mice. The modular design enables a variety of microwire types and sizes to be integrated with different types of pixel arrays, connecting the rapid progress of commercial multiplexing, digitisation and data acquisition hardware together with a three-dimensional neural interface.

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10

Deng, Fang Ming, and Yi Gang He. "A Low-Cost Low-Power Capacitive Humidity Sensor in CMOS Technology." Applied Mechanics and Materials 556-562 (May 2014): 1842–46. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1842.

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This paper presents a capacitive humidity sensor in CMOS technology. The humidity sensor element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication cost. The sensor interface is based on a delta-sigma converter and can be easily reconfigured to compensate for process variation of the sensing element. The proposed humidity sensor is fabricated in 0.16μm standard CMOS process and the chip occupies 0.25mm2. The measurement result shows that this humidity sensor acquires a resolution of 0.1%RH in the range of 20%RH to 90%RH. The interface achieves a 12.5-bits capacitance-to-digital conversion and consumes only 9.6μW power at 1.2V supply voltage.

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11

Terutsuki, Daigo, Hidefumi Mitsuno, Takeshi Sakurai, Yuki Okamoto, Agnès Tixier-Mita, Hiroshi Toshiyoshi, Yoshio Mita, and Ryohei Kanzaki. "Increasing cell–device adherence using cultured insect cells for receptor-based biosensors." Royal Society Open Science 5, no. 3 (March 2018): 172366. http://dx.doi.org/10.1098/rsos.172366.

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Field-effect transistor (FET)-based biosensors have a wide range of applications, and a bio-FET odorant sensor, based on insect (Sf21) cells expressing insect odorant receptors (ORs) with sensitivity and selectivity, has emerged. To fully realize the practical application of bio-FET odorant sensors, knowledge of the cell–device interface for efficient signal transfer, and a reliable and low-cost measurement system using the commercial complementary metal-oxide semiconductor (CMOS) foundry process, will be indispensable. However, the interfaces between Sf21 cells and sensor devices are largely unknown, and electrode materials used in the commercial CMOS foundry process are generally limited to aluminium, which is reportedly toxic to cells. In this study, we investigated Sf21 cell–device interfaces by developing cross-sectional specimens. Calcium imaging of Sf21 cells expressing insect ORs was used to verify the functions of Sf21 cells as odorant sensor elements on the electrode materials. We found that the cell–device interface was approximately 10 nm wide on average, suggesting that the adhesion mechanism of Sf21 cells may differ from that of other cells. These results will help to construct accurate signal detection from expressed insect ORs using FETs.

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12

Zhang, Mingrui, Mitchell Adkins, and Zhe Wang. "Recent Progress on Semiconductor-Interface Facing Clinical Biosensing." Sensors 21, no. 10 (May 16, 2021): 3467. http://dx.doi.org/10.3390/s21103467.

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Semiconductor (SC)-based field-effect transistors (FETs) have been demonstrated as amazing enhancer gadgets due to their delicate interface towards surface adsorption. This leads to their application as sensors and biosensors. Additionally, the semiconductor material has enormous recognizable fixation extends, high affectability, high consistency for solid detecting, and the ability to coordinate with other microfluidic gatherings. This review focused on current progress on the semiconductor-interfaced FET biosensor through the fundamental interface structure of sensor design, including inorganic semiconductor/aqueous interface, photoelectrochemical interface, nano-optical interface, and metal-assisted interface. The works that also point to a further advancement for the trademark properties mentioned have been reviewed here. The emergence of research on the organic semiconductor interface, integrated biosensors with Complementary metal–oxide–semiconductor (CMOS)-compatible, metal-organic frameworks, has accelerated the practical application of biosensors. Through a solid request for research along with sensor application, it will have the option to move forward the innovative sensor with the extraordinary semiconductor interface structure.

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13

Houssa, Michel, Evgueni Chagarov, and Andrew Kummel. "Surface Defects and Passivation of Ge and III–V Interfaces." MRS Bulletin 34, no. 7 (July 2009): 504–13. http://dx.doi.org/10.1557/mrs2009.138.

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AbstractThe need for high-κ gate dielectrics and metal gates in advanced integrated circuits has reopened the door to Ge and III–V compounds as potential replacements for silicon channels, offering the possibility to further increase the performances of complementary metal oxide semiconductor (CMOS) circuits, as well as adding new functionalities. Yet, a fundamental issue related to high-mobility channels in CMOS circuits is the electrical passivation of their interfaces (i.e., achieving a low density of interface defects) approaching state-of-the-art Si-based devices. Here we discuss promising approaches for the passivation of Ge and III–V compounds and highlight insights obtained by combining experimental characterization techniques with first-principles simulations.

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14

Xu, Hua, and Zhe Qiao. "A Low Noise CMOS Digital Output Interface Circuit." Advanced Materials Research 1049-1050 (October 2014): 653–56. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.653.

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A digital CMOS output interface circuit is proposed, which lowers down the peak and lengthen the duration of the pulse of current supplied by the power supply to reduce the SSN (simultaneously-switching noise) effects. The simulation shows that the maximal SSN voltage of the proposed circuit is 331.5mV compared to 662.4mV of the traditional one.

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15

Kayastha, Shrijandra Nath. "Interfacing C328 CMOS camera with an ATMega32L microcontroller." Journal of Science and Engineering 1 (February 1, 2012): 38–42. http://dx.doi.org/10.3126/jsce.v1i0.22492.

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A small low power VGA camera module C328 can perform as a JPEG compressed still camera and can be attached to a microcontroller, PC, wireless or PDA host, etc. This paper introduces the C328 CMOS camera interface with a low power CMOS 8 bit ATMega32L microcontroller based on AVR enhanced RISC architecture. The ATMega32L executes powerful instruction in single clock cycle and achieves throughputs approaching 1MIPS per MHz that allows designing the system with optimum power consumption versus processing speed. The camera module C328 was serially interfaced with microcontroller, and the lowest resolution JPEG image (80x64) compression mode was made for the analysis of packet of image data in hex format. It was specifically designed for the cost effective embedded vision system that can be used in robot, security, monitoring etc.

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16

Boni, Andrea, Michele Caselli, Alessandro Magnanini, and Matteo Tonelli. "CMOS Interface Circuits for High-Voltage Automotive Signals." Electronics 11, no. 6 (March 21, 2022): 971. http://dx.doi.org/10.3390/electronics11060971.

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The acquisition of high-voltage signals from sensors and actuators in an internal-combustion engine is often required for diagnostic purposes or in the case of conversion to alternative fuels, such as hydrogen, natural gas, or biogas. The integration of electronic interfaces and acquisition circuits in a single device provides benefits in terms of component-count reduction and performance. Nonetheless, the high voltage level of the involved signals makes on-chip design challenging. Additionally, the circuits should be compatible with the CMOS technology, with limited use of high-voltage options and a minimum number of off-chip components. This paper describes the design and the implementation in 350 nm CMOS technology of electronic interfaces and acquisition circuits for typical high-voltage signals of automotive context. In particular, a novel co-design of dedicated voltage clamps with electro-static discharge (ESD) protections is described. The proposed circuits require only a single off-chip resistor, and they are suitable for the acquisition of signals with peak voltages up to 400 V. The measured performance of the silicon prototypes, in the [−40 °C, +125 °C] temperature range, make the proposed electronic interfaces suitable for the automotive domain.

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17

TOKUDA, Takashi, Hiroaki TAKEHARA, Toshihiko NODA, Kiyotaka SASAGAWA, and Jun OHTA. "CMOS-Based Optoelectronic On-Chip Neural Interface Device." IEICE Transactions on Electronics E99.C, no. 2 (2016): 165–72. http://dx.doi.org/10.1587/transele.e99.c.165.

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18

Tokuda, Takashi, Hiroshi Kimura, Yosmongkol Sawadsaringkarn, Yasuyo Maezawa, Arata Nakajima, Takuma Kobayashi, Toshihiko Noda, Kiyotaka Sasagawa, and Jun Ohta. "CMOS-based intelligent neural interface device for optogenetics." Neuroscience Research 71 (September 2011): e307-e308. http://dx.doi.org/10.1016/j.neures.2011.07.1341.

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19

Cellere, G., M. G. Valentini, and A. Paccagnella. "Plasma-induced Si/SiO2 interface damage in CMOS." Microelectronic Engineering 63, no. 4 (September 2002): 433–42. http://dx.doi.org/10.1016/s0167-9317(02)00594-4.

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20

Tsukada, Keiji, Takuya Maruizumi, and Hiroyuki Miyagi. "A multiple-ISFET integrated with CMOS interface circuits." Electronics and Communications in Japan (Part II: Electronics) 71, no. 12 (1988): 93–99. http://dx.doi.org/10.1002/ecjb.4420711211.

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21

Strukov, Dmitri B., and Konstantin K. Likharev. "Defect-Tolerant Architectures for Nanoelectronic Crossbar Memories." Journal of Nanoscience and Nanotechnology 7, no. 1 (January 1, 2007): 151–67. http://dx.doi.org/10.1166/jnn.2007.18012.

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We have calculated the maximum useful bit density that may be achieved by the synergy of bad bit exclusion and advanced (BCH) error correcting codes in prospective crossbar nanoelectronic memories, as a function of defective memory cell fraction. While our calculations are based on a particular ("CMOL") memory topology, with naturally segmented nanowires and an area-distributed nano/CMOS interface, for realistic parameters our results are also applicable to "global" crossbar memories with peripheral interfaces. The results indicate that the crossbar memories with a nano/CMOS pitch ratio close to 1/3 (which is typical for the current, initial stage of the nanoelectronics development) may overcome purely semiconductor memories in useful bit density if the fraction of nanodevice defects (stuck-on-faults) is below ∼15%, even under rather tough, 30 ns upper bound on the total access time. Moreover, as the technology matures, and the pitch ratio approaches an order of magnitude, the crossbar memories may be far superior to the densest semiconductor memories by providing, e.g., a 1 Tbit/cm2 density even for a plausible defect fraction of 2%. These highly encouraging results are much better than those reported in literature earlier, including our own early work, mostly due to more advanced error correcting codes.

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22

Gignac, L. M., and K. P. Rodbell. "Metal Microstructures in Advanced CMOS Devices." Proceedings, annual meeting, Electron Microscopy Society of America 54 (August 11, 1996): 358–59. http://dx.doi.org/10.1017/s0424820100164258.

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As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.

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23

Yang, Ping Xian, Zhen Bao Liu, and Tao Jin. "Research on Driver Design for CMOS Image Sensor Based on DM642." Applied Mechanics and Materials 321-324 (June 2013): 994–97. http://dx.doi.org/10.4028/www.scientific.net/amm.321-324.994.

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This paper mainly researches on the TI company fixed-point digital signal processor TMS320DM642 video capture technology for CMOS image sensors, sensor interface and video mini-driver carried out a detailed analysis, established different levels of peripheral structures under different CMOS Sensor, the research in this field has flexible characteristics and high practical value.

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24

Wong, Hei, Jieqiong Zhang, Hiroshi Iwai, and Kuniyuki Kakushima. "Characteristic Variabilities of Subnanometer EOT La2O3 Gate Dielectric Film of Nano CMOS Devices." Nanomaterials 11, no. 8 (August 20, 2021): 2118. http://dx.doi.org/10.3390/nano11082118.

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As CMOS devices are scaled down to a nanoscale range, characteristic variability has become a critical issue for yield and performance control of gigascale integrated circuit manufacturing. Nanoscale in size, few monolayers thick, and less thermally stable high-k interfaces all together cause more significant surface roughness-induced local electric field fluctuation and thus leads to a large device characteristic variability. This paper presents a comprehensive study and detailed discussion on the gate leakage variabilities of nanoscale devices corresponding to the surface roughness effects. By taking the W/La2O3/Si structure as an example, capacitance and leakage current variabilities were found to increase pronouncedly for samples even with a very low-temperature thermal annealing at 300 °C. These results can be explained consistently with the increase in surface roughness as a result of local oxidation at the La2O3/Si interface and the interface reactions at the W/La2O3 interface. The surface roughness effects are expected to be severe in future generations’ devices with even thinner gate dielectric film and smaller size of the devices.

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25

Steyaert, M. S. J., W. Bijker, P. Vorenkamp, and J. Sevenhans. "ECL-CMOS and CMOS-ECL interface in 1.2- mu m CMOS for 150-MHz digital ECL data transmission systems." IEEE Journal of Solid-State Circuits 26, no. 1 (1991): 18–24. http://dx.doi.org/10.1109/4.65705.

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26

Haggag, Amr, William McMahon, Karl Hess, Björn Fischer, and Leonard F. Register. "Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability." VLSI Design 13, no. 1-4 (January 1, 2001): 111–15. http://dx.doi.org/10.1155/2001/90787.

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Silicon-hydrogen bonds passivate the interface defects at the silicon-silicon dioxide interface of CMOS transistors. The activation of these bonds and subsequent creation of interface traps is an important source of transistor degradation at current operating conditions. There is now evidence for a distribution in the activation energies of these bonds instead of a single threshold value. We show that conventional CMOS scaling rules are substantially affected by this energy distribution, as it causes an increased probability of smaller devices having lower activation thresholds and therefore faster activation times. Further, we quantify the voltage shift necessary to overcome the decreased yield due to the increased number of early device failures, and show, for 0.1 μm MOSFET scaling, that this shift can be a considerable fraction of the conventionally designed supply voltage.

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27

Heinssen, Sascha, Theodor Hillebrand, Maike Taddiken, Steffen Paul, and Dagmar Peters-Drolshagen. "On-Line Error Correction in Sensor Interface Circuits by Using Adaptive Filtering and Digital Calibration." Proceedings 2, no. 13 (November 30, 2018): 963. http://dx.doi.org/10.3390/proceedings2130963.

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Numerous non-ideal effects can distort the functionality of sensor interfaces and have to be considered during the design phase. In order to relax the requirements for the analog circuit components, adaptive filtering and digital calibration are used in this work to detect and correct different gain- and offset-errors. The error detection is performed by transmitting a test signal through the sensor interface continuously and in parallel to the sensor signal. In the digital domain, variations of the test signal are evaluated and present errors can be determined and eliminated. In this way, an on-line error correction is realized, which makes the sensor interface more robust against static and dynamic non-idealities. The proposed concept is demonstrated by correcting different gain- and offset-errors in a 65nm CMOS sensor interface.

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28

Li, Xiangyu, Jianping Hu, and Xiaowei Liu. "Study of a closed-loop high-precision front-end circuit for tunneling magneto-resistance sensors." Modern Physics Letters B 33, no. 08 (March 20, 2019): 1950085. http://dx.doi.org/10.1142/s0217984919500854.

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A closed-loop high-precision front-end interface circuit in a standard 0.35 [Formula: see text]m CMOS technology for a tunneling magneto-resistance (TMR) sensor is presented in this paper. In consideration of processing a low frequency and weak geomagnetic signal, a low-noise front-end detection circuit is proposed with chopper technique to eliminate the 1/f noise and offset of operational amplifier. A novel ripple suppression loop is proposed for eliminating the ripple in a tunneling magneto-resistance sensor interface circuit. Even harmonics is eliminated by fully differential structure. The interface is fabricated in a standard 0.35 [Formula: see text]m CMOS process and the active circuit area is about [Formula: see text]. The interface chip consumes 7 mW at a 5 V supply and the 1/f noise corner frequency is lower than 1 Hz. The interface circuit of TMR sensors can achieve a better noise level of [Formula: see text]. The ripple can be suppressed to less than 10 [Formula: see text]V by ripple suppression loop.

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29

Ren, Ming Yuan, Xiao Wei Liu, Hai Feng Zhang, and Zhi Gang Mao. "High Resolution Micro-Displacement Sensing Circuit for Rotor Micro-Gyroscope." Key Engineering Materials 645-646 (May 2015): 538–42. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.538.

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A novel CMOS interface circuit with high resolution is designed and realized to achieve the integration of interface circuit for liquid suspended rotor micro-gyroscope. The detecting circuit adopts continuous-time current sensing circuit for capacitance measurement. The equivalent output noise power spectral density of phase-sensitive demodulation is 120 nV/Hz1/2. The whole circuitry is realized with 0.5 μm 2P2M CMOS process and its testing results show the circuit has a relative capacitance resolution of 1×10-8, in which the power supply is 18 V and the power consumption is 30 mW. The area of the chip is merely 18.5 mm2.

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30

Li, Xiangyu, Liang Yin, Weiping Chen, Zhiqiang Gao, and Xiaowei Liu. "A high-resolution tunneling magneto-resistance sensor interface circuit." Modern Physics Letters B 31, no. 04 (February 10, 2017): 1750030. http://dx.doi.org/10.1142/s0217984917500300.

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In this paper, a chopper instrumentation amplifier and a high-precision and low-noise CMOS band gap reference in a standard 0.5 [Formula: see text] CMOS technology for a tunneling magneto-resistance (TMR) sensor is presented. The noise characteristic of TMR sensor is an important factor in determining the performance of the sensor. In order to obtain a larger signal to noise ratio (SNR), the analog front-end chip ASIC weak signal readout circuit of the sensor includes the chopper instrumentation amplifier; the high-precision and low-noise CMOS band gap reference. In order to achieve the low noise, the chopping technique is applied in the first stage amplifier. The low-frequency flicker noise is modulated to high-frequency by chopping switch, so that the modulator has a better noise suppression performance at the low frequency. The test results of interface circuit are shown as below: At a single 5 V supply, the power dissipation is 40 mW; the equivalent offset voltage is less than 10 uV; the equivalent input noise spectral density 30 nV/Hz[Formula: see text](@10 Hz), the equivalent input noise density of magnetic is 0.03 nTHz[Formula: see text](@10 Hz); the scale factor temperature coefficient is less than 10 ppm/[Formula: see text]C, the equivalent input offset temperature coefficient is less than 70 nV/[Formula: see text]C; the gain error is less than 0.05%, the common mode rejection ratio is greater than 120 dB, the power supply rejection ratio is greater than 115 dB; the nonlinear is 0.1% FS.

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31

Ren, Mingyuan, Honghai Xu, Xiaowei Han, Changchun Dong, and Xuebin Lu. "Low Noise Interface ASIC of Micro Gyroscope with Ball-disc Rotor." Sensors 20, no. 4 (February 24, 2020): 1238. http://dx.doi.org/10.3390/s20041238.

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A low noise interface ASIC for micro gyroscope with ball-disc rotor is realized in 0.5µm CMOS technology. The interface circuit utilizes a transimpedance pre-amplifier which reduces input noise. The proposed interface achieves 0.003°/s/Hz1/2 noise density and 0.003°/s sensitivity with ±100°/s measure range. The functionality of the full circuit, including circuit analysis, noise analysis and measurement results, has been demonstrated.

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32

Zhang, Cheng, and Kofi A. A. Makinwa. "Interface Electronics for a CMOS Electrothermal Frequency-Locked-Loop." IEEE Journal of Solid-State Circuits 43, no. 7 (July 2008): 1603–8. http://dx.doi.org/10.1109/jssc.2008.922405.

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33

Mansoorian, B., V. Ozguz, and S. Esener. "Diode-biased AC-coupled ECL-to-CMOS interface circuit." IEEE Journal of Solid-State Circuits 28, no. 3 (March 1993): 397–99. http://dx.doi.org/10.1109/4.210011.

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34

Hageman, Kristin N., Zaven K. Kalayjian, Francisco Tejada, Bryce Chiang, Mehdi A. Rahman, Gene Y. Fridman, Chenkai Dai, et al. "A CMOS Neural Interface for a Multichannel Vestibular Prosthesis." IEEE Transactions on Biomedical Circuits and Systems 10, no. 2 (April 2016): 269–79. http://dx.doi.org/10.1109/tbcas.2015.2409797.

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35

Shi, Zhan, Zhenan Tang, Chong Feng, and Hong Cai. "Improvement to the signaling interface for CMOS pixel sensors." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 832 (October 2016): 77–84. http://dx.doi.org/10.1016/j.nima.2016.06.012.

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36

Dong, Chang Chun, and Zhan Peng Jiang. "Noise Analysis and Characterization of a CMOS Interface Circuit for Fluxgate Sensor." Advanced Materials Research 981 (July 2014): 107–10. http://dx.doi.org/10.4028/www.scientific.net/amr.981.107.

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In this paper, noise analysis and characterization of a 5V CMOS interface circuit for the fluxgate is presented, which is based on second-harmonic detection of the output voltage. The circuit consists of oscillator, band pass filter, phase sensitive demodulation, low pass filter. The chip is fabricated in the 0.5μm two–metal and two-poly n-well CMOS process with an area of 4 mm2. Experimental results shows, the system exhibits a sensitivity of 16.5μV/nT for a magnetic field range of ±90μT in open-loop with 5kHz excitation frequency. Using 5V supply voltage, the power consumption of the system is measured to be 35 mW.

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37

Guo, Jing Jing, Xiao Jing Xu, and Jin Tao Kang. "A Design of Image Acquisition System Based on FPGA and USB2.0." Applied Mechanics and Materials 552 (June 2014): 155–60. http://dx.doi.org/10.4028/www.scientific.net/amm.552.155.

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The paper introduces a realization method of high-speed image acquisition system based on FPGA and USB2.0. After introducing the CMOS chip MT9T001 of Micron Technology, Inc. and the universal interface chip CY7C68013 of Cypress Semiconductor Corporation, we design the hardware platform of image acquisition system and the control program written by Verilog HDL language through which FPGA can simulate I2C bus to configure CMOS. Then we introduce the development of firmware, driver and application of the USB interface. This paper completed the design and the experiment of image acquisition system well. In the test, the system achieves the requirement of real-time display. The collected images are clear, which can satisfy design requests.

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Idris, Muhammad I., Ming Hung Weng, H. K. Chan, A. E. Murphy, Dave A. Smith, R. A. R. Young, Ewan P. Ramsay, David T. Clark, Nick G. Wright, and Alton B. Horsfall. "Electrical Stability Impact of Gate Oxide in Channel Implanted SiC NMOS and PMOS Transistors." Materials Science Forum 897 (May 2017): 513–16. http://dx.doi.org/10.4028/www.scientific.net/msf.897.513.

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Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) and effective charge (NEFF) have been acquired from C-V characteristics to assess the effectiveness of the fabrication process in realising high quality gate dielectrics. The performance of SiC based CMOS transistors were analyzed by correlating the characteristics of the MOS interface properties, the MOSFET 1/f noise performance and transistor on-state stability at 300°C. The observed instability of PMOS devices is more significant than in equivalent NMOS devices. The results from MOS capacitors comprising interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) for both N and P MOS are in agreement with the expected characteristics of the respective transistors.

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Zhang, Yu, and Chun Yang Wang. "The Design of Image Acquisition System Based on CMOS Image Sensor USB Interface." Applied Mechanics and Materials 602-605 (August 2014): 2756–60. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.2756.

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The system selected OmniVisiON company's CMOS chip OV7620, it is an integrated color camera chip, a 640 × 480 (300,000 pixels) image matrix. Considered that the CPLD control system is similar to the DMA mode of data transmission; Cypress's USB 2.0 chip is used by CY7C68013 chip. Finally, it is become the microcontroller firmware and device driver. The paper presents the design of Image acquisition system based on CMOS image sensor USB interface. Design an image acquisition and transmission system, and describes its firmware as well as the development of USB device drivers and PC-side application .

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Hu, Zhi Yu, and Li Li. "The Design of Image Acquisition System Based on CMOS Image Sensor USB Interface." Advanced Materials Research 989-994 (July 2014): 3861–64. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.3861.

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The system selected OmniVisiON company's CMOS chip OV7620, it is an integrated color camera chip, a 640 × 480 (300,000 pixels) image matrix. Considered that the CPLD control system is similar to the DMA mode of data transmission; Cypress's USB 2.0 chip is used by CY7C68013 chip. Finally, it is become the microcontroller firmware and device driver. The paper presents the design of Image acquisition system based on CMOS image sensor USB interface. Design an image acquisition and transmission system, and describes its firmware as well as the development of USB device drivers and PC-side application.

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41

Jeon, Hyuntak, Injun Choi, Soon-Jae Kweon, and Minkyu Je. "A Power-Efficient Radiation Sensor Interface with a Peak-Triggered Sampling Scheme for Mobile Dosimeters." Sensors 20, no. 11 (June 7, 2020): 3255. http://dx.doi.org/10.3390/s20113255.

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Radiation sensor interfaces for battery-powered mobile dosimeters must consume low power to monitor the amount of radiation exposure over a long period. This paper proposes a power-efficient radiation sensor interface using a peak-triggered sampling scheme. Since the peak of the analog-to-digital converter’s (ADC’s) input represents radiation energy, our ADC only operates around the peak value thanks to the proposed sampling scheme. Although our ADC operates with a high sampling frequency, this proposed sampling scheme reduces the power consumption of the sensor interface because of the reduced operation time of the ADC. Our sensor interface does not have signal distortion caused by a conventional shaper because the interface quantizes the peak value using the high sampling frequency instead of the shaper. When the radiation input occurs once every 10 μs, the power consumption of the ADC with the proposed sampling scheme is only about 21.5% of the ADC’s power consumption when the ADC continuously operates. In this worst case, the fabricated radiation sensor interface in a 0.18-μm complementary metal-oxide-semiconductor (CMOS) process consumes only 1.11 mW.

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Zhan, Yongzheng, Tuo Li, Yuqiu Yue, Tongqiang Liu, Yulong Zhou, and Xiaofeng Zou. "Low-power 25Gb/s 16:1 Multiplexer for 400Gb/s Ethernet PHY." Journal of Physics: Conference Series 2083, no. 2 (November 1, 2021): 022032. http://dx.doi.org/10.1088/1742-6596/2083/2/022032.

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Abstract A lower power 25Gb/s 16:1 multiplexer using 65nm CMOS technology for 400Gb/s Ethernet (400GbE) physical layer (PHY) interface was presented. CMOS+CML mixed logic is adopted to achieve hierarchical architecture, avoiding the high clock requirement of one-step structure and improving the transmission speed. In order to reduce power while achieving high data rate, multiplexing structure is also optimized by utilizing multi-frequency multi-phase technology which not only ensures the requirement of the phase stabilization, but also leaves out some flip-flops. For CMOS-CML conversion circuit, transmission gate and cross-coupled CMOS inverter are used to match the delay of CMOS inverter, suppressing the effect of common-mode noise. Simulation results show that the multiplexer works correctly and jitter of output signal is less than 0.1UI. When voltage is 1.2V, the total power is 32.7mW at 25Gb/s.

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Yang, Min-Jae, Eun-Jung Yoon, and Chong-Gun Yu. "A CMOS Interface Circuit for Vibrational Energy Harvesting with MPPT Control." Journal of IKEEE 20, no. 1 (March 31, 2016): 45–53. http://dx.doi.org/10.7471/ikeee.2016.20.1.045.

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OKTYABRSKY, SERGE, MICHAEL YAKIMOV, VADIM TOKRANOV, RAMA KAMBHAMPATI, HASSARAM BAKHRU, SERGEI KOVESHNIKOV, WILMAN TSAI, FENG ZHU, and JACK LEE. "CHALLENGES AND PROGRESS IN III-V MOSFETs FOR CMOS CIRCUITS." International Journal of High Speed Electronics and Systems 18, no. 04 (December 2008): 761–72. http://dx.doi.org/10.1142/s0129156408005746.

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An overview of III-V MOSFET technological challenges in comparison to well-established heterostructure-based FET technologies is presented with an emphasis on required properties and possible solutions. Possible approaches to achieve thermodynamically stable high- k gate stack with low interface trap density are reviewed, followed with our results on amorphous Si interface passivation layer (IPL) in-situ deposited on top of GaAs or strained InGaAs MOSFET channels grown by molecular beam epitaxy. Main issues of Si IPL, namely increased equivalent oxide thickness due to IPL oxidation and Si diffusion into the semiconductor channel, are addressed using an in-situ deposited HfO 2 with ultrathin (down to 0.25 nm) Si IPL and controlling its bonding state at the interface. Enhancement mode inversion-type MOSFET with HfO 2 high- k oxide is demonstrated. The device employs amorphous Si interface passivation layer, sputter-deposited high- k oxide and metal TaN gate and modulation p-doped GaAs / AlGaAs heterostructure with inversion n -channel formed at the interface with the oxide. The MOSFET with equivalent oxide thickness of 3.7 nm and long 100 μm channel have maximum DC transonductance of 0.9 mS/mm, Ion/Ioff = 2×104 (at low Ioff of 30 nA) and effective channel mobility exceeding 1000 cm2/V-s at sheet electron density <2×1012 cm-2.

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Dei, Michele, Joan Aymerich, Massimo Piotto, Paolo Bruschi, Francisco del Campo, and Francesc Serra-Graells. "CMOS Interfaces for Internet-of-Wearables Electrochemical Sensors: Trends and Challenges." Electronics 8, no. 2 (January 31, 2019): 150. http://dx.doi.org/10.3390/electronics8020150.

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Smart wearables, among immediate future IoT devices, are creating a huge and fast growing market that will encompass all of the next decade by merging the user with the Cloud in a easy and natural way. Biological fluids, such as sweat, tears, saliva and urine offer the possibility to access molecular-level dynamics of the body in a non-invasive way and in real time, disclosing a wide range of applications: from sports tracking to military enhancement, from healthcare to safety at work, from body hacking to augmented social interactions. The term Internet of Wearables (IoW) is coined here to describe IoT devices composed by flexible smart transducers conformed around the human body and able to communicate wirelessly. In addition the biochemical transducer, an IoW-ready sensor must include a paired electronic interface, which should implement specific stimulation/acquisition cycles while being extremely compact and drain power in the microwatts range. Development of an effective readout interface is a key element for the success of an IoW device and application. This review focuses on the latest efforts in the field of Complementary Metal–Oxide–Semiconductor (CMOS) interfaces for electrochemical sensors, and analyses them under the light of the challenges of the IoW: cost, portability, integrability and connectivity.

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Zhang, Jie Qiong, Dan Qun Yu, Hei Wong, Kuniyuki Kakushima, and Hiroshi Iwai. "Observation of Substrate Silicon Incorporation into Thin Lanthanum Oxide Film during Rapid Thermal Annealing." Advanced Materials Research 1120-1121 (July 2015): 414–18. http://dx.doi.org/10.4028/www.scientific.net/amr.1120-1121.414.

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Lanthanum oxide (La2O3) has been proposed as the promising gate dielectric material for future complementary metal-oxide-semiconductor (CMOS) technology. However, unlike the conventional homopolar materials such as silicon oxide or silicon nitride, La2O3 is more ionic and in particular at the La2O3/Si interface is less thermally stable. This work investigates the chemical and compositional variations of La2O3 thin film on the silicon substrate during rapid thermal annealing by using angle-resolved x-ray photoelectron spectroscopy (ARXPS) measurements. Results show that thermal annealing at temperatures above 500 °C would result in the incorporation of substrate Si atoms deep into the bulk of the La2O3 film and forming silicate phases both at the interface and in the bulk. These effects would result in the characteristic degradation of CMOS devices.

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TORIUMI, Akira. "Interface Control of GeO2/Ge for High-performance Ge CMOS." Hyomen Kagaku 33, no. 11 (2012): 622–27. http://dx.doi.org/10.1380/jsssj.33.622.

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Martin, Lucy Claire, Hua Khee Chan, David T. Clark, Ewan P. Ramsay, A. E. Murphy, Dave A. Smith, Robin F. Thompson, et al. "Low Frequency Noise Analysis of Monolithically Fabricated 4H-SiC CMOS Field Effect Transistors." Materials Science Forum 778-780 (February 2014): 428–31. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.428.

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Low frequency noise in 4H-SiC lateral p-channel metal oxide semiconductor field effect transistors (PMOSFETs) in the frequency range from 1 Hz to 100 kHz has been used to investigate the relationship between gate dielectric fabrication techniques and the resulting density of interface traps at the semiconductor-dielectric interface in order to examine the impact on device performance. The results show that the low frequency noise characteristics in p-channel 4H-SiC MOSFETs in weak inversion are in agreement with the McWhorter model and are dominated by the interaction of channel carriers with interface traps at the gate dielectric/semiconductor interface.

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Suzuki, M., M. Maezawa, H. Takato, H. Nakagawa, F. Hirayama, S. Kiryu, M. Aoyagi, T. Sekigawa, and A. Shoji. "An interface circuit for a Josephson-CMOS hybrid digital system." IEEE Transactions on Appiled Superconductivity 9, no. 2 (June 1999): 3314–17. http://dx.doi.org/10.1109/77.783738.

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Sano, B., B. Madhavan, and A. F. J. Levi. "8 Gbit/s CMOS interface for parallel fibre-optic interconnects." Electronics Letters 32, no. 24 (1996): 2262. http://dx.doi.org/10.1049/el:19961502.

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